WO2016112857A1 - Ldpc码编码器和译码器 - Google Patents

Ldpc码编码器和译码器 Download PDF

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Publication number
WO2016112857A1
WO2016112857A1 PCT/CN2016/070865 CN2016070865W WO2016112857A1 WO 2016112857 A1 WO2016112857 A1 WO 2016112857A1 CN 2016070865 W CN2016070865 W CN 2016070865W WO 2016112857 A1 WO2016112857 A1 WO 2016112857A1
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Prior art keywords
check
node
matrix
information
memory
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PCT/CN2016/070865
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English (en)
French (fr)
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黄勤
蔡琛
陆国雷
王祖林
冯文全
何善宝
Original Assignee
北京航空航天大学
北京航天华科技有限公司
中国空间技术研究院总体部
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Priority to CN201680015662.3A priority Critical patent/CN107852176A/zh
Priority to US15/529,620 priority patent/US10536169B2/en
Publication of WO2016112857A1 publication Critical patent/WO2016112857A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H03M13/1188—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/611—Specific encoding aspects, e.g. encoding by means of decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations

Definitions

  • the present application relates to a data processing apparatus, and in particular to an LDPC code encoder and decoder.
  • a low-density parity check (LDPC) code is a type of linear block code whose decoding performance is close to the channel limit. Due to its excellent error correction performance, binary LDPC codes have been widely used in various communication, navigation and digital storage systems. Multi-ary LDPC codes have also become favorable competitors for error correction coding schemes in these systems in the future.
  • LDPC low-density parity check
  • the embodiment of the present application provides a data processing apparatus, thereby achieving the purpose of reducing hardware resource consumption.
  • an embodiment of the present application provides a data processing apparatus, including: m data processing modules, configured to process N i data or operations in an i-th cycle according to a calculation order; And m ⁇ n, m, n and N i are positive integers,
  • an embodiment of the present application provides an LDPC code translation.
  • the coder comprises: a variable node calculation unit; a check node calculation unit; a memory storing the iterative information of each side of the check matrix of the LDPC code; the controller, the control node calculation unit performing the decoding iterative operation until the translation End of code, wherein in each decoding iteration operation, the controller controls the variable node calculation unit to traverse the variable node information of all variable nodes, and update the iteration information of the memory according to the calculated variable node information, and The controller controls the check node calculation unit to traverse the check node information of all the check nodes, and update the iteration information of the memory according to the calculation result of the check node obtained by the calculation.
  • an embodiment of the present application provides an LDPC code decoder, including: a plurality of variable node calculation units; a plurality of check node calculation units; and a memory that stores a check matrix of the LDPC code.
  • the edge of the iterative information; the controller, the control node calculating unit performs a decoding iterative operation until the end of the decoding, wherein in each decoding iteration operation, the controller controls the plurality of variable nodes to calculate the unit traversal calculation Variable node information of all variable nodes, and updating iteration information of the memory according to the calculated variable node information, and the controller controls the plurality of check node calculation units to traverse the check node information of all the check nodes, and The iteration information of the memory is updated according to the calculation result of the check node obtained by the calculation.
  • an embodiment of the present application provides an LDPC code decoder, including: a node calculation unit; a first memory, storing iteration information of a variable node of a parity check matrix of the LDPC code; and a second memory And storing iteration information of each side of the check matrix of the LDPC code; the controller, the control node calculating unit performs a decoding iterative operation until the decoding ends, wherein in each decoding iteration operation, the controller controls The node calculation unit traverses all variable node information and all check node information, and updates the iteration information in the first memory and the second memory according to the variable node information and the check node information.
  • an embodiment of the present application provides an LDPC code decoding method, including: storing iteration information of each side of a check matrix of an LDPC code; performing a decoding iterative operation until the end of decoding, In each decoding iteration operation, the variable node information of all variable nodes is successively traversed, and the stored iteration information is updated correspondingly, and the check node information of all check nodes is calculated successively, and the stored iterations are updated accordingly.
  • FIG. 1 is a schematic diagram of an encoder of a fully parallel structure provided by the prior art
  • FIG. 2 is a schematic diagram of a data processing apparatus according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a data processing apparatus according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a data processing apparatus according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a generation matrix as a sparse matrix
  • FIG. 7 is a schematic diagram of a submatrix in which a matrix is generated as a cyclic matrix
  • Figure 8 shows a check matrix of a schematic LDPC code.
  • FIG. 9 shows a Tanner graph of the check matrix shown in FIG.
  • FIG. 10 shows a schematic diagram of an LDPC code decoder according to an embodiment of the present application
  • FIG. 11 is a schematic diagram of an LDPC code decoder according to an embodiment of the present application.
  • FIG. 12 is a diagram showing a check matrix of an LDPC code including a plurality of cyclic matrices
  • FIG. 13 shows a basic matrix corresponding to a check matrix of an LDPC code of a schematic GPS system
  • FIG. 14 is a view showing a Tanner graph corresponding to the LDPC code shown in FIG. 13;
  • FIG. 15 shows a variable node, a check node, and a corresponding edge connection relationship corresponding to one block edge in FIG. 14;
  • Figure 16 is a timing chart showing the successive traversal operations of the variable node calculation unit
  • Figure 17 is a timing chart showing the successive traversal operations of the check node calculation unit
  • FIG. 18 is a schematic diagram of an LDPC code decoder according to an embodiment of the present application.
  • Each data processing module outputs a code character number of the final code sequence, so that n data processing modules will output all code words in one operation cycle.
  • the encoder of the full parallel structure causes waste of hardware resources. To solve this technical problem, the present application provides a data processing apparatus.
  • the data processing apparatus can be applied to LDPC coded or decoded scenarios, where the apparatus can be an LDPC code encoder, or an LDPC code decoder.
  • the data processing apparatus includes: m data processing modules 201 for processing N i data or operations in an i-th cycle according to a calculation order; And m ⁇ n, m, n and N i are positive integers,
  • N i in the first cycle is m;
  • Each data processing module 201 is processed as much as possible to process a single data or operation.
  • N i data or operations are processed, where N i operations can be understood as N i multiplication operations, where N i data can be understood as N i specific numbers, or N i vectors, matrices, etc. The embodiments of the present application do not limit this.
  • the operation uses k-1 adders to calculate the sum of the above products, and a code character number can be generated by the action of the multiplier and the adder.
  • An embodiment of the present application provides a data processing apparatus, where the apparatus includes: m data processing modules, configured to process N i data or operations in an i-th cycle according to a calculation order; And m ⁇ n, m, n and N i are positive integers, Through the multiplexing of m data processing modules in time, the processing of n data or operations is achieved, thereby reducing the consumption of hardware resources.
  • FIG. 3 is a schematic diagram of a data processing apparatus according to an embodiment of the present application.
  • the apparatus may be specifically an LDPC encoder, where the encoder includes m data processing modules, and the m data processing modules are specifically configured to:
  • the length of n; the number of columns of the generator matrix G k ⁇ n , and the calculation of c (c 0 , c 1 ...
  • the degree of parallelism of the data processing apparatus can be referred to as m.
  • the operation uses k-1 adders to calculate the sum of the above products, and a code character number can be generated by the action of the multiplier and the adder.
  • An embodiment of the present application provides a data processing apparatus, where the apparatus includes m data processing modules, where the m data processing modules are specifically configured to separately calculate data to be encoded in a low density parity check LDPC encoding process.
  • each of the generation matrices G k ⁇ n is divided into blocks based on the idea of blocking.
  • the data processing module in the data processing device includes: a first storage unit 401 and a second storage unit 402; wherein the data processing module is configured to divide each column of the generation matrix G k ⁇ n into P first data blocks; Where P ⁇ 2. As shown in FIG.
  • the first storage unit 401 is configured to store a first data block; the second storage unit 402 is configured to store a second data block corresponding to the data to be encoded corresponding to the first data block;
  • the storage unit 401 stores the first data block of length d at this time, and the second storage unit 402 stores the second data block of length d at this time.
  • the data processing module further includes a multiplier, an adder and an accumulator
  • the first storage unit can be multiplexed with respect to each of the first data blocks, and the second storage unit can also be multiplexed with respect to the second data block, that is, no unnecessary storage space needs to be opened, and all of the first The data block may use one first storage unit in time series, and all the second data blocks may use one second storage unit in time series.
  • each column is divided into two first data blocks, for each column, from top to bottom
  • the first element constitutes a first data block
  • the second element and the third element constitute a first data block.
  • the generation matrix G 3 ⁇ 5 actually includes 10 first data blocks, and accordingly,
  • the second data block formed by the first element and the first data block formed by the first element of the first column in the generation matrix G 3 ⁇ 5 , c (c 0 , c 1 ,
  • the product of the second block of the first element of c 2 ) and the first block of the generator matrix G 3 ⁇ 5 consisting of the first element of the second column, c (c 0 , c 1 ,
  • the data processing module of the data processing apparatus includes: a first storage unit and a second storage unit; the data processing module is configured to divide each column of the generation matrix G k ⁇ n into P first data blocks a first storage unit is configured to store a first data block, a second storage unit is configured to store a second data block of the data to be encoded corresponding to the first data block, and m data processing modules are specifically configured to:
  • the data processing apparatus implements multiplexing of the storage space based on the idea that the check matrix acquires the final encoded sequence.
  • the first redundant bit p 1 can be calculated directly from the elements in the data to be encoded, and the second redundant bit p 2 can be calculated jointly by the first redundant bit p 1 and the elements in the data to be encoded, Such a push, p nk can be calculated jointly by p nk-1 and the elements in the data to be encoded. Therefore, it is possible to first read from the memory module storing (M, p 1 , p 2 ... p nk ) the corresponding one of the first non-zero elements in the first row of the check matrix (M, p 1 , p 2 ...
  • FIG. 5 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application.
  • the data processing apparatus includes a first storage module 502 for storing a generation matrix in addition to the m data processing modules 501.
  • the first storage module 502 is specifically configured to:
  • the first storage module stores only the position coordinates corresponding to the non-zero elements of the generation matrix and the non-zero elements.
  • the number of non-zero elements in the matrix is much smaller than the total number of matrix elements, and the matrix is called a sparse matrix. Therefore, the first storage module stores only the position coordinates corresponding to the non-zero elements and non-zero elements of the generated matrix. Further, when the binary LDPC encoding is used in the present application, the non-zero element in the generated matrix is only 1. Therefore, only the location coordinates corresponding to the non-zero element 1 may be stored in the first storage module.
  • the first storage module stores only all non-zero elements in the cyclic matrix, and position coordinates corresponding to one column of non-zero elements and adjacent two columns The loop offset.
  • the generation matrix is a quasi-cyclic matrix, such as a generation matrix.
  • the first storage module can store only q non-zero elements, and then store the position of the first column non-zero element g 0 and the cyclic offset 1 of the adjacent two columns, so that the non-zero elements of other columns can pass the first
  • the position and cyclic offset of a list of non-zero elements are derived.
  • the non-zero element in the generation matrix is only 1, so that only the position and the cyclic offset corresponding to the non-zero element 1 can be stored in the first storage module.
  • the embodiment provides a data processing device, and the device further includes a first storage module, configured to store a generation matrix. If the generation matrix is a sparse matrix, the first storage module stores only the position coordinates corresponding to the non-zero elements of the generation matrix and the non-zero elements; if the sub-matrix of the generation matrix is a cyclic matrix, the first storage module stores only the loop. All non-zero elements in the matrix, and the position coordinates corresponding to one of the non-zero elements and the cyclic offset of the adjacent two columns, thereby achieving the multiplexing effect of the first storage module. Thereby reducing the consumption of hardware resources.
  • Figure 6 is a schematic diagram of the generation matrix as a sparse matrix.
  • the data stored in the first address in the first storage module 502 is: (1, 3, 0), indicating that the first row block of the first column block is in the first row block.
  • the position of the non-zero element, the first data processing module sets the first bit of its first storage unit 401 to 1 according to 1, and the second data processing module sets the third bit of its first storage unit 401 according to 3.
  • the data stored in the second address of the first storage module 502 is: (0, 0, 1), indicating the position of the non-zero element in the second row block of the first column block, and the third data processing module is based on 1
  • the first bit of the first storage unit 401 is set to 1 ... and so on, and the entire generation matrix can be completely represented by coexisting 12 sets of data, and only the non-recording of each data block is required in the first storage module.
  • the position of the zero element can guide the data processing module to complete the coding work. For multi-ary LDPC codes, you also need to record the value of non-zero elements.
  • FIG. 7 is a schematic diagram of a submatrix of a generator matrix as a cyclic matrix.
  • the data stored in the first address in the first storage module 502 is: (1, 1, 1), indicating the first non-zero of the first column block.
  • the sub-matrix is located in the first row block, the first column is a non-zero element in the first position, and the loop offset is 1 (the loop offset is not stored when the loop offset is a fixed value), the first data processing
  • the module sets the first bit of its first storage unit 401 to 1
  • the second data processing module sets the second bit of its first storage unit 401 to 1
  • the third data processing module sets its first storage unit 401.
  • the third bit is set to 1; the data stored in the second address of the first storage module 502 is: (4, 3, 1), indicating that the second non-zero sub-matrix of the first column block is located in the fourth row.
  • the first column of non-zero elements is in the third position, the cyclic offset is 1, the first data processing module sets the third bit of its first storage unit 401 to 1, and the second data processing module sets its The first bit of a storage unit 401 is set to 1, and the third data processing module sets its first The second bit of the storage unit 401 is set to 1 and so on.
  • a total of 6 sets of data are required to completely represent the entire generation matrix, and only the non-zero elements of each data block need to be recorded in the first storage module.
  • the location guides the data processing module to complete the encoding. For multi-ary LDPC codes, you also need to record the value of non-zero elements.
  • an LDPC code decoder and a decoding method are also provided.
  • the decoding algorithm in the decoder and decoding method according to the present application may employ an iterative decoding algorithm such as a belief propagation algorithm, a minimum sum algorithm, a message passing algorithm, and the like.
  • the iterative decoding algorithm is implemented based on the Tanner graph of the check matrix of the LDPC code.
  • Figure 8 shows a check matrix of a schematic LDPC code.
  • FIG. 9 shows a Tanner graph of the check matrix shown in FIG.
  • the column of the check matrix corresponds to the variable node
  • the row of the check matrix corresponds to the check node
  • the line between the connection variable node and the check node corresponds to a non-zero element in the check matrix, which is called an edge.
  • the decoding process can be viewed as an iterative process of iterative information passing between the variable node and the check node.
  • FIG. 10 shows a schematic diagram of an LDPC code decoder in accordance with an embodiment of the present application.
  • the LDPC code decoder includes: a variable node calculation unit 1100, a check node calculation unit 1200, a memory 2000, and a controller 3000.
  • the variable node calculation unit 1100 stores iterative information of each side of the check matrix of the LDPC code.
  • the iterative information may include, for example, a code character number and a confidence level corresponding to each side of the check matrix.
  • the controller 3000 controls the node calculation unit to perform a decoding iterative operation until the decoding ends.
  • the controller control variable node calculation unit 1100 traverses the variable node information of all the variable nodes, and updates the iteration information of the memory according to the calculated variable node information.
  • the variable node information of the variable node may include, for example, a code character number and a confidence of each side of the variable node.
  • the controller 3000 also controls the check node calculation unit 1200 to traverse the check node information of all the check nodes, and updates the iteration information of the memory 3000 according to the calculation result of the check node obtained by the calculation.
  • the check node information of the check node may include, for example, the confidence of each side of the check node.
  • the node calculation unit can implement the entire iterative decoding process serially. And the input and output ports between the variable node calculation unit and the check node calculation unit are not directly connected, but are connected through a memory according to the control of the controller. By multiplexing the node computing unit in time, hardware resources are greatly saved and the implementation cost is reduced.
  • the decoder according to the present application can be used for the case where the LDPC code is binary or the case where the LDPC code is a multi-ary code.
  • the code character number in the iterative information may be, for example, a corresponding hard decision, and the confidence may be, for example, an LLR value.
  • the iterative information may include a plurality of code character numbers corresponding to each side of the check matrix and a corresponding plurality of confidence levels. Multiple code character numbers and corresponding multiple confidences may be in the form of vector information.
  • the controller 3000 controls the variable node calculation unit to traverse the variable node information of all variable nodes (including the code character number and confidence of the edge corresponding to the variable node), and obtains the variable node according to the calculation. Iterative information of the information update memory.
  • the controller 3000 controls the check node calculation unit to traverse the check node information of all the check nodes (including the confidence of the edge corresponding to the check node), and updates the iterative information of the memory according to the calculation result of the check node obtained by the calculation. .
  • the variable node calculation unit 1100 when the variable node calculation unit 1100 performs the variable node calculation, it is necessary to obtain the initial confidence corresponding to the variable node.
  • the initial confidence is the input information that the receiver receives from the channel and is demodulated by the receiver front-end device (such as a demodulator) and then passed to the decoder.
  • the initial confidence can be stored in an input buffer (not shown).
  • variable node calculation unit 1100 When the variable node calculation unit 1100 performs the current variable node calculation, the initial confidence corresponding to the currently calculated variable node is queried, and the iteration information of all the edges corresponding to the currently calculated variable node is obtained from the memory 3000, and according to the obtained The initial confidence and iteration information performs a variable node operation to obtain the code character number and confidence of all edges corresponding to the currently calculated variable node, and correspondingly update the iterative information of all edges in the memory corresponding to the currently calculated variable node. Code character number and confidence.
  • the check node calculation unit 1200 When the check node calculation unit 1200 performs the current check node calculation, the iteration information of all the edges corresponding to the currently calculated check node is obtained from the memory 3000, and the check node operation is performed according to the obtained iterative information to obtain participation. The confidence of all edges corresponding to the currently calculated check node, and updating all of the memory corresponding to the currently verified check node Confidence in the iterative information of the edge.
  • FIG. 11 shows a schematic diagram of an LDPC code decoder in accordance with an embodiment of the present application.
  • the LDPC code decoder includes a variable node calculation unit 1100, a check node calculation unit 1200, a memory 2000, and a controller 3000.
  • the controller further includes an addressing unit 3100 and a computing unit 3200.
  • Addressing unit 3100 can provide addressing for interaction between variable node computing unit 1100 and memory 2000.
  • the addressing unit 3100 may store a first mapping relationship between the traversal order of the variable node calculation unit for all variable nodes and the storage order of each side of the check matrix in the memory.
  • Addressing unit 3100 can also provide addressing for interaction between check node computing unit 1200 and memory 2000.
  • the addressing unit 3100 may also store a second mapping relationship between the traversal order of the check nodes calculation unit for all check nodes and the storage order of each side of the check matrix in the memory.
  • the calculation unit 3200 counts the traversal calculation of the variable node calculation unit 1100 to determine the current variable node calculation state.
  • the addressing unit 3100 determines the first current mapped address based on the current variable node calculation state.
  • the variable node calculation unit 1100 updates the iteration information in the memory according to the first current mapping address indicated by the addressing unit 3100. For example, the variable node calculation unit 1100 obtains the iteration information required to perform the current variable node operation from the memory 2000 according to the address indicated by the addressing unit 3100, and stores the variable node information obtained by the current variable node operation into the corresponding memory 2000. Address to update iteration information.
  • the calculation unit 3200 After the variable node calculation unit 1100 traverses the variable node operations of all the variable nodes in the check matrix of the LDPC code, the calculation unit 3200 counts the traversal calculation of the check node calculation unit to determine the current check node calculation state.
  • the addressing unit 3100 determines a second current mapped address according to the current check node calculation state.
  • the check node calculation unit 1200 updates the iteration information in the memory according to the second current mapped address indicated by the addressing unit 3100. For example, the check node calculation unit 1200 obtains the iteration information required to perform the current check node operation from the memory 2000 according to the address indicated by the address unit 3100, and stores the check node information obtained by the current check node operation.
  • the corresponding address of the memory 2000 is to update the iteration information.
  • the controller 3000 can determine whether the checksum corresponding to each check node is zero, if it is zero, the decoding is successful; if not, the controller controls the execution.
  • One-time decoding iteration operation if the number of iterations reaches the maximum number of iterations, it means The decoding failed.
  • the checksum corresponding to the check node is the sum of the hard decision of each side of the check node and the non-zero element of the position corresponding to each side in the check matrix.
  • the check matrix of the LDPC code generally includes a plurality of cyclic matrices and a plurality of zero matrices.
  • FIG. 12 shows a schematic diagram of a check matrix of an LDPC code including a plurality of cyclic matrices.
  • the addressing unit 3100 can store only one mapping address for the interaction between the variable node computing unit 1100 and the memory 2000, that is, the variable node computing unit 1100 can implement the entire circular matrix stored in the memory 2000. Update of the iteration information for all sides. Similarly, for each of the cyclic matrices, the addressing unit 3100 can store only one mapping address only for the interaction between the check node computing unit 1200 and the memory 2000, that is, the check node computing unit 1200 can store the entire memory in the memory 2000. Update of the iteration information of all edges of the cyclic matrix. This further saves hardware resources and reduces costs.
  • the addressing unit 3100 for each of the cyclic matrices, iterative information of each side of the cyclic matrix is sequentially stored in the memory 2000.
  • the addressing unit 3100 only the first mapping address of the edge in the memory 2000 corresponding to any one of the variable nodes in the circular matrix may be stored, for example, only the edge in the memory corresponding to the first variable node in the circular matrix is stored.
  • the first mapped address The first mapping address of the other variable nodes in the circular matrix and the corresponding edges in the memory can be directly generated according to the cyclic rules in the cyclic matrix.
  • the addressing unit 3100 only the second mapping address of the edge in the memory 2000 corresponding to any one of the check nodes may be stored, for example, only the first check node in the circular matrix is stored.
  • the second mapped address of the edge in the memory The second mapping address of the other check nodes in the circular matrix and the corresponding edges in the memory can be directly generated according to the loop rules in the cyclic matrix. For example, it may be determined based on a known second mapping address, an offset of other check nodes relative to a known check node, and/or an offset of the cyclic matrix.
  • variable node calculation unit 1100 checks the traversal calculation order of the variable nodes of all the cyclic matrices in the check matrix of the LDPC code and the check of the LDPC code in the memory 2000
  • the storage order of the iterative information of the edges of all the cyclic matrices in the matrix is the same, the addressing unit 3100 may not store the interactive mapping address between the variable node computing unit 1100 and the memory 2000, as long as the variable node calculates according to the count of the controller 3000.
  • the self-incremental addressing between the unit 1100 and the memory 2000 is sufficient.
  • the addressing unit 3100 may not store the interaction mapping address between the check node computing unit 1200 and the memory 2000, as long as the check node computing unit 1200 and the memory 2000 are self-determined according to the count of the controller 3000. Add addressing.
  • the decoder of the present application it is particularly suitable for the field where the receiver side is strict in resource consumption and the throughput is not high, such as the field of satellite navigation.
  • the following takes the LDPC code of the GPS system as an example to explain the working process of the decoder in detail.
  • a (1200, 600) LDPC code having a cyclic matrix size of 60x60 in the GPS system is considered.
  • Fig. 13 shows a basic matrix corresponding to the check matrix of the LDPC code of the schematic GPS system.
  • Each number in the base matrix represents a 60x60 submatrix in the check matrix, including the all zero matrix and the corrupt block.
  • the number "-1" represents the all-zero matrix
  • the other numbers represent the cyclic matrix
  • the size of the number represents the offset of the cyclic matrix.
  • the number "0" represents no offset, that is, the unit matrix
  • the number "16” represents a matrix obtained by shifting the unit array cycle by 16 bits to the right.
  • FIG. 14 shows a Tanner graph corresponding to the LDPC code shown in FIG.
  • Each of the squares represents a set of 60 check nodes, each of which represents a group of 60 variable nodes, each of which represents a block edge.
  • FIG. 15 shows a variable node, a check node, and a corresponding edge connection relationship corresponding to one block edge in FIG. 14.
  • the block edge connecting the variable node group 1 and the check node group 2 is taken as an example, corresponding to 16 of the first row of the second row in the basic matrix.
  • variable node computing unit 1100 is implemented by VNU
  • check node computing unit 1200 is implemented by CNU
  • memory 2000 is implemented by RAM.
  • Each memory address in the RAM corresponds to a non-zero element in the check matrix of the LDPC code, that is, one side in FIG.
  • the storage order of the iteration information of the check matrix of the LDPC code of the RAM is in the order of grouping position (for example, column order) of the corresponding sub-matrix (circular matrix) in each matrix in the check matrix, and the order of the packet port (for example, each The row order of a column), the edge of the strip is stored within the group within the loop matrix (eg, the order of the columns in the group).
  • the computing unit of the controller can count the operations of the VNU or CNU, and obtain the number of packets unitnum where the edge of the current operation is located, the groupnum in the group in the group, and the current input and output port number portnum.
  • the total non-zero row number Max_port_V of each column in the base matrix can also be recorded in the calculation unit or the addressing unit of the controller, and the record The total number of non-zero columns Max_port_C for each row in the base matrix.
  • the number of packets unitnum represents the column order of the corresponding circular matrix of the edge corresponding to the variable node calculated by the current variable node, and the input and output ports.
  • the port number represents the row order of the corresponding loop matrix of the strip in the base matrix in this column, and the group position in the group indicates the position of the column in the loop matrix.
  • the group number unitnum represents the row order of the corresponding circular matrix of the edge corresponding to the variable node calculated by the current variable node, and the input and output port number portnum indicates that the edge is The order of the corresponding cyclic matrix in the base matrix in this row, the group position in the group represents the row position of the edge in the circular matrix.
  • the mapping unit records the mapping relationship between the storage address grp_addr in the RAM and the packet number unitnum, the port number portnum, and the intra-group location groupnum.
  • the addressing unit may store a mapping table between the address grp_addr and the VNU (unitnum, portnum, groupnum), and store a mapping table between the storage address grp_addr and the CNU (unitnum, portnum, groupnum).
  • mapping unit may store a mapping table between the address grp_addr and the VNU (unitnum, portnum), and store a mapping table between the storage address grp_addr and the CNU (unitnum, portnum).
  • the initialization is first performed, that is, 1200 (the number of columns of the LDPC code check matrix) initial LLR values are sequentially written into the RAM.
  • the VNU reads the first initial LLR value from the input buffer and makes a hard decision.
  • the calculation unit starts counting, and the group position in the group is updated according to the count status. It can be understood that each update of the group position in the group corresponds to the VNU writing to an initial LLR value (or a calculation process of the VNU during iterative calculation), during the writing of an initial LLR value (or a VNU calculation process).
  • the controller increases the port number portnum from "1" to the corresponding Max_port_V.
  • the addressing unit finds the corresponding addressing address according to the packet number unitnum and the port number portnum, and the stored first mapping relationship.
  • the write address of the VNU can be obtained by combining the addressed address indicated by the addressing unit with the intra-group location groupnum indicated by the computing unit.
  • the VNU writes the first hard decision and the initial LLR value to the corresponding write address in RAM. Subsequently, the VNU sequentially writes the RAM to the RAM based on the initial LLR value.
  • the calculation unit counts the number of initial writes, and according to the count state, increments the group position in the group by one, until 60 (equal to the size of the loop matrix), then returns to zero, and the number of units unitnum is increased by 1, until 20 (the number of columns of the basic matrix) ).
  • Figure 16 shows a timing diagram of the VNU successive traversal operation. As shown, the VNU will perform 1200 operations.
  • the above initialization process is performed by the VNU sequentially reading the initial LLR value from the input buffer, performing a hard decision according to the initial LLR value, and sequentially saving the hard decision and the LLR value to the corresponding storage unit in the RAM. If the initial value in RAM is zero before initialization, the VNU can also be initialized by a variable node traversal operation.
  • the VNU can be connected to the addressing unit to read and write RAM according to the address indicated by the addressing unit; the VNU can also be connected to the RAM without being connected to the addressing unit, and the addressing unit is only used to generate the read and write address of the RAM.
  • the check node operation is performed.
  • the input information required for the check node operation is serially read from the RAM according to the control of the controller, and the operation result is written to the corresponding position in the RAM according to the control of the controller.
  • the calculation unit counts the traversal operation of the CNU, and updates the position groupnum in the group according to the count state. It can be understood that each update of the group position in the group corresponds to a calculation process of the CNU. During a CNU calculation process, the controller increases the port number portnum from "1" to the corresponding Max_port_C. In addition, since the cyclic matrix has the offset off_addr, the initial value of groupnum is the offset off_addr, during the counting process, if If groupnum is greater than 60, the group position in the group is updated to groupnum minus 60 until the count of the calculation unit reaches 60, groupnum returns to the initial value, and the number of units is increased by 1.
  • the computing unit outputs the packet number unitnum and the port number portnum to the addressing unit, and the addressing unit finds the corresponding addressing address according to the stored control node-edge mapping relationship.
  • the CNU read and write address can be obtained by combining the addressed address indicated by the addressing unit with the intra-group location groupnum indicated by the computing unit.
  • the CNU can sequentially read the edge corresponding to each control node from the RAM according to the control of the controller (ie, the corresponding port number portnum is from "1" to The LLR value and the hard decision of Max_port_C) calculate the minimum and minimum values of the input LLR values of all the edges corresponding to each control node. The second smallest value is written to the address whose input is the minimum value, and the other address is written to the minimum value. It then traverses each control node.
  • Figure 17 shows a timing diagram of the CNU successive traversal operation. As shown, the CNU will perform 600 operations.
  • the CNU can sequentially read the edge corresponding to each control node from the RAM according to the control of the controller (ie, the corresponding port number portnum is from "1" to Iteration information for Max_port_C).
  • the iterative information may include, for example, vector information consisting of a plurality of code character numbers and corresponding plurality of confidence levels.
  • the operation of inputting data between multiple ports of the check node of the multi-ary code is a multiple convolution sort operation, that is, the new vector information obtained by the convolution sort operation of the two iterative vector information and other iterative information vectors continue. Perform a convolution sort operation.
  • the CNU of the serial structure can be designed. By allocating at least Max_port buffer space internally by the CNU, a CNU calculation can be realized in the case where the number of input ports is not fixed, wherein the number of Max_ports is Equal to the maximum of the maximum number of columns Max_port_C for all rows.
  • Max_port+1 cache space can be allocated inside the CNU.
  • the CNU can have four buffer spaces internally.
  • the iterative vector information of the three ports is serially read and cached into three different buffer spaces, and then the first port and the second port are calculated.
  • the convolutional sorting result between the input iterative vector information is saved to the fourth buffer space.
  • the result of the convolutional sort operation between the iterative vector information input by the first port and the third port is calculated and saved in the first buffer space.
  • Finally calculate the second port and The result of the convolutional sorting operation between the iterative vector information input by the third port is saved in the second buffer space, that is, the calculation of all output iterative vector information of all ports is completed.
  • the CNU may have five buffer spaces internally.
  • the newly added cache space is idle, and all the output iterative vector information of all three ports is still completed in the foregoing order.
  • the input iteration vector information of the fourth port is buffered into the newly added cache space, and the operation between the input vector information of the first three ports is first completed according to the foregoing sequence. Then calculating a convolution sorting operation between the iterative vector information of the third port input and the vector information obtained by the first port and the second port in the first buffer space, and saving the result to the third buffer space.
  • the convolution sorting operation result between the input iteration vector information of the fourth port and the vector information in the first, second, and fourth buffer spaces is calculated in turn, and saved back to the first, second, and fourth buffer spaces, that is, completed.
  • the calculation of the iterative vector information for all four ports is output.
  • the CNU internally can only allocate Max_port cache spaces to complete the intermediate vector information and output the iterative vector information.
  • the cache is fine.
  • the controller adds all the hard decisions to determine whether the checksum is zero. If the checksum is zero, the decoding is completed; if the checksum is not zero, it is necessary to continue iterating for the variable node operation.
  • the checksum is the sum of the product of the hard decision of each side of the check node and the non-zero element of the position of the check matrix corresponding to each side. For multi-ary LDPC codes, you also need to record the value of non-zero elements.
  • the operation mode of the LDPC code is binary code and multi-ary code.
  • the VNU reads the initial LLR value from the input buffer and reads the LLR value of the first port from the RAM, adds them and saves the first port input inside the VNU.
  • the LLR value then read in and accumulate the LLR values of other ports in turn, to get LLR_total.
  • the VNU also caches the LLR value entered on each port.
  • a hard decision is made on LLR_total, and the hard decision and the difference between the LLR_total and the input value of the corresponding port are output to each port and stored in the RAM.
  • variable node and check node update process continue to iterate the variable node and check node update process until the decoding succeeds or reaches the preset maximum number of iterations.
  • the mapping relationship recorded in the addressing unit may not be in the form of a mapping table, but directly calculated or spliced by the unitnum, portnum, and groupnum given by the computing unit. VNU traversal address. If the storage order of the RAM is consistent with the traversal calculation order of the CNU, the mapping relationship recorded in the addressing unit may not be in the form of a mapping table, but directly calculated or spliced by unitnum, portnum, and groupnum given by the computing unit to obtain CNU traversal. address. This can further save hardware resources.
  • an LDPC code decoder includes a variable node calculation unit and a check node calculation unit in accordance with an embodiment of the present application
  • the LDPC code decoder is The method may further include a plurality of variable node calculation units and a plurality of check node calculation units, and the controller may control, in a similar manner, the plurality of variable node calculation units to traverse the variable node information of all the variable nodes, and obtain the variable nodes according to the calculation.
  • the information updates the iteration information of the memory, and controls the plurality of check node calculation units to traverse the check node information of all the check nodes, and updates the iteration information of the memory according to the calculation result of the check node obtained by the calculation.
  • all variable node information is traversed by a variable node operator
  • all check node information is traversed by a check node operator to implement an iterative decoding process of the LDPC code decoder, according to the present application.
  • the decoder may also include only one node operation unit, and the node operator traverses all variable node information and all check node information to implement an iterative decoding process of the hierarchical structure.
  • FIG. 18 shows a schematic diagram of an LDPC code decoder in accordance with an embodiment of the present application.
  • the LDPC code decoder includes a node computing unit 1000, a first memory 2100, a second memory 2200, and a controller 3000.
  • the first memory 2100 stores iterative information of the variable nodes of the check matrix of the LDPC code. For example, the total confidence LLR_total of each variable node of the check matrix of the LDPC code is stored.
  • the second memory 2200 stores iterative information of each side of the check matrix of the LDPC code. For example, the code character number and confidence of each side of the check matrix of the LDPC code are stored.
  • the controller 3000 the control node calculation unit performs a decoding iterative operation until the end of the decoding, wherein in each decoding iteration operation, the controller controls the node calculation unit to traverse all the variable nodes according to the check node order Information and all check node information, and updating iteration information in the first memory and the second memory according to the variable node information and the check node information.
  • the controller 3000 may also include an addressing unit 3100 and a computing unit 3200.
  • the addressing unit 3100 stores a first mapping relationship between the check node and the variable node, and stores a second mapping between the traversal order of the check nodes for all check nodes and the storage order of each side of the check matrix in the memory. relationship.
  • the calculating unit 3200 counts the calculation of the node calculating unit 1000, and controls the addressing unit to indicate the address of the storage unit corresponding to the current calculation according to the counting state, and controls the verification of the current operation obtained by the node calculating unit according to the indicated address.
  • the first memory and the second memory are updated by the total confidence of the variable nodes corresponding to the node and the code character number and confidence of each side corresponding to the check node of the current operation.
  • the addressing unit 310 may store only one mapped address for the interaction between the variable node computing unit and the first memory and the second memory, thereby further saving hardware resources. cut costs. For each cyclic matrix, iterative information for each edge of the circular matrix is stored sequentially in memory.
  • the addressing unit 3100 stores only the first mapping address of the variable node in the memory corresponding to any one of the check nodes in the loop matrix, and stores only the edges in the memory corresponding to any one of the check nodes in the loop matrix. The second mapped address.
  • mapping addresses of the other check nodes in the circular matrix and the corresponding edges in the first memory are determined according to the first mapping address, the position of the other check nodes relative to the one of the check nodes, and/or the offset of the circular matrix.
  • the mapping addresses of the other variable nodes in the circular matrix and the corresponding edges in the second memory are determined according to the second mapping address, the position of the other variable node relative to the variable node and/or the offset of the circular matrix.
  • Embodiments in accordance with the present application may be implemented in the form of hardware, software, or a combination thereof.
  • One aspect of the present application provides a computer program comprising LDPC code encoder and decoder executable instructions for implementing an embodiment in accordance with the present application.
  • such computer programs can It is stored in any form of memory, such as an optical or magnetically readable medium, chip, ROM, PROM, or other volatile or non-volatile device.
  • a machine readable memory storing such a computer program is provided.

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Abstract

一种LDPC码译码器，包括：一个变量节点计算单元（1100）；一个校验节点计算单元（1200）；存储器（2000），存储LDPC码的校验矩阵的每条边的迭代信息；控制器（3000），控制节点计算单元执行译码迭代运算，直到译码结束，其中，在每一次译码迭代运算中，所述控制器（3000）控制所述变量节点计算单元（1100）遍历计算所有变量节点的变量节点信息，并根据计算获得的变量节点信息更新存储器（2000）的迭代信息，以及所述控制器（3000）控制所述校验节点计算单元（1200）遍历计算所有校验节点的校验节点信息，并根据计算获得的校验节点的运算结果更新存储器（2000）的迭代信息。

Description

LDPC码编码器和译码器 技术领域
本申请涉及一种数据处理装置，具体地，涉及一种LDPC码编码器和译码器。
背景技术
伴随着通信技术的飞速发展以及各种传输方式对信息可靠性要求的不断提高，差错控制编码技术作为抗干扰技术的一种重要手段，在数字通信领域和数字传输系统中显示出越来越重要的作用。
低密度奇偶校验(low-density parity check，LDPC)码是一类译码性能接近信道极限的线性分组码。由于其优异的纠错性能，二进制LDPC码已经被广泛地应用于各种通信、导航和数字存储系统。多进制LDPC码也已成为未来这些系统中纠错编码方案的有利竞争者。
但是，目前现有技术中实现LDPC码的编码器或者译码器大多数采用的是全并行结构，以全并行结构的编码器为例，假设待编码数据为c＝(c0，c1…ck-1)，生成矩阵为Gk×n，它们的乘积结果则为最终编码序列，因此，所谓全并行结构编码器指的是：该编码器具有n个数据处理模块，每个数据处理模块用来计算c＝(c0，c1…ck-1)与Gk×n中的一列的乘积，然而这种全并行结构造成大量硬件资源的消耗。
发明内容
本申请实施方式提供一种数据处理装置，从而达到降低硬件资源消耗的目的。
根据本申请的一个方面，本申请实施方式提供一种数据处理装置，包括：m个数据处理模块，用于按照计算顺序在第i个周期处理Ni个数据或者操作；其中
Figure PCTCN2016070865-appb-000001
且m＜n，m、n和Ni均为正整数，
Figure PCTCN2016070865-appb-000002
通过m个数据处理模块在时间上的复用，从而达到对n个数据或者操作的处理，从而降低了对硬件资源的消耗。
根据本申请的另一个方面，本申请实施方式提供了一种LDPC码译 码器，包括：一个变量节点计算单元；一个校验节点计算单元；存储器，存储LDPC码的校验矩阵的每条边的迭代信息；控制器，控制节点计算单元执行译码迭代运算，直到译码结束，其中，在每一次译码迭代运算中，所述控制器控制所述变量节点计算单元遍历计算所有变量节点的变量节点信息，并根据计算获得的变量节点信息更新存储器的迭代信息，以及所述控制器控制所述校验节点计算单元遍历计算所有校验节点的校验节点信息，并根据计算获得的校验节点的运算结果更新存储器的迭代信息。
根据本申请的另一个方面，本申请实施方式提供了一种LDPC码译码器，包括：多个变量节点计算单元；多个校验节点计算单元；存储器，存储LDPC码的校验矩阵的每条边的迭代信息；控制器，控制节点计算单元执行译码迭代运算，直到译码结束，其中，在每一次译码迭代运算中，所述控制器控制所述多个变量节点计算单元遍历计算所有变量节点的变量节点信息，并根据计算获得的变量节点信息更新存储器的迭代信息，以及所述控制器控制所述多个校验节点计算单元遍历计算所有校验节点的校验节点信息，并根据计算获得的校验节点的运算结果更新存储器的迭代信息。
根据本申请的另一个方面，本申请实施方式提供了一种LDPC码译码器，包括：一个节点计算单元；第一存储器，存储LDPC码的校验矩阵的变量节点的迭代信息；第二存储器，存储LDPC码的校验矩阵的每条边的迭代信息；控制器，控制节点计算单元执行译码迭代运算，直到译码结束，其中，在每一次译码迭代运算中，所述控制器控制所述节点计算单元遍历计算所有变量节点信息和所有校验节点信息，并根据所述变量节点信息和所述校验节点信息更新第一存储器和第二存储器中的迭代信息。
根据本申请的另一个方面，本申请实施方式提供了一种LDPC码译码方法，包括：存储LDPC码的校验矩阵的每条边的迭代信息；执行译码迭代运算，直到译码结束，其中，在每一次译码迭代运算中，逐次遍历计算所有变量节点的变量节点信息，并相应更新存储的迭代信息，以及逐次遍历计算所有校验节点的校验节点信息，并相应更新存储的迭代信 息。
附图说明
图1为现有技术提供的一种全并行结构的编码器的示意图；
图2为根据本申请的一种实施方式的数据处理装置的示意图；
图3为根据本申请的一种实施方式的数据处理装置的示意图；
图4为根据本申请的一种实施方式的数据处理装置的示意图；
图5为根据本申请的一种实施方式的数据处理装置的结构示意图；
图6为生成矩阵为稀疏矩阵的示意图；
图7为生成矩阵为的子矩阵为循环矩阵的示意图；
图8示出了一种示意的LDPC码的校验矩阵。
图9示出了图8所示的校验矩阵的Tanner图。
图10示出了根据本申请的一种实施方式的LDPC码译码器的示意图；
图11为根据本申请的一种实施方式的LDPC码译码器的示意图；
图12示出了包括多个循环矩阵的LDPC码的校验矩阵的示意图；
图13示出了示意的GPS系统的LDPC码的校验矩阵对应的基础矩阵；
图14示出了图13所示的LDPC码对应的Tanner图；
图15示出了图14中一个块边所对应的变量节点、校验节点、以及相应的边连接关系；
图16示出了变量节点计算单元逐次遍历运算的时序图；
图17示出了校验节点计算单元逐次遍历运算的时序图；以及
图18为根据本申请的一种实施方式的LDPC码译码器的示意图；
具体实施方式
下面参照附图对本申请公开的LDPC码编码器和译码器进行详细说明。为简明起见，本申请各实施方式的说明中，相同或类似的装置使用了相同或相似的附图标记。
在LDPC编码过程中，假设待编码数据为c＝(c0，c1…ck-1)，生成矩阵 为Gk×n，它们的乘积结果则为最终编码序列，因此编码器需要计算c＝(c0，c1…ck-1)与Gk×n每一列的乘积。图1为现有技术提供的一种全并行结构的编码器的示意图。如图1所示，该编码器包括n个数据处理模块，每个数据处理模块用来计算c＝(c0，c1…ck-1)与Gk×n中的一列的乘积，即每一个数据处理模块输出最终编码序列的一个码字符号，因此在一个运算周期内，n个数据处理模块将输出全部码字。这种全并行结构的编码器会造成硬件资源的浪费，为了解决这一技术问题，本申请提供了一种数据处理装置。
图2为根据本申请的一种实施方式的数据处理装置的示意图。该数据处理装置可以应用于LDPC编码或者译码的场景，其中该装置可以为LDPC码编码器，或者LDPC码译码器。如图2所示，该数据处理装置包括：m个数据处理模块201，用于按照计算顺序在第i个周期处理Ni个数据或者操作；其中
Figure PCTCN2016070865-appb-000003
且m＜n，m、n和Ni均为正整数，
Figure PCTCN2016070865-appb-000004
具体地，比如：由于计算c＝(c0，c1…ck-1)与Gk×n相乘的计算顺序为：c＝(c0，c1…ck-1)分别与Gk×n的第一列至第n列相乘，本实施方式中的数据处理装置具有m个数据处理模块201，并且m＜n，因此，在第一个周期，可以分别计算c＝(c0，c1…ck-1)与Gk×n的第一列至第m列相乘，输出m个码字，该例子中，第一个周期中的Ni即为m；在第二个周期，可以分别计算c＝(c0，c1…ck-1)与Gk×n的第m+1列至第2m列，为了充分利用已有的硬件资源，在每一个周期尽可能的使每一个数据处理模块201处理一个数据或者操作。进一步地，在第i个周期处理Ni个数据或者操作，这里的Ni个操作可以理解为Ni个相乘操作，这里的Ni个数据可以理解为Ni个具体数字，也可以是Ni个向量、矩阵等。本申请实施方式对此不做限制。
进一步地，该数据处理装置还包括用于存储长度为k的待编码数据c＝(c0，c1…ck-1)的存储模块，以及用于存储长度为k的生成矩阵Gk×n的每一列的存储模块。由于每一列都是按照先后顺序与c＝(c0，c1…ck-1)相乘，因此用于存储每一列的存储模块可以实现复用的效果。
更进一步地，该数据处理装置还包括乘法器和加法器，使用k个乘法 器用来完成待编码数据c＝(c0，c1…ck-1)的各个元素与生成矩阵的对应元素乘法运算，使用k-1个加法器用来计算上述乘积之和，通过乘法器和加法器的作用则可以生成一个码字符号。
本申请实施方式提供了一种数据处理装置，其中该装置包括：m个数据处理模块，用于按照计算顺序在第i个周期处理Ni个数据或者操作；其中
Figure PCTCN2016070865-appb-000005
且m＜n，m、n和Ni均为正整数，
Figure PCTCN2016070865-appb-000006
通过m个数据处理模块在时间上的复用，从而达到对n个数据或者操作的处理，从而降低了对硬件资源的消耗。
图3为根据本申请的一种实施方式的数据处理装置的示意图，该装置具体可以为LDPC编码器，其中该编码器包括m个数据处理模块，所述m个数据处理模块具体用于：在低密度奇偶校验LDPC编码过程中，分别计算待编码数据c＝(c0，c1…ck-1)与生成矩阵Gk×n中每一列相乘，其中k表示所述待编码数据的长度；n表示所述生成矩阵Gk×n的列数，在第i个周期计算c＝(c0，c1…ck-1)与生成矩阵Gk×n中的Ni个列相乘，其中在前
Figure PCTCN2016070865-appb-000007
个周期，所述Ni＝m，
Figure PCTCN2016070865-appb-000008
若n不能被m整除，则在第
Figure PCTCN2016070865-appb-000009
个周期，所述Ni＝n mod m，
Figure PCTCN2016070865-appb-000010
由于该数据处理装置包括m个数据处理模块，因此可以称该数据处理装置的并行度为m。
举个例子，假设m＝3，k＝3，n＝5，则在低密度奇偶校验LDPC编码过程中，在第1个周期，3个数据处理模块分别计算c＝(c0，c1，c2)与生成矩阵G3×5中的第1列、第2列和第3列相乘；在第2个周期，其中2个数据处理模块分别计算c＝(c0，c1，c2)与生成矩阵G3×5中的第4列和第5列相乘。
进一步地，该数据处理装置还包括用于存储长度为k的待编码数据c＝(c0，c1…ck-1)的存储模块，以及用于存储长度为k的生成矩阵Gk×n的每一列的存储模块。由于每一列都是按照先后顺序与c＝(c0，c1…ck-1)相乘，因此用于存储每一列的存储模块可以实现复用的效果。
更进一步地，该数据处理装置还包括乘法器和加法器，使用k个乘法器用来完成待编码数据c＝(c0，c1…ck-1)的各个元素与生成矩阵的对应元素乘法运算，使用k-1个加法器用来计算上述乘积之和，通过乘法器和加法器的作用则可以生成一个码字符号。
本申请实施方式提供了一种数据处理装置，该装置包括m个数据处理模块，所述m个数据处理模块具体用于：在低密度奇偶校验LDPC编码过程中，分别计算待编码数据c＝(c0，c1…ck-1)与生成矩阵Gk×n中每一列相乘，其中k表示所述待编码数据的长度，n表示所述生成矩阵Gk×n的列数，在第i个周期计算c＝(c0，c1…ck-1)与生成矩阵Gk×n中的Ni个列相乘，其中在前
Figure PCTCN2016070865-appb-000011
个周期，所述Ni＝m，
Figure PCTCN2016070865-appb-000012
若n不能被m整除，则在第
Figure PCTCN2016070865-appb-000013
个周期，所述Ni＝n mod m，
Figure PCTCN2016070865-appb-000014
因而实现了数据处理模块在时间上的复用，进而降低了对硬件资源的消耗。
图4为根据本申请的一种实施方式的数据处理装置的示意图。在本实施方式中，基于分块的思想，将对生成矩阵Gk×n中每一列进行分块。数据处理装置中的数据处理模块包括：第一存储单元401和第二存储单元402；其中，数据处理模块用于将所述生成矩阵Gk×n的每一列分为P个第一数据块；其中P≥2。如图4所示，第一存储单元401用于存储一个第一数据块；第二存储单元402用于存储第一数据块对应的待编码数据的第二数据块；图4所示的第一存储单元401此时存储长度为d的第一数据块，第二存储单元402此时存储长度为d的第二数据块，当然，该数据处理模块还包括乘法器、加法器和累加器，m个数据处理模块具体用于：在低密度奇偶校验LDPC编码过程中，根据分块结果，在第i个周期计算Ni个第二数据块与对应的Ni个第一数据块相乘，其中在前
Figure PCTCN2016070865-appb-000015
个周期，所述Ni＝m，
Figure PCTCN2016070865-appb-000016
若n不能被m整除，则在第
Figure PCTCN2016070865-appb-000017
个周期至第
Figure PCTCN2016070865-appb-000018
个周期，所述Ni＝n mod m，
Figure PCTCN2016070865-appb-000019
具体地，第一存储单元相对于每一个第一数据块都可以实现复用，第二存储单元相对于第二数据块也可以实现复用，即不需要开辟多余的存储空间，所有的第一数据块按照时间顺序使用一个第一存储单元即可，所有的第二数据块按照时间顺序使用一个第二存储单元即可。
举个例子：假设m＝3，k＝3，n＝5，P＝2，即生成矩阵G3×5每一列被分成了2个第一数据块，针对每一列，从上至下的顺序，第一个元素构成一个第一数据块，第二个元素和第三个元素构成一个第一数据块，因此，生成矩阵G3×5实际包括了10个第一数据块，相应地，待编码数据c＝(c0，c1，c2)也被分为2个第二数据块，从左至右，第一个元素c0构成一个第二数据块，第二个元素c1和第三个元素c2构成一个第二数据块，则在低密度奇偶校验LDPC编码过程中，按照计算顺序，即在第1个周期，3个数据处理模块分别计算c＝(c0，c1，c2)的第一个元素构成的第二数据块与生成矩阵G3×5中由第一列第一个元素构成的第一数据块的乘积，c＝(c0，c1，c2)的第一个元素构成的第二数据块与生成矩阵G3×5中由第二列第一个元素构成的第一数据块的乘积，c＝(c0，c1，c2)的第一个元素构成的第二数据块与生成矩阵G3×5中由第三列第一个元素构成的第一数据块的乘积；在第2个周期，3个数据处理模块分别计算c＝(c0，c1，c2)的第二个元素和第三个元素构成的第二数据块与生成矩阵G3×5中由第一列第二个元素和第三个元素构成的第一数据块的乘积，c＝(c0，c1，c2)的第二个元素和第三个元素构成的第二数据块与生成矩阵G3×5中由第二列第二个元素和第三个元素构成的第一数据块的乘积，c＝(c0，c1，c2)的第二个元素和第三个元素构成的第二数据块与生成矩阵G3×5中由第三列第二个元素和第三个元素构成的第一数据块的乘积，并将计算结果分别与第1个周期中的计算结果累加，以此类推。因而实现数据处理模块的复用。
根据一种实施方式，数据处理装置的数据处理模块包括：第一存储单元和第二存储单元；数据处理模块用于将所述生成矩阵Gk×n的每一列分为P个第一数据块；第一存储单元用于存储一个第一数据块；第二存储单元用于存储第一数据块对应的所述待编码数据的第二数据块；m个数据 处理模块，具体用于：在低密度奇偶校验LDPC编码过程中，根据分块结果，在第i个周期计算Ni个第二数据块与对应的Ni个第一数据块相乘，其中在前
Figure PCTCN2016070865-appb-000020
个周期，所述Ni＝m，
Figure PCTCN2016070865-appb-000021
若n不能被m整除，则在第
Figure PCTCN2016070865-appb-000022
个周期至第
Figure PCTCN2016070865-appb-000023
个周期，所述Ni＝n mod m，
Figure PCTCN2016070865-appb-000024
从而提高数据处理模块、以及该模块中的第一存储单元和第二存储单元的利用效率，降低了每个数据处理模块上的计算复杂度。
根据一种实施方式，数据处理装置基于校验矩阵获取最终编码序列的思想实现存储空间的复用。具体地，通过校验矩阵获取最终编码序列的具体方法为：假设待编码数据为M＝(m0，m1…mk-1)，校验矩阵为Hl×n，校验符号为p1，p2…pn-k，则
Figure PCTCN2016070865-appb-000025
假设校验矩阵为Hl×n＝(QI)，其中Q为(n-k)×k的矩阵，对应M，I为(n-k)×(n-k)的矩阵，对应已编码数据的冗余位，当I为准双对角矩阵，即该I除对角线上的元素，以及对角线上方或上方元素之外的元素均为0时，该矩阵就为准双对角矩阵。基于
Figure PCTCN2016070865-appb-000026
第一个冗余位p1可以直接由待编码数据中的元素计算得到，第二个冗余位p2可以由第一个冗余位p1和待编码数据中的元素共同计算得到，以此类推，pn-k可以由pn-k-1和待编码数据中的元素共同计算得到。因此，可以首先从存储(M，p1，p2…pn-k)的存储模块中读出校验矩阵中第一行第一个非零元素对应的(M，p1，p2…pn-k)中的信息位，从存储校验矩阵的存储模块中读出该非零元素，然后将它们相乘，存入累加器中，接着从存储(M，p1，p2…pn-k)的存储模块中读出校验矩阵中第一行第二个非零元素对应的(M，p1，p2…pn-k)中的信息位，从存储校验矩阵的存储模块中读出该非零元素，然后将它们相乘，结果与累加器中的结果相加，以此类推，直到计算出第一个校验位，将累加器中的结果存入存储(M，p1，p2…pn-k)的存储模块中。最后，清空累加器，重复上述步骤，直到所有冗余位计算完毕。上述过程根据计算时间的先后顺序实现了存储空间的复用。
图5为根据本申请的一种实施方式的数据处理装置的结构示意图。在上述实施方式的基础之上，该数据处理装置除了包括m个数据处理模块501之外，还包括第一存储模块502，该第一存储模块502用于存储生成矩阵。
具体地，第一存储模块502具体用于：
(1)若生成矩阵为稀疏矩阵，则第一存储模块仅存储生成矩阵的非零元素和非零元素对应的位置坐标。
具体地，矩阵中非零元素的个数远远小于矩阵元素的总数，则称该矩阵为稀疏矩阵，因此，第一存储模块仅存储生成矩阵的非零元素和非零元素对应的位置坐标。进一步地，当本申请采用的是二进制LDPC编码，则生成矩阵中的非零元素只是1，因此，第一存储模块中可以仅存储非零元素1对应的位置坐标即可。
(2)若所述生成矩阵的子矩阵为循环矩阵，则所述第一存储模块仅存储所述循环矩阵中所有的非零元素、以及其中一列非零元素对应的位置坐标和相邻两列的循环偏移量。
具体地，若所述生成矩阵的子矩阵为循环矩阵，则成该生成矩阵为准循环矩阵，比如生成矩阵
Figure PCTCN2016070865-appb-000027
其中Gij为循环矩阵，(i＝1，2…s；j＝1，2…r)，基于循环矩阵具有的特点，则第一存储模块仅存储循环矩阵中所有的非零元素、以及其中一列非零元素对应的位置坐标和相邻两列的循环偏移量。比如：q×q的循环矩阵
Figure PCTCN2016070865-appb-000028
则第一存储模块可以只存储q个非零元素，然后存储第一列非零元素g0的位置、以及相邻两列的循环偏移量1，这样其他列的非零元素则可以 通过第一列非零元素的位置和循环偏移量推导得到。进一步地，当本申请采用的是二进制LDPC编码，则生成矩阵中的非零元素只是1，因此，第一存储模块中可以仅存储非零元素1对应的位置和循环偏移量即可。
本实施方式提供一种数据处理装置，该装置还包括第一存储模块，用于存储生成矩阵。其中若生成矩阵为稀疏矩阵，则第一存储模块仅存储生成矩阵的非零元素和非零元素对应的位置坐标；若生成矩阵的子矩阵为循环矩阵，则第一存储模块仅存储所述循环矩阵中所有的非零元素、以及其中一列非零元素对应的位置坐标和相邻两列的循环偏移量，从而实现第一存储模块的复用效果。进而降低对硬件资源的消耗。
图6为生成矩阵为稀疏矩阵的示意图。如图6所示，当m＝3，P＝4时，第一存储模块502中第一个地址存储的数据为：(1，3，0)，表示第一列块的第一行块中非零元素的位置，第一个数据处理模块根据1将其第一存储单元401的第一位设为1，第二个数据处理模块根据3将其第一存储单元401的第三位设为1；第一存储模块502中第二个地址存储的数据为：(0，0，1)，表示第一列块的第二行块中非零元素的位置，第三个数据处理模块根据1将其第一存储单元401的第一位设为1......以此类推，共存12组数据即可完整表示整个生成矩阵，第一存储模块中只需对每个数据块记录非零元素的位置即可指导数据处理模块完成编码工作。而对于多进制LDPC码，则还需记录非零元素的数值。
图7为生成矩阵的子矩阵为循环矩阵的示意图。如图所示，当m＝3，P＝4时，第一存储模块502中第一个地址存储的数据为：(1，1，1)，表示第一个列块的第一个非零子矩阵位于第一个行块，第一列非零元素位于第一位，循环偏移量为1(当循环偏移量为固定值时也可不存储循环偏移量)，第一个数据处理模块将其第一存储单元401的第一位设为1，第二个数据处理模块将其第一存储单元401的第二位设为1，第三个数据处理模块将其第一存储单元401的第三位设为1；第一存储模块502中第二个地址存储的数据为：(4，3，1)，表示第一个列块的第二个非零子矩阵位于第四个行块，第一列非零元素位于第三位，循环偏移量为1，第一个数据处理模块将其第一存储单元401的第三位设为1，第二个数据处理模块将其第一存储单元401的第一位设为1，第三个数据处理模块将其第一 存储单元401的第二位设为1......以此类推，共需6组数据即可完整表示整个生成矩阵，第一存储模块中只需对每个数据块记录非零元素的位置即可指导数据处理模块完成编码工作。对于多进制LDPC码，则还需记录非零元素的数值。
根据本申请的另一个方面，还提供了一种LDPC码译码器和译码方法。本领域技术人员理解，译码器的结构相对复杂。根据本申请的译码器和译码方法中的译码算法可以采用迭代译码算法，例如置信传播算法、最小和算法、消息传递算法等。迭代译码算法是基于LDPC码的校验矩阵的Tanner图来实现的。图8示出了一种示意的LDPC码的校验矩阵。图9示出了图8所示的校验矩阵的Tanner图。其中，校验矩阵的列对应变量节点，校验矩阵的行对应校验节点，连接变量节点与校验节点之间的线对应校验矩阵中的非零元素，称之为边。译码过程可以视为迭代信息通过边在变量节点与校验节点之间的迭代过程。
下面结合附图详细说明根据本申请的实施方式的LDPC码译码器和译码方法。
图10示出了根据本申请的一种实施方式的LDPC码译码器的示意图。LDPC码译码器包括：一个变量节点计算单元1100，一个校验节点计算单元1200、存储器2000、以及控制器3000。变量节点计算单元1100存储LDPC码的校验矩阵的每条边的迭代信息。迭代信息例如可以包括与校验矩阵的每条边对应的码字符号和置信度。控制器3000控制节点计算单元执行译码迭代运算，直到译码结束。其中，在每一次译码迭代运算中，所述控制器控制变量节点计算单元1100遍历计算所有变量节点的变量节点信息，并根据计算获得的变量节点信息更新存储器的迭代信息。变量节点的变量节点信息例如可以包括该变量节点对应的各边的码字符号和置信度。控制器3000还控制校验节点计算单元1200遍历计算所有校验节点的校验节点信息，并根据计算获得的校验节点的运算结果更新存储器3000的迭代信息。校验节点的校验节点信息例如可以包括该校验节点对应的各边的置信度。
根据本申请的实施方式，仅需要一个变量节点计算单元和一个校验 节点计算单元，就可以串行实现整个迭代译码过程。并且变量节点计算单元和校验节点计算单元之间的输入输出端口并不直接连接，而是根据控制器的控制通过存储器连接。通过在时间上复用节点计算单元，极大地节省了硬件资源，降低了实现成本。
本领域技术人员可以理解，根据本申请的译码器既可以用于LDPC码为二进制的情况，也可以用于LDPC码为多进制码的情况。当LDPC码为二进制码时，迭代信息中码字符号例如可以是相应的硬判决，置信度例如可以是LLR值。当LDPC码为多进制码时，迭代信息可以包括校验矩阵的每条边对应的多个码字符号和相应的多个置信度。多个码字符号和相应的多个置信度可以采用向量信息的方式。当LDPC码为多进制码时，硬判决是指置信度最高的码字符号。在每一次译码迭代运算中，控制器3000控制变量节点计算单元遍历计算所有变量节点的变量节点信息(包括该变量节点对应的边的码字符号和置信度)，并根据计算获得的变量节点信息更新存储器的迭代信息。控制器3000控制校验节点计算单元遍历计算所有校验节点的校验节点信息(包括该校验节点对应的边的置信度)，并根据计算获得的校验节点的运算结果更新存储器的迭代信息。
根据一种实施方式，变量节点计算单元1100执行变量节点计算时，需要获得该变量节点所对应的初始置信度。初始置信度是指接收机从信道接收到的信号经接收机前端设备(例如解调器)解调后传递给译码器的输入信息。初始置信度可以存储在输入缓存(未示出)中。当变量节点计算单元1100执行当前变量节点计算时，查询参与当前计算的变量节点对应的初始置信度，并从存储器3000获得参与当前计算的变量节点对应的所有边的迭代信息，并根据所获得的初始置信度和迭代信息执行变量节点运算以获得参与当前计算的变量节点所对应的所有边的码字符号和置信度，并相应地更新存储器中与当前计算的变量节点对应的所有边的迭代信息中的码字符号和置信度。
当校验节点计算单元1200在执行当前校验节点计算时，从存储器3000获得参与当前计算的校验节点对应的所有边的迭代信息，并根据所获得的迭代信息执行校验节点运算以获得参与当前计算的校验节点对应的所有边的置信度，并更新存储器中与当前校验的校验节点对应的所有 边的迭代信息中的置信度。
图11示出了根据本申请的一种实施方式的LDPC码译码器的示意图。如图所示，LDPC码译码器包括一个变量节点计算单元1100、一个校验节点计算单元1200、存储器2000、以及控制器3000。控制器进一步包括寻址单元3100和计算单元3200。寻址单元3100可以为变量节点计算单元1100与存储器2000之间的交互提供寻址。例如，寻址单元3100可以存储变量节点计算单元对所有变量节点的遍历顺序与存储器中校验矩阵每条边的存储顺序之间的第一映射关系。寻址单元3100还可以为校验节点计算单元1200与存储器2000之间的交互提供寻址。例如，寻址单元3100还可以存储校验节点计算单元对所有校验节点的遍历顺序与存储器中校验矩阵每条边的存储顺序之间的第二映射关系。
计算单元3200对变量节点计算单元1100的遍历计算进行计数以确定当前变量节点计算状态。寻址单元3100根据当前变量节点计算状态确定第一当前映射地址。变量节点计算单元1100根据寻址单元3100所指示的第一当前映射地址对存储器中的迭代信息进行更新。例如，变量节点计算单元1100根据寻址单元3100所指示的地址，从存储器2000中获得执行当前变量节点运算所需要的迭代信息，并将当前变量节点运算所得到变量节点信息存入存储器2000相应的地址以更新迭代信息。
当变量节点计算单元1100遍历完成对LDPC码的校验矩阵中所有变量节点的变量节点运算后，计算单元3200对校验节点计算单元的遍历计算进行计数以确定当前校验节点计算状态。寻址单元3100根据当前校验节点计算状态确定第二当前映射地址。校验节点计算单元1200根据寻址单元3100所指示的第二当前映射地址对存储器中的迭代信息进行更新。例如，校验节点计算单元1200根据寻址单元3100所指示的地址，从存储器2000中获得执行当前校验节点运算所需要的迭代信息，并将当前校验节点运算所得到校验节点信息存入存储器2000相应的地址以更新迭代信息。
当一次译码迭代运算结束后，控制器3000可以判断每个校验节点对应的校验和是否为零，若为零则指示译码成功；若不为零，则所述控制器控制执行下一次译码迭代运算，若迭代次数达到最大迭代次数，则指 示译码失败。校验节点对应的校验和是校验节点对应的各边的硬判决与校验矩阵中与各边相对应的位置的非零元素的乘积之和。
在实际应用中，LDPC码的校验矩阵一般包括由多个循环矩阵和多个零矩阵组成。在译码时，仅需要考虑循环矩阵中的非零元素。图12示出了包括多个循环矩阵的LDPC码的校验矩阵的示意图。
在每一个循环矩阵，一个变量节点仅与一个校验节点相连构成边，并且这种连接关系仅受循环矩阵偏移量的影响。因此，对于每一个循环矩阵，寻址单元3100可以仅为变量节点计算单元1100与存储器2000之间的交互存储一个映射地址，即可实现变量节点计算单元1100对存储器2000中存储的整个循环矩阵的所有边的迭代信息的更新。同样地，对于每一个循环矩阵，寻址单元3100可以仅为校验节点计算单元1200与存储器2000之间的交互存储一个映射地址，即可实现校验节点计算单元1200对存储器2000中存储的整个循环矩阵的所有边的迭代信息的更新。因而进一步地节省了硬件资源，降低了成本。
根据一种具体实施方式，对于每一个循环矩阵，在存储器2000中顺序存储该循环矩阵的每条边的迭代信息。寻址单元3100中可以仅存储该循环矩阵中任一个变量节点所对应的存储器2000中的边的第一映射地址，例如，仅存储该循环矩阵中第一个变量节点所对应的存储器中的边的第一映射地址。这个循环矩阵中其他变量节点与存储器中的相应边的第一映射地址，可以根据循环矩阵内的循环规则直接生成。例如，可以根据已知的第一映射地址、其他变量节点相对于已知变量节点的位置和/或循环矩阵的偏移量确定。类似地，寻址单元3100中可以仅存储该循环矩阵中任一个校验节点所对应的存储器2000中的边的第二映射地址，例如，仅存储该循环矩阵中第一个校验节点所对应的存储器中的边的第二映射地址。这个循环矩阵中其他校验节点与存储器中的相应边的第二映射地址，可以根据循环矩阵内的循环规则直接生成。例如，可以根据已知的第二映射地址、其他校验节点相对于已知校验节点的位置和/或循环矩阵的偏移量确定。
此外，如果变量节点计算单元1100对LDPC码的校验矩阵中的所有循环矩阵的变量节点的遍历计算顺序与存储器2000中对LDPC码的校验 矩阵中的所有循环矩阵的边的迭代信息的存储顺序相同，则寻址单元3100可以不存储变量节点计算单元1100与存储器2000之间的交互映射地址，只要根据控制器3000的计数，变量节点计算单元1100与存储器2000之间自增寻址即可。类似地，如果校验节点计算单元1200对LDPC码的校验矩阵中的所有循环矩阵的校验节点的遍历计算顺序与存储器2000中对LDPC码的校验矩阵中的所有循环矩阵的边的迭代信息的存储顺序相同，则寻址单元3100可以不存储校验节点计算单元1200与存储器2000之间的交互映射地址，只要根据控制器3000的计数，校验节点计算单元1200与存储器2000之间自增寻址即可。
根据本申请的译码器的串行实现，尤其适用于接收机端对资源消耗要求严格而对吞吐量要求不高的领域，例如卫星导航领域。下面以GPS系统的LDPC码为例详细说明译码器的工作过程。根据本实施方式，考虑GPS系统中循环矩阵大小为60x60的(1200，600)LDPC码。
图13示出了示意的GPS系统的LDPC码的校验矩阵对应的基础矩阵。基础矩阵中的每一个数字代表校验矩阵中的一个60x60的子矩阵，包括全零矩阵和循坏块。其中，数字“-1”代表全零矩阵，其他数字代表循环矩阵，数字的大小代表循环矩阵的偏移量。例如，数字“0”代表不偏移，即单位矩阵，数字“16”代表单位阵循环右移16位得到的矩阵。
图14示出了图13所示的LDPC码对应的Tanner图。其中每个方块代表一组60个校验节点，每个圆圈都代表一组60个变量节点，每条边都代表一个块边。图15示出了图14中一个块边所对应的变量节点、校验节点、以及相应的边连接关系。其中，以连接变量节点组1和校验节点组2的块边为例，对应于基础矩阵中第二行第一列的16。
在本实施方式中，变量节点计算单元1100通过VNU实现，校验节点计算单元1200通过CNU实现，存储器2000通过RAM实现。
RAM中每个存储地址对应LDPC码的校验矩阵中的一个非零元素，即，图15中的一条边。RAM对LDPC码的校验矩阵的迭代信息的存储顺序按照校验矩阵中每一条边在基础矩阵中对应的子矩阵(循环矩阵)的分组位置顺序(例如列顺序)、分组端口顺序(例如每一列的行顺序)、该条边在循环矩阵内的组内位置(例如组内列顺序)存储。
这样，控制器的计算单元可以对VNU或者CNU的运算进行计数，得到当前运算的边所在的分组数unitnum，在分组中的组内位置groupnum，以及当前输入输出端口号portnum。此外，对于基础矩阵中循环矩阵分布不规则(行重或列重不固定)情况，控制器的计算单元或者寻址单元中还可以记录基础矩阵中每一列的总非零行数Max_port_V，以及记录基础矩阵中每一行的总非零列数Max_port_C。本领域技术人员可以理解，当控制器的计算单元对VNU的运算进行计数时，分组数unitnum表示当前变量节点计算的变量节点对应的边在基础矩阵中对应的循环矩阵的列顺序，输入输出端口号portnum表示该条边在基础矩阵中对应的循环矩阵在这一列中的行顺序，组内位置groupnum表示该条边在循环矩阵中的列位置。当控制器的计算单元对CNU的运算进行计数时，分组数unitnum表示当前变量节点计算的变量节点对应的边在基础矩阵中对应的循环矩阵的行顺序，输入输出端口号portnum表示该条边在基础矩阵中对应的循环矩阵在这一行中的列顺序，组内位置groupnum表示该条边在循环矩阵中的行位置。
寻址单元中记录RAM中的存储地址grp_addr与分组数unitnum、端口号portnum和组内位置groupnum之间的映射关系。例如，寻址单元可以存储地址grp_addr与VNU的(unitnum，portnum，groupnum)之间的映射对照表，并存储存储地址grp_addr与CNU的(unitnum，portnum，groupnum)之间的映射对照表。
考虑到每一个循环矩阵内的边与变量节点和校验节点的对应关系唯一且固定(由偏移量决定)，因此，对于一个循环矩阵，寻址单元中可以仅记录RAM中的存储地址与分组数unitnum、端口号portnum、以及组内任一位置(例如groupnum＝0)之间的映射关系，并记录该循环矩阵的偏移量，就可以确定整个循环矩阵的寻址映射关系。例如，寻址单元中可以存储地址grp_addr与VNU的(unitnum，portnum)之间的映射对照表，并存储存储地址grp_addr与CNU的(unitnum，portnum)之间的映射对照表。
译码器的译码过程开始后，首先进行初始化，即将1200(LDPC码校验矩阵的列数)个初始LLR值逐次写入RAM中。
例如，VNU从输入缓存中读取第一个初始LLR值，并进行硬判决。计算单元开始计数，根据计数状态，更新组内位置groupnum。可以理解，组内位置groupnum的每一次更新对应着VNU对一个初始LLR值的写入(或者迭代计算时VNU的一次计算过程)，在一个初始LLR值的写入过程中(或者一次VNU计算过程中)，控制器将端口号portnum从“1”增加到相应的Max_port_V。由于初始LLR值要写入每一个分组数unitnum与组内位置groupnum所对应的所有端口，寻址单元根据分组数unitnum和端口号portnum，以及存储的第一映射关系，找到相应的寻址地址。VNU的写入地址可以由寻址单元所指示的寻址地址与计算单元指示的组内位置groupnum组合得到。VNU将第一个硬判决和初始LLR值写入RAM中相应的写入地址中。随后，VNU根据初始LLR值逐次对RAM进行初始化写入。计算单元对初始化写入次数进行计数，根据计数状态，将组内位置groupnum逐次增加1，直到60(等于循环矩阵大小)则归零，且分组数unitnum增加1，直到20(基础矩阵的列数)。图16示出了VNU逐次遍历运算的时序图。如图所示，VNU将进行1200次运算。
上述初始化过程由VNU从输入缓存中依次读取初始LLR值，根据初始LLR值进行硬判决并将硬判决和LLR值依次保存到RAM中对应的存储单元。如果初始化前，RAM中的初始值均为零，则VNU也可以通过一次变量节点遍历运算完成初始化。
此外，VNU可以与寻址单元连接，根据寻址单元指示的地址读写RAM；VNU也可以不与寻址单元连接，而直接与RAM相连，寻址单元只用来生成RAM的读写地址。
初始化完成后，进行校验节点运算。校验节点运算中需要用到的输入信息根据控制器的控制从RAM中串行读出，运算结果根据控制器的控制写入RAM中的相应位置。
计算单元对CNU的遍历运算进行计数，根据计数状态，更新组内位置groupnum。可以理解，组内位置groupnum的每一次更新对应CNU的一次计算过程，在一次CNU计算过程中，控制器将端口号portnum从“1”增加到相应的Max_port_C。此外，由于循环矩阵存在偏移量off_addr，因此，groupnum的初始值为偏移量off_addr，在计数过程中，如果 groupnum大于60，则将组内位置groupnum更新为groupnum减去60，直到计算单元的计数达到60次，groupnum回到初始值，分组数unitnum增加1。迭代上述计算，直到unitnum增加至10(基础矩阵的行数)。计算单元向寻址单元输出分组数unitnum和端口号portnum，寻址单元根据存储的控制节点-边映射关系，找到相应的寻址地址。CNU的读写地址可以由寻址单元所指示的寻址地址与计算单元指示的组内位置groupnum组合得到。
例如，当LDPC码为二进制码时，在一次CNU计算过程中，CNU可以根据控制器的控制从RAM中依次读入每个控制节点对应的边(即，相应的端口号portnum从“1”至Max_port_C)的LLR值及硬判决，计算每个控制节点所对应的所有边的输入LLR值中的最小值及次小值。对输入为最小值的地址写入次小值，其他地址写入最小值。随后遍历每一个控制节点。图17示出了CNU逐次遍历运算的时序图。如图所示，CNU将进行600次运算。
当LDPC码为多进制码时，在一次CNU计算过程中，CNU可以根据控制器的控制从RAM中依次读入每个控制节点对应的边(即，相应的端口号portnum从“1”至Max_port_C)的迭代信息。迭代信息例如可以包括由多个码字符号和相应的多个置信度组成的向量信息。多进制码的校验节点的多个端口之间输入数据的运算为多次卷积排序运算，即两个迭代向量信息进行卷积排序运算后得到的新的向量信息与其他迭代信息向量继续进行卷积排序运算。对于基础矩阵中行重不为固定值的情况，可以设计串行结构的CNU，通过CNU内部分配至少Max_port个缓存空间，就可以实现一个CNU在输入端口数不固定情况下的CNU计算，其中Max_port数等于所有行对应的最大列数Max_port_C中的最大值。
例如，可以在CNU内部分配Max_port+1个缓存空间。当Max_port等于3时，CNU内部可以设有四个缓存空间，首先串行读取并缓存三个端口的迭代向量信息至三个不同的缓存空间中，然后计算第一个端口和第二个端口输入的迭代向量信息之间卷积排序运算结果，保存至第四个缓存空间中。再计算第一个端口和第三个端口输入的迭代向量信息之间卷积排序运算结果，保存至第一个缓存空间中。最后计算第二个端口和 第三个端口输入的迭代向量信息之间卷积排序运算结果，保存至第二个缓存空间中，即完成了所有端口全部输出迭代向量信息的计算。此外，例如当Max_port等于4时，CNU内部可以设有五个缓存空间，对于基础矩阵中行重为3的行，新增的缓存空间闲置，仍按前述顺序完成所有三个端口全部输出迭代向量信息的计算；对于基础矩阵中行重为4的行，将第四个端口的输入迭代向量信息缓存至新增的缓存空间中，首先按照前述顺序完成前三个端口输入迭代向量信息之间的运算，然后计算第三个端口输入的迭代向量信息与第一个缓存空间中第一个端口与第二个端口运算得到的向量信息之间的卷积排序运算结果，保存至第三个缓存空间中，然后依次计算第四个端口的输入迭代向量信息与第一、二、四个缓存空间中向量信息之间的卷积排序运算结果，并保存回第一、二、四个缓存空间中，即完成了所有四个端口全部输出迭代向量信息的计算。以此类推，每当Max_port增加1，只需在CNU内部增加一个缓存空间，即可完成输入端口数不大于Max_port的任意CNU运算。
此外，当参与运算的输入迭代向量信息不缓存在CNU内部，而是当使用时直接从外部重新读入时，则CNU内部可以仅分配Max_port个缓存空间来完成中间向量信息及输出迭代向量信息的缓存即可。
可以看出，根据本实施方式的译码器中的CNU中仅需分配Max_port个或者至多Max_port+1个缓存空间，就可以完成多进制情况下复杂的CNU运算。
当完成控制节点的遍历计算后，控制器对所有硬判决进行加和判断校验和是否为零。若校验和为零，则完成译码；如果校验和不为零，则需要继续迭代进行变量节点运算。校验和是校验节点对应的各边的硬判决与校验矩阵中与各边相对应的位置的非零元素的乘积之和。对于多进制LDPC码，则还需记录非零元素的数值。
变量节点运算过程中，LDPC码为二进制码和多进制码的运算方式类似。以二进制码为例，对于每一次VNU运算，VNU从输入缓存中读入初始LLR值并从RAM中读入第一个端口的LLR值，将它们相加并在VNU内部保存第一个端口输入的LLR值，之后依次读入并累加其他端口的LLR值，得到LLR_total。VNU还要缓存每一个端口输入的LLR值。 对LLR_total进行硬判决，对每个端口输出该硬判决以及LLR_total与对应端口的输入值之差，存入RAM中。
之后继续迭代进行变量节点和校验节点更新过程，直至译码成功或达到预设的最大迭代次数为止。
可以理解，如果RAM的存储顺序与VNU的遍历计算顺序一致时，寻址单元中记录的映射关系可以不采用映射表的形式，而直接由计算单元给出的unitnum、portnum及groupnum计算或者拼接得到VNU的遍历地址。如果RAM的存储顺序与CNU的遍历计算顺序一致，则寻址单元中记录的映射关系可以不采用映射表的形式，而直接由计算单元给出的unitnum、portnum及groupnum计算或者拼接得到CNU的遍历地址。这样可以进一步节省硬件资源。
虽然根据本申请的实施方式，LDPC码译码器中包括一个变量节点计算单元和一个校验节点计算单元，但是本领域技术人员可以理解，虽然根据本申请的实施方式，LDPC码译码器中也可以包括多个变量节点计算单元和多个校验节点计算单元，控制器可以以类似的方式，控制多个变量节点计算单元遍历计算所有变量节点的变量节点信息，并根据计算获得的变量节点信息更新存储器的迭代信息，以及控制多个校验节点计算单元遍历计算所有校验节点的校验节点信息，并根据计算获得的校验节点的运算结果更新存储器的迭代信息。
此外，除了上述由一个变量节点运算器遍历运算所有变量节点信息，并由一个校验节点运算器遍历运算所有校验节点信息，以实现LDPC码译码器的迭代译码过程外，根据本申请的另一种实施方式，译码器也可以仅包括一个节点运算单元，由该节点运算器遍历运算所有变量节点信息和所有校验节点信息，以实现分层结构的迭代译码过程。
分层译码的LDPC码译码器的串行实现思想与前述实施方式类似。图18示出了根据本申请的一种实施方式的LDPC码译码器的示意图。如图所示，LDPC码译码器包括：一个节点计算单元1000，第一存储器2100，第二存储器2200，以及控制器3000。
第一存储器2100存储LDPC码的校验矩阵的变量节点的迭代信息。 例如，存储LDPC码的校验矩阵的各个变量节点的总置信度LLR_total。第二存储器2200，存储LDPC码的校验矩阵的每条边的迭代信息。例如，存储LDPC码的校验矩阵的每条边的码字符号和置信度。控制器3000，控制节点计算单元执行译码迭代运算，直到译码结束，其中，在每一次译码迭代运算中，所述控制器控制所述节点计算单元按照校验节点顺序遍历计算所有变量节点信息和所有校验节点信息，并根据所述变量节点信息和所述校验节点信息更新第一存储器和第二存储器中的迭代信息。
控制器3000还可以包括寻址单元3100和计算单元3200。寻址单元3100存储校验节点与变量节点之间的第一映射关系，并存储节点计算单元对所有校验节点的遍历顺序与存储器中校验矩阵每条边的存储顺序之间的第二映射关系。计算单元3200对节点计算单元1000的计算进行计数，根据计数状态控制寻址单元指示当前计算所对应的存储单元的地址，并控制节点计算单元按照所指示的地址通过运算获得的当前运算的校验节点所对应的变量节点的总置信度和当前运算的校验节点所对应的每条边的码字符号和置信度更新第一存储器和第二存储器。
当LDPC码是包含多个循环矩阵的LDPC码时，寻址单元310可以仅为变量节点计算单元与第一存储器和第二存储器之间的交互分别存储一个映射地址，从而进一步地节省硬件资源，降低成本。对于每一个循环矩阵，存储器中顺序存储该循环矩阵的每条边的迭代信息。寻址单元3100中仅存储该循环矩阵中任一个校验节点所对应的存储器中的变量节点的第一映射地址，以及仅存储该循环矩阵中任一个校验节点所对应的存储器中的边的第二映射地址。该循环矩阵中其他校验节点与第一存储器中的相应边的映射地址根据第一映射地址、其他校验节点相对于该任一个校验节点的位置和/或该循环矩阵的偏移量确定；该循环矩阵中其他变量节点与第二存储器中的相应边的映射地址根据第二映射地址、其他变量节点相对于该任一个变量节点的位置和/或该循环矩阵的偏移量确定。
根据本申请的实施方式可以硬件、软件或其组合的形式来实现。本申请的一个方面提供了包括用于实现根据本申请的实施方式的LDPC码编码器和译码器可执行指令的计算机程序。此外，此类计算机程序可使 用例如光学或磁性可读介质、芯片、ROM、PROM或其它易失性或非易失性设备的任何形式的存储器来存储。根据本申请的一种实施方式，提供了存储此类计算机程序的机器可读存储器。
以上参照附图对本申请的示例性的实施方案进行了描述。本领域技术人员应该理解，上述实施方案仅仅是为了说明的目的而所举的示例，而不是用来进行限制，凡在本申请的教导和权利要求保护范围下所作的任何修改、等同替换等，均应包含在本申请要求保护的范围内。

Claims (31)

  1. 一种LDPC码译码器，包括：
    一个变量节点计算单元；
    一个校验节点计算单元；
    存储器，存储LDPC码的校验矩阵的每条边的迭代信息；
    控制器，控制节点计算单元执行译码迭代运算，直到译码结束，其中，在每一次译码迭代运算中，所述控制器控制所述变量节点计算单元遍历计算所有变量节点的变量节点信息，并根据计算获得的变量节点信息更新存储器的迭代信息，以及所述控制器控制所述校验节点计算单元遍历计算所有校验节点的校验节点信息，并根据计算获得的校验节点的运算结果更新存储器的迭代信息。
  2. 如权利要求1所述的LDPC码译码器，其中所述控制器进一步包括寻址单元，所述寻址单元存储变量节点计算单元对所有变量节点的遍历顺序与存储器中校验矩阵的每条边的迭代信息的存储顺序之间的第一映射关系，以及存储校验节点计算单元对所有校验节点的遍历顺序与存储器中校验矩阵的每条边的迭代信息的存储顺序之间的第二映射关系。
  3. 如权利要求2所述的LDPC码译码器，其中，所述控制器进一步包括计算单元，所述计算单元对变量节点计算单元的遍历计算进行计数以确定当前变量节点计算状态，所述变量节点寻址单元根据当前计算状态和第一映射关系确定第一当前映射地址，所述变量节点计算单元根据所述第一当前映射地址对存储器中的迭代信息进行更新；所述计算单元对校验节点计算单元的遍历计算进行计数以确定当前校验节点计算状态，所述校验节点寻址单元根据当前校验节点计算状态和第二映射关系确定第二当前映射地址，所述校验节点计算单元根据所述第二当前映射地址对存储器中的迭代信息进行更新。
  4. 如权利要求3所述的LDPC码译码器，其中，所述LDPC码的校验矩阵包括多个循环矩阵，对于每一个循环矩阵：
    所述存储器中顺序存储该循环矩阵的每条边的迭代信息，所述寻址单元中仅存储该循环矩阵中任一个变量节点所对应的存储器中的边的第一映射地址，以及仅存储该循环矩阵中任一个校验节点所对应的存储器中的边的第二映射地址。
  5. 如权利要求4所述的LDPC码译码器，其中，所述一个循环矩阵中其他变量节点与存储器中的相应边的映射地址根据所述第一映射地址、所述其他变量节点相对于所述任一个变量节点的位置和/或所述一个循环矩阵的偏移量确定；所述一个循环矩阵中其他校验节点与存储器中的相应边的映射地址根据所述第二映射地址、所述其他校验节点相对于所述任一个校验节点的位置和/或所述一个循环矩阵的偏移量确定。
  6. 如权利要求1所述的LDPC码译码器，其中，所述存储器中存储的每条边的迭代信息包括与该条边对应的码字符号和置信度，所述变量节点的变量节点信息包括该变量节点对应的各边的码字符号和置信度，所述校验节点的校验节点信息包括该校验节点对应的各边的码字符号和置信度。
  7. 如权利要求6所述的LDPC码译码器，其中，所述变量节点计算单元在执行当前变量节点计算时，从存储器获得参与当前计算的变量节点对应的所有边的迭代信息，并将该迭代信息与参与当前计算的变量节点对应的初始置信度进行运算以获得参与当前计算的变量节点所对应的所有边的码字符号和置信度，并更新存储器中与当前计算的变量节点对应的所有边的迭代信息中的码字符号和置信度。
  8. 如权利要求6所述的LDPC码译码器，其中，所述校验节点计算单元在执行当前校验节点计算时，从存储器获得参与当前计算的校验节点对应的所有边的迭代信息，并对该迭代信息进行计算以获得参与当前计算的校验节点对应的所有边的码字符号和置信度，并更新存储器中与当前校验的校验节点对应的所有边的迭代信息中的码字符号和置信度。
  9. 如权利要求8所述的LDPC码译码器，其中，当所述LDPC码为多进制码时，所述校验节点计算器包括多个缓存空间以缓存校验节点运算的中间结果，其中所述多个缓存空间的数量根据校验矩阵的基础矩阵中循环矩阵分布的所有行对应的最大列数的最大值确定。
  10. 如权利要求1所述的LDPC码译码器，其中，当一次译码迭代运算结束后，所述控制器判断每个校验节点对应的校验和是否为零，若为零则指示译码成功；若不为零，则所述控制器控制执行下一次译码迭代运算，若迭代次数达到最大迭代次数，则指示译码失败。
  11. 一种LDPC码译码器，包括：
    多个变量节点计算单元；
    多个校验节点计算单元；
    存储器，存储LDPC码的校验矩阵的每条边的迭代信息；
    控制器，控制节点计算单元执行译码迭代运算，直到译码结束，其中，在每一次译码迭代运算中，所述控制器控制所述多个变量节点计算单元遍历计算所有变量节点的变量节点信息，并根据计算获得的变量节点信息更新存储器的迭代信息，以及所述控制器控制所述多个校验节点计算单元遍历计算所有校验节点的校验节点信息，并根据计算获得的校验节点的运算结果更新存储器的迭代信息。
  12. 一种LDPC码译码器，包括：
    一个节点计算单元；
    第一存储器，存储LDPC码的校验矩阵的变量节点的迭代信息；
    第二存储器，存储LDPC码的校验矩阵的每条边的迭代信息；
    控制器，控制节点计算单元执行译码迭代运算，直到译码结束，其中，在每一次译码迭代运算中，所述控制器控制所述节点计算单元按照校验节点顺序遍历计算所有变量节点信息和所有校验节点信息，并根据所述变量节点信息和所述校验节点信息更新第一存储器和第二存储器中的迭代信息。
  13. 如权利要求12所述的LDPC码译码器，其中，所述第一存储器中存储的迭代信息包括变量节点的总置信度，所述第二存储器中存储的迭代信息包括校验矩阵的每条边的码字符号和置信度。
  14. 如权利要求13所述的LDPC码译码器，其中，控制器包括寻址单元和计算单元，所述寻址单元存储校验节点与变量节点之间的第一映射关系，并存储节点计算单元对所有校验节点的遍历顺序与存储器中校验矩阵每条边的存储顺序之间的第二映射关系，所述计算单元对节点计算单元的计算进行计数，根据计数状态控制寻址单元指示当前计算所对应的存储单元的地址，并控制节点计算单元按照所指示的地址通过运算获得的当前运算的校验节点所对应的变量节点的总置信度和当前运算的校验节点所对应的每条边的码字符号和置信度更新第一存储器和第二存储器。
  15. 如权利要求12所述的LDPC码译码器，其中，所述LDPC码的校验矩阵包括多个循环矩阵，对于每一个循环矩阵：
    所述寻址单元中仅存储该循环矩阵中任一个校验节点所对应的存储器中的变量节点的第一映射地址，以及仅存储该循环矩阵中任一个校验节点所对应的存储器中的边的第二映射地址。
  16. 如权利要求15所述的LDPC码译码器，其中，所述一个循环矩阵中其他校验节点与第一存储器中的相应边的映射地址根据所述第一映射地址、所述其他校验节点相对于所述任一个校验节点的位置和/或所述一个循环矩阵的偏移量确定；所述一个循环矩阵中其他变量节点与第二存储器中的相应边的映射地址根据所述第二映射地址、所述其他变量节点相对于所述任一个变量节点的位置和/或所述一个循环矩阵的偏移量确定。
  17. 一种LDPC码译码方法，包括：
    存储LDPC码的校验矩阵的每条边的迭代信息；
    执行译码迭代运算，直到译码结束，其中，在每一次译码迭代运算 中，
    逐次遍历计算所有变量节点的变量节点信息，并相应更新存储的迭代信息；以及
    逐次遍历计算所有校验节点的校验节点信息，并相应更新存储的迭代信息。
  18. 如权利要求17所述的LDPC码译码方法，进一步包括：存储第一映射关系和第二映射关系，其中，所述第一映射关系包括对所有变量节点进行逐次变量节点计算的遍历顺序与所存储的校验矩阵的每条边的迭代信息的存储顺序之间的映射关系，所述第二映射关系包括对所有校验节点进行逐次校验节点计算的遍历顺序与所存储的校验矩阵的每条边的迭代信息的存储顺序之间的映射关系。
  19. 如权利要求18所述的LDPC码译码方法，其中，对变量节点计算单元的遍历计算进行计数以确定当前变量节点计算状态，根据当前计算状态和第一映射关系确定第一当前映射地址，根据所述第一当前映射地址对存储的迭代信息进行更新；对校验节点计算单元的遍历计算进行计数以确定当前校验节点计算状态，根据当前校验节点计算状态和第二映射关系确定第二当前映射地址，根据所述第二当前映射地址对存储器中的迭代信息进行更新。
  20. 如权利要求19所述的LDPC码译码方法，其中，所述LDPC码的校验矩阵包括多个循环矩阵，对于每一个循环矩阵：
    第一映射关系中仅包括该循环矩阵中任一个变量节点所对应的存储的边的迭代信息的第一映射地址，以及第二映射关系中仅包括该循环矩阵中任一个校验节点所对应的存储的边的迭代信息的第一映射地址。
  21. 如权利要求20所述的LDPC码译码方法，其中，所述一个循环矩阵中其他变量节点与存储的边的迭代信息的映射地址根据所述第一映射地址、所述其他变量节点相对于所述任一个变量节点的位置和/或所述一个循环矩阵的偏移量确定；所述一个循环矩阵中其他校验节点与存储 的边的迭代信息的映射地址根据所述第二映射地址、所述其他校验节点相对于所述任一个校验节点的位置和/或所述一个循环矩阵的偏移量确定。
  22. 如权利要求17所述的LDPC码译码方法，其中，所存储的每条边的迭代信息包括与该条边对应的码字符号和置信度，所述变量节点的变量节点信息包括该变量节点对应的各边的码字符号和置信度，所述校验节点的校验节点信息包括该校验节点对应的各边的码字符号和置信度。
  23. 如权利要求22所述的LDPC码译码方法，其中，在执行当前变量节点计算时，逐次获得所存储的参与当前计算的变量节点对应的所有边的迭代信息，并将该迭代信息与参与当前计算的变量节点对应的初始置信度进行运算以获得参与当前计算的变量节点所对应的所有边的码字符号和置信度，并更新所存储的与当前计算的变量节点对应的所有边的迭代信息中的码字符号和置信度。
  24. 如权利要求23所述的LDPC码译码方法，其中，在执行当前校验节点计算时，逐次获得所存储的参与当前计算的校验节点对应的所有边的迭代信息，并对该迭代信息进行计算以获得参与当前计算的校验节点对应的所有边的码字符号和置信度，并更新所存储的与当前校验的校验节点对应的所有边的迭代信息中的码字符号和置信度。
  25. 如权利要求17所述的LDPC码译码方法，其中，当一次译码迭代运算结束后，判断每个校验节点对应的校验和是否为零，若为零则译码成功；若不为零，则执行下一次译码迭代运算，若迭代次数达到最大迭代次数，则译码失败。
  26. 一种数据处理装置，包括：
    m个数据处理模块，按照计算顺序在第i个周期处理Ni个数据或者操作；
    其中
    Figure PCTCN2016070865-appb-100001
    且m＜n，m、n和Ni均为正整数，
    Figure PCTCN2016070865-appb-100002
  27. 根据权利要求26所述的装置，其中，所述m个数据处理模块，
    在低密度奇偶校验LDPC编码过程中，分别计算待编码数据c＝(c0，c1…ck-1)与生成矩阵Gk×n中每一列相乘，其中k表示所述待编码数据的长度，n表示所述生成矩阵Gk×n的列数；
    在第i个周期计算c＝(c0，c1…ck-1)与生成矩阵Gk×n中的Ni个列相乘，其中在前
    Figure PCTCN2016070865-appb-100003
    个周期，所述Ni＝m，
    Figure PCTCN2016070865-appb-100004
    若n不能被m整除，则在第
    Figure PCTCN2016070865-appb-100005
    个周期，所述Ni＝n mod m，
    Figure PCTCN2016070865-appb-100006
  28. 根据权利要求26所述的装置，其中，所述数据处理模块包括：第一存储单元和第二存储单元；
    所述数据处理模块将所述生成矩阵Gk×n的每一列分为P个第一数据块，其中P≥2；
    所述第一存储单元存储一个所述第一数据块；
    所述第二存储单元存储所述第一数据块对应的所述待编码数据的第二数据块；
    所述m个数据处理模块，在低密度奇偶校验LDPC编码过程中，根据分块结果，在第i个周期计算Ni个第二数据块与对应的Ni个第一数据块相乘，其中在前
    Figure PCTCN2016070865-appb-100007
    个周期，所述Ni＝m，
    Figure PCTCN2016070865-appb-100008
    若n不能被m整除，则在第
    Figure PCTCN2016070865-appb-100009
    个周期至第
    Figure PCTCN2016070865-appb-100010
    个周期，所述Ni＝n mod m，
    Figure PCTCN2016070865-appb-100011
  29. 根据权利要求26-28中任一项所述的装置，还包括：第一存储模块，存储所述生成矩阵。
  30. 根据权利要求29所述的装置，其中，
    若所述生成矩阵为稀疏矩阵，则所述第一存储模块仅存储所述生成矩阵的非零元素和所述非零元素对应的位置坐标；
    若所述生成矩阵的子矩阵为循环矩阵，则所述第一存储模块仅存储所述循环矩阵中所有的非零元素、以及其中一列非零元素对应的位置坐标和相邻两列的循环偏移量。
  31. 一种数据处理装置，包括：第一存储模块，第二存储模块，和数据处理模块，其中，
    所述第一存储模块，存储校验矩阵Hl×n，所述LDPC码的校验矩阵包含准双对角矩阵I；
    所述第二存储模块，存储待编码数据M＝(m0，m1…mk-1)，以及存储由数据处理模块迭代计算得到的校验位p1，p2…pn-k；
    所述数据处理模块，根据校验矩阵Hl×n与校验位p1，p2…pn-k之间的关系
    Figure PCTCN2016070865-appb-100012
    迭代计算LDPC码的校验位p1，p2…pn-k，其中，
    在第i次迭代计算后，将这一次迭代所获得的第i个校验位pi存入第二存储模块中，
    在第i+1次迭代计算时，数据处理模块从第一存储模块中获得校验矩阵第i+1行非零元素的数值，并根据校验矩阵中第i+1行非零元素的位置从第二存储模块中获得对应数据，将所获得的非零元素的数值与从第二存储模块中获得对应数据进行组合运算得到第i+1校验位pi+1。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110518919A (zh) * 2019-08-01 2019-11-29 湖南国科锐承电子科技有限公司 低密度奇偶校验码的分层译码方法和系统

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107872231B (zh) * 2016-09-28 2023-04-28 北京忆芯科技有限公司 Ldpc译码方法与装置
TWI684856B (zh) * 2018-04-20 2020-02-11 慧榮科技股份有限公司 解碼方法及相關的快閃記憶體控制器與電子裝置
CN117040546A (zh) * 2018-04-24 2023-11-10 北京忆芯科技有限公司 低延迟ldpc译码器及其译码方法
CN112328208A (zh) * 2018-09-18 2021-02-05 安徽寒武纪信息科技有限公司 运算装置及方法
CN111064475A (zh) * 2018-10-16 2020-04-24 华为技术有限公司 基于低密度奇偶校验码的译码方法及装置
CN110474647B (zh) * 2019-07-03 2023-05-23 深圳市通创通信有限公司 有限域构造的ldpc码的译码方法、装置、译码器及存储介质
CN112583420B (zh) * 2019-09-30 2024-01-09 上海华为技术有限公司 一种数据处理方法和译码器
CN110768679B (zh) * 2019-10-30 2023-08-22 湖南国科微电子股份有限公司 64进制ldpc的码字校验方法及系统
CN111211791A (zh) * 2020-02-27 2020-05-29 深圳市航天华拓科技有限公司 Ldpc编译码方法及系统
CN112152637B (zh) * 2020-09-10 2024-04-30 南京中科晶上通信技术有限公司 Dvb-s2 ldpc译码变量节点更新模块及其实现方法
CN112242851B (zh) * 2020-11-23 2024-03-19 湖南国科锐承电子科技有限公司 一种ldpc码的分层译码中迭代数据处理方法及译码器系统
CN113411087B (zh) * 2021-06-30 2023-05-09 展讯半导体(成都)有限公司 解码q元LDPC的方法、电路及包括其的接收机
CN113595563B (zh) * 2021-08-02 2024-03-29 上海金卓科技有限公司 一种ldpc译码的方法、装置、设备及存储介质
CN114584259B (zh) * 2022-02-18 2024-02-09 阿里巴巴（中国）有限公司 译码方法、装置、设备及存储介质
CN117375636B (zh) * 2023-12-07 2024-04-12 成都星联芯通科技有限公司 提高qc-ldpc译码器吞吐率的方法、装置及设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101488760A (zh) * 2009-02-13 2009-07-22 华中科技大学 一种低码率ldpc码的编码方法
US20100192043A1 (en) * 2008-06-23 2010-07-29 Ramot At Tel Aviv University Ltd. Interruption criteria for block decoding
CN102801432A (zh) * 2012-07-20 2012-11-28 航天恒星科技有限公司 一种多进制ldpc的串行fht-bp译码方法及装置
CN103929189A (zh) * 2014-04-23 2014-07-16 荣成市鼎通电子信息科技有限公司 近地通信中部分并行输入的累加左移qc-ldpc编码器

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266750B1 (en) * 2002-07-10 2007-09-04 Maxtor Corporation Error recovery strategies for iterative decoders
US7159170B2 (en) * 2003-06-13 2007-01-02 Broadcom Corporation LDPC (low density parity check) coded modulation symbol decoding
US7395490B2 (en) * 2004-07-21 2008-07-01 Qualcomm Incorporated LDPC decoding methods and apparatus
CN100486118C (zh) * 2005-11-21 2009-05-06 东南大学 一种基于分段偏移修正的最小和译码方法
US8359522B2 (en) * 2007-05-01 2013-01-22 Texas A&M University System Low density parity check decoder for regular LDPC codes
TW200908569A (en) * 2007-05-21 2009-02-16 Ramot At Tel Aviv University Co Ltd Memory-efficient LDPC decoding
CN101383618B (zh) * 2007-09-05 2013-02-27 中兴通讯股份有限公司 一种传输块的循环冗余校验码的编码方法
CN101640543B (zh) * 2008-07-31 2013-06-05 深圳市同洲电子股份有限公司 一种ldpc码的编码装置及方法
US8335949B2 (en) * 2009-11-06 2012-12-18 Trellisware Technologies, Inc. Tunable early-stopping for decoders
JP5310701B2 (ja) * 2010-10-29 2013-10-09 株式会社Ｊｖｃケンウッド 復号装置および復号方法
US8549387B2 (en) * 2010-11-04 2013-10-01 Himax Media Solutions, Inc. System and method of decoding LDPC code blocks
JP2012244305A (ja) * 2011-05-17 2012-12-10 Toshiba Corp メモリコントローラ、半導体メモリ装置、および復号方法
CN202395755U (zh) * 2011-09-29 2012-08-22 中国电子科技集团公司第五十四研究所 Qc_ldpc高速部分并行信道译码器
US8707144B2 (en) * 2011-10-17 2014-04-22 Lsi Corporation LDPC decoder with targeted symbol flipping
CN103023516A (zh) * 2013-01-01 2013-04-03 苏州威士达信息科技有限公司 联合生成矩阵和校验矩阵的ldpc编码器和编码方法
GB2510932B (en) * 2013-08-27 2015-01-21 Imagination Tech Ltd An improved decoder for low-density parity-check codes
KR102114860B1 (ko) * 2013-09-04 2020-05-25 엘지전자 주식회사 가전기기, 가전기기 시스템 및 그 제어 방법
US9184767B2 (en) * 2013-09-19 2015-11-10 SanDisk Technologies, Inc. Scoring variable nodes for low density parity check code decoding
CN103916134B (zh) * 2014-03-24 2017-01-11 清华大学 低密度奇偶校验码的混叠译码方法及多核协同混叠译码器
CN103905055A (zh) * 2014-04-23 2014-07-02 荣成市鼎通电子信息科技有限公司 部分并行输入的右移累加qc-ldpc编码器
CN103929207A (zh) * 2014-04-23 2014-07-16 荣成市鼎通电子信息科技有限公司 Cmmb中部分并行输入的右移累加qc-ldpc编码器
US9503125B2 (en) * 2014-05-08 2016-11-22 Sandisk Technologies Llc Modified trellis-based min-max decoder for non-binary low-density parity-check error-correcting codes
CN103957015B (zh) * 2014-05-12 2017-02-01 福州大学 用于ldpc码解码的非均匀量化编码方法及其在解码器的应用

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100192043A1 (en) * 2008-06-23 2010-07-29 Ramot At Tel Aviv University Ltd. Interruption criteria for block decoding
CN101488760A (zh) * 2009-02-13 2009-07-22 华中科技大学 一种低码率ldpc码的编码方法
CN102801432A (zh) * 2012-07-20 2012-11-28 航天恒星科技有限公司 一种多进制ldpc的串行fht-bp译码方法及装置
CN103929189A (zh) * 2014-04-23 2014-07-16 荣成市鼎通电子信息科技有限公司 近地通信中部分并行输入的累加左移qc-ldpc编码器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110518919A (zh) * 2019-08-01 2019-11-29 湖南国科锐承电子科技有限公司 低密度奇偶校验码的分层译码方法和系统

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