WO2016107295A1

WO2016107295A1 - Method for removing film on leadless gilt plate

Info

Publication number: WO2016107295A1
Application number: PCT/CN2015/094366
Authority: WO
Inventors: 谢添华; 卢汝烽; 李志东
Original assignee: 广州兴森快捷电路科技有限公司; 深圳市兴森快捷电路科技股份有限公司; 宜兴硅谷电子科技有限公司
Priority date: 2014-12-31
Filing date: 2015-11-12
Publication date: 2016-07-07
Also published as: CN104582287B; CN104582287A; KR20160141709A

Abstract

A method for removing a film on a leadless gilt plate comprises: electrolessly plating copper on a circuit board after circuit manufacturing is performed; after an anti-etching dry film pretreatment is performed, attaching an anti-etching dry film to an anti-etching position on a surface layer of an anti-etching electroless plating copper; when the anti-etching dry film is exposed, reducing an exposure energy, and performing a first development and a first flash rusting; attaching an anti-gild dry film to an anti-gild position on the circuit board; when the anti-gild dry film is exposed, opening a window above a through hole in the circuit board; after the second development is performed, electrically plating gold on the circuit board; removing the film on the circuit board and performing a second flash rusting. By reducing the exposure energy when the anti-etching dry film (ER) is exposed, the production efficiency of the ER exposure is improved, and the production time is shortened by 30%. The design of opening a window above the through hole completely resolves a problem that film removal cannot be performed completely on a TLP micro-through hole product, and thereby greatly improving the production efficiency and the product defect-free rate. The method is suitable for all through hole circuit boards of the TLP procedure.

Description

Lead-free gold-plated plate film-removing method

Technical field

The invention relates to the technical field of printed circuit boards, in particular to a method for film unloading of leadless gold plate.

Background technique

With the development of electronic products in the direction of light, thin and small, electronic components are also advancing toward high density and miniaturization. The Tailless Process (TLP) is widely used in package substrates, which utilizes a copper-clad layer. Conductive medium, with the excellent plating resistance of special dry film, achieves the purpose of gold plating in gold fingers or other welding areas.

In the lead-free gold-plated plate, when the anti-gold plating dry film is attached, in order to ensure the filling of the line gap to avoid the short circuit of the gold leakage, the vacuum film method is generally adopted, and the vacuum film has a strong fluidity for the dry film, and the dry film is subjected to temperature and pressure. The function fully fills the line gap under vacuum and will also fill the micro-via. The dry film flowing into the pores is sufficiently exposed to light after exposure, and is difficult to be removed at the time of film detachment, especially after secondary dry film attachment and double exposure, dry film polymerization is more sufficient, and it is difficult to perform a film detaching operation. The dry film in the through hole is removed, and the through hole is not completely removed.

Summary of the invention

Based on this, it is necessary for the dry film of the lead-free gold-plated plate to be more fully polymerized after the double exposure, and it is difficult to remove the dry film in the through hole, resulting in the film being uncoated, and providing a leadless gold plating. Plate peeling method.

The embodiment of the invention is achieved by the method for unrolling a lead-free gold plate, the method comprising:

The circuit board after the line is fabricated is copper-plated;

After the anti-etching dry film pre-treatment, and attaching a resist dry film to the surface portion corresponding to the anti-etching copper;

When the anti-etching dry film is exposed, the exposure energy is lowered, and the first development and flashing are performed;

Attaching a corresponding anti-gold plating portion of the circuit board to the anti-gold plating dry film;

When performing an anti-gold plating dry film exposure, opening a window above the through hole in the circuit board;

After performing the second development, the circuit board is plated with gold;

Depressing the circuit board and performing a second flash

In one embodiment, the reducing the exposure energy is specifically:

The exposure energy ranges from 30 to 40 mj;

Where mj is the energy unit of millijoule.

In one embodiment, when the anti-gold plating dry film exposure is performed, the window opening above the through hole in the circuit board is specifically:

Exposure is prevented above the vias in the board.

In one embodiment, the copper plate of the circuit board after the line fabrication is specifically:

The thickness of the copper on the circuit board is 0.5 to 1 μm.

In one of the embodiments, the attached resist dry film and the anti-gold plating dry film are performed under a vacuum environment.

In one of the embodiments, the specific parameters of the vacuum environment are:

The vacuum laminating temperature is 60-90 ° C, the vacuuming time is 30 to 50 s, the pressure is 0.4 to 0.6 MPa, and the pressing time is 20 to 50 s.

The above method for stripping the gold-plated plate without lead wire has the following beneficial effects:

First, by reducing the exposure energy of ER (Etch Resist, anti-etch dry film) exposure, the production efficiency of ER exposure is improved, and the single-process production time is shortened by 30%.

Secondly, through the opening window design of the AR (Au Resist, anti-gold plating dry film), the TLP micro-via products are completely eliminated, which greatly improves the production efficiency and product yield.

In addition, the above-described film-removing method is applicable to through-hole wiring boards of all TLP processes.

DRAWINGS

FIG. 1 is a flow chart showing an implementation of a method for removing a lead-free gold-plated plate according to an embodiment of the present invention; FIG.

2 is a state diagram of a leadless gold plated ER film according to an embodiment of the present invention;

3 is a state diagram of an ER exposure of a leadless gold-plated plate according to an embodiment of the present invention;

4 is a state diagram of exposure and development of a leadless gold plated AR according to an embodiment of the present invention;

FIG. 5 is a state diagram of a lead-free gold plated plate after gold plating according to an embodiment of the present invention; FIG.

FIG. 6 is a state diagram of the leadless gold plate after the film is removed according to an embodiment of the present invention.

detailed description

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the present invention will be described in detail below with reference to the embodiments, which are to be described herein, the terms "first", "second", "third" The words "vertical", "horizontal", "above", "below" and the like are for illustrative purposes only and are not meant to be the only embodiment.

In order to explain the technical solution described in the present invention, the following description will be made by way of specific embodiments.

FIG. 1 is a flowchart showing an implementation process of a method for removing a lead-free gold-plated plate provided by an embodiment of the present invention, and the details are as follows:

In step S101, the circuit board after the line fabrication is made to sink copper;

In the embodiment of the present invention, the copper is deposited by a chemical deposition method on the surface of the substrate to form a thin layer of copper. The thickness of the whole plate of copper is between 0.5 and 1 μm, which ensures that the circuit is turned on without affecting the circuit of the board.

In step S102, an anti-etching dry film pre-treatment is performed, and a resist dry film is attached to a surface portion corresponding to the anti-etching copper surface;

In the embodiment of the present invention, the anti-etching dry film is attached to a portion of the copper-clad layer that needs to be prevented from being etched. The anti-etching dry film can protect the copper-plated layer that conducts in the TLP process, ensuring good continuity of the circuit.

Attaching ER (Etch Resist) to the board requires vacuuming. The vacuum laminating temperature is 60 to 90 ° C, the vacuuming time is controlled to 30 to 50 s, the pressure is 0.4 to 0.6 MPa, and the pressing time is 20 to 50 s. Through the action of the temperature and pressure, the vacuum film gives the dry film a strong fluidity, so that the dry film sufficiently fills the line gap (see Fig. 2). The vacuum film is widely used in the package substrate, and the dry film is fully filled into the line gap by vacuuming and hot pressing, and is also filled into the micro through hole, and the dry film will play a protective role in the resist process.

In step S103, when the anti-etching dry film is exposed, the exposure energy is lowered, and the first development and flashing are performed;

When the ER is exposed, the exposure energy is lowered, and the dry film entering the through hole can be insufficiently polymerized, thereby creating favorable conditions for the reaction between the dry film in the through hole and the film release agent (see FIG. 3). The first development and flash erosion can be ER development and ER flashing. The purpose of flash etching is to expose the lines that need to be plated. The flashing operation is the same as the existing etching operation, except that the etching time is relatively short, mainly due to the thin copper layer that needs to be etched away.

As a preferred embodiment of the invention, the exposure energy is typically 70 mj (milli-joule), where exposure energy ranges from 30 to 40 mj. Exposure in this range creates favorable conditions for the reaction between the dry film in the through-hole and the film-removing solution, so that the film-removing effect is better.

In step S104, attaching a corresponding anti-gold plating portion of the circuit board to the anti-gold plating dry film;

In the embodiment of the present invention, the AR (Au Resist) is sufficiently filled with the line gap, including the micro through hole, by the vacuum filming method. The through hole usually does not require gold plating, and the anti-gold plating dry film can prevent the gold plating from being applied to the through hole.

In step S105, when the anti-gold plating dry film exposure is performed, a window is opened above the through hole in the circuit board;

Referring to FIG. 4(a), the fenestration design above the through hole may prevent exposure at the corresponding through hole and avoid secondary polymerization of the dry film in the hole. In particular, after secondary dry film attachment and double exposure, dry film polymerization is more sufficient, making it difficult to remove the dry film.

In the embodiment of the present invention, the exposure may be blocked in the design file corresponding to the circuit board, and the corresponding position of the through hole is not exposed; in other embodiments of the present invention, the exposure may be prevented by other conventional means in the industry. Alternative.

In step S106, after performing the second development, the circuit board is plated with gold;

In the embodiment of the present invention, the second development may be AR development (see Fig. 4(b)), and then the wiring board is plated with gold to resist oxidation (see Fig. 5).

In step S107, the wiring board is peeled off and a second flash is performed.

Referring to Fig. 6, after the film is successfully removed by the film-removing syrup, the dry film of the surface is not completely polymerized, thereby reducing the difficulty of film detachment, thereby completely removing the dry film. purpose.

In the embodiment of the present invention, the method for removing the lead-free gold-plated plate is provided, and the production efficiency of the ER exposure is improved by reducing the exposure energy during the ER exposure, and the single-process production time is shortened by 30%, and then The window opening design at the through hole during AR exposure completely solves the problem of unsatisfactory film removal of TLP micro-via products, greatly improving production efficiency and product yield, and is suitable for through-hole circuit boards of all TLP processes.

The above-mentioned embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims

A method for unrolling a lead-free gold plate, characterized in that the method comprises:

The circuit board after the line is fabricated is copper-plated;

After the anti-etching dry film pre-treatment, and attaching a resist dry film to the surface portion corresponding to the anti-etching copper;

When the anti-etching dry film is exposed, the exposure energy is lowered, and the first development and flashing are performed;

Attaching a corresponding anti-gold plating portion of the circuit board to the anti-gold plating dry film;

When performing an anti-gold plating dry film exposure, opening a window above the through hole in the circuit board;

After performing the second development, the circuit board is plated with gold;

The circuit board is peeled off and a second flash is applied.
The method for removing a lead-free gold-plated plate according to claim 1, wherein the reducing the exposure energy is specifically:

The exposure energy ranges from 30 to 40 mj;

Where mj is the energy unit of millijoule.
The method for unwinding a lead-free gold-plated plate according to claim 1, wherein when the anti-gold plating dry film is exposed, the window opening above the through hole in the circuit board is:

Exposure is prevented above the vias in the board.
The method for unwinding a lead-free gold-plated plate according to claim 1, wherein the copper plate of the circuit board after the line fabrication is specifically:

The thickness of the copper on the circuit board is 0.5 to 1 μm.
The lead-free gold-plated plate peeling method according to claim 1, wherein the attached dry resist film and the anti-gold plating dry film are performed in a vacuum environment.
The method for stripping a lead-free gold-plated plate according to claim 5, wherein the specific parameters of the vacuum environment are:

The vacuum laminating temperature is 60-90 ° C, the vacuuming time is 30 to 50 s, the pressure is 0.4 to 0.6 MPa, and the pressing time is 20 to 50 s.