WO2016106850A1 - 一种用于获取阵列基板中电容容值的结构体及方法 - Google Patents

一种用于获取阵列基板中电容容值的结构体及方法 Download PDF

Info

Publication number
WO2016106850A1
WO2016106850A1 PCT/CN2015/070692 CN2015070692W WO2016106850A1 WO 2016106850 A1 WO2016106850 A1 WO 2016106850A1 CN 2015070692 W CN2015070692 W CN 2015070692W WO 2016106850 A1 WO2016106850 A1 WO 2016106850A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive
area
region
layer
measurement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/070692
Other languages
English (en)
French (fr)
Inventor
阙祥灯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/418,604 priority Critical patent/US9678398B2/en
Publication of WO2016106850A1 publication Critical patent/WO2016106850A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a structure and method for acquiring capacitance values in an array substrate.
  • LCD monitors have the advantages of high image quality, small size, light weight, low voltage drive and low power consumption. They are now widely used in various IT digital products, such as automotive guidance systems, engineering workstations, monitors, and portable devices.
  • Information terminals electronic terminals, e-books, notebook computers, and large direct-view flat-panel TVs.
  • a conventional liquid crystal panel mainly includes a thin film transistor array substrate, a color filter substrate, and a liquid crystal layer disposed between the two substrates.
  • the resolution of such a display panel is poor, the aperture ratio of the pixel is low, and the alignment error is likely to occur when the color filter substrate is bonded to the thin film transistor array substrate.
  • the liquid crystal panel technology has developed a technology of directly integrating a color filter layer into a thin film transistor array substrate (Color Filter on Array, referred to as COA).
  • the liquid crystal panel produced based on the COA technology mainly includes a COA substrate 101, a counter substrate 102, and a liquid crystal layer 103 disposed between the two substrates.
  • the COA substrate 101 includes a glass substrate 104, a silicon nitride insulating layer 105, a capacitor electrode 106, a first silicon nitride passivation protective layer 107, a color filter layer 108, a second silicon nitride passivation protective layer 109, and a pixel.
  • Electrode 110 is a technology of directly integrating a color filter layer into a thin film transistor array substrate.
  • the opposite substrate 102 does not contain a color filter layer at this time.
  • the color filter layer is directly formed on the thin film transistor array substrate, so that the alignment error is not generated when the color filter substrate is bonded to the thin film transistor array substrate.
  • the COA technology can also enable the resulting liquid crystal panel to have better resolution and higher pixel aperture ratio.
  • a color filter layer 108 is disposed between the capacitor electrode 106 and the pixel electrode 110.
  • the dielectric constant of the color filter layer changes with temperature, this also results from the storage electrode and the pixel electrode.
  • the capacitance value of the formed storage capacitor is unstable, so that the capacitance value of the storage capacitor in the COA substrate production process cannot meet the requirements. Therefore, there is a need for a device that can acquire the capacitance value of the storage capacitor in the array substrate during the production process.
  • an embodiment of the present invention first provides a structure for acquiring a capacitance value in an array substrate, the structure comprising:
  • a second conductive region disposed in the same layer as the second conductive layer in the array substrate, the second conductive region partially or completely overlapping the first conductive region;
  • a second measurement area connected to the second conductive area.
  • the first conductive layer is a conductive layer where the capacitor electrode is located
  • the second conductive layer is a conductive layer where the pixel electrode is located.
  • the first conductive layer is a conductive layer where the common electrode is located
  • the second conductive layer is a conductive layer where the pixel electrode is located.
  • the first measurement area is in the same layer as the first conductive area, and/or the second measurement area is in the same layer as the second conductive area.
  • the second measurement area is in the same layer as the first measurement area, and is connected to the second conductive area through a via.
  • the shape of the first conductive region and/or the second conductive region is circular.
  • the first measurement area and the second measurement area have the same geometrical size.
  • the first measurement area is spaced apart from the second measurement area by a predetermined distance.
  • a first matching network exists between the first conductive area and the first measurement area;
  • a second matching network exists between the second conductive area and the second measurement area.
  • the present invention also provides a method for obtaining a capacitance value in an array substrate, the method comprising:
  • an array substrate according to the obtained capacitance value and the overlapping area of the first conductive region and the second conductive region
  • the overlapping area of the pixel electrode of the neutron pixel and the common electrode or the capacitor electrode calculates the capacitance of the capacitance formed by the pixel electrode of the sub-pixel and the common electrode or the capacitor electrode.
  • the structure provided by the present invention and the corresponding portion of the sub-pixel in the array substrate (for example, a structure formed by the pixel electrode and the common electrode of the sub-pixel, or a structure formed by the pixel electrode and the capacitor electrode of the sub-pixel)
  • the structure is the same.
  • the plate area of the capacitor formed according to the structure ie, the overlapping area of the first conductive region and the second conductive region
  • the capacitance value of the corresponding capacitance in the sub-pixel is obtained, thereby realizing the pair of sub-pixels
  • the detection of the corresponding capacitance value in the middle provides a data basis for judging the quality of the sub-pixel and the liquid crystal panel.
  • the method for obtaining the capacitance value of the array substrate forms a structure similar to the sub-pixel structure in the array substrate at a preset position of the liquid crystal panel, and determines the capacitance value of the capacitance formed by the structure body to determine The capacitance value of the corresponding part in the sub-pixel.
  • the method realizes the measurement of the capacitance value of the sub-pixels in the liquid crystal panel, and provides a data basis for analyzing the performance parameters and the production state of the liquid crystal panel according to the capacitance value.
  • FIG. 1 is a schematic structural view of a liquid crystal panel based on COA technology
  • FIG. 2 is a schematic view of a structure according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a first region in the structure shown in FIG. 2;
  • FIG. 4 is a flow chart of a method of acquiring a capacitance value in an array substrate in accordance with one embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a structure for acquiring a capacitance value in an array substrate provided by the embodiment.
  • the structure provided by this embodiment includes a region 201, a first measurement region 202, and a second measurement region 203.
  • the region 201 of the structure provided by the present embodiment includes a first conductive region 204 and a second conductive region 205.
  • the structure of the structure provided in this embodiment is the same as the structure of the corresponding portion of the sub-pixel in the array substrate, that is, the first conductive region 204 of the structure is in the same layer as the capacitor electrode in the array substrate, and the second conductive region 205 and the array substrate
  • the pixel electrode in the same layer has a color filter layer 206 and a passivation protective layer between the first conductive region 204 and the second conductive region 205.
  • the first conductive region 204 and the second conductive region 205 all overlap, that is, they are distributed at the same position of different material layers of the array substrate, and both have the same geometric size. Therefore, the plate area of the capacitor formed by the first conductive region 204 and the second conductive region 205 is also the area of the first conductive region 204 or the second conductive region 205.
  • the first conductive region 204 and the second conductive region 205 may also partially overlap.
  • the plate area of the capacitor formed by the first conductive region 204 and the second conductive region 205 is the area of the overlapping portion of the first conductive region 204 and the second conductive region 205.
  • the shapes of the first conductive region 204 and the second conductive region 205 are both circular shapes having a diameter of 500 ⁇ m. Such a circular structure of the first conductive region 204 and the second conductive region 205 can effectively reduce the deformation generated during processing, thereby improving the stability of the conductive region.
  • the size of the first conductive region 204 and/or the second conductive region 205 may also be other reasonable values, such as other values between 300 micrometers and 700 micrometers, etc.
  • the shape of the regions may also be other reasonable shapes such as a rectangle, a polygon, etc., and the present invention is not limited thereto.
  • the first measurement area 202 is connected to the first conductive area 204, and the second measurement area 203 is connected to the second conductive area 205. Therefore, by applying a probe to the first measurement region 202 and the second measurement region 203, the capacitance capacitance formed by the first conductive region 204 and the second conductive region 205 can be measured.
  • the second measurement area of the structure Since the thickness of the metal layer of the pixel electrode in the existing production process is thin, if the second measurement area of the structure is disposed in the same layer as the pixel electrode, the probe easily pierces the second measurement area when measuring the capacitance. , causing damage to the structure.
  • the metal layer of the capacitor electrode is thick and is not easily pierced by the probe. Therefore, in the embodiment, the first measurement area 202 and the second measurement area 203 are both disposed in the same layer as the capacitor electrode, and the second measurement area 203 is connected to the second conductive area 205 through the via hole. This can ensure that when the probe is applied to the first measurement area 202 and the second measurement area 203, the two measurement areas are not punctured, thereby ensuring the reliability of the capacitor electrode and the measurement result. accuracy.
  • the first measurement region 202 and the second measurement region 203 of the structure provided by the embodiment are not covered by other non-conductive materials.
  • the first measurement area and/or the second measurement area can also be set to The layer is in the same layer as the pixel electrode, and the present invention is not limited thereto.
  • the shapes of the first measurement area 202 and the second measurement area 204 are each a rectangle having a length of 300 ⁇ m and a width of 200 ⁇ m, and the distance between the two is 200 ⁇ m.
  • the shape and size of the first measurement area 202 and the second measurement area 203 are the same, which can reduce the influence on the measurement result due to the difference in geometrical dimensions of the two.
  • the first measurement area 202 and the second measurement area 203 are spaced apart by a certain distance to reduce mutual interference between the two, thereby ensuring the accuracy of the capacitance measurement result.
  • a matching network is disposed between the first measurement area 202 and the first conductive area 204, and between the second measurement area 203 and the second conductive area 205.
  • the matching network can reduce the influence of the metal trace on the measurement result, thereby further improving the accuracy of the measurement result.
  • the first conductive region may be disposed in the same layer as the common electrode of the array substrate, such that there is a liquid crystal layer between the first conductive region and the second conductive region, and the present invention is not limited thereto. this.
  • the structure provided by the embodiment and the corresponding portion of the sub-pixel in the array substrate (for example, the structure formed by the pixel electrode and the common electrode of the sub-pixel, or the pixel electrode and the capacitance of the sub-pixel)
  • the structure formed by the electrodes, etc. has the same structure.
  • the plate area of the capacitor formed according to the structure ie, the overlapping area of the first conductive region and the second conductive region
  • the capacitance value of the corresponding capacitance in the sub-pixel is obtained, thereby realizing the pair of sub-pixels
  • the detection of the corresponding capacitance value in the middle provides a data basis for judging the quality of the sub-pixel and the liquid crystal panel.
  • the present invention also provides a method for obtaining a capacitance value in an array substrate by using the above structure.
  • the capacitance of the storage capacitor formed by the pixel electrode and the capacitor electrode in the array substrate can be obtained by the method.
  • FIG. 4 shows a flow chart of the method.
  • the method provided in this embodiment first forms a structure in the array substrate in step S401.
  • the first conductive region of the structure is in the same layer as the capacitor electrode in the array substrate, and the second conductive region is in the same layer as the pixel electrode in the array substrate, and the first measurement region and the second measurement region are both the same as the first conductive region.
  • Floor Since the thickness of the metal layer where the pixel electrode is located is thin, if the second measurement area of the structure is set to be in the same layer as the pixel electrode, the probe can easily puncture the second measurement area when measuring the capacitance, thereby causing the structure. damage. Where the capacitor electrode is located The metal layer is thick and is not easily pierced by the probe. Therefore, in this embodiment, the first measurement area and the second measurement area are both in the same layer as the capacitor electrode, and are exposed.
  • the first measurement area and/or the second measurement area can also be set to The layer is in the same layer as the pixel electrode, and the present invention is not limited thereto.
  • step S402 the capacitance value C 1 of the capacitance formed by the first conductive region and the second conductive region in the structure is measured by the first measurement region and the second measurement region of the structure formed in step S401.
  • the capacitance value C of a capacitor can usually be calculated by the following expression:
  • ⁇ and ⁇ 0 represent the relative dielectric constant and the vacuum dielectric constant, respectively
  • S represents the overlapping area of the two plates of the capacitor
  • d represents the distance between the two plates of the capacitor.
  • step S401 since the structure formed in step S401 has the same structure as the corresponding portion of the sub-pixel in the array substrate, the relative dielectric constant ⁇ , vacuum dielectric constant ⁇ 0 and distance d of the structure and the sub-pixel are equal. Therefore, after determining the capacitance C 1 of the capacitance formed by the first conductive region and the second conductive region in the structure, according to the overlapping area S 1 of the first conductive region and the second conductive region in the structure, and the sub-pixel The overlapping area S 2 of the pixel electrode and the capacitor electrode can calculate the capacitance C x of the capacitance formed by the pixel electrode and the capacitor electrode of the sub-pixel according to the following expression:
  • the method provided in this embodiment acquires the overlapping area S 1 of the first conductive region and the second conductive region in the structure in step S403, and acquires the overlapping area S 2 of the pixel electrode and the capacitor electrode of the sub-pixel in step S404. .
  • step S405 according to the capacitance value C 1 acquired in step S402, the overlapping area S 1 acquired in step S403, and the overlapping area S 2 acquired in step S404, the expression (2) can be used.
  • the capacitance C x of the capacitance formed by the pixel electrode and the capacitor electrode of the sub-pixel is calculated.
  • a color filter layer exists between the pixel electrode and the capacitor electrode of the sub-pixel.
  • the capacitance of the capacitor formed by the pixel electrode and the capacitor electrode of the sub-pixel is only the dielectric of the color filter layer.
  • the constant is related. Since the dielectric constant of the color filter layer is a function of temperature, the measurement of the production temperature can be realized by measuring the capacitance of the capacitance formed by the pixel electrode and the capacitor electrode of the sub-pixel.
  • the first conductive region in the structure formed in step S401 may also be disposed in the same layer as the common electrode of the sub-pixel, and the final measured capacitance value is The capacitance of the capacitance formed by the pixel electrode of the sub-pixel and the common electrode is not limited thereto.
  • the method for obtaining the capacitance value in the array substrate provided by the embodiment is in the liquid crystal
  • the structure of the sub-pixel structure in the array substrate is formed at a preset position of the panel, and the capacitance value of the corresponding portion in the sub-pixel is determined by measuring the capacitance value formed by the structure.
  • the method realizes the measurement of the capacitance value of the sub-pixel in the liquid crystal panel, thereby providing a data basis for analyzing the performance parameters and the production state of the liquid crystal panel according to the capacitance value.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种用于获取阵列基板中电容容值的结构体及方法，该结构体包括：与阵列基板中的第一导电层同层的第一导电区域（204）；与阵列基板中的第二导电层同层的第二导电区域（205），第二导电区域（205）与第一导电区域（204）部分或全部重叠；与第一导电区域（204）连接的第一测量区域（202）；以及与第二导电区域（205）连接的第二测量区域（203）。该结构体能够实现对子像素中相应电容容值的检测，为判断子像素以及液晶面板的性能和质量提供了数据依据。

Description

一种用于获取阵列基板中电容容值的结构体及方法
相关技术的交叉引用
本申请要求享有2014年12月31日提交的名称为：“一种用于获取阵列基板中电容容值的结构体及方法”的中国专利申请CN201410855647.2的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术领域，具体地说，涉及一种用于获取阵列基板中电容容值的结构体及方法。
背景技术
液晶显示器具有高画质、体积小、重量轻、低电压驱动以及低功率消耗等优点，其现已被广泛地应用于各种IT数码产品中，例如汽车导向系统、工程工作站、监视器、便携式信息终端、电子终端、电子书刊、笔记本计算机以及大型直视式平板电视机等。
传统的液晶面板主要包括薄膜晶体管阵列基板、彩色滤光基板以及设置在这两个基板之间的液晶层。然而，这种显示面板的解析度较差、像素的开口率较低，并且彩色滤波基板与薄膜晶体管阵列基板接合时容易出现对位误差。
近年来，液晶面板技术中又发展出了将彩色滤光层直接整合于薄膜晶体管阵列基板中(Color Filter on Array，简称为COA)的技术。如图1所示，基于COA技术生产的液晶面板主要包括COA基板101、对向基板102以及配置在这两个基板之间的液晶层103。其中，COA基板101包括玻璃基板104、氮化硅绝缘层105、电容电极106、第一氮化硅钝化保护层107、彩色滤光层108、第二氮化硅钝化保护层109和像素电极110。由于COA基板101中已经整合有彩色滤光层108，因此对向基板102此时不含有彩色滤光层。在COA技术中，彩色滤光层是直接形成于薄膜晶体管阵列基板上的，所以彩色滤波基板与薄膜晶体管阵列基板接合时也就不会产生对位误差。此外，COA技术还还能够使得所得到的液晶面板具有更好的解析度和更高的像素开口率。
在COA基板中，彩色滤光层108设置在电容电极106与像素电极110之间。然而，由于彩色滤光层的介电常数是会随温度变化的，因此这也就会导致由存储电极和像素电极 构成的存储电容的电容值不稳定，使得COA基板生产过程中存储电容的电容值无法满足要求。所以就需要一种能够在生产过程中获取阵列基板中存储电容的电容值的装置。
发明内容
本发明所要解决的技术问题是为了解决如何获取阵列基板中电容容值的问题。为了解决上述问题，本发明的实施例首先提供了一种用于获取阵列基板中电容容值的结构体，所述结构体包括：
第一导电区域，其设置为与阵列基板中的第一导电层同层；
第二导电区域，其设置为与所述阵列基板中的第二导电层同层，所述第二导电区域与第一导电区域部分或全部重叠；
第一测量区域，其与所述第一导电区域连接；
第二测量区域，其与所述第二导电区域连接。
根据本发明的一个实施例，所述第一导电层为电容电极所处的导电层，所述第二导电层为像素电极所处的导电层。
根据本发明的一个实施例，所述第一导电层为公共电极所处的导电层，所述第二导电层为像素电极所处的导电层。
根据本发明的一个实施例，所述第一测量区域与第一导电区域同层，且/或，第二测量区域与第二导电区域同层。
根据本发明的一个实施例，所述第二测量区域与第一测量区域同层，其通过过孔与所述第二导电区域连接。
根据本发明的一个实施例，所述第一导电区域和/或第二导电区域的形状为圆形。
根据本发明的一个实施例，所述第一测量区域与第二测量区域的几何尺寸相同。
根据本发明的一个实施例，所述第一测量区域与第二测量区域间隔预设距离。
根据本发明的一个实施例，所述第一导电区域与第一测量区域之间存在第一匹配网络；且/或，
所述第二导电区域与第二测量区域之间存在第二匹配网络。
本发明还提供了一种用于获取阵列基板中电容容值的方法，所述方法包括：
在阵列基板上形成如上任一项所述的结构体；
通过所述结构体中第一测量区域和第二测量区域，测量得到所述结构体中第一导电区域与第二导电区域所形成的电容的容值；
根据所得到的容值和所述第一导电区域与第二导电区域的重叠面积，以及阵列基板 中子像素的像素电极与公共电极或电容电极的重叠面积，计算得到所述子像素的像素电极与公共电极或电容电极所形成的电容的容值。
本发明所提供的结构体与阵列基板中子像素的相应部位(例如，子像素的像素电极与公共电极所形成的结构体，或是子像素的像素电极与电容电极所形成的结构体等)的结构相同。所以测量得到该结构体所形成的电容的容值后，根据该结构体所形成的电容的极板面积(即第一导电区域与第二导电区域的重叠面积)和子像素中相应电容的极板面积(即该子像素的像素电极与公共电极的重叠面积，或是该像素的像素电极与电容电极的重叠面积)，即可得到该子像素中相应电容的容值，从而实现在对子像素中相应电容容值的检测，这为判断该子像素以及液晶面板的质量提供了数据依据。
本发明所提供的获取阵列基板中电容容值的方法在液晶面板的预设位置处形成与阵列基板中子像素结构相同的结构体，通过测量该结构体所形成的电容的容值来确定出子像素中相应部位的电容容值。该方法实现了对液晶面板中子像素中电容容值的测量，为根据电容容值来对液晶面板的性能参数以及生产状态进行分析提供了数据依据。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要的附图做简单的介绍：
图1是基于COA技术的液晶面板的结构示意图；
图2是根据本发明一个实施例的结构体的示意图；
图3是图2所示的结构体中第一区域的结构示意图；
图4是根据本发明一个实施例的获取阵列基板中电容容值的方法的流程图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
同时，在以下说明中，出于解释的目的而阐述了许多具体细节，以提供对本发明实 施例的彻底理解。然而，对本领域的技术人员来说显而易见的是，本发明可以不用这里的具体细节或者所描述的特定方式来实施。
图2示出了本实施例所提供的用于获取阵列基板中电容容值的结构体的示意图。
从图2中可以看出，本实施例所提供的结构体包括区域201、第一测量区域202和第二测量区域203。结合图3所示出的区域201的结构示意图可以看出，本实施例所提供的结构体的区域201包括第一导电区域204和第二导电区域205。本实施例所提供的结构体的结构与阵列基板中子像素的相应部位的结构相同，即结构体的第一导电区域204与阵列基板中的电容电极同层，第二导电区域205与阵列基板中的像素电极同层，第一导电区域204与第二导电区域205之间存在有彩色滤光层206以及钝化保护层。
本实施例中，第一导电区域204与第二导电区域205全部重叠，即二者分布在阵列基板不同材料层的相同位置处，并且二者具有相同的几何尺寸。所以，由第一导电区域204与第二导电区域205所形成的电容的极板面积也就是第一导电区域204或第二导电区域205的面积。
需要说明的是，在本发明的其他实施例中，第一导电区域204与第二导电区域205也可以部分重叠。此时，由第一导电区域204与第二导电区域205所形成的电容的极板面积也就是第一导电区域204与第二导电区域205的重叠部分的面积。
本实施例中，第一导电区域204与第二导电区域205的形状均为直径为500微米的圆形。第一导电区域204和第二导电区域205的这种圆形结构能够有效减小其在加工过程中所产生的形变，从而提高导电区域的稳定性。然而，在本发明的其他实施例中，第一导电区域204和/或第二导电区域205的尺寸也可以为其他合理值，例如300微米到700微米之间的其他值等，同时，这两个区域的形状也可以为其他合理形状，例如矩形、多边形等，本发明不限于此。
第一测量区域202与第一导电区域204连接，第二测量区域203与第二导电区域205连接。所以，通过对第一次测量区域202与第二测量区域203施加探针，即可实现对第一导电区域204与第二导电区域205所形成的电容容值的测量。
由于现有的生产工艺中像素电极所处的金属层厚度较薄，因此如果结构体的第二测量区域设置为与像素电极同层，那么测量电容时探针很容易将第二测量区域刺破，从而造成结构体的损坏。电容电极所处的金属层厚度较厚，不易被探针刺破。所以本实施例中，第一测量区域202和第二测量区域203均设置为与电容电极同层，第二测量区域203通过过孔与第二导电区域205连接。这样能够保证对第一测量区域202和第二测量区域203施加探针时，这两个测量区域不会被刺破，从而保障了电容电极的可靠性以及测量结果的 准确性。
为了方便施加探针，本实施例所提供的结构体的第一测量区域202和第二测量区域203的上方(即靠近液晶层的方向)均无其他非导电介质覆盖。
当然，在本发明的其他实施例中，如果像素电极所处的金属层的物理强度能够使得该金属层不易被探针刺破，那么第一测量区域和/或第二测量区域也可以设置为与像素电极同层，本发明不限于此。
本实施例中，第一测量区域202和第二测量区域204的形状均为长300微米、宽200微米的矩形，同时二者之间的间隔距离为200微米。第一测量区域202与第二测量区域203的形状和尺寸相同，这样能够减小因二者几何尺寸不同而对测量结果造成的影响。第一测量区域202与第二测量区域203间隔一定距离能够减小二者之间的相互干扰，从而保证电容测量结果的准确性。
本实施例中，第一测量区域202与第一导电区域204之间，以及第二测量区域203与第二导电区域205之间，均配置有相应的匹配网络。匹配网络能够减小金属走线对测量结果造成的影响，从而进一步地提高测量结果的准确性。
当然，在本发明的其他实施例中，第一导电区域还可以设置为与阵列基板的公共电极同层，这样有第一导电区域与第二导电区域之间则为液晶层，本发明不限于此。
从上述描述中可以看出，本实施例所提供的结构体与阵列基板中子像素的相应部位(例如，子像素的像素电极与公共电极所形成的结构，或是子像素的像素电极与电容电极所形成的结构等)的结构相同。所以测量得到该结构体所形成的电容的容值后，根据该结构体所形成的电容的极板面积(即第一导电区域与第二导电区域的重叠面积)和子像素中相应电容的极板面积(即该子像素的像素电极与公共电极的重叠面积，或是该像素的像素电极与电容电极的重叠面积)，即可得到该子像素中相应电容的容值，从而实现在对子像素中相应电容容值的检测，这为判断该子像素以及液晶面板的质量提供了数据依据。
本发明还提供了一种利用上述结构体来获取阵列基板中电容容值的方法。本实施例中，通过该方法能够获取到阵列基板中由像素电极和电容电极所构成的存储电容的容值，图4示出了该方法的流程图。
如图4所示，本实施例所提供的方法首先在步骤S401中在阵列基板中形成一结构体。其中，该结构体的第一导电区域与阵列基板中的电容电极同层，第二导电区域与阵列基板中的像素电极同层，第一测量区域和第二测量区域均与第一导电区域同层。由于像素电极所处的金属层厚度较薄，因此如果结构体的第二测量区域设为与像素电极同层，那么测量电容时探针很容易将第二测量区域刺破，从而造成结构体的损坏。而电容电极所处的 金属层厚度较厚，不易被探针刺破。所以本实施例中，第一测量区域和第二测量区域均与电容电极同层，并裸露在外。
当然，在本发明的其他实施例中，如果像素电极所处的金属层的物理强度能够使得该金属层不易被探针刺破，那么第一测量区域和/或第二测量区域也可以设置为与像素电极同层，本发明不限于此。
在步骤S402中，通过步骤S401中所形成的结构体的第一测量区域和第二测量区域，测量得到该结构体中第一导电区域与第二导电区域所形成的电容的容值C1。
电容的容值C通常可以通过如下表达式计算得到：
Figure PCTCN2015070692-appb-000001
其中，ε和ε0分别表示相对介电常数和真空介电常数，S表示电容的两个极板的重叠面积，d表示电容的两个极板之间的距离。
本实施例中，由于步骤S401中所形成的结构体与阵列基板中子像素的相应部位的结构相同，所以该结构体与子像素的相对介电常数ε、真空介电常数ε0和距离d相等。因此，当确定出结构体中第一导电区域与第二导电区域所形成的电容的容值C1后，根据结构体中第一导电区域与第二导电区域的重叠面积S1，以及子像素的像素电极与电容电极的重叠面积S2，根据如下表达式便可以计算得到子像素的像素电极与电容电极所形成的电容的容值Cx：
Figure PCTCN2015070692-appb-000002
因此本实施例所提供的方法在步骤S403中获取结构体中第一导电区域与第二导电区域的重叠面积S1，并在步骤S404中获取子像素的像素电极与电容电极的重叠面积S2。
最后在步骤S405中，根据步骤S402中所获取的容值C1、步骤S403中所获取的重叠面积S1，以及在步骤S404中所获取的重叠面积S2，利用表达式(2)即可计算得到子像素的像素电极与电容电极所形成的电容的容值Cx。
子像素的像素电极与电容电极之间存在彩色滤光层，对于某一型号的阵列基板来说，子像素的像素电极与电容电极所构成的电容的容值仅与彩色滤光层的介电常数有关。而彩色滤光层的介电常数与温度存在函数关系，所以通过测量子像素的像素电极与电容电极所构成的电容的容值，还能够实现对生产温度的监控。
当然，在本发明的其他实施例中，在步骤S401中所形成结构体中的第一导电区域也可以设置为与子像素的公共电极同层，此时最终测量得到的电容容值则是该子像素的像素电极与公共电极所构成的电容的容值，本发明不限于此。
从上述描述中可以看出，本实施例所提供的获取阵列基板中电容容值的方法在液晶 面板的预设位置处形成与阵列基板中子像素结构相同的结构体，通过测量该结构体所形成的电容容值来确定出子像素中相应部位的电容容值。该方法实现了对液晶面板中子像素中电容容值的测量，从而为根据电容容值来对液晶面板的性能参数以及生产状态进行分析提供了数据基础。
应该理解的是，本发明所公开的实施例不限于这里所公开的特定结构、处理步骤或材料，而应当延伸到相关领域的普通技术人员所理解的这些特征的等同替代。还应当理解的是，在此使用的术语仅用于描述特定实施例的目的，而并不意味着限制。
说明书中提到的“一个实施例”或“实施例”意指结合实施例描述的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，说明书通篇各个地方出现的短语“一个实施例”或“实施例”并不一定均指同一个实施例。
为了方便，在此使用的多个项目、结构单元、组成单元和/或材料可出现在共同列表中。然而，这些列表应解释为该列表中的每个元素分别识别为单独唯一的成员。因此，在没有反面说明的情况下，该列表中没有一个成员可仅基于它们出现在共同列表中便被解释为相同列表的任何其它成员的实际等同物。另外，在此还可以连同针对各元件的替代一起来参照本发明的各种实施例和示例。应当理解的是，这些实施例、示例和替代并不解释为彼此的等同物，而被认为是本发明的单独自主的代表。
此外，所描述的特征、结构或特性可以任何其他合适的方式结合到一个或多个实施例中。在上面的描述中，提供一些具体的细节，例如长度、宽度、形状等，以提供对本发明的实施例的全面理解。然而，相关领域的技术人员将明白，本发明无需上述一个或多个具体的细节便可实现，或者也可采用其它方法、组件、材料等实现。在其它示例中，周知的结构、材料或操作并未详细示出或描述以免模糊本发明的各个方面。
虽然上述示例用于说明本发明在一个或多个应用中的原理，但对于本领域的技术人员来说，在不背离本发明的原理和思想的情况下，明显可以在形式上、用法及实施的细节上作各种修改而不用付出创造性劳动。因此，本发明由所附的权利要求书来限定。

Claims (18)

  1. 一种用于获取阵列基板中电容容值的结构体，其中，所述结构体包括：
    第一导电区域，其设置为与阵列基板中的第一导电层同层；
    第二导电区域，其设置为与所述阵列基板中的第二导电层同层，所述第二导电区域与第一导电区域部分或全部重叠；
    第一测量区域，其与所述第一导电区域连接；
    第二测量区域，其与所述第二导电区域连接。
  2. 如权利要求1所述的结构体，其中，所述第一导电层为电容电极所处的导电层，所述第二导电层为像素电极所处的导电层。
  3. 如权利要求1所述的结构体，其中，所述第一导电层为公共电极所处的导电层，所述第二导电层为像素电极所处的导电层。
  4. 如权利要求1所述的结构体，其中，所述第一测量区域与第一导电区域同层，且/或，第二测量区域与第二导电区域同层。
  5. 如权利要求1所述的结构体，其中，所述第二测量区域与第一测量区域同层，其通过过孔与所述第二导电区域连接。
  6. 如权利要求1所述的结构体，其中，所述第一导电区域和/或第二导电区域的形状为圆形。
  7. 如权利要求1所述的结构体，其中，所述第一测量区域与第二测量区域的几何尺寸相同。
  8. 如权利要求1所述的结构体，其中，所述第一测量区域与第二测量区域间隔预设距离。
  9. 如权利要求1所述的结构体，其中，
    所述第一导电区域与第一测量区域之间存在第一匹配网络；且/或，
    所述第二导电区域与第二测量区域之间存在第二匹配网络。
  10. 一种用于获取阵列基板中电容容值的方法，其中，所述方法包括：
    在阵列基板上形成结构体，所述结构体包括：
    第一导电区域，其设置为与阵列基板中的第一导电层同层；
    第二导电区域，其设置为与所述阵列基板中的第二导电层同层，所述第二导电区域与第一导电区域部分或全部重叠；
    第一测量区域，其与所述第一导电区域连接；
    第二测量区域，其与所述第二导电区域连接；
    通过所述结构体中第一测量区域和第二测量区域，测量得到所述结构体中第一导电区域与第二导电区域所形成的电容的容值；
    根据所得到的容值和所述第一导电区域与第二导电区域的重叠面积，以及阵列基板中子像素的像素电极与公共电极或电容电极的重叠面积，计算得到所述子像素的像素电极与公共电极或电容电极所形成的电容的容值。
  11. 如权利要求10所述的方法，其中，所述第一导电层为电容电极所处的导电层，所述第二导电层为像素电极所处的导电层。
  12. 如权利要求10所述的方法，其中，所述第一导电层为公共电极所处的导电层，所述第二导电层为像素电极所处的导电层。
  13. 如权利要求10所述的方法，其中，所述第一测量区域与第一导电区域同层，且/或，第二测量区域与第二导电区域同层。
  14. 如权利要求10所述的方法，其中，所述第二测量区域与第一测量区域同层，其通过过孔与所述第二导电区域连接。
  15. 如权利要求10所述的方法，其中，所述第一导电区域和/或第二导电区域的形状为圆形。
  16. 如权利要求10所述的方法，其中，所述第一测量区域与第二测量区域的几何尺寸相同。
  17. 如权利要求10所述的方法，其中，所述第一测量区域与第二测量区域间隔预设距离。
  18. 如权利要求10所述的方法，其中，
    所述第一导电区域与第一测量区域之间存在第一匹配网络；且/或，
    所述第二导电区域与第二测量区域之间存在第二匹配网络。
PCT/CN2015/070692 2014-12-31 2015-01-14 一种用于获取阵列基板中电容容值的结构体及方法 Ceased WO2016106850A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/418,604 US9678398B2 (en) 2014-12-31 2015-01-14 Structure and method for obtaining capacitance in array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410855647.2A CN104536169B (zh) 2014-12-31 2014-12-31 一种用于获取阵列基板中电容容值的结构体及方法
CN201410855647.2 2014-12-31

Publications (1)

Publication Number Publication Date
WO2016106850A1 true WO2016106850A1 (zh) 2016-07-07

Family

ID=52851722

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/070692 Ceased WO2016106850A1 (zh) 2014-12-31 2015-01-14 一种用于获取阵列基板中电容容值的结构体及方法

Country Status (3)

Country Link
US (1) US9678398B2 (zh)
CN (1) CN104536169B (zh)
WO (1) WO2016106850A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106094292A (zh) * 2016-08-17 2016-11-09 京东方科技集团股份有限公司 一种液晶盒的检测装置、检测方法及显示面板的制备方法
CN107329307B (zh) * 2017-08-16 2021-02-09 上海天马微电子有限公司 显示装置
CN112631030B (zh) * 2020-12-03 2022-04-01 Tcl华星光电技术有限公司 阵列基板及测量阵列基板电容的方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001051620A (ja) * 1999-08-05 2001-02-23 Asia Electronics Inc 画素容量検査装置
US20040100287A1 (en) * 2002-08-29 2004-05-27 International Business Machines Corporation Apparatus and method for inspecting array substrate
CN1743858A (zh) * 2004-09-01 2006-03-08 安捷伦科技公司 Tft阵列试验方法以及试验装置
CN1773442A (zh) * 2004-11-09 2006-05-17 夏普株式会社 用于测量电容的装置和传感器阵列
US20060279321A1 (en) * 2003-04-12 2006-12-14 Uwe Ruppender Control system and control method for checking the function of liquid crystal displays
CN101140744A (zh) * 2006-09-07 2008-03-12 恩益禧电子股份有限公司 液晶显示器和驱动电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4051190B2 (ja) * 2000-10-31 2008-02-20 シャープ株式会社 表示装置の製造方法、表示装置用基板および測定システム
JP2004094169A (ja) * 2002-09-04 2004-03-25 Toshiba Matsushita Display Technology Co Ltd コモン回路及びコモン電圧調整方法
JP2006163202A (ja) * 2004-12-09 2006-06-22 Agilent Technol Inc アレイ基板の検査方法及び検査装置
JP5203293B2 (ja) * 2009-05-21 2013-06-05 株式会社ジャパンディスプレイウェスト 表示装置および電子機器
CN103246092B (zh) * 2013-04-28 2015-08-19 京东方科技集团股份有限公司 阵列基板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001051620A (ja) * 1999-08-05 2001-02-23 Asia Electronics Inc 画素容量検査装置
US20040100287A1 (en) * 2002-08-29 2004-05-27 International Business Machines Corporation Apparatus and method for inspecting array substrate
US20060279321A1 (en) * 2003-04-12 2006-12-14 Uwe Ruppender Control system and control method for checking the function of liquid crystal displays
CN1743858A (zh) * 2004-09-01 2006-03-08 安捷伦科技公司 Tft阵列试验方法以及试验装置
CN1773442A (zh) * 2004-11-09 2006-05-17 夏普株式会社 用于测量电容的装置和传感器阵列
CN101140744A (zh) * 2006-09-07 2008-03-12 恩益禧电子股份有限公司 液晶显示器和驱动电路

Also Published As

Publication number Publication date
CN104536169B (zh) 2018-01-12
US20160246141A1 (en) 2016-08-25
US9678398B2 (en) 2017-06-13
CN104536169A (zh) 2015-04-22

Similar Documents

Publication Publication Date Title
CN105511679A (zh) 玻璃基板、触控显示屏及触控压力计算方法
CN103558942B (zh) 触摸屏及其制造方法
CN104460116B (zh) 一种液晶显示面板、其制作方法及显示装置
WO2017008472A1 (zh) Ads阵列基板及其制作方法、显示器件
US10684175B2 (en) Substrate and display device
US20160349582A1 (en) Liquid Crystal Display Panel and Color Film Substrate thereof
WO2017117962A1 (zh) 压力感应面板及检测方法、3d触控面板、触控显示面板
US20160266678A1 (en) Capacitive touch panel, method of determining touch position and display device
WO2016106850A1 (zh) 一种用于获取阵列基板中电容容值的结构体及方法
CN105549241B (zh) 显示用基板、显示面板、封框胶涂布质量检测方法及装置
US20160268316A1 (en) Array substrate and manufacturing method thereof, and display device
US20200090564A1 (en) Display panel and method for detecting display panel
WO2017177649A1 (en) Array substrate, display panel and display apparatus having the same, and fabricating method thereof
US9590055B2 (en) Thin film transistor, method for manufacturing the same, array substrate, and display device
US20170168607A1 (en) In-cell touch screen, display device and method for manufacturing the same
US10379685B2 (en) Touch electrode structure, touch pad, and method for fabricating the touch electrode structure
CN110718559B (zh) 阵列基板、制备方法及显示面板
US9823515B2 (en) Substrate and an array substrate
CN110261318B (zh) 测量导电层的导电性能的方法及其系统
US9786693B2 (en) Thin film transistor substrate
CN105093651B (zh) 一种彩膜基板及其制作方法、显示装置
CN204515307U (zh) 显示面板
CN108061983A (zh) 配向膜边界到显示区的距离的测量方法及测量装置
US9305342B2 (en) Method for acquiring a boundary line of an alignment film and method for inspecting the alignment film
US20160216583A1 (en) Liquid crystal display panel, manufacturing method for the same, and liquid crystal display device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14418604

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15874543

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15874543

Country of ref document: EP

Kind code of ref document: A1