WO2016106831A1 - 一种检测电路及显示装置 - Google Patents

一种检测电路及显示装置 Download PDF

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Publication number
WO2016106831A1
WO2016106831A1 PCT/CN2015/070541 CN2015070541W WO2016106831A1 WO 2016106831 A1 WO2016106831 A1 WO 2016106831A1 CN 2015070541 W CN2015070541 W CN 2015070541W WO 2016106831 A1 WO2016106831 A1 WO 2016106831A1
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Prior art keywords
transistors
transistor
line
group
lines
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English (en)
French (fr)
Inventor
王醉
郭晋波
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/435,466 priority Critical patent/US9489877B2/en
Publication of WO2016106831A1 publication Critical patent/WO2016106831A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes

Definitions

  • the present invention relates to the field of electronics, and in particular, to a detection circuit and a display device.
  • the outer trace of the shorting bar/shorting bar is usually designed on the outer side of the pixel area, and the scan line is respectively led out to the outer trace according to the odd and even numbers. That is, the odd and even scan lines on the entire display panel are each shorted together at the periphery of the display panel.
  • This design is to check whether there is a short circuit or an open circuit in the display panel by using different electrical signals for the odd and even scan lines in the detection process of the TFT (Thin Film Transistor) process.
  • the data signal can also detect other types of defects.
  • the shorting bar is also used in the lighting detection process in the process of the liquid crystal cell, and is disconnected or removed after the detection, so that it does not affect the normal display of the finished product.
  • the charge sharing scan line is charged with the N+th even after The scan lines are connected (where N is a positive integer), so that both are odd or even in order, so that the short-circuit strips which are respectively extracted by the above-mentioned parity are unable to detect the short-circuit phenomenon in the TFT process section. It can only be detected by means of Cell lighting or even finished product inspection, which will result in a decrease in product yield.
  • the technical problem to be solved by the present invention is to provide a detecting circuit and a display device for detecting an abnormal phenomenon occurring in a display device efficiently and accurately, thereby improving the yield of the display device.
  • the present invention provides a detecting circuit for detecting an abnormal condition of a display device, the detecting circuit including first to third detecting lines, first and second control lines, and first to sixth group transistors, The first to sixth group of transistors are connected to the first to sixth scan lines of the display device, wherein each group of transistors includes a first transistor and a second transistor, and the control terminals of the first transistor are connected to the a first control line, a first end of the first transistor is connected to one of the first to third detection lines, and a control end of the second transistor is connected to the second control line a first end of the second transistor is connected to one of the first to third detecting lines, and a second end of the first transistor is connected to a second end of the second transistor of the same group.
  • connection nodes of the first to third detection lines constitute a pre-configuration a set of points, the set of preset points being [(3, 3), (2, 2), (3, 1), (2, 3), (3, 2), (2, 1)], wherein
  • the numbers 1, 2, and 3 represent first to third detection lines
  • the first digit of the point represents detection of the first end of the first transistor and the first digit representation a line connection
  • the second digit of the point indicating that the first end of the second transistor is connected to the detection line represented by the second number
  • the first or second is controlled by the first and second control lines
  • the transistor is closed to detect an abnormal condition of the display device.
  • the first ends of the first and second transistors of the first group of transistors are both connected to the third detecting line, and the second ends of the first and second transistors of the first group of transistors are connected to the a first scan line, a first end of the first and second transistors of the second group of transistors are connected to the second detection line, and a second end of the first and second transistors of the second group of transistors Connected to the second scan line, a first end of the first transistor of the third group of transistors is connected to a third detection line, and a first end of the second transistor of the third group of transistors is connected to the a detection line, a second end of the first and second transistors of the third group of transistors are connected to the third scan line, and a first end of the first transistor of the fourth group of transistors is connected to the a second detecting line, a first end of the second transistor of the fourth group of transistors is connected to the third detecting line, and a second end of the first and second transistors of the fourth group of transistors
  • the first to sixth groups of transistors are sequentially arranged along a preset direction, and the first to sixth scan lines are sequentially arranged along the predetermined direction.
  • the first transistor and the second transistor of the first to sixth groups of transistors are N-type transistors, and the control terminals, the first terminals and the second terminals of the first and second transistors are respectively N-type transistors. Gate, source and drain.
  • the first to sixth scans are first to sixth charging scan lines.
  • the present invention also provides a display device including first to sixth scan lines, first to third detection lines, first and second control lines, and first to sixth group transistors, the first to sixth groups Transistors are connected to the first to sixth scan lines, wherein each set of transistors includes a first transistor and a second transistor, a control terminal of the first transistor is connected to the first control line, the first a first end of the transistor is connected to one of the first to third detecting lines, a control end of the second transistor is connected to the second control line, and a first end of the second transistor Connected to one of the first to third detection lines, the second end of the first transistor is connected to the second end of the same group of second transistors, and is connected to the first to sixth a scan line in the scan line, a set of transistors corresponding to one scan line, and a connection node of the first end of the first and second transistors and the first to third detection lines form a preset point set,
  • the set of preset points is [(3,3), (2,2), (3,1),
  • the first ends of the first and second transistors of the first group of transistors are both connected to the third detecting line, and the second ends of the first and second transistors of the first group of transistors are connected to the a first scan line, a first end of the first and second transistors of the second group of transistors are connected to the second detection line, and a second end of the first and second transistors of the second group of transistors Connected to the second scan line, a first end of the first transistor of the third group of transistors is connected to a third detection line, and a first end of the second transistor of the third group of transistors is connected to the a detection line, a second end of the first and second transistors of the third group of transistors are connected to the third scan line, and the first of the fourth group of transistors a first end of the transistor is coupled to the second detection line, a first end of the second transistor of the fourth group of transistors is coupled to the third detection line, and the first and second transistors of the fourth group of transistors
  • the first to sixth groups of transistors are sequentially arranged along a preset direction, and the first to sixth scan lines are sequentially arranged along the predetermined direction.
  • the first to sixth scan lines are first to sixth charge scan lines
  • the display device further includes first to sixth charge share scan lines, first and second additional charge scan lines, and first a second additional charge sharing scan line and first to sixth pixel rows, the first to sixth charge sharing scan lines respectively corresponding to the first to sixth scan lines and the first to sixth pixel rows, a first scan line is further connected to the first additional charge sharing scan line, the second scan line is further connected to the second additional charge share scan line, the first charge share scan line is further connected to the first a third scan line, the second charge share scan line is further connected to the fourth scan line, the third charge share scan line is connected to the fifth scan line, and the fourth charge share scan line is connected to the a sixth scan line connected to the first additional charge scan line, the sixth charge share scan line being connected to the second additional charge scan line, wherein the first to the first Six scan lines and the first and the first Charging additional scan lines are sequentially received signals.
  • the first transistor and the second transistor of the first to sixth groups of transistors are N-type transistors, and the control terminals, the first terminals and the second terminals of the first and second transistors are respectively N-type transistors. Gate, source and drain.
  • the detecting circuit of the present invention includes first to third detecting lines, first and second control lines, and first to sixth group transistors, and the first to sixth group transistors are connected to the first to the display device a sixth scan line, wherein each group of transistors includes a first transistor and a second transistor, a control terminal of the first transistor is connected to the first control line, and a first end of the first transistor is connected to the One of the first to third detection lines, the control terminal of the second transistor is connected to the second control a first terminal of the second transistor is connected to one of the first to third detection lines, and a second end of the first transistor is connected to a second end of the second transistor of the same group And connected to one of the first to sixth scan lines, one set of transistors corresponding to one scan line, and first ends of the first and second transistors of the first to sixth sets of transistors
  • the connection nodes of the first to third detection lines constitute a preset point set, and the preset point set is [(3, 3), (2, 2), (3, 1), (2, 3),
  • Figure 1 is a schematic view of a conventional display device
  • FIG. 2 is a schematic diagram of application of a detection circuit according to a preferred embodiment of the first aspect of the present invention
  • FIG. 3 is a first schematic diagram of a specific example of a detection circuit according to a preferred embodiment of the first aspect of the present invention.
  • FIG. 4 is a second schematic diagram of a specific example of a detection circuit according to a preferred embodiment of the first aspect of the present invention.
  • FIG. 5 is a schematic diagram of a display device according to a second embodiment of the present invention.
  • a first embodiment of the present invention provides a detection circuit 100.
  • Said The detection circuit 100 is for detecting a short circuit condition of the display device.
  • the detection circuit 100 includes first to third detection lines 11-13, first and second control lines 14 and 15, and first to sixth sets of transistors 21-26.
  • the first to sixth sets of transistors 21-26 are connected to the first to sixth scan lines 31-36 of the display device.
  • Each of the sets of transistors includes a first transistor T1 and a second transistor T2.
  • the control terminals of the first transistor T1 are each connected to the first control line 14.
  • the first end of the first transistor T1 is connected to one of the first to third detecting lines 11-13.
  • the control terminals of the second transistor T2 are both connected to the second control line 15.
  • the first end of the second transistor T2 is connected to one of the first to third detecting lines 11-13.
  • the second end of the first transistor T1 is connected to the second end of the second transistor T2 of the same group, and is connected to one of the first to sixth scan lines 31-36, and one set of transistors corresponds to a scan line, the first ends of the first and second transistors T1 and T2 of the first to sixth sets of transistors 21-26 and the connection nodes of the first to third detection lines form a preset point set.
  • the set of preset points is [(3,3), (2,2), (3,1), (2,3), (3,2), (2,1)].
  • the numbers 1, 2 and 3 represent first to third detection lines
  • the first digit of the point represents the first end of the first transistor and the first digit representation a detection line connection
  • the second digit of the point indicating that the first end of the second transistor is connected to the detection line represented by the second number
  • the first and second control lines 14 and 15 are used to control the The first transistor T1 or the second transistor T2 is closed to detect an abnormal condition of the display device.
  • the first transistor T1 and the second transistor T2 are controlled to be in different states by the first and second control lines 14 and 15. That is, when the first transistor T1 is closed, the second transistor T2 is turned off; when the first transistor T1 is turned off, the second transistor T2 is turned off.
  • the first to sixth scan lines 31-36 are first to sixth charge scan lines.
  • the display device further includes first to sixth charge sharing scan lines and first to sixth pixel rows.
  • the first shared scan line corresponds to the first charging scan line 31 and corresponds to the first pixel row.
  • the second shared scan line corresponds to the second charging scan line 32 and corresponds to the second pixel row.
  • the third shared scan line corresponds to the third charging scan line 33 and corresponds to the third pixel row.
  • the fourth shared scan line corresponds to the fourth charge scan line 34 and corresponds to the fourth pixel row.
  • the fifth shared scan line corresponds to the fifth charge scan line 35 and corresponds to the fifth pixel row.
  • the sixth shared scan line corresponds to the sixth charge scan line 36 and corresponds to the sixth pixel row.
  • the first to sixth shared scan lines and the latter N+ even charge scan line connections (where N is a positive integer).
  • a point at which the first to sixth scan lines 31-36 are connected to the first to third detection lines 11-13 may constitute the set of preset points [(3, 3), (2, 2) , (3, 1), (2, 3), (3, 2), (2, 1)], and the first transistor T1 is turned off by the first and second control lines 14 and 15, The second transistor T2 is closed, so that the charging scan line and the charge sharing scan line, which are short-circuited, can be connected to different detection lines. Once a short circuit occurs, it can be accurately detected by the detection line, thereby improving the yield of the display device.
  • the first transistor T1 when detecting other types of abnormalities, the first transistor T1 can be controlled to be closed by the first and second control lines 14 and 15, and the second transistor T2 is turned off, so that the first to The sixth scan lines 31-36 are only connected to the two detection lines, so that one detection can be idle, and the display device can be detected by using three detection lines at the same time, which saves the detection time and improves the detection efficiency.
  • the first detecting line 11 is idle, and the detecting device connected to the first detecting line 11 does not need to be reused, thereby reducing the detecting cost.
  • the first ends of the first and second transistors T1 and T2 of the first group of transistors 21 are both connected to the third detecting line 13.
  • the second ends of the first and second transistors T1 and T2 of the first group of transistors 21 are both connected to the first scan line 31.
  • the first ends of the first and second transistors T1 and T2 of the second group of transistors 22 are both connected to the second detecting line 12.
  • the second ends of the first and second transistors T1 and T2 of the second group of transistors 22 are both connected to the second scan line 32.
  • the first end of the first transistor T1 of the third group of transistors 23 is connected to the third detection line 13.
  • a first end of the second transistor T2 of the third group of transistors 23 is connected to the first detection line 11.
  • the second ends of the first and second transistors T1 and T2 of the third group of transistors 23 are both connected to the third scan line 33.
  • a first end of the first transistor T1 of the fourth group of transistors 24 is coupled to the second detection line 12.
  • a first end of the second transistor T2 of the fourth group of transistors 24 is coupled to the third detection line 13.
  • the second ends of the first and second transistors T1 and T2 of the fourth group of transistors 24 are both connected to the fourth scan line 34.
  • a first end of the first transistor T1 of the fifth group of transistors 25 is connected to the third detecting line 13.
  • a first end of the second transistor T2 of the fifth group of transistors 25 is coupled to the second detection line 12.
  • the second ends of the first and second transistors T1 and T2 of the fifth group of transistors 25 are connected to the fifth scan line 35.
  • a first end of the first transistor T1 of the sixth group of transistors 26 is coupled to the second detection line 12.
  • a first end of the second transistor T2 of the sixth group of transistors 26 is coupled to the first detection line 11.
  • the first and second transistors T1 and T2 of the sixth group of transistors 26 The second ends are each connected to the sixth scan line 36.
  • the first transistor T1 is in an off state and the second transistor T2 is in a closed state.
  • the first scan line 31 is connected to the third detection line 13; the second scan line 32 is connected to the second detection line 12; the third scan line 33 is connected to the first detection line 11
  • the fourth scan line 34 is connected to the third detection line 13; the fifth scan line 35 is connected to the second detection line 12; the sixth scan line 36 is connected to the first detection line 11.
  • the first transistor T1 and the second transistor T2 of the first to sixth group transistors 21-26 are all N-type transistors.
  • the control terminal, the first terminal and the second terminal of the first and second transistors T1 and T2 are respectively a gate, a source and a drain of the N-type transistor.
  • the first transistor T1 is controlled to be in an off state by the first and second control lines 14 and 15, and the second transistor T2 is in a closed state, that is, the first control line 14 outputs a low level signal to the The control terminal of the first transistor T1, the second control line 15 outputs a high level signal to the control terminal of the second transistor T2, then the first transistor T1 is in an off state, and the second transistor T2 It is in a closed state.
  • the first and second control lines 14 and 15 control the first A transistor T1 is in an off state, and the second transistor T2 is in a closed state, that is, the first control line 14 outputs a high level signal to the control end of the first transistor T1, and the second control line 15 outputs A low level signal is sent to the control terminal of the second transistor T2, then the first transistor T1 is in an off state, and the second transistor T2 is in a closed state.
  • the first to sixth groups of transistors 21-26 are arranged in sequence along a predetermined direction.
  • the first to sixth scan lines 31-36 are arranged in sequence along the predetermined direction.
  • the preset direction is an order in which the first to sixth scan lines 31-36 sequentially receive detection signals, that is, the first to sixth scan lines 31-36 sequentially receive detection signals.
  • the first transistor T1 is controlled to be in a closed state by the first and second control lines 14 and 15, and the second transistor T2 is in an off state.
  • the first scan line 31 is connected to the third detection line 13; the second scan line 32 is connected to the second detection line 12; the third scan line 33 is connected to the third detection line 13
  • the fourth scan line 34 is connected to the second detection line 12; the fifth scan line 35 is connected to the third detection line 13; the sixth scan line 36 is connected to the second detection line 12.
  • the display device can be detected by the second and third detection lines 12 and 13.
  • the first detecting line 11 is idle, and it is no longer necessary to simultaneously detect the display device by using three detecting lines, thereby saving detection time and improving detection efficiency. At the same time, the first detecting line 11 is idle, and the detecting device connected to the first detecting line 11 does not need to be reused, thereby reducing the detecting cost.
  • the first transistor T1 and the second transistor T2 of the first to sixth group transistors 21-26 are all N-type transistors.
  • the control terminal, the first terminal and the second terminal of the first and second transistors T1 and T2 are respectively a gate, a source and a drain of the N-type transistor.
  • the first transistor T1 is controlled to be in a closed state by the first and second control lines 14 and 15, and the second transistor T2 is in an off state, that is, the first control line 14 outputs a high level signal to the The control terminal of the first transistor T1, the second control line 15 outputs a low level signal to the control terminal of the second transistor T2, then the first transistor T1 is in a closed state, and the second transistor T2 is in a closed state. Disconnected state.
  • the first and second control lines 14 and 15 control the first A transistor T1 is in a closed state, and the second transistor T2 is in an off state, that is, the first control line 14 outputs a low level signal to the control end of the first transistor T1, and the second control line 15 outputs A high level signal is sent to the control terminal of the second transistor T2, then the first transistor T1 is in a closed state, and the second transistor T2 is in an off state.
  • the display device includes not only the first to sixth charge scans, the first to sixth charge share scan lines, and the first to sixth pixel rows, and the display device includes a plurality of charge scan lines and if Dry charge sharing scan lines and several pixel rows.
  • the number of the charging scan lines, the charge sharing scan lines, and the pixel rows are the same, and are all in one-to-one correspondence.
  • the first to sixth charging scan lines are each used as one scan line cycle unit. Therefore, the display device includes a plurality of circulation units, and each of the circulation units is connected to the first to third detection lines 11-13 in the same manner.
  • the first to sixth group transistors 21-26 also function as one transistor cycle unit to correspond to the scan line cycle unit.
  • the detection circuit 100 also includes the same number of transistor cycle units and is in one-to-one correspondence with the scan line cycle unit.
  • a second embodiment of the present invention provides a display device 200.
  • the display device 200 includes first to sixth scan lines 31-36 and the detection circuit 100 provided by the first aspect described above.
  • the detection circuit 100 is connected to the first to sixth scan lines 31-36.
  • the detecting circuit 100 includes first to third detecting lines 11-13, first and second control lines 14 and 15 and first to sixth group transistors 21-26.
  • the first to sixth sets of transistors 21-26 are connected to the first to sixth scan lines 31-36 of the display device.
  • Each of the sets of transistors includes a first transistor T1 and a second transistor T2.
  • the control terminals of the first transistor T1 are each connected to the first control line 14.
  • the first end of the first transistor T1 is connected to one of the first to third detecting lines 11-13.
  • the control terminals of the second transistor T2 are both connected to the second control line 15.
  • the first end of the second transistor T2 is connected to one of the first to third detecting lines 11-13.
  • the second end of the first transistor T1 is connected to the second end of the second transistor T2 of the same group, and is connected to one of the first to sixth scan lines 31-36, and one set of transistors corresponds to a scan line, the first ends of the first and second transistors T1 and T2 of the first to sixth sets of transistors 21-26 and the connection nodes of the first to third detection lines form a preset point set.
  • the set of preset points is [(3,3), (2,2), (3,1), (2,3), (3,2), (2,1)].
  • the numbers 1, 2 and 3 represent first to third detection lines
  • the first digit of the point represents the first end of the first transistor and the first digit representation a detection line connection
  • the second digit of the point indicating that the first end of the second transistor is connected to the detection line represented by the second number
  • the first and second control lines 14 and 15 are used to control the The first transistor T1 or the second transistor T2 is closed to detect an abnormal condition of the display device.
  • the first and second control lines 14 and 15 are controlled.
  • the first transistor T1 and the second transistor T2 are in different states. That is, when the first transistor T1 is closed, the second transistor T2 is turned off; when the first transistor T1 is turned off, the second transistor T2 is turned off.
  • the first to sixth scan lines 31-36 are first to sixth charge scan lines.
  • the display device 200 further includes first to sixth charge sharing scan lines 211-216, first and second additional charge scan lines 237 and 238, first and second additional charge sharing scan lines 217 and 218, and first to The sixth pixel row 241-246.
  • the first to sixth charge sharing scan lines 211-216 correspond to the first to sixth scan lines 31-36 and the first to sixth pixel rows 241-246, respectively.
  • the first scan line 31 is also connected to the first additional charge sharing scan line 217.
  • the second scan line 32 is also coupled to the second additional charge sharing scan line 218.
  • the first charge sharing scan line 211 is also connected to the third scan line 33.
  • the second charge sharing scan line 212 is also coupled to the fourth scan line 34.
  • the third charge sharing scan line 213 is connected to the fifth scan line 35.
  • the fourth charge sharing scan line 214 is connected to the sixth scan line 36.
  • the fifth charge sharing scan line 215 is connected to the first additional charge scan line 237.
  • the sixth charge sharing scan line 216 is coupled to the second additional charge scan line 238.
  • the first to sixth scan lines and the first and second additional charge scan lines sequentially receive signals.
  • the first shared scan line corresponds to the first charging scan line 31 and corresponds to the first pixel row.
  • the second shared scan line corresponds to the second charging scan line 32 and corresponds to the second pixel row.
  • the third shared scan line corresponds to the third charging scan line 33 and corresponds to the third pixel row.
  • the fourth shared scan line corresponds to the fourth charge scan line 34 and corresponds to the fourth pixel row.
  • the fifth shared scan line corresponds to the fifth charge scan line 35 and corresponds to the fifth pixel row.
  • the sixth shared scan line corresponds to the sixth charge scan line 36 and corresponds to the sixth pixel row.
  • the first to sixth shared scan lines are connected to the N+th charge scan line (where N is a positive integer).
  • a point at which the first to sixth scan lines 31-36 are connected to the first to third detection lines 11-13 may constitute the set of preset points [(3, 3), (2, 2) , (3, 1), (2, 3), (3, 2), (2, 1)], and the first transistor T1 is turned off by the first and second control lines 14 and 15, The second transistor T2 is closed, so that the charging scan line and the charge sharing scan line, which are short-circuited, can be connected to different detection lines. Once a short circuit occurs, it can be accurately detected by the detection line, thereby improving the yield of the display device.
  • the first and second control lines may pass 14 and 15 control the first transistor T1 to be closed, and the second transistor T2 is turned off, so that the first to sixth scan lines 31-36 are connected only to two detection lines, so that one detection can be idled, reducing The output of the detection signal reduces the equipment that is connected to the detection line, which reduces the detection cost and thus reduces the production capacity.
  • the first ends of the first and second transistors T1 and T2 of the first group of transistors 21 are both connected to the third detecting line 13.
  • the second ends of the first and second transistors T1 and T2 of the first group of transistors 21 are both connected to the first scan line 31.
  • the first ends of the first and second transistors T1 and T2 of the second group of transistors 22 are both connected to the second detecting line 12.
  • the second ends of the first and second transistors T1 and T2 of the second group of transistors 22 are both connected to the second scan line 32.
  • the first end of the first transistor T1 of the third group of transistors 23 is connected to the third detection line 13.
  • a first end of the second transistor T2 of the third group of transistors 23 is connected to the first detection line 11.
  • the second ends of the first and second transistors T1 and T2 of the third group of transistors 23 are both connected to the third scan line 33.
  • a first end of the first transistor T1 of the fourth group of transistors 24 is coupled to the second detection line 12.
  • a first end of the second transistor T2 of the fourth group of transistors 24 is coupled to the third detection line 13.
  • the second ends of the first and second transistors T1 and T2 of the fourth group of transistors 24 are both connected to the fourth scan line 34.
  • a first end of the first transistor T1 of the fifth group of transistors 25 is connected to the third detecting line 13.
  • a first end of the second transistor T2 of the fifth group of transistors 25 is coupled to the second detection line 12.
  • the second ends of the first and second transistors T1 and T2 of the fifth group of transistors 25 are connected to the fifth scan line 35.
  • a first end of the first transistor T1 of the sixth group of transistors 26 is coupled to the second detection line 12.
  • a first end of the second transistor T2 of the sixth group of transistors 26 is coupled to the first detection line 11.
  • the second ends of the first and second transistors T1 and T2 of the sixth group of transistors 26 are both connected to the sixth scan line 36.
  • the first to sixth groups of transistors 21-26 are arranged in sequence along a predetermined direction.
  • the first to sixth scan lines 31-36 are arranged in sequence along the predetermined direction.
  • the preset direction is an order in which the first to sixth scan lines 31-36 sequentially receive detection signals, that is, the first to sixth scan lines 31-36 sequentially receive detection signals.
  • the display device 200 includes not only the first to sixth scans 31-36, the first to sixth charge share scan lines 211-216, and the first to sixth pixel rows 241-246, and the display device 200 includes a plurality of charge scan lines and a plurality of charge share scan lines and a plurality of pixel rows.
  • the charging scan The number of lines, the charge-sharing scan lines, and the pixel rows are the same, and each has a one-to-one correspondence.
  • the first to sixth charging scan lines are each used as one scan line cycle unit. Therefore, the display device 200 includes a plurality of circulation units, and each of the circulation units is connected to the first to third detection lines 11-13 in the same manner.
  • the first to sixth group transistors 21-26 also function as one transistor cycle unit to correspond to the scan line cycle unit.
  • the detection circuit 100 also includes the same number of transistor cycle units and is in one-to-one correspondence with the scan line cycle unit.
  • the first transistor T1 and the second transistor T2 of the first to sixth group transistors 21-26 are all N-type transistors.
  • the control terminal, the first terminal and the second terminal of the first and second transistors T1 and T2 are respectively a gate, a source and a drain of the N-type transistor.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种检测电路包括第一至第三检测线、第一及第二控制线及第一至第六组晶体管，第一至第六组晶体管连接至显示装置的第一至第六扫描线，每组晶体管均包括第一及第二晶体管，第一及第二晶体管的控制端均分别连接至第一及第二控制线，其第一端分别连接至第一至第三检测线中的一根，其第二端连接至同组的第二晶体管的第二端，并分别连接至第一至第六扫描线中的一根，第一及第二晶体管的第一端与第一至第三检测线的连接节点构成点集合[(3,3),(2,2),(3,1),(2,3),(3,2),(2,1)]，数字1-3代表第一至第三检测线，点的第一及第二位数字分别为第一及第二晶体管的第一端与该第一及第二位数字代表的检测线连接。该检测电路提高了显示装置的良率。

Description

一种检测电路及显示装置
本发明要求2014年12月31日递交的发明名称为“一种检测电路及显示装置”的申请号201410849907.5的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及电子领域，尤其涉及一种检测电路及显示装置。
背景技术
在传统的显示面板的线路设计中，通常会在像素区域的外侧设计短路条/短路棒(Shorting Bar)的外围走线，并将扫描线按照奇数和偶数分别引出至该外围走线。即，整个显示面板上的奇数和偶数扫描线在所述显示面板的外围各自短接在一起。这种设计是为了在TFT(Thin Film Transistor，薄膜晶体管)制程的检测环节中，可以通过给奇数和偶数扫描线不同的电讯号来检查所述显示面板内是否存在短路或断路的情况，配合不同的数据信号还可以检查出其他类型的不良。短路条也会被用于液晶盒制程中的点灯检测环节，并在检测后被断开或去除，使其不会影响到成品的正常显示。
如图1所示，如果同一行的充电扫描线103和电荷共享扫描线104间发生短路(第二短路位置102或第一短路位置101)，由于该电荷共享扫描线与后面第N+偶数的充电扫描线相连(其中，N为正整数)，使得二者在顺序上皆为奇数或偶数，那么仅通过上述奇偶分别引出的短路条的检测方式是无法在TFT制程段将短路现象检出的，只能依靠Cell点灯甚至成品检测的方式方能检出，因此会导致产品良率降低。
发明内容
本发明所要解决的技术问题在于提供一种检测电路及显示装置，以高效且精准地对显示装置中出现的异常现象进行检测，从而提高显示装置的良率。
为了实现上述目的，本发明实施方式提供如下技术方案：
本发明供了一种检测电路，用于对显示装置的异常状况进行检测，所述检测电路包括第一至第三检测线、第一及第二控制线及第一至第六组晶体管，所述第一至第六组晶体管连接至所述显示装置的第一至第六扫描线，其中，每组晶体管均包括第一晶体管及第二晶体管，所述第一晶体管的控制端均连接至所述第一控制线，所述第一晶体管的第一端连接至所述第一至第三检测线中的一根检测线，所述第二晶体管的控制端均连接至所述第二控制线，所述第二晶体管的第一端连接至所述第一至第三检测线中的一根检测线，所述第一晶体管的第二端连接至同组的第二晶体管的第二端，并连接至所述第一至第六扫描线中的一根扫描线，一组晶体管对应一个扫描线，所述第一至第六组晶体管的第一及第二晶体管的第一端与所述第一至第三检测线的连接节点构成预设点集合，所述预设点集合为[(3,3),(2,2),(3,1),(2,3),(3,2),(2,1)]，其中，在所述预设点集合中，数字1、2及3代表第一至第三检测线，该点的第一位数字表示所述第一晶体管的第一端与该第一位数字代表的检测线连接，该点的第二位数字表示所述第二晶体管的第一端与该第二数字代表的检测线连接，通过所述第一及第二控制线来控制所述第一或第二晶体管闭合来对所述显示装置的异常状况进行检测。
其中，所述第一组晶体管的第一及第二晶体管的第一端均连接至所述第三检测线，所述第一组晶体管的第一及第二晶体管的第二端均连接至所述第一扫描线，所述第二组晶体管的第一及第二晶体管的第一端均连接至所述第二检测线，所述第二组晶体管的第一及第二晶体管的第二端均连接至所述第二扫描线，所述第三组晶体管的第一晶体管的第一端连接至第三检测线，所述第三组晶体管的第二晶体管的第一端连接至所述第一检测线，所述第三组晶体管的第一及第二晶体管的第二端均连接至所述第三扫描线，所述第四组晶体管的第一晶体管的第一端连接至所述第二检测线，所述第四组晶体管的第二晶体管的第一端连接至所述第三检测线，所述第四组晶体管的第一及第二晶体管的第二端均连接至所述第四扫描线，所述第五组晶体管的第一晶体管的第一端连接至所述第三检测线，所述第五组晶体管的第二晶体管的第一端连接至所述第二检测线，所述第五组晶体管的第一及第二晶体管的第二端连接所述第五扫描线，所述第六组晶体管的第一晶体管的第一端连接至所述第二检测线，所述第六组晶体管的第二晶体管的第一端连接至所述第一检测线，所述第六组晶体管的第一 及第二晶体管的第二端均连接至所述第六扫描线。
其中，所述第一至第六组晶体管沿着预设方向依次排布设置，所述第一至第六扫描线沿着所述预设方向依次排布设置。
其中，所述第一至第六组晶体管的第一晶体管及第二晶体管均为N型晶体管，所述第一及第二晶体管的控制端、第一端及第二端分别为N型晶体管的栅极、源极及漏极。
其中，所述第一至第六扫描为第一至第六充电扫描线。
本发明还提供一种显示装置，包括第一至第六扫描线、第一至第三检测线、第一及第二控制线及第一至第六组晶体管，所述第一至第六组晶体管连接至所述第一至第六扫描线，其中，每组晶体管均包括第一晶体管及第二晶体管，所述第一晶体管的控制端均连接至所述第一控制线，所述第一晶体管的第一端连接至所述第一至第三检测线中的一根检测线，所述第二晶体管的控制端均连接至所述第二控制线，所述第二晶体管的第一端连接至所述第一至第三检测线中的一根检测线，所述第一晶体管的第二端连接至同组的第二晶体管的第二端，并连接至所述第一至第六扫描线中的一根扫描线，一组晶体管对应一个扫描线，所述第一及第二晶体管的第一端与所述第一至第三检测线的连接节点构成预设点集合，所述预设点集合为[(3,3),(2,2),(3,1),(2,3),(3,2),(2,1)]，其中，在所述预设点集合中，数字1、2及3代表第一至第三检测线，该点的第一位数字表示所述第一晶体管的第一端与该第一位数字代表的检测线连接，该点的第二位数字表示所述第二晶体管的第一端与该第二数字代表的检测线连接，通过所述第一及第二控制线来控制所述第一晶体管或第二晶体管闭合来对所述显示装置的异常状况进行检测。
其中，所述第一组晶体管的第一及第二晶体管的第一端均连接至所述第三检测线，所述第一组晶体管的第一及第二晶体管的第二端均连接至所述第一扫描线，所述第二组晶体管的第一及第二晶体管的第一端均连接至所述第二检测线，所述第二组晶体管的第一及第二晶体管的第二端均连接至所述第二扫描线，所述第三组晶体管的第一晶体管的第一端连接至第三检测线，所述第三组晶体管的第二晶体管的第一端连接至所述第一检测线，所述第三组晶体管的第一及第二晶体管的第二端均连接至所述第三扫描线，所述第四组晶体管的第一 晶体管的第一端连接至所述第二检测线，所述第四组晶体管的第二晶体管的第一端连接至所述第三检测线，所述第四组晶体管的第一及第二晶体管的第二端均连接至所述第四扫描线，所述第五组晶体管的第一晶体管的第一端连接至所述第三检测线，所述第五组晶体管的第二晶体管的第一端连接至所述第二检测线，所述第五组晶体管的第一及第二晶体管的第二端端连接所述第五扫描线，所述第六组晶体管的第一晶体管的第一端连接至所述第二检测线，所述第六组晶体管的第二晶体管的第一端连接至所述第一检测线，所述第六组晶体管的第一及第二晶体管的第二端均连接至所述第六扫描线。
其中，所述第一至第六组晶体管沿着预设方向依次排布设置，所述第一至第六扫描线沿着所述预设方向依次排布设置。
其中，所述第一至第六扫描线为第一至第六充电扫描线，所述显示装置还包括第一至第六电荷共享扫描线、第一及第二额外充电扫描线、第一及第二额外电荷共享扫描线及第一至六像素行，所述第一至第六电荷共享扫描线分别对应所述第一至第六扫描线及所述第一至第六像素行，所述第一扫描线还连接至所述第一额外电荷共享扫描线，所述第二扫描线还连接至所述第二额外电荷共享扫描线，所述第一电荷共享扫描线还连接至所述第三扫描线，所述第二电荷共享扫描线还连接至所述第四扫描线，所述第三电荷共享扫描线连接至所述第五扫描线，所述第四电荷共享扫描线连接至所述第六扫描线，所述第五电荷共享扫描线连接至第一额外充电扫描线，所述第六电荷共享扫描线连接至所述第二额外充电扫描线，其中，所述第一至第六扫描线及所述第一及第二额外充电扫描线依次接收信号。
其中，所述第一至第六组晶体管的第一晶体管及第二晶体管均为N型晶体管，所述第一及第二晶体管的控制端、第一端及第二端分别为N型晶体管的栅极、源极及漏极。
本发明所述检测电路包括第一至第三检测线、第一及第二控制线及第一至第六组晶体管，所述第一至第六组晶体管连接至所述显示装置的第一至第六扫描线，其中，每组晶体管均包括第一晶体管及第二晶体管，所述第一晶体管的控制端均连接至所述第一控制线，所述第一晶体管的第一端连接至所述第一至第三检测线中的一根检测线，所述第二晶体管的控制端均连接至所述第二控制 线，所述第二晶体管的第一端连接至所述第一至第三检测线中的一根检测线，所述第一晶体管的第二端连接至同组的第二晶体管的第二端，并连接至所述第一至第六扫描线中的一根扫描线，一组晶体管对应一个扫描线，所述第一至第六组晶体管的第一及第二晶体管的第一端与所述第一至第三检测线的连接节点构成预设点集合，所述预设点集合为[(3,3),(2,2),(3,1),(2,3),(3,2),(2,1)]，其中，在所述预设点集合中，数字1、2及3代表第一至第三检测线，该点的第一位数字表示所述第一晶体管的第一端与该第一位数字代表的检测线连接，该点的第二位数字表示所述第二晶体管的第一端与该第二数字代表的检测线连接，通过所述第一及第二控制线来控制所述第一或第二晶体管闭合来对所述显示装置的异常状况进行检测。因此，本发明实现了高效精准地对所述显示装置进行检测，从而提高了显示装置的良率。
附图说明
为了更清楚地说明本发明的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以如这些附图获得其他的附图。
图1是传统的显示装置的示意图；
图2是本发明第一方案较佳实施方式提供的检测电路的应用示意图；
图3是本发明第一方案较佳实施方式提供的检测电路的一具体实例的第一示意图；
图4是本发明第一方案较佳实施方式提供的检测电路的一具体实例的第二示意图；
图5是本发明第二方案较佳实施方式提供的显示装置的示意图。
具体实施方式
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述。
请参阅图2，本发明第一方案较佳实施方式提供一种检测电路100。所述 检测电路100用于对显示装置的短路状况进行检测。所述检测电路100包括第一至第三检测线11-13、第一及第二控制线14及15及第一至第六组晶体管21-26。所述第一至第六组晶体管21-26连接至所述显示装置的第一至第六扫描线31-36。其中，每组晶体管均包括第一晶体管T1及第二晶体管T2。所述第一晶体管T1的控制端均连接至所述第一控制线14。所述第一晶体管T1的第一端连接至所述第一至第三检测线11-13中的一根检测线。所述第二晶体管T2的控制端均连接至所述第二控制线15。所述第二晶体管T2的第一端连接至所述第一至第三检测线11-13中的一根检测线。所述第一晶体管T1的第二端连接至同组的第二晶体管T2的第二端，并连接至所述第一至第六扫描线31-36中的一根扫描线，一组晶体管对应一个扫描线，所述第一至第六组晶体管21-26的第一及第二晶体管T1及T2的第一端与所述第一至第三检测线的连接节点构成预设点集合，所述预设点集合为[(3,3),(2,2),(3,1),(2,3),(3,2),(2,1)]。其中，在所述预设点集合中，数字1、2及3代表第一至第三检测线，该点的第一位数字表示所述第一晶体管的第一端与该第一位数字代表的检测线连接，该点的第二位数字表示所述第二晶体管的第一端与该第二数字代表的检测线连接，通过所述第一及第二控制线14及15来控制所述第一晶体管T1或第二晶体管T2闭合来对所述显示装置的异常状况进行检测。
需要说明的是，在进行检测时，通过所述第一及第二控制线14及15控制所述第一晶体管T1及所述第二晶体管T2处于不同的状态。即当所述第一晶体管T1闭合时，所述第二晶体管T2断开；当所述第一晶体管T1断开时，所述第二晶体管T2闭合。
在本实施方式中，所述第一至第六扫描线31-36为第一至第六充电扫描线。其中，在显示装置中，所述显示装置还包括第一至第六电荷共享扫描线及第一至第六像素行。所述第一共享扫描线对应第一充电扫描线31，且对应第一像素行。所述第二共享扫描线对应第二充电扫描线32，且对应第二像素行。所述第三共享扫描线对应第三充电扫描线33，且对应第三像素行。所述第四共享扫描线对应第四充电扫描线34，且对应第四像素行。所述第五共享扫描线对应第五充电扫描线35，且对应第五像素行。所述第六共享扫描线对应第六充电扫描线36，且对应第六像素行。且所述第一至第六共享扫描线与后面第 N+偶数的充电扫描线连接(其中，N为正整数)。当所述第一至第六扫描线31-36与所述第一至第三检测线11-13的连接的点可以构成所述预设点集合[(3,3),(2,2),(3,1),(2,3),(3,2),(2,1)]，且通过所述第一及第二控制线14及15使得所述第一晶体管T1断开，所述第二晶体管T2闭合，可以使得会发生短路的充电扫描线及电荷共享扫描线均连接不同的检测线。一旦发生短路现象，则可以通过检测线准确的检测出来，从而提高了显示装置的良率。
另外，当对其他类型的异常进行检测时，可以通过所述第一及第二控制线14及15控制所述第一晶体管T1闭合，所述第二晶体管T2断开，使得所述第一至第六扫描线31-36只与两根检测线进行连接，从而可以闲置一条检测，而无需再同时利用三根检测线对所述显示装置进行检测，节约了检测时间，提高了检测效率。同时，所述第一检测线11被闲置，则所述第一检测线11连接的检测设备也无需再利用，从而降低了检测成本。
具体地，所述第一组晶体管21的第一及第二晶体管T1及T2的第一端均连接至所述第三检测线13。所述第一组晶体管21的第一及第二晶体管T1及T2的第二端均连接至所述第一扫描线31。所述第二组晶体管22的第一及第二晶体管T1及T2的第一端均连接至所述第二检测线12。所述第二组晶体管22的第一及第二晶体管T1及T2的第二端均连接至所述第二扫描线32。所述第三组晶体管23的第一晶体管T1的第一端连接至第三检测线13。所述第三组晶体管23的第二晶体管T2的第一端连接至所述第一检测线11。所述第三组晶体管23的第一及第二晶体管T1及T2的第二端均连接至所述第三扫描线33。所述第四组晶体管24的第一晶体管T1的第一端连接至所述第二检测线12。所述第四组晶体管24的第二晶体管T2的第一端连接至所述第三检测线13。所述第四组晶体管24的第一及第二晶体管T1及T2的第二端均连接至所述第四扫描线34。所述第五组晶体管25的第一晶体管T1的第一端连接至所述第三检测线13。所述第五组晶体管25的第二晶体管T2的第一端连接至所述第二检测线12。所述第五组晶体管25的第一及第二晶体管T1及T2的第二端连接所述第五扫描线35。所述第六组晶体管26的第一晶体管T1的第一端连接至所述第二检测线12。所述第六组晶体管26的第二晶体管T2的第一端连接至所述第一检测线11。所述第六组晶体管26的第一及第二晶体管T1及T2的 第二端均连接至所述第六扫描线36。
请参阅图3，现举一实例说明如何检测所述显示装置是否存在短路异常状况，则在所述显示装置的量产初期时，通过所述第一及第二控制线14及15控制所述第一晶体管T1处于断开状态，所述第二晶体管T2处于闭合状态。所述第一扫描线31连接至所述第三检测线13；所述第二扫描线32连接至所述第二检测线12；所述第三扫描线33连接至所述第一检测线11；所述第四扫描线34连接至所述第三检测线13；所述第五扫描线35连接至所述第二检测线12；所述第六扫描线36连接至所述第一检测线11。假设对应所述第一扫描线31的电荷共享扫描线与所述第一扫描线31发生短路，其中，对应所述第一扫描线31的电荷共享扫描线连接至所述第三扫描线33。此时，所述第三扫描线33连接至所述第一检测线11，而所述第一扫描线31连接至所述第三扫描线13。因此，通过所述第一检测线11及所述第三检测线33即可准确地检测出所述第一扫描线31与其对应的电荷共享扫描线存在短路现象。
需要说明的是，在本实施方式中，所述第一至第六组晶体管21-26的第一晶体管T1及第二晶体管T2均为N型晶体管。所述第一及第二晶体管T1及T2的控制端、第一端及第二端分别为N型晶体管的栅极、源极及漏极。通过所述第一及第二控制线14及15控制所述第一晶体管T1处于断开状态，所述第二晶体管T2处于闭合状态即为所述第一控制线14输出低电平信号至所述第一晶体管T1的控制端，所述第二控制线15输出高电平信号至所述第二晶体管T2的控制端，则所述第一晶体管T1处于断开状态，所述第二晶体管T2处于闭合状态。
同理，当所述第一至第六组晶体管21-26的第一晶体管T1及第二晶体管T2均为P型晶体管时，通过所述第一及第二控制线14及15控制所述第一晶体管T1处于断开状态，所述第二晶体管T2处于闭合状态即为所述第一控制线14输出高电平信号至所述第一晶体管T1的控制端，所述第二控制线15输出低电平信号至所述第二晶体管T2的控制端，则所述第一晶体管T1处于断开状态，所述第二晶体管T2处于闭合状态。
在本实施方式中，所述第一至第六组晶体管21-26沿着预设方向依次排布设置。所述第一至第六扫描线31-36沿着所述预设方向依次排布设置。
需要说明的是，所述预设方向是所述第一至第六扫描线31-36的依次接收检测信号的顺序，即所述第一至第六扫描线31-36依次接收检测信号。
请参阅图4，现举一实例说明如何高效地检测所述显示装置异常状况。当所述显示装置制程条件稳定后，通过所述第一及第二控制线14及15控制所述第一晶体管T1处于闭合状态，所述第二晶体管T2处于断开状态。所述第一扫描线31连接至所述第三检测线13；所述第二扫描线32连接至所述第二检测线12；所述第三扫描线33连接至所述第三检测线13；所述第四扫描线34连接至所述第二检测线12；所述第五扫描线35连接至所述第三检测线13；所述第六扫描线36连接至所述第二检测线12。则通过所述第二及第三检测线12及13即可对所述显示装置进行检测。因此，所述第一检测线11被闲置，而无需再同时利用三根检测线对所述显示装置进行检测，节约了检测时间，提高了检测效率。同时，所述第一检测线11被闲置，则所述第一检测线11连接的检测设备也无需再利用，从而降低了检测成本。
需要说明的是，在本实施方式中，所述第一至第六组晶体管21-26的第一晶体管T1及第二晶体管T2均为N型晶体管。所述第一及第二晶体管T1及T2的控制端、第一端及第二端分别为N型晶体管的栅极、源极及漏极。通过所述第一及第二控制线14及15控制所述第一晶体管T1处于闭合状态，所述第二晶体管T2处于断开状态即为所述第一控制线14输出高电平信号至所述第一晶体管T1的控制端，所述第二控制线15输出低电平信号至所述第二晶体管T2的控制端，则所述第一晶体管T1处于闭合状态，所述第二晶体管T2处于断开状态。
同理，当所述第一至第六组晶体管21-26的第一晶体管T1及第二晶体管T2均为P型晶体管时，通过所述第一及第二控制线14及15控制所述第一晶体管T1处于闭合状态，所述第二晶体管T2处于断开状态即为所述第一控制线14输出低电平信号至所述第一晶体管T1的控制端，所述第二控制线15输出高电平信号至所述第二晶体管T2的控制端，则所述第一晶体管T1处于闭合状态，所述第二晶体管T2处于断开状态。
需要说明的是，所述显示装置不仅包括第一至第六充电扫描、第一至第六电荷共享扫描线及第一至第六像素行，所述显示装置包括若干充电扫描线及若 干电荷共享扫描线及若干像素行。所述充电扫描线、所述电荷共享扫描线及像素行的数量相同，且均一一对应。在本实施方式中，所述第一至第六充电扫描线均作为一个扫描线循环单元。故，所述显示装置包括多个循环单元，且每个循环单元与所述第一至第三检测线11-13的连接方式相同。当然，在所述检测电路100中，所述第一至第六组晶体管21-26同样作为一个晶体管循环单元来对应所述扫描线循环单元。当所述显示装置包括多个扫描线循环单元时，所述检测电路100也包括相同数量的晶体管循环单元，且与所述扫描线循环单元一一对应。
请参阅图5，本发明第二方案较佳实施方式提供一种显示装置200。所述显示装置200包括第一至第六扫描线31-36及上述第一方案提供的检测电路100。所述检测电路100连接至所述第一至第六扫描线31-36。
具体地，所述检测电路100包括第一至第三检测线11-13、第一及第二控制线14及15及第一至第六组晶体管21-26。所述第一至第六组晶体管21-26连接至所述显示装置的第一至第六扫描线31-36。其中，每组晶体管均包括第一晶体管T1及第二晶体管T2。所述第一晶体管T1的控制端均连接至所述第一控制线14。所述第一晶体管T1的第一端连接至所述第一至第三检测线11-13中的一根检测线。所述第二晶体管T2的控制端均连接至所述第二控制线15。所述第二晶体管T2的第一端连接至所述第一至第三检测线11-13中的一根检测线。所述第一晶体管T1的第二端连接至同组的第二晶体管T2的第二端，并连接至所述第一至第六扫描线31-36中的一根扫描线，一组晶体管对应一个扫描线，所述第一至第六组晶体管21-26的第一及第二晶体管T1及T2的第一端与所述第一至第三检测线的连接节点构成预设点集合，所述预设点集合为[(3,3),(2,2),(3,1),(2,3),(3,2),(2,1)]。其中，在所述预设点集合中，数字1、2及3代表第一至第三检测线，该点的第一位数字表示所述第一晶体管的第一端与该第一位数字代表的检测线连接，该点的第二位数字表示所述第二晶体管的第一端与该第二数字代表的检测线连接，通过所述第一及第二控制线14及15来控制所述第一晶体管T1或第二晶体管T2闭合来对所述显示装置的异常状况进行检测。
需要说明的是，在进行检测时，通过所述第一及第二控制线14及15控制 所述第一晶体管T1及所述第二晶体管T2处于不同的状态。即当所述第一晶体管T1闭合时，所述第二晶体管T2断开；当所述第一晶体管T1断开时，所述第二晶体管T2闭合。
在本实施方式中，所述第一至第六扫描线31-36为第一至第六充电扫描线。所述显示装置200还包括第一至第六电荷共享扫描线211-216、第一及第二额外充电扫描线237及238、第一及第二额外电荷共享扫描线217及218及第一至第六像素行241-246。所述第一至第六电荷共享扫描线211-216分别对应所述第一至第六扫描线31-36及第一至第六像素行241-246。所述第一扫描线31还连接至所述第一额外电荷共享扫描线217。所述第二扫描线32还连接至所述第二额外电荷共享扫描线218。所述第一电荷共享扫描线211还连接至所述第三扫描线33。所述第二电荷共享扫描线212还连接至所述第四扫描线34。所述第三电荷共享扫描线213连接至所述第五扫描线35。所述第四电荷共享扫描线214连接至所述第六扫描线36。所述第五电荷共享扫描线215连接至第一额外充电扫描线237。所述第六电荷共享扫描线216连接至所述第二额外充电扫描线238。其中，所述第一至第六扫描线及所述第一及第二额外充电扫描线依次接收信号。
具体地，所述第一共享扫描线对应第一充电扫描线31，且对应第一像素行。所述第二共享扫描线对应第二充电扫描线32，且对应第二像素行。所述第三共享扫描线对应第三充电扫描线33，且对应第三像素行。所述第四共享扫描线对应第四充电扫描线34，且对应第四像素行。所述第五共享扫描线对应第五充电扫描线35，且对应第五像素行。所述第六共享扫描线对应第六充电扫描线36，且对应第六像素行。且所述第一至第六共享扫描线与后面第N+偶数的充电扫描线连接(其中，N为正整数)。当所述第一至第六扫描线31-36与所述第一至第三检测线11-13的连接的点可以构成所述预设点集合[(3,3),(2,2),(3,1),(2,3),(3,2),(2,1)]，且通过所述第一及第二控制线14及15使得所述第一晶体管T1断开，所述第二晶体管T2闭合，可以使得会发生短路的充电扫描线及电荷共享扫描线均连接不同的检测线。一旦发生短路现象，则可以通过检测线准确的检测出来，从而提高了显示装置的良率。
另外，当对其他类型的异常进行检测时，可以通过所述第一及第二控制线 14及15控制所述第一晶体管T1闭合，所述第二晶体管T2断开，使得所述第一至第六扫描线31-36只与两根检测线进行连接，从而可以闲置一条检测，减少了检测信号的输出，减少了接入检测线的设备，降低了检测成本，进而降低了产能。
具体地，所述第一组晶体管21的第一及第二晶体管T1及T2的第一端均连接至所述第三检测线13。所述第一组晶体管21的第一及第二晶体管T1及T2的第二端均连接至所述第一扫描线31。所述第二组晶体管22的第一及第二晶体管T1及T2的第一端均连接至所述第二检测线12。所述第二组晶体管22的第一及第二晶体管T1及T2的第二端均连接至所述第二扫描线32。所述第三组晶体管23的第一晶体管T1的第一端连接至第三检测线13。所述第三组晶体管23的第二晶体管T2的第一端连接至所述第一检测线11。所述第三组晶体管23的第一及第二晶体管T1及T2的第二端均连接至所述第三扫描线33。所述第四组晶体管24的第一晶体管T1的第一端连接至所述第二检测线12。所述第四组晶体管24的第二晶体管T2的第一端连接至所述第三检测线13。所述第四组晶体管24的第一及第二晶体管T1及T2的第二端均连接至所述第四扫描线34。所述第五组晶体管25的第一晶体管T1的第一端连接至所述第三检测线13。所述第五组晶体管25的第二晶体管T2的第一端连接至所述第二检测线12。所述第五组晶体管25的第一及第二晶体管T1及T2的第二端连接所述第五扫描线35。所述第六组晶体管26的第一晶体管T1的第一端连接至所述第二检测线12。所述第六组晶体管26的第二晶体管T2的第一端连接至所述第一检测线11。所述第六组晶体管26的第一及第二晶体管T1及T2的第二端均连接至所述第六扫描线36。
在本实施方式中，所述第一至第六组晶体管21-26沿着预设方向依次排布设置。所述第一至第六扫描线31-36沿着所述预设方向依次排布设置。
需要说明的是，所述预设方向是所述第一至第六扫描线31-36的依次接收检测信号的顺序，即所述第一至第六扫描线31-36依次接收检测信号。
需要说明的是，所述显示装置200不仅包括第一至第六扫描31-36、第一至第六电荷共享扫描线211-216及第一至第六像素行241-246，所述显示装置200包括若干充电扫描线及若干电荷共享扫描线及若干像素行。所述充电扫描 线、所述电荷共享扫描线及像素行的数量相同，且均一一对应。在本实施方式中，所述第一至第六充电扫描线均作为一个扫描线循环单元。故，所述显示装置200包括多个循环单元，且每个循环单元与所述第一至第三检测线11-13的连接方式相同。当然，在所述检测电路100中，所述第一至第六组晶体管21-26同样作为一个晶体管循环单元来对应所述扫描线循环单元。当所述显示装置200包括多个扫描线循环单元时，所述检测电路100也包括相同数量的晶体管循环单元，且与所述扫描线循环单元一一对应。
在本实施方式中，所述第一至第六组晶体管21-26的第一晶体管T1及第二晶体管T2均为N型晶体管。所述第一及第二晶体管T1及T2的控制端、第一端及第二端分别为N型晶体管的栅极、源极及漏极。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (10)

  1. 一种检测电路，用于对显示装置的异常状况进行检测，其中：所述检测电路包括第一至第三检测线、第一及第二控制线及第一至第六组晶体管晶体管，所述第一至第六组晶体管连接至所述显示装置的第一至第六扫描线，其中，每组晶体管均包括第一晶体管及第二晶体管，所述第一晶体管的控制端均连接至所述第一控制线，所述第一晶体管的第一端连接至所述第一至第三检测线中的一根检测线，所述第二晶体管的控制端均连接至所述第二控制线，所述第二晶体管的第一端连接至所述第一至第三检测线中的一根检测线，所述第一晶体管的第二端连接至同组的第二晶体管的第二端，并连接至所述第一至第六扫描线中的一根扫描线，一组晶体管对应一个扫描线，所述第一至第六组晶体管的第一及第二晶体管的第一端与所述第一至第三检测线的连接节点构成预设点集合，所述预设点集合为[(3,3),(2,2),(3,1),(2,3),(3,2),(2,1)]，其中，在所述预设点集合中，数字1、2及3代表第一至第三检测线，该点的第一位数字表示所述第一晶体管的第一端与该第一位数字代表的检测线连接，该点的第二位数字表示所述第二晶体管的第一端与该第二数字代表的检测线连接，通过所述第一及第二控制线来控制所述第一或第二晶体管闭合来对所述显示装置的异常状况进行检测。
  2. 如权利要求1所述的检测电路，其中，所述第一组晶体管的第一及第二晶体管的第一端均连接至所述第三检测线，所述第一组晶体管的第一及第二晶体管的第二端均连接至所述第一扫描线，所述第二组晶体管的第一及第二晶体管的第一端均连接至所述第二检测线，所述第二组晶体管的第一及第二晶体管的第二端均连接至所述第二扫描线，所述第三组晶体管的第一晶体管的第一端连接至第三检测线，所述第三组晶体管的第二晶体管的第一端连接至所述第一检测线，所述第三组晶体管的第一及第二晶体管的第二端均连接至所述第三扫描线，所述第四组晶体管的第一晶体管的第一端连接至所述第二检测线，所述第四组晶体管的第二晶体管的第一端连接至所述第三检测线，所述第四组晶体管的第一及第二晶体管的第二端均连接至所述第四扫描线，所述第五组晶体管的第一晶体管的第一端连接至所述第三检测线，所述第五组晶体管的第二晶体 管的第一端连接至所述第二检测线，所述第五组晶体管的第一及第二晶体管的第二端连接所述第五扫描线，所述第六组晶体管的第一晶体管的第一端连接至所述第二检测线，所述第六组晶体管的第二晶体管的第一端连接至所述第一检测线，所述第六组晶体管的第一及第二晶体管的第二端均连接至所述第六扫描线。
  3. 如权利要求2所述的检测电路，其中，所述第一至第六组晶体管沿着预设方向依次排布设置，所述第一至第六扫描线沿着所述预设方向依次排布设置。
  4. 如权利要求2所述的检测电路，其中，所述第一至第六组晶体管的第一晶体管及第二晶体管均为N型晶体管，所述第一及第二晶体管的控制端、第一端及第二端分别为N型晶体管的栅极、源极及漏极。
  5. 如权利要求1所述的检测电路，其中，所述第一至第六扫描为第一至第六充电扫描线。
  6. 一种显示装置，包括第一至第六扫描线、第一至第三检测线、第一及第二控制线及第一至第六组晶体管，所述第一至第六组晶体管连接至所述第一至第六扫描线，其中，每组晶体管均包括第一晶体管及第二晶体管，所述第一晶体管的控制端均连接至所述第一控制线，所述第一晶体管的第一端连接至所述第一至第三检测线中的一根检测线，所述第二晶体管的控制端均连接至所述第二控制线，所述第二晶体管的第一端连接至所述第一至第三检测线中的一根检测线，所述第一晶体管的第二端连接至同组的第二晶体管的第二端，并连接至所述第一至第六扫描线中的一根扫描线，一组晶体管对应一个扫描线，所述第一及第二晶体管的第一端与所述第一至第三检测线的连接节点构成预设点集合，所述预设点集合为[(3,3),(2,2),(3,1),(2,3),(3,2),(2,1)]，其中，在所述预设点集合中，数字1、2及3代表第一至第三检测线，该点的第一位数字表示所述第一晶体管的第一端与该第一位数字代表的检测线连接，该点的第二位数字表示所述第二晶体管的第一端与该第二数字代表的检测线连接，通过所述第一及第二控制线来控制所述第一晶体管或第二晶体管闭合来对所述显示装置的异常状况进行检测。
  7. 如权利要求6所述的显示装置，其中，所述第一组晶体管的第一及第二 晶体管的第一端均连接至所述第三检测线，所述第一组晶体管的第一及第二晶体管的第二端均连接至所述第一扫描线，所述第二组晶体管的第一及第二晶体管的第一端均连接至所述第二检测线，所述第二组晶体管的第一及第二晶体管的第二端均连接至所述第二扫描线，所述第三组晶体管的第一晶体管的第一端连接至第三检测线，所述第三组晶体管的第二晶体管的第一端连接至所述第一检测线，所述第三组晶体管的第一及第二晶体管的第二端均连接至所述第三扫描线，所述第四组晶体管的第一晶体管的第一端连接至所述第二检测线，所述第四组晶体管的第二晶体管的第一端连接至所述第三检测线，所述第四组晶体管的第一及第二晶体管的第二端均连接至所述第四扫描线，所述第五组晶体管的第一晶体管的第一端连接至所述第三检测线，所述第五组晶体管的第二晶体管的第一端连接至所述第二检测线，所述第五组晶体管的第一及第二晶体管的第二端端连接所述第五扫描线，所述第六组晶体管的第一晶体管的第一端连接至所述第二检测线，所述第六组晶体管的第二晶体管的第一端连接至所述第一检测线，所述第六组晶体管的第一及第二晶体管的第二端均连接至所述第六扫描线。
  8. 如权利要求7所述的显示装置，其中，所述第一至第六组晶体管沿着预设方向依次排布设置，所述第一至第六扫描线沿着所述预设方向依次排布设置。
  9. 如权利要求8所述的显示装置，其中，所述第一至第六扫描线为第一至第六充电扫描线，所述显示装置还包括第一至第六电荷共享扫描线、第一及第二额外充电扫描线、第一及第二额外电荷共享扫描线及第一至六像素行，所述第一至第六电荷共享扫描线分别对应所述第一至第六扫描线及所述第一至第六像素行，所述第一扫描线还连接至所述第一额外电荷共享扫描线，所述第二扫描线还连接至所述第二额外电荷共享扫描线，所述第一电荷共享扫描线还连接至所述第三扫描线，所述第二电荷共享扫描线还连接至所述第四扫描线，所述第三电荷共享扫描线连接至所述第五扫描线，所述第四电荷共享扫描线连接至所述第六扫描线，所述第五电荷共享扫描线连接至第一额外充电扫描线，所述第六电荷共享扫描线连接至所述第二额外充电扫描线，其中，所述第一至第六扫描线及所述第一及第二额外充电扫描线依次接收信号。
  10. 如权利要求7所述的显示装置，其中，所述第一至第六组晶体管的第一晶体管及第二晶体管均为N型晶体管，所述第一及第二晶体管的控制端、第一端及第二端分别为N型晶体管的栅极、源极及漏极。
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