WO2016106605A1 - 一种fpga功能模块仿真验证方法及其系统 - Google Patents
一种fpga功能模块仿真验证方法及其系统 Download PDFInfo
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- WO2016106605A1 WO2016106605A1 PCT/CN2014/095667 CN2014095667W WO2016106605A1 WO 2016106605 A1 WO2016106605 A1 WO 2016106605A1 CN 2014095667 W CN2014095667 W CN 2014095667W WO 2016106605 A1 WO2016106605 A1 WO 2016106605A1
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- 238000004088 simulation Methods 0.000 title claims abstract description 63
- 238000012795 verification Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000012360 testing method Methods 0.000 claims abstract description 122
- 230000005284 excitation Effects 0.000 claims abstract description 24
- 230000009977 dual effect Effects 0.000 claims description 6
- 230000006870 function Effects 0.000 description 71
- 238000010586 diagram Methods 0.000 description 6
- 238000012938 design process Methods 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 230000003542 behavioural effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31704—Design for test; Design verification
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
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- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G01R31/3177—Testing of logic operation, e.g. by logic analysers
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318364—Generation of test inputs, e.g. test vectors, patterns or sequences as a result of hardware simulation, e.g. in an HDL environment
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- G01R31/317—Testing of digital circuits
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Definitions
- the invention relates to an FPGA verification technology, in particular to an FPGA function module simulation method and a system thereof.
- FPGA verification is the process of verifying the correctness of the design through simulation, timing analysis, and on-board debugging.
- the consistency verification of specific modules becomes more important.
- Behavioral simulation as a common method of consistency verification the key is how to improve test coverage.
- the object of the present invention is to provide a simulation verification system for improving test coverage, thereby solving the technical problem of low coverage in behavior simulation.
- the present invention provides an FPGA function module simulation verification method, which comprises: generating all test cases by enumerating all parameter characteristics of each FPGA function module; and according to the input FPGA function to be tested The module type and parameter characteristics are generated to generate a simulation test platform that matches the configuration of the corresponding function module of the FPGA to be tested; the simulation test platform randomly generates a test stimulus and a corresponding expected output according to the input parameter characteristics of the FPGA function module to be tested, and the desired output and the test stimulus are generated. The actual output after the test case corresponding to the FPGA function module to be tested is compared, and the test report of the FPGA function module to be tested is output according to the comparison result.
- the method further includes: determining whether the FPGA function module to be tested is an upgrade based on the existing function module, if Yes, the test stimulus is first applied to the first value after the FPGA function module to be tested and the second value after the existing function module is applied. Comparing, if the first value and the second value are different, the simulation reports an error; if the first value and the second value are the same, the first value is compared with the expected output, and if different, the simulation reports an error, if the same Then the simulation passes.
- the present invention provides an FPGA function module simulation verification system, the system comprising: a verification platform control center, and the verification platform control center is configured to generate all test cases by enumerating all parameter features of each FPGA function module; According to the input type and parameter characteristics of the FPGA function module to be tested, a simulation test platform matching the configuration of the FPGA function module to be tested is generated; the simulation test platform randomly generates test excitation and corresponding expectation according to the input parameter characteristics of the FPGA function module to be tested. The output compares the expected output and the test stimulus to the actual output of the test case corresponding to the FPGA function module to be tested, and outputs a test report of the FPGA function module to be tested according to the comparison result.
- the verification platform control center includes a test case generator and a test platform generator, and the test case generator is used to generate all the test cases by enumerating all the parameter features of each FPGA function module; the test platform generator is configured to be based on the input The type and parameter characteristics of the FPGA function module are measured to generate a simulation test platform that matches the configuration of the FPGA function module to be tested.
- the simulation test platform comprises a random excitation generator and a comparator
- the random excitation generator is configured to randomly generate the test excitation and the corresponding expected output according to the input parameter characteristics of the FPGA function module to be tested
- the comparator is used for the desired output and the test excitation The actual output after the test case corresponding to the FPGA function module to be tested is compared, and the test report of the FPGA function module to be tested is output according to the comparison result.
- the simulation test platform comprises a random excitation generator and a double comparator, and the random excitation generator is configured to randomly generate the test excitation and the corresponding expected output according to the input parameter characteristics of the FPGA function module to be tested; the dual comparator is used to determine the FPGA to be tested.
- the function module is an upgrade based on the existing function module, if yes, first applying the test stimulus to the first value after the FPGA function module to be tested and the second value after applying the existing function module Comparing, if the first value and the second value are different, the simulation reports an error; if the first value and the second value are the same, the first The value is compared to the expected output, and if different, the simulation reports an error, and if the same, the simulation passes.
- the invention acquires all test cases based on all parameter characteristic information of the FPGA function module, thereby establishing a simulation verification system with a test coverage of 100%.
- FIG. 1 is a flowchart of a method for verifying and verifying an FPGA function module according to an embodiment of the present invention
- FIG. 2 is a schematic diagram of a process for generating an FPGA module test case
- FIG. 3 is a schematic diagram of a process of generating an FPGA module simulation test platform
- Figure 4a is a schematic diagram of a simulation verification process of the FPGA module
- Figure 4b is a schematic diagram of another simulation verification process of the FPGA module
- FIG. 5 is a structural diagram of an FPGA function module simulation verification system according to an embodiment of the present invention.
- FIG. 1 is a flowchart of a method for verifying and verifying an FPGA function module according to an embodiment of the present invention. As shown in Figure 1, the method includes steps 101-103:
- step 101 all test cases are generated by enumerating all of the parameter characteristics of each FPGA function module.
- the simulation verification system generates all test cases by enumerating all the parameter features of the module for different FPGA functional modules, such as a phase locked loop module, a digital processor module, a configurable logic block, and a memory module (eg, Figure 2).
- FPGA functional modules such as a phase locked loop module, a digital processor module, a configurable logic block, and a memory module (eg, Figure 2).
- step 102 according to the input type of the FPGA functional module to be tested and the parameter characteristics, a simulation test platform matching the configuration of the corresponding functional module to be tested is generated;
- the simulation verification system generates a simulation test platform (shown in FIG. 3) that matches the configuration of the corresponding FPGA function module according to the input FPGA function module type and parameter characteristics.
- step 103 the simulation test platform randomly generates the test excitation and the corresponding expected output according to the input parameter characteristics of the FPGA function module to be tested, and applies the expected output and the test excitation to the actual output after the test case corresponding to the FPGA function module to be tested. Comparing, the test message of the FPGA function module to be tested is output according to the comparison result.
- the simulation verification platform randomly generates the test excitation and the corresponding expected output according to the input parameter characteristics, and applies the generated test excitation to the test case corresponding to the FPGA function module to be tested (ie, the function module to be tested), and outputs the same.
- the result is compared with the expected output, and the test report of the FPGA function module to be tested is output according to the comparison result (as shown in FIG. 4a).
- the simulation verification platform determines whether the FPGA function module to be tested is an upgrade based on the existing function module before comparing the expected output with the actual output of the test excitation module after the FPGA function module is tested.
- the first value after the test stimulus is applied to the FPGA function module to be tested is compared with the second value applied to the existing function module. If the first value and the second value are different, the simulation reports an error; The first value and the second value are the same, and the first value is compared with the expected output. If different, the simulation reports an error, and if they are the same, the simulation passes.
- the comparison module instance is in the FPGA function module design process, if the new function module is upgraded based on the existing function module, the existing function will be introduced during the test of the new function module. Module as a comparison module instance
- the FPGA function module to be tested is an embedded 9K memory module of a new generation device, which is a relatively complex embedded memory module and includes the following parameter features:
- memory mode single port (sp), simple dual port (sdp), dual port (tdp);
- write mode write first (write_first), read first (read_first), read hold (no_change);
- the output register is set and reset.
- the output latch is set and reset.
- Read data bit width 1, 2, 4, 9, 18, 36;
- write output (write_first), read first (read_first), read hold (no_change) corresponds to the expected output in the test platform:
- the simulation verification system automatically executes all tests and captures the message output for each test process. After all tests are completed, a unified test report is output.
- the embodiment of the invention acquires all test cases based on all parameter feature information of the FPGA function module, thereby establishing a simulation verification system with a test coverage of 100%.
- FIG. 5 is a structural diagram of an FPGA function module simulation verification system according to an embodiment of the present invention.
- the system includes a verification platform control center 50 and a simulation test platform 60, wherein the verification platform control center 50 includes a test case generator 51 and a test platform generator 52; the simulation test platform 60 includes a random excitation generator 61 and Comparator 62.
- the test case generator 51 is used to generate all test cases by enumerating all the parameter characteristics of each FPGA function module.
- the test platform generator 52 is configured to generate a simulation test platform that matches the configuration of the FPGA function module to be tested according to the type and parameter characteristics of the input FPGA function module to be tested.
- the random excitation generator 61 is configured to randomly generate the test excitation and the corresponding expected output according to the input parameter characteristics of the FPGA function module to be tested.
- the comparator 62 is configured to compare the expected output and the test excitation to the actual output after the test case corresponding to the FPGA function module to be tested, and output a test report of the FPGA function module to be tested according to the comparison result.
- the comparator 62 is configured as a dual comparator for determining whether the FPGA function module to be tested is an upgrade based on an existing function module, and if so, first applying a test stimulus to the FPGA function module to be tested. The first value is compared with a second value applied to the existing function module, and if the first value and the second value are different, the simulation reports an error; if the first value and the second value are the same, the first value is The value is compared to the expected output, and if different, the simulation reports an error, and if the same, the simulation passes.
- the embodiment of the invention acquires all test cases based on all parameter feature information of the FPGA function module, thereby establishing a simulation verification system with a test coverage of 100%.
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Abstract
Description
Claims (6)
- 一种FPGA功能模块仿真验证方法,其特征在于,通过枚举各个FPGA功能模块全部的参数特征,产生全部的测试用例;根据输入的待测FPGA功能模块类型和参数特征,产生匹配相应待测FPGA功能模块配置的仿真测试平台;所述仿真测试平台根据输入的待测FPGA功能模块参数特征,随机生成测试激励和相应的期望输出,将所述期望输出与所述测试激励施加在待测FPGA功能模块对应的测试用例后的实际输出进行比较,根据比较结果输出待测FPGA功能模块的测试报告。
- 根据权利要求1所述的方法,其特征在于,所述在将所述期望输出与所述测试激励施加在待测FPGA功能模块对应的测试用例后的实际输出进行比较步骤之前还包括:判断待测FPGA功能模块是否为已有功能模块基础上的升级,如果是,则先将测试激励施加在所述待测FPGA功能模块后的第一值与施加在所述已有功能模块后的第二值进行比较,如果第一值和第二值不同,则仿真报错;如果第一值和第二值相同,再将所述第一值与所述期望输出进行比较,如果不同,则仿真报错,如果相同,则仿真通过。
- 一种FPGA功能模块仿真验证系统,其特征在于,包括:验证平台控制中心,所述验证平台控制中心用于通过枚举各个FPGA功能模块全部的参数特征,产生全部的测试用例;并根据输入的待测FPGA功能模块的类型和参数特征,产生匹配待测FPGA功能模块配置的仿真测试平台;所述仿真测试平台根据输入的待测FPGA功能模块参数特征,随机生成测试激励和相应的期望输出,将所述期望输出与所述测试激励施加在待测FPGA功能模块对应的测试用例后的实际输出进行比较,根据比较结果输出待测FPGA功能模块的测试报告。
- 根据权利要求3所述的系统,其特征在于,所述验证平台控制中心 包括测试用例生成器和测试平台生成器,所述测试用例生成器,用于通过枚举各个FPGA功能模块全部的参数特征,产生全部的测试用例;所述测试平台生成器,用于根据输入的待测FPGA功能模块的类型和参数特征,产生匹配待测FPGA功能模块配置的仿真测试平台。
- 根据权利要求3所述的系统,其特征在于,所述仿真测试平台包括随机激励发生器和比较器,所述随机激励发生器,用于根据输入的待测FPGA功能模块参数特征,随机生成测试激励和相应的期望输出;比较器,用于将所述期望输出和所述测试激励施加在待测FPGA功能模块对应的测试用例后的实际输出进行比较,根据比较结果输出待测FPGA功能模块的测试报告。
- 根据权利要求3所述的系统,其特征在于,所述仿真测试平台包括随机激励发生器和双重比较器,所述随机激励发生器,用于根据输入的待测FPGA功能模块参数特征,随机生成测试激励和相应的期望输出;所述双重比较器,用于判断待测FPGA功能模块是否为已有功能模块基础上的升级,如果是,则先将测试激励施加在所述待测FPGA功能模块后的第一值与施加在所述已有功能模块后的第二值进行比较,如果第一值和第二值不同,则仿真报错;如果第一值和第二值相同,再将所述第一值与所述期望输出进行比较,如果不同,则仿真报错,如果相同,则仿真通过。
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