WO2016103835A1 - 光半導体デバイス - Google Patents
光半導体デバイス Download PDFInfo
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- WO2016103835A1 WO2016103835A1 PCT/JP2015/078087 JP2015078087W WO2016103835A1 WO 2016103835 A1 WO2016103835 A1 WO 2016103835A1 JP 2015078087 W JP2015078087 W JP 2015078087W WO 2016103835 A1 WO2016103835 A1 WO 2016103835A1
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- Prior art keywords
- layer
- compound semiconductor
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/34333—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02389—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
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Definitions
- This disclosure relates to optical semiconductor devices.
- Improvement of light emission efficiency and reduction of threshold current in various light emitting diodes and semiconductor laser elements are indispensable items for improving output and power consumption, and are intensively studied at present.
- the amount of current injection increases as the emission wavelength increases, resulting in problems such as a decrease in light emission efficiency and an increase in threshold current.
- One of these causes is the non-uniformity of carriers in the active layer (light emitting layer). That is, as the emission wavelength increases, the energy gap difference between the barrier layer and the well layer constituting the multiple quantum well structure increases, and when an active layer is formed on the c-plane of the GaN substrate, the influence of the piezoelectric field is affected by the well layer. Since the carrier (electrons and holes) once entered the well layer is difficult to go out of the well layer, the carrier non-uniformity in the active layer (light emitting layer) is given. be able to.
- Non-Patent Document 1 IEEE, “Journal” of “Selected”, Topics, in, Quantum, Electronics, Vol.15, No.5 (2011), p.1390.
- the emission wavelength is 400 nm or more
- the wavelength is 450 nm or more
- the state in which the carriers in the well layer are difficult to come out of the well layer is shown by the relationship between the light emission recombination time and the carrier escape time from the well layer (see FIG. 12).
- FIG. 12 the relationship between the light emission recombination time and the carrier escape time from the well layer
- A indicates the behavior of holes when the active layer is formed on the c-plane of the GaN substrate
- B indicates the electron behavior when the active layer is formed on the c-plane of the GaN substrate.
- A shows the behavior of holes when an active layer is formed on the nonpolar surface of the GaN substrate
- b shows the electron behavior when the active layer is formed on the nonpolar surface of the GaN substrate. Shows behavior.
- carrier movement between well layers in a multiple quantum well structure having two or more well layers is performed in a very short time of about 100 femtoseconds or less. The length becomes longer, and electrons and holes cannot freely move between the well layers.
- the electron concentration and the hole concentration in each well layer become different, and the surplus carriers do not contribute to light emission, so that the light emission efficiency is lowered.
- the carrier concentration between the well layers changes greatly, the emission wavelength shifts and the gain peak (wavelength) shift, which also causes a decrease in light emission efficiency and an increase in threshold current.
- a technique for forming a tunnel barrier layer is disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-174328.
- the thickness of the tunnel barrier layer is controlled in order to change the tunnel probability in the tunnel barrier layer.
- the effective mass difference between electrons and holes is large, even if such a tunnel barrier layer is provided, it cannot be said that the elimination of carrier nonuniformity is sufficient.
- it is conceivable to reduce the thickness of only the barrier layer without forming the tunnel barrier layer if the barrier layer is thinned, there arises a problem that the light emission efficiency of the adjacent well layer is lowered.
- the thickness of the barrier layer is 10 nm and when the thickness is 2.5 nm, the latter luminous efficiency is about 1/4 of the former. It is known to be.
- an object of the present disclosure is to provide an optical semiconductor device having a configuration and a structure capable of suppressing a decrease in light emission efficiency and an increase in threshold current.
- An optical semiconductor device for achieving the above object is as follows: An n-type compound semiconductor layer, an active layer, and a p-type compound semiconductor layer have a stacked structure in which the layers are stacked in this order, The active layer has a multiple quantum well structure having a tunnel barrier layer.
- the composition fluctuation of the well layer adjacent to the p-type compound semiconductor layer is larger than the composition fluctuation of the other well layers.
- the band gap energy of the well layer adjacent to the p-type compound semiconductor layer is smaller than the band gap energy of the other well layers.
- the thickness of the well layer adjacent to the p-type compound semiconductor layer is larger than the thickness of the other well layers.
- the distribution of electrons is largely biased toward the p-type compound semiconductor layer, and as a result, the p-type compound semiconductor layer
- the light emission peak wavelength and the optical gain peak wavelength of the well layer adjacent to are different from the light emission peak wavelength and the optical gain peak wavelength of the other well layers. Specifically, in the well layer adjacent to the p-type compound semiconductor layer, these wavelengths are short.
- the composition fluctuation of the well layer adjacent to the p-type compound semiconductor layer is made larger than the composition fluctuation of the other well layers.
- the band gap energy of the well layer adjacent to the p-type compound semiconductor layer is made smaller than the band gap energy of the other well layers.
- the thickness of the well layer adjacent to the p-type compound semiconductor layer is made thicker than the thickness of the other well layers, the emission peak wavelength and the optical gain peak wavelength are changed between the well layers. They can be aligned, or the deviation can be suppressed. As a result, it is possible to improve the light emission efficiency and reduce the threshold current. Note that the effects described in the present specification are merely examples and are not limited, and may have additional effects.
- 1A and 1B are a schematic partial cross-sectional view of the optical semiconductor device of Example 1, and a structural schematic diagram of a multiple quantum well structure in an active layer.
- 2A and 2B are schematic partial cross-sectional views of the optical semiconductor device of Example 5 and its modification.
- 3A, 3B, and 3C are schematic partial end views of a substrate and the like for explaining the method for manufacturing the surface emitting laser element of Example 5.
- FIG. 4A and 4B are schematic partial cross-sectional views of the surface emitting laser element of Example 6 and a modification thereof, respectively.
- 5A and 5B are schematic partial end views of a laminated structure and the like for describing the method for manufacturing the surface emitting laser element of Example 6.
- FIG. 6 is a schematic partial cross-sectional view of the surface emitting laser element of Example 7.
- 7A and 7B are schematic partial cross-sectional views of the surface emitting laser elements of Example 8 and Example 9, respectively.
- 8A, 8B, and 8C are schematic partial end views of a laminated structure and the like for describing the method for manufacturing the surface emitting laser element of Example 8.
- FIG. 9A and 9B are schematic partial end views of the laminated structure and the like for explaining the method for manufacturing the surface emitting laser element of Example 7 following FIG. 8C.
- FIG. 10 is a schematic partial end view of a laminated structure and the like for explaining the method for manufacturing the surface emitting laser element of Example 7 following FIG. 9B.
- 11A and 11B are schematic partial cross-sectional views of the surface emitting laser element of Example 10.
- FIG. FIG. 12 is a graph showing the relationship between the luminescence recombination time and the carrier escape time from the well layer.
- Example 1 (Optical Semiconductor Device and Semiconductor Laser Element According to First Aspect of Present Disclosure) 3.
- Example 2 an optical semiconductor device and a semiconductor laser element according to the second aspect of the present disclosure) 4).
- Example 3 an optical semiconductor device and a semiconductor laser element according to the third aspect of the present disclosure) 5.
- Example 4 (Modification of Examples 1 to 3, Light-Emitting Diode) 6).
- Example 5 (Modification of Examples 1 to 3, Surface Emitting Laser Element) 7).
- Example 6 (Modification of Example 5) 8).
- Example 7 (another modification of Example 5 to Example 6) 9.
- Example 8 (Modification of Example 6) 10.
- Example 9 (another modification of Example 8) 11.
- Example 10 (modification of Example 8 to Example 9) 12 Other
- the surface of the n-type compound semiconductor layer in contact with the active layer is defined as the second surface of the n-type compound semiconductor layer, and the surface facing the second surface. This is called the first surface of the n-type compound semiconductor layer.
- the surface of the p-type compound semiconductor layer in contact with the active layer is referred to as a first surface of the p-type compound semiconductor layer, and the surface facing the first surface is referred to as a second surface of the p-type compound semiconductor layer.
- the band gap energy of the well layer adjacent to the p-type compound semiconductor layer may be smaller than the band gap energy of the other well layers.
- the thickness of the well layer adjacent to the p-type compound semiconductor layer may be thicker than the thickness of the other well layers.
- the band gap of the well layer adjacent to the p-type compound semiconductor layer The energy can be in a form smaller than the band gap energy of the other well layers.
- the thickness of the well layer adjacent to the p-type compound semiconductor layer may be larger than the thickness of the other well layers.
- the tunnel barrier layer may be formed between the well layer and the barrier layer. it can.
- the active layer is composed of two well layers and one barrier layer, from the n-type compound semiconductor layer side, the first well layer, the first tunnel barrier layer, the barrier layer, the second layer The tunnel barrier layer and the second well layer are formed.
- the number of well layers constituting the active layer is not limited to this, and may be three or more.
- the thickness of the tunnel barrier layer is preferably 4 nm or less.
- the lower limit value of the thickness of the tunnel barrier layer is not particularly limited as long as the tunnel barrier layer is formed.
- the thickness of the tunnel barrier layer may be constant or different.
- the active layer can be composed of an AlInGaN-based compound semiconductor.
- the tunnel barrier layer can be made of GaN, and in these cases, the n-type compound semiconductor layer can be made on the c-plane of the GaN substrate.
- the emission wavelength may be 440 nm or more.
- composition fluctuation and composition of the well layer in the optical semiconductor device according to the first aspect of the present disclosure can be measured based on, for example, a three-dimensional atom probe (3DAP).
- 3DAP three-dimensional atom probe
- the composition fluctuation and composition of In may be measured based on a three-dimensional atom probe.
- 3D atom probes see, for example, http://www.nanoanalysis.co.jp/business/case_example_49.html.
- the composition fluctuation of the well layer adjacent to the p-type compound semiconductor layer is It can be said that it is larger than the composition fluctuation of the other well layers.
- the value of the band gap energy in the optical semiconductor device according to the second aspect of the present disclosure can be confirmed by, for example, the average value of the In composition measured by the three-dimensional atom probe.
- the thickness of the well layer in the optical semiconductor device according to the aspect can be obtained by, for example, a high-resolution electron microscope.
- the band gap of the well layer adjacent to the p-type compound semiconductor layer The energy is smaller than the band gap energy of other well layers, but is limited as the value obtained by subtracting the maximum value of the band gap energy of other well layers from the band gap energy of the well layer adjacent to the p-type compound semiconductor layer.
- 1 ⁇ 10 ⁇ 4 eV to 2 ⁇ 10 ⁇ 1 eV can be exemplified.
- the thickness of the well layer adjacent to the p-type compound semiconductor layer Is thicker than the thickness of the other well layer, but is not limited to a value obtained by subtracting the maximum value of the thickness of the other well layer from the thickness of the well layer adjacent to the p-type compound semiconductor layer. .05 nm to 2 nm can be exemplified.
- a GaN-based compound semiconductor as a material constituting the active layer, and further, as a material constituting the stacked structure, a GaN-based compound semiconductor, specifically, as described above.
- AlInGaN-based compound semiconductors can be mentioned, and more specifically, GaN, AlGaN, InGaN, and AlInGaN can be mentioned.
- these compound semiconductors may contain boron (B) atoms, thallium (Tl) atoms, arsenic (As) atoms, phosphorus (P) atoms, and antimony (Sb) atoms as desired. .
- the thickness of the well layer is 1 nm or more and 10 nm or less, preferably 1 nm or more and 8 nm or less, and the impurity doping concentration of the barrier layer is 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less, Preferably, it is preferably 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less, but is not limited thereto.
- an electron barrier layer may be formed in the vicinity of the active layer or adjacent to the active layer, and a non-doped compound semiconductor is provided between the active layer and the electron barrier layer.
- a layer (for example, a non-doped InGaN layer or a non-doped AlGaN layer) may be formed.
- a non-doped InGaN layer as a light guide layer may be formed between the active layer and the non-doped compound semiconductor layer.
- a structure in which the uppermost layer of the p-type compound semiconductor layer is occupied by an Mg-doped GaN layer (p-side contact layer, p-contact layer) can also be employed.
- the electron barrier layer, the non-doped compound semiconductor layer, the light guide layer, and the p-side contact layer (p-contact layer) constitute a p-type compound semiconductor layer.
- the n-type compound semiconductor layer is preferably formed on the c-plane of the GaN substrate, that is, the ⁇ 0001 ⁇ plane, but is not limited to this.
- the a-plane which is the ⁇ 11-20 ⁇ plane, ⁇ A nonpolar surface such as an m-plane that is a 1-100 ⁇ plane, a ⁇ 1-102 ⁇ plane, or a ⁇ 11-2n ⁇ plane that includes a ⁇ 11-24 ⁇ plane or a ⁇ 11-22 ⁇ plane, ⁇ 10- It can also be formed on a semipolar plane such as an 11 ⁇ plane, a ⁇ 10-12 ⁇ plane, or a ⁇ 20-21 ⁇ plane.
- GaN substrate sapphire substrate, GaAs substrate, GaN substrate, SiC substrate, alumina substrate, ZnS substrate, ZnO substrate, AlN substrate, LiMgO substrate, LiGaO 2 substrate, MgAl 2 O 4 substrate, InP substrate , Si substrates, and those having a base layer and a buffer layer formed on the surface (main surface) of these substrates.
- a metal organic chemical vapor deposition method MOCVD method, MOVPE method
- MBE molecular beam epitaxy method
- hydride vapor phase growth method in which halogen contributes to transport or reaction.
- trimethylgallium (TMG) gas and triethylgallium (TEG) gas can be exemplified as the organic gallium source gas in the MOCVD method, and ammonia gas and hydrazine gas can be exemplified as the nitrogen source gas.
- silicon (Si) may be added as an n-type impurity (n-type dopant), or a GaN-based compound having a p-type conductivity.
- magnesium (Mg) may be added as a p-type impurity (p-type dopant).
- trimethylaluminum (TMA) gas may be used as the Al source, and trimethylindium (TMI) gas is used as the In source. Use it.
- monosilane gas (SiH 4 gas) may be used as the Si source, and cyclopentadienyl magnesium gas, methylcyclopentadienyl magnesium, or biscyclopentadienyl magnesium (Cp 2 Mg) may be used as the Mg source. .
- n-type impurities examples include Si, Ge, Se, Sn, C, Te, S, O, Pd, and Po, and p-type impurities (p-type dopants) other than Mg.
- Zn, Cd, Be, Ca, Ba, C, Hg, and Sr can be exemplified.
- a p-side electrode is formed on a p-type compound semiconductor layer (a compound semiconductor layer having a p-type conductivity type).
- the p-side electrode is, for example, a palladium (Pd) single layer, a nickel (Ni) single layer, a platinum (Pt) single layer, a transparent conductive material layer such as ITO, and the palladium layer is in contact with the p-type compound semiconductor layer. It can be comprised from the laminated structure of a palladium layer / platinum layer, or the laminated structure of the palladium layer / nickel layer which a palladium layer touches a p-type compound semiconductor layer.
- the thickness of the upper metal layer is preferably 0.1 ⁇ m or more, preferably 0.2 ⁇ m or more.
- the p-side electrode is preferably composed of a single layer of palladium (Pd), and in this case, the thickness is desirably 20 nm or more, preferably 50 nm or more.
- the p-side electrode may be a palladium (Pd) single layer, a nickel (Ni) single layer, a platinum (Pt) single layer, or a lower metal layer and an upper metal layer where the lower metal layer is in contact with the p-type compound semiconductor layer. It is preferable to comprise a laminated structure.
- the n-side electrode electrically connected to the n-type compound semiconductor layer is gold (Au), silver (Ag), palladium (Pd), Al (aluminum), Ti ( Having a single layer configuration or a multilayer configuration including at least one metal selected from the group consisting of titanium), tungsten (W), Cu (copper), Zn (zinc), tin (Sn), and indium (In)
- Au gold
- Ti gold
- W gold
- Cu copper
- Zn zinc
- Zn zinc
- Sn tin
- In indium
- Ti / Au, Ti / Al, and Ti / Pt / Au can be exemplified.
- the n-side electrode is electrically connected to the n-type compound semiconductor layer, but the n-side electrode is formed on the n-type compound semiconductor layer, and the n-side electrode has a conductive material layer or a conductive substrate or base.
- the form connected to the n-type compound semiconductor layer via is included.
- the n-side electrode and the p-side electrode can be formed by various PVD methods such as vacuum deposition and sputtering, for example.
- a pad electrode may be provided on the n-side electrode or the p-side electrode for electrical connection with an external electrode or circuit.
- the pad electrode has a single-layer configuration or a multi-layer configuration including at least one metal selected from the group consisting of Ti (titanium), aluminum (Al), Pt (platinum), Au (gold), and Ni (nickel). It is desirable to have.
- the pad electrode may have a multilayer configuration exemplified by a multilayer configuration of Ti / Pt / Au and a multilayer configuration of Ti / Au.
- a light emitting diode LED
- LD semiconductor laser element
- SLD super luminescent diode
- VCSEL vertical cavity laser
- SOA semiconductor optical amplifier
- the basic structure and structure of these optical semiconductor devices can be a known structure and structure.
- the light generated in the active layer may be emitted to the outside through the n-type compound semiconductor layer, or may be emitted to the outside through the p-type compound semiconductor layer. .
- the light generated in the active layer is emitted to the outside from the end face of the laminated structure. That is, a resonator is configured by optimizing the light reflectance of the first end face of the multilayer structure and the light reflectance of the second end face facing the first end face, and light is emitted from the first end face. Is done.
- an external resonator may be disposed, or a monolithic semiconductor laser element may be used.
- the external resonator type semiconductor laser element may be a condensing type or a collimating type.
- the light reflectance of the first end face in the multilayer structure is set to a very low value, and the light reflectance of the second end face is set to a very high value to constitute a resonator. Without being generated, the light generated in the active layer is emitted from the first end face.
- a non-reflective coating layer (AR) or a low reflection coating layer is formed on the first end surface, and a high reflection coating layer (HR) is formed on the second end surface.
- a semiconductor optical amplifier (SOA) does not convert an optical signal into an electrical signal, but amplifies it in the state of direct light. It has a laser structure that eliminates the resonator effect as much as possible, and is incident at the optical gain of the semiconductor optical amplifier.
- the light reflectance of the first end face and the second end face in the stacked structure is set to a very low value, and the light incident from the second end face is amplified without forming a resonator.
- the light exits from one end face.
- the first light reflection layer is formed on the first surface of the n-type compound semiconductor layer, and the second surface of the p-type compound semiconductor layer or above the second surface.
- a second light reflecting layer is formed on the.
- An antireflective coating layer (AR) or a low reflective coating layer is formed on the first end surface and the second end surface.
- Non-reflective coating layer low reflection coating layer or high reflection coating layer, from the group consisting of titanium oxide layer, tantalum oxide layer, zirconium oxide layer, silicon oxide layer, aluminum oxide layer, aluminum nitride layer, and silicon nitride layer
- a laminated structure of at least two kinds of selected layers can be given, and can be formed based on a PVD method such as a sputtering method or a vacuum evaporation method.
- the ridge stripe structure when the stacked structure has a ridge stripe structure, the ridge stripe structure may be constituted by a part of the p-type compound semiconductor layer in the thickness direction, or the p-type compound semiconductor layer. Or a p-type compound semiconductor layer and an active layer, or a part of the p-type compound semiconductor layer, the active layer, and the n-type compound semiconductor layer in the thickness direction. It may be configured.
- the compound semiconductor layer may be patterned by, for example, a dry etching method.
- Example 1 relates to an optical semiconductor device according to the first aspect of the present disclosure, specifically, a semiconductor laser element (LD).
- FIG. 1A shows a diagram
- FIG. 1B shows a structural schematic diagram of a multiple quantum well structure in an active layer.
- FIG. 1B for convenience, a band structure diagram in which the influence of the piezoelectric field is not taken into consideration is shown.
- the semiconductor optical devices of Example 1 or Examples 1 to 10 described later have a stacked structure 20 in which an n-type compound semiconductor layer 21, an active layer 23, and a p-type compound semiconductor layer 22 are stacked in this order.
- the active layer 23 has a multiple quantum well structure having a tunnel barrier layer 33. Specifically, the tunnel barrier layer 33 is formed between the well layer 31 and the barrier layer 32.
- the active layer 23 is composed of two well layers 31 1 and 31 2 and one barrier layer 32.
- the active layer 23 includes, from the n-type compound semiconductor layer 21 side, a first well layer 31 1 , a first tunnel barrier layer 33 1 , a barrier layer 32, a second tunnel barrier layer 33 2 , In addition, a multiple quantum well structure having a second well layer 312 is provided.
- the thickness of the tunnel barrier layers 33 1 and 33 2 is 4 nm or less.
- the laminated structure 20 is formed on the substrate 11.
- the substrate 11 is specifically composed of a GaN substrate, and the laminated structure 20, specifically the n-type compound semiconductor layer 21, is formed on the c-plane (0001) plane of the GaN substrate.
- An n-side electrode 25 is formed on the back surface of the substrate 11, and a p-side electrode 26 is formed on the p-type compound semiconductor layer 22.
- the laminated structure 20 is covered with an insulating layer 24.
- the refractive index of the material constituting the insulating layer 24 is preferably smaller than the refractive index of the material constituting the laminated structure 20.
- Examples of the material constituting the insulating layer 24 include SiO x -based materials including SiO 2 , SiN x -based materials, SiO x N z -based materials, TaO x , ZrO x , AlN x , AlO x , and GaO x. Alternatively, organic materials such as polyimide resin can also be mentioned.
- a Si layer may be formed on the insulating layer 24.
- a method for forming the insulating layer 24 for example, a PVD method such as a vacuum deposition method or a sputtering method, or a CVD method can be cited, or a formation method can be used.
- the configuration of the laminated structure 20 and the like is as shown in Table 1 below.
- Table 2 shows the configuration of the active layer 23 in the optical semiconductor device of Example 1.
- the In composition value in the two tunnel barrier layers 33 1 and 33 2 may be smaller than the In composition value in the barrier layer 32.
- the active layer 23 is made of an AlInGaN-based compound semiconductor, and the tunnel barrier layers 33 1 and 33 3 are made of GaN.
- the emission wavelength of the semiconductor laser device of Example 1 is 440 nm or more, specifically, 460 nm.
- p-side electrode 26 Pd / Au p-type compound semiconductor layer 22 p-contact layer 22C GaN (thickness 0.1 ⁇ m) p-cladding layer 22B AlGaN (thickness: 0.3 ⁇ m)
- Electron barrier layer 22A AlGaN Active layer 23 See Table 2 n-type compound semiconductor layer 21 n-guide layer 21B InGaN (thickness: 0.1 ⁇ m) n-cladding layer 21A AlGaN (thickness: 0.4 ⁇ m)
- Active layer Second well layer In 0.30 Ga 0.70 N (thickness: 2.5 nm) Second tunnel barrier layer GaN (thickness: 2.0 nm) Barrier layer In 0.05 Ga 0.95 N (thickness: 4.0 nm) First tunnel barrier layer GaN (thickness: 2.0 nm) First well layer In 0.30 Ga 0.70 N (thickness: 2.5 nm)
- the composition fluctuation of the well layer adjacent to the p-type compound semiconductor layer is larger than the composition fluctuation of the other well layers.
- the first and the growth rate and deposition temperature and / or the deposition pressure first well layer 31, a second well layer 31 2 Growth by varying the speed and the deposition temperature and / or deposition pressure, to increase the fluctuation in the in composition of the well layer 31 1, 31 2.
- the fluctuation and composition of the In composition can be measured based on a three-dimensional atom probe (3DAP).
- the horizontal axis represents the In composition and the vertical axis represents the In composition by the three-dimensional atom probe.
- optical semiconductor devices of Example 1 or Examples 2 to 3 described later can be manufactured by the following method.
- an n-type compound semiconductor layer 21, an active layer 23, and a p-type compound semiconductor layer 22 are sequentially formed on a substrate 11, specifically, on a (0001) plane of an n-type GaN substrate based on a well-known MOCVD method. Then, the laminated structure 20 formed by lamination is formed. Then, the ridge stripe structure 27 is formed by partially etching the p-type compound semiconductor layer 22 in the thickness direction. The thickness of the portion of the p-type compound semiconductor layer 22 constituting the ridge stripe structure 27 was set to 0.12 ⁇ m.
- Step-110 Thereafter, an insulating layer 24 made of SiO 2 covering the p-type compound semiconductor layer 22 is formed, and then an Si layer (not shown) is formed on the insulating layer 24. Then, after removing the insulating layer 24 and the Si layer where the p-side electrode 26 is to be formed, the p-side electrode 26 is formed on the p-type compound semiconductor layer 22. Specifically, after forming a p-side electrode layer on the entire surface based on a vacuum deposition method, an etching resist layer is formed on the p-side electrode layer based on a photolithography technique.
- the p-side electrode 26 may be formed on the p-type compound semiconductor layer 22 based on a lift-off method.
- the substrate 11 is polished from the back surface to reduce the thickness of the substrate 11, and then the n-side electrode 25 is formed on the back surface of the substrate 11, and the pad electrode is formed on the p-side electrode 26. Then, in order to cleave the substrate 11 and control the light reflectance at the first end face and the second end face of the laminated structure 20, an antireflective coating layer (AR) or a low reflection coating layer is formed on the first end face. Then, a highly reflective coating layer (HR) is formed on the second end face. Further, by performing packaging, an optical semiconductor device can be manufactured.
- AR antireflective coating layer
- HR highly reflective coating layer
- the distribution of electrons is biased toward the p-type compound semiconductor layer side.
- the emission peak wavelength and optical gain peak wavelength of the well layer adjacent to the p-type compound semiconductor layer are different from the emission peak wavelength and optical gain peak wavelength of the other well layers. Specifically, in the well layer adjacent to the p-type compound semiconductor layer, these wavelengths are shortened.
- the well adjacent to the p-type compound semiconductor layer since the composition fluctuation of the well layer adjacent to the p-type compound semiconductor layer is larger than the composition fluctuation of other well layers, the well adjacent to the p-type compound semiconductor layer As a result of the increase in the emission peak wavelength and the optical gain peak wavelength of the layer, the emission peak wavelength and the optical gain peak wavelength can be made uniform between the well layers, or the divergence can be suppressed. As a result, it is possible to improve the light emission efficiency and reduce the threshold current. In addition, even if an active layer is formed on the c-plane of the GaN substrate, the influence of the piezoelectric field on the well layer and the barrier layer can be eliminated, and as a result, carriers are prevented from becoming non-uniform in the active layer. be able to.
- the superluminescent diode (SLD) and the semiconductor optical amplifier (SOA) are different from the semiconductor laser device in optimizing the light reflectivity at the first and second end surfaces and forming the resonator. Except for this point, it has substantially the same configuration and structure as the semiconductor laser device described in the first embodiment or the semiconductor laser devices described in the second to third embodiments described later.
- Example 2 relates to an optical semiconductor device according to the second aspect of the present disclosure, specifically, a semiconductor laser element (LD).
- the band gap energy of the well layer (second well layer 31 2 ) adjacent to the p-type compound semiconductor layer is different from that of the other well layers (specifically, the first well layer 31 2 ). It is smaller than the band gap energy of the well layer 31 1 ) (see Table 4).
- the configuration of the active layer 23 in the optical semiconductor device of Example 2 is shown in Table 3.
- the emission wavelength of the semiconductor laser device of Example 2 is 440 nm or more, specifically, 460 nm.
- trimethyl indium (TMI) forming the first well layer 31 1 a supply amount of gas as an In source during the second well layer 31 and second film forming
- the band gap energy of the well layer (second well layer 31 2 ) adjacent to the p-type compound semiconductor layer is increased by increasing the amount of trimethylindium gas supplied as an In source or increasing the growth rate.
- the band gap energy of other well layers can be made smaller.
- Active layer Second well layer In 0.19 Ga 0.81 N (thickness: 2.5 nm) Second tunnel barrier layer GaN (thickness: 2.0 nm) Barrier layer In 0.04 Ga 0.96 N (thickness: 4.0 nm) First tunnel barrier layer GaN (thickness: 2.0 nm) First well layer In 0.18 Ga 0.82 N (thickness: 2.5 nm)
- the band gap energy of the well layer adjacent to the p-type compound semiconductor layer is made smaller than the band gap energy of the other well layers, the emission peak wavelength and the optical gain peak wavelength are set. In addition, they can be aligned between the well layers, or the deviation can be suppressed. As a result, it is possible to improve the light emission efficiency and reduce the threshold current.
- Example 3 relates to an optical semiconductor device according to the third aspect of the present disclosure, specifically, a semiconductor laser element (LD).
- the thickness of the well layer (second well layer 31 2 ) adjacent to the p-type compound semiconductor layer is different from that of the other well layers (specifically, the first well). Thicker than the thickness of layer 31 1 ).
- Table 5 shows the configuration of the active layer 23 in the optical semiconductor device of Example 3.
- the emission wavelength of the semiconductor laser device of Example 3 is 440 nm or more, specifically, 460 nm.
- the thickness of the well layer (second well layer 31 2 ) adjacent to the p-type compound semiconductor layer is made thicker than the thickness of the other well layers (specifically, the first well layer 31 1 ). Can do.
- Active layer Second well layer In 0.18 Ga 0.82 N (thickness: 2.8 nm) Second tunnel barrier layer GaN (thickness: 2.0 nm) Barrier layer In 0.05 Ga 0.95 N (thickness: 4.0 nm) First tunnel barrier layer GaN (thickness: 2.0 nm) First well layer In 0.18 Ga 0.82 N (thickness: 2.5 nm)
- the thickness of the well layer adjacent to the p-type compound semiconductor layer is made thicker than the thicknesses of the other well layers. Can also be arranged, or the deviation can be suppressed. As a result, it is possible to improve the light emission efficiency and reduce the threshold current.
- Example 1 and Example 2 can be combined, Example 1 and Example 3 can be combined, Example 2 and Example 3 can be combined, Example 1 can be combined. Example 2 and Example 3 can be combined.
- Example 4 is a modification of Example 1 to Example 3, and specifically relates to a light emitting diode (LED).
- the configuration (composition) of the multilayer structure in the optical semiconductor device of Example 4 is the same as the configuration (composition) of the multilayer structure in the optical semiconductor devices of Examples 1 to 3 shown in Tables 1 to 5. be able to.
- the light generated in the active layer is emitted to the outside through the n-type compound semiconductor layer 21 or is also emitted to the outside through the p-type compound semiconductor layer 22.
- the structure of the optical semiconductor device described in Embodiments 1 to 3 can be substantially the same as that described in Embodiments 1 to 3 except that it is unnecessary to form a ridge stripe structure. Description is omitted.
- Example 5 is also a modification of Examples 1 to 3, and specifically relates to a surface emitting laser element (vertical cavity laser, VCSEL).
- the surface emitting laser elements of Example 5 or Examples 6 to 7 described later are based on lateral growth using a method of epitaxial growth in the lateral direction such as an ELO (Epitaxial Lateral Overgrowth) method.
- ELO Epilium Lateral Overgrowth
- the surface-emitting laser element in which the n-type compound semiconductor layer is formed on the substrate on which the layer is formed is used, but the present invention is not limited to such a surface-emitting laser element.
- the “optical semiconductor device” may be referred to as a “surface emitting laser element”.
- the surface emitting laser elements of Example 5 or Examples 6 to 10 described later are: First light reflecting layer 51, A stacked structure 20 formed of the n-type compound semiconductor layer 21, the active layer 23, and the p-type compound semiconductor layer 22 formed on the first light reflecting layer 51, and a p-side electrode 42 and a second light reflecting layer 52 formed on the p-type compound semiconductor layer 22; It has.
- a first light reflecting layer 51 is formed on the first surface 21 a of the n-type compound semiconductor layer 21, and a second light reflecting layer 52 is formed above the second surface 22 b of the p-type compound semiconductor layer 22. ing.
- the second light reflection layer 52 is opposed to the first light reflection layer 51.
- the planar shape of the first light reflecting layer may be various polygons including regular hexagons, circles, ellipses, lattices (rectangles), islands, or stripes.
- the cross-sectional shape of the first light reflecting layer may be rectangular, it is more preferable that the first light reflecting layer is trapezoidal, that is, the side surface of the first light reflecting layer is forward tapered.
- the substrate may be left as it is.
- an active layer, a p-type compound semiconductor layer, a p-side electrode, and a second light reflecting layer are sequentially formed on the n-type compound semiconductor layer.
- the substrate may be removed.
- an active layer, a p-type compound semiconductor layer, a p-side electrode, and a second light reflecting layer are sequentially formed on the n-type compound semiconductor layer, and then the second light reflecting layer is fixed to the support substrate.
- the substrate is removed (in some cases, for example, the substrate is removed using the first light reflection layer as a polishing stopper layer) to expose the n-type compound semiconductor layer (the first surface of the n-type compound semiconductor layer).
- the first light reflection layer may be exposed.
- an n-side electrode may be formed on the n-type compound semiconductor layer (the first surface of the n-type compound semiconductor layer).
- an n-side electrode may be formed on the back surface of the substrate.
- the GaN substrate can be removed based on a chemical / mechanical polishing method (CMP method).
- CMP method chemical / mechanical polishing method
- alkaline aqueous solution such as sodium hydroxide aqueous solution or potassium hydroxide aqueous solution, ammonia solution + hydrogen peroxide solution, sulfuric acid solution + hydrogen peroxide solution, hydrochloric acid solution + hydrogen peroxide solution, phosphoric acid solution + hydrogen peroxide solution
- a part of the GaN substrate is removed by a wet etching method using a dry etching method, a dry etching method, a lift-off method using a laser, a mechanical polishing method, or a combination thereof, or the thickness of the GaN substrate.
- the chemical / mechanical polishing method is performed to expose the n-type compound semiconductor layer (the first surface of the n-type compound semiconductor layer). If formed, the first light reflection layer may be exposed.
- the surface roughness Ra of the p-type compound semiconductor layer (the second surface of the p-type compound semiconductor layer) is 1.0 nm or less. Is preferred.
- the surface roughness Ra is defined in JIS B-610: 2001, and can be specifically measured based on observation based on AFM or cross-section TEM.
- the distance from the first light reflecting layer to the second light reflecting layer is preferably 0.15 ⁇ m or more and 50 ⁇ m or less.
- the second light reflecting layer is positioned on the normal to the first light reflecting layer passing through the center of gravity of the area of the first light reflecting layer. It is preferable that the area centroid point does not exist.
- the area centroid of the active layer (specifically, the area centroid of the active layer constituting the element region. In the following, on the normal to the first light reflection layer passing through the area centroid of the first light reflection layer. The same is also preferred.
- a lateral epitaxial growth method such as an ELO (Epitaxial Lateral Overgrowth) method
- ELO Epi Lateral Overgrowth
- n-type compound semiconductor layers that are epitaxially grown from the edge of the light reflecting layer toward the center of the first light reflecting layer are associated, a large number of crystal defects may occur at the associated portion. If the meeting part where many crystal defects exist is located at the center of the element region (described later), there is a possibility that the characteristics of the surface emitting laser element are adversely affected.
- the form in which the area centroid of the second light reflecting layer does not exist on the normal to the first light reflecting layer passing through the area centroid of the first light reflecting layer, and the first passing through the area centroid of the first light reflecting layer By adopting a configuration in which the area centroid of the active layer does not exist on the normal line to the one-light reflecting layer, it is possible to reliably suppress the adverse effects on the characteristics of the surface emitting laser element.
- the light generated in the active layer is emitted to the outside through the second light reflecting layer (hereinafter referred to as “second” for convenience.
- a light emitting layer emitting type surface emitting laser element and a form that is emitted to the outside through the first light reflecting layer (hereinafter referred to as “first light reflecting layer emitting type surface” for convenience). It may also be referred to as a “light emitting laser element”.
- the substrate In the first light reflection layer emitting type surface emitting laser element, the substrate may be removed as described above.
- the area of the portion of the first light reflecting layer in contact with the first surface of the n-type compound semiconductor layer (the portion of the first light reflecting layer facing the second light reflecting layer) is S 1
- the area of the p-type compound semiconductor layer is when the area of the portion of the second light reflecting layer facing the second surface (portions of the first light reflecting layer facing the second light reflecting layer) was S 2
- S 1 ⁇ S 2 In the case of the surface emitting laser element of the second light reflection layer emission type, S 1 ⁇ S 2
- the present invention is not limited to this.
- the second light reflecting layer when the substrate is removed, as described above, the second light reflecting layer is It can be set as the form fixed to the support substrate.
- an n-side electrode may be formed on the exposed surface of the substrate.
- the first light reflecting layer and the n-side electrode can be separated from each other, and depending on the case, the n-side up to or below the edge of the first light reflecting layer.
- the state in which the electrode is formed can also be mentioned.
- the first light reflection layer and the n-side electrode may be separated from each other, that is, have an offset, and the separation distance may be within 1 mm.
- the n-side electrode can be made of a metal, an alloy, or a transparent conductive material
- the p-side electrode can be It can be made into the form which consists of a transparent conductive material.
- the current can be spread in the lateral direction (in-plane direction of the p-type compound semiconductor layer), and the current can be efficiently supplied to the element region (described below). Can do.
- “Element region” means a region where a confined current is injected (current confinement region), a region where light is confined due to a difference in refractive index, or the first light reflecting layer and the second light reflecting layer. Among the regions sandwiched between the regions, the region where laser oscillation occurs, or the region between the first light reflection layer and the second light reflection layer, which actually contributes to laser oscillation.
- the surface emitting laser element may be configured by a surface emitting laser element that emits light from the top surface of the n-type compound semiconductor layer through the first light reflecting layer, or may be a p-type.
- a configuration may also be adopted in which the surface emitting laser element emits light from the top surface of the compound semiconductor layer through the second light reflecting layer.
- a current confinement structure is preferably formed between the p-side electrode and the p-type compound semiconductor layer.
- a current confinement layer made of an insulating material for example, SiO x , SiN x , AlO x
- the p-type compound semiconductor layer may be etched by RIE or the like to form a mesa structure, or a part of the stacked p-type compound semiconductor layer may be partially oxidized from the lateral direction.
- a current confinement region may be formed, a region with reduced conductivity may be formed by ion implantation of impurities into the p-type compound semiconductor layer, or these may be combined as appropriate.
- the p-side electrode needs to be electrically connected to the portion of the p-type compound semiconductor layer through which current flows due to current confinement.
- the support substrate may be composed of various substrates such as a GaN substrate, a sapphire substrate, a GaAs substrate, an SiC substrate, an alumina substrate, a ZnS substrate, a ZnO substrate, a LiMgO substrate, a LiGaO 2 substrate, an MgAl 2 O 4 substrate, and an InP substrate.
- a insulating substrate made of AlN or the like, a semiconductor substrate made of Si, SiC, Ge or the like, a metal substrate, or an alloy substrate can be used, but it is preferable to use a conductive substrate.
- a metal substrate or an alloy substrate from the viewpoints of mechanical properties, elastic deformation, plastic deformability, heat dissipation, and the like.
- the thickness of the support substrate include 0.05 mm to 0.5 mm.
- a known method such as a solder bonding method, a room temperature bonding method, a bonding method using an adhesive tape, or a bonding method using wax bonding can be used. From the viewpoint of securing the property, it is desirable to employ a solder bonding method or a room temperature bonding method.
- the bonding temperature may be 400 ° C. or higher.
- the n-side electrode is, for example, gold (Au), silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), Ti (titanium), vanadium (V), tungsten (W), chromium (Cr ), Al (aluminum), Cu (copper), Zn (zinc), tin (Sn) and at least one metal selected from the group consisting of indium (In) (including alloys) or It is desirable to have a multilayer structure, specifically, for example, Ti / Au, Ti / Al, Ti / Al / Au, Ti / Pt / Au, Ni / Au, Ni / Au / Pt, Ni / Pt, Pd / Pt and Ag / Pd can be exemplified.
- the n-side electrode can be formed by, for example, a PVD method such as a vacuum evaporation method or a sputtering method.
- Indium-tin oxide including ITO, Indium Tin Oxide, Sn-doped In 2 O 3 , crystalline ITO, and amorphous ITO
- indium-zinc oxide as transparent conductive material constituting n-side electrode or p-side electrode
- IZO Indium Zinc Oxide
- IGO indium-gallium oxide
- IGZO indium-doped gallium-zinc oxide
- IFO IFO
- tin oxide examples thereof include SnO 2 ), ATO (Sb-doped SnO 2 ), FTO (F-doped SnO 2 ), and zinc oxide (including ZnO, Al-doped ZnO, and B-doped ZnO).
- the p-side electrode a transparent conductive film whose base layer is gallium oxide, titanium oxide, niobium oxide, nickel oxide, or the like can be given.
- the material constituting the p-side electrode depends on the arrangement state of the second light reflecting layer and the p-side electrode, but is not limited to the transparent conductive material. Palladium (Pd), platinum (Pt), Metals such as nickel (Ni), gold (Au), cobalt (Co), and rhodium (Rh) can also be used.
- the p-side electrode may be composed of at least one of these materials.
- the p-side electrode can be formed by, for example, a PVD method such as a vacuum evaporation method or a sputtering method.
- a pad electrode may be provided on the n-side electrode or the p-side electrode for electrical connection with an external electrode or circuit.
- the pad electrode includes a single layer containing at least one metal selected from the group consisting of Ti (titanium), aluminum (Al), Pt (platinum), Au (gold), Ni (nickel), and Pd (palladium). It is desirable to have a configuration or a multi-layer configuration.
- the pad electrode may be a Ti / Pt / Au multilayer structure, a Ti / Au multilayer structure, a Ti / Pd / Au multilayer structure, a Ti / Pd / Au multilayer structure, a Ti / Ni / Au multilayer structure, A multi-layer structure exemplified by a multi-layer structure of Ti / Ni / Au / Cr / Au can also be used.
- n-side electrode is composed of an Ag layer or an Ag / Pd layer
- a cover metal layer made of Ni / TiW / Pd / TiW / Ni is formed on the surface of the n-side electrode, and on the cover metal layer,
- a pad electrode having a multilayer structure of Ti / Ni / Au or a multilayer structure of Ti / Ni / Au / Cr / Au.
- the light reflecting layer (distributed Bragg reflector layer, distributed Bragg reflector layer, DBR layer) is composed of, for example, a semiconductor multilayer film or a dielectric multilayer film.
- the dielectric material include oxides and nitrides such as Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, and Ti (for example, SiN x , AlN x , and AlGaN). GaN x , BN x etc.) or fluorides.
- a light reflection layer can be obtained by laminating
- a dielectric multilayer film such as SiO x / SiN y , SiO x / NbO y , SiO x / ZrO y , SiO x / AlN y is preferable.
- each dielectric film may be appropriately selected.
- a surface emitting laser element having an emission wavelength ⁇ 0 of 450 nm when the light reflection layer is made of SiO x / NbO Y, about 40 nm to 70 nm can be exemplified.
- the number of stacked layers is 2 or more, preferably about 5 to 20. Examples of the total thickness of the light reflecting layer include about 0.6 ⁇ m to 1.7 ⁇ m.
- the first light reflecting layer preferably includes a dielectric film containing at least N (nitrogen) atoms. Furthermore, the dielectric film containing N atoms is the outermost layer of the dielectric multilayer film. The upper layer is more desirable.
- the first light reflecting layer is preferably covered with a dielectric material layer containing at least N (nitrogen) atoms. Alternatively, by nitriding the surface of the first light reflecting layer, the surface of the first light reflecting layer is referred to as a layer containing at least N (nitrogen) atoms (hereinafter referred to as “surface layer” for convenience). ) Is desirable.
- the thickness of the dielectric film or dielectric material layer containing at least N atoms, or the surface layer is preferably an odd multiple of ⁇ 0 / (4n).
- Specific examples of the material constituting the dielectric film or the dielectric material layer containing at least N atoms include SiN x and SiO x NZ .
- the light reflecting layer can be formed based on a well-known method. Specifically, for example, a vacuum deposition method, a sputtering method, a reactive sputtering method, an ECR plasma sputtering method, a magnetron sputtering method, an ion beam assisted deposition method, PVD methods such as ion plating method and laser ablation method; various CVD methods; coating methods such as spray method, spin coating method, dip method; method combining two or more of these methods; these methods and all or part A combination of at least one of typical pretreatment, inert gas (Ar, He, Xe, etc.) or plasma irradiation, oxygen gas or ozone gas, plasma irradiation, oxidation treatment (heat treatment), exposure treatment, etc. Can be mentioned.
- the substrate is made of a GaN substrate,
- the off angle of the surface orientation of the GaN substrate surface is within 0.4 degrees, preferably within 0.40 degrees.
- the area of the GaN substrate is S 0
- the area of the first light reflecting layer is 0.8S 0 or less
- the thermal expansion relaxation film is formed on the GaN substrate as the lowermost layer of the first light reflecting layer, or the linear thermal expansion coefficient CTE of the lowermost layer of the first light reflecting layer in contact with the GaN substrate is 1 ⁇ 10 ⁇ 6 / K ⁇ CTE ⁇ 1 ⁇ 10 ⁇ 5 / K
- 1 ⁇ 10 ⁇ 6 / K ⁇ CTE ⁇ 1 ⁇ 10 ⁇ 5 / K Is preferably satisfied.
- the surface roughness of the p-type compound semiconductor layer can be reduced by defining the off-angle of the plane orientation of the crystal plane of the GaN substrate surface and the ratio of the area of the first light reflecting layer. That is, a p-type compound semiconductor layer having an excellent surface morphology can be formed. Therefore, the second light reflecting layer having excellent smoothness can be obtained, that is, a desired light reflectance can be obtained, and the characteristic variation hardly occurs.
- a thermal expansion mitigating film or defining the value of CTE it is possible to obtain the first from the GaN substrate due to the difference between the linear thermal expansion coefficient of the GaN substrate and the linear thermal expansion coefficient of the first light reflecting layer.
- the occurrence of the problem that the one-light reflecting layer is peeled off can be avoided, and a surface emitting laser element having high reliability can be provided. Furthermore, when a GaN substrate is used, the problem that dislocations hardly occur in the compound semiconductor layer and the thermal resistance of the surface emitting laser element increases can be avoided, and high reliability is imparted to the surface emitting laser element.
- the n-side electrode can be provided on the side different from the p-side electrode (the back side of the substrate) with respect to the GaN substrate.
- the off-angle of the surface orientation of the GaN substrate surface refers to the angle formed by the crystal surface orientation of the GaN substrate surface and the normal of the GaN substrate surface viewed macroscopically.
- the area of the GaN substrate is S 0
- the area of the first light reflecting layer is defined to be 0.8 S 0 or less, but the “area S 0 of the GaN substrate” It refers to the area of the GaN substrate left when a light emitting laser element is obtained. In these cases, the lowermost layer of the first light reflection layer does not have a function as a light reflection layer.
- the thermal expansion relaxation film includes silicon nitride (SiN x ), aluminum oxide (AlO x ), niobium oxide (NbO x ), tantalum oxide (TaO x ), titanium oxide (TiO x ), magnesium oxide (MgO x ), zirconium oxide. It can be in the form of at least one material selected from the group consisting of (ZrO x ) and aluminum nitride (AlN x ).
- the value of the subscript “X” attached to the chemical formula of each substance, the subscript “Y”, and the subscript “Z”, which will be described later, is based not only on the stoichiometry but also on the stoichiometry.
- the thickness of the thermal expansion relaxation film t 1
- the emission wavelength of the surface emitting laser element is ⁇ 0
- the refractive index of the thermal expansion relaxation film is n 1
- t 1 ⁇ 0 / (4n 1 )
- t 1 ⁇ 0 / (2n 1 )
- the value of the thickness t 1 of the thermal expansion relaxation film can be essentially arbitrary, for example, 1 ⁇ 10 ⁇ 7 m or less.
- the lowest layer of the first light reflecting layer is silicon nitride (SiN x ), aluminum oxide (AlO x ), niobium oxide (NbO x ), tantalum oxide (TaO x ), titanium oxide (TiO x ), magnesium oxide (MgO x ). ), Zirconium oxide (ZrO x ) and aluminum nitride (AlN x ).
- the thickness of the lowermost layer of the first light reflecting layer t 1
- the emission wavelength of the surface emitting laser element is ⁇ 0
- the refractive index of the lowermost layer of the first light reflecting layer is n 1
- t 1 ⁇ 0 / (4n 1 )
- t 1 ⁇ 0 / (2n 1 )
- the value of the thickness t 1 of the lowermost layer of the first light reflecting layer can be essentially arbitrary, for example, 1 ⁇ 10 ⁇ 7 m or less.
- the planar shape of the first light reflecting layer 51 is a regular hexagon.
- the regular hexagons are arranged or arranged so that the compound semiconductor layer epitaxially grows laterally in the [11-20] direction or a crystallographically equivalent direction.
- the shape of the 1st light reflection layer 51 is not limited to this, For example, it can also be made circular, a grid
- the n-type compound semiconductor layer 21, the active layer 23, and the p-type compound semiconductor layer 22 are made of a GaN-based compound semiconductor. More specifically, An n-type compound semiconductor layer 21 made of a GaN-based compound semiconductor and having a first surface 21a and a second surface 21b opposite to the first surface 21a; An active layer (light emitting layer) 23 made of a GaN-based compound semiconductor and in contact with the second surface 21b of the n-type compound semiconductor layer 21, and A p-type compound semiconductor layer 22 made of a GaN-based compound semiconductor, having a first surface 22a and a second surface 22b facing the first surface 22a, the first surface 22a being in contact with the active layer 23; Are laminated.
- a p-side electrode 42 and a second light reflecting layer 52 made of a dielectric multilayer film are formed, and the substrate 11 on which the laminated structure 20 is formed.
- An n-side electrode 41 is formed on the other surface 11b of the substrate 11 facing the surface 11a.
- the first light reflection layer 51 made of a dielectric multilayer film is formed on the surface 11 a of the substrate 11 and is in contact with the first surface 21 a of the n-type compound semiconductor layer 21.
- the surface emitting laser element of Example 5 is a surface emitting laser element that emits light from the top surface of the p-type compound semiconductor layer 22 through the second light reflecting layer 52. Specifically, it is a second light reflection layer emission type surface emitting laser element in which light is emitted from the second surface 22 b of the p-type compound semiconductor layer 22 through the second light reflection layer 52.
- the substrate 11 remains.
- the configuration and structure of the multilayer structure 20 can be substantially the same as the configuration and structure of the multilayer structure 20 in the surface emitting laser elements described in the first to third embodiments.
- an insulating material such as SiO x , SiN x , and AlO x is formed between the p-side electrode 42 and the p-type compound semiconductor layer 22.
- a current confinement layer 43 is formed.
- An opening 43A is formed in the current confinement layer 43, and the p-type compound semiconductor layer 22 is exposed at the bottom of the opening 43A.
- the p-side electrode 42 is formed on the current confinement layer 43 from the second surface 22 b of the p-type compound semiconductor layer 22, and the second light reflecting layer 52 is formed on the p-side electrode 42.
- a pad electrode 44 for electrical connection with an external electrode or circuit is connected on the edge of the p-side electrode 42.
- the planar shape of the first light reflection layer 51 is a regular hexagon, and is provided in the second light reflection layer 52 and the current confinement layer 43.
- the planar shape of the opening 43A is a circle.
- the first light reflection layer 51 and the second light reflection layer 52 have a multilayer structure, but are shown as one layer for the sake of simplification of the drawing.
- the formation of the current confinement layer 43 is not essential.
- the distance from the first light reflecting layer 51 to the second light reflecting layer 52 is not less than 0.15 ⁇ m and not more than 50 ⁇ m, specifically, for example, 10 ⁇ m.
- the normal to the first light reflecting layer 51 through the centroid point of the first light reflection layer 51 shown in LN 1 normal to the second light reflecting layer 52 through the area center of gravity of the second light reflecting layer 52 Is denoted by LN 2.
- LN 1 and LN 2 coincide with each other.
- the n-type compound semiconductor layer 21 is composed of an n-type GaN layer having a thickness of 5 ⁇ m
- the active layer 23 has the configuration and structure described in the first to third embodiments
- the p-type compound semiconductor layer 22 is a p-type AlGaN electron. It has a two-layer structure of a barrier layer (thickness 10 nm) and a p-type GaN layer. The electron barrier layer is located on the active layer side.
- the n-side electrode 41 is made of Ti / Pt / Au
- the p-side electrode 42 is made of a transparent conductive material, specifically, ITO
- the pad electrode 44 is made of Ti / Pd / Au or Ti / Pt / Au
- the first light reflecting layer 51 and the second light reflecting layer 52 have a laminated structure of SiN X layers and SiO Y layers (total number of laminated dielectric multilayer films: 20 layers), and the thickness of each layer is ⁇ 0 / (4n ).
- FIGS. 3A, 3B, and 3C are schematic partial end views of the substrate and the like.
- a first light reflecting layer 51 is formed on a substrate (specifically, a GaN substrate) 11. Specifically, first, a dielectric multilayer film for forming the first light reflecting layer 51 on the entire surface is formed on the substrate 11 based on the sputtering method, and then the dielectric multilayer film based on the photolithography technique and the dry etching technique.
- the first light reflection layer 51 can be obtained by patterning (see FIG. 3A).
- the n-type compound semiconductor layer 21, the active layer 23, and the p-type compound semiconductor layer 22 are formed on the entire surface.
- the n-type compound semiconductor layer 21 made of n-type GaN is formed on the entire surface based on an MOCVD method (using TMG gas and SiH 4 gas) that is epitaxially grown in the lateral direction such as the ELO method.
- the active layer 23 and the p-type compound semiconductor layer 22 are formed on the entire surface.
- an active layer 23 is formed on the n-type compound semiconductor layer 21 using TMG gas and TMI gas, and then electrons are generated using TMG gas, TMA gas, and Cp 2 Mg gas.
- a p-type compound semiconductor layer 22 is obtained by forming a barrier layer and forming a p-type GaN layer using TMG gas and Cp 2 Mg gas.
- the laminated structure 20 can be obtained through the above steps. That is, on the substrate (specifically, the GaN substrate) 11 including the first light reflecting layer 51, An n-type compound semiconductor layer 21 made of a GaN-based compound semiconductor and having a first surface 21a and a second surface 21b facing the first surface 21a; An active layer 23 made of a GaN-based compound semiconductor and in contact with the second surface 21b of the n-type compound semiconductor layer 21, and A p-type compound semiconductor layer 22 made of a GaN-based compound semiconductor, having a first surface 22a and a second surface 22b facing the first surface 22a, the first surface 22a being in contact with the active layer 23; The laminated structure 20 formed by laminating is epitaxially grown. In this way, the structure shown in FIG. 3B can be obtained.
- a current confinement layer 43 made of an insulating material having a thickness of 0.2 ⁇ m and having an opening 43A is formed on the second surface 22b of the p-type compound semiconductor layer 22 based on a known method.
- a p-side electrode and a second light reflecting layer facing the first light reflecting layer 51 are formed on the p-type compound semiconductor layer 22.
- the second light reflecting layer 52 including the p-side electrode 42 and the dielectric multilayer film is formed on the second surface 22 b of the p-type compound semiconductor layer 22.
- a p-side electrode 42 made of ITO having a thickness of 50 nm is formed over the current confinement layer 43 from the second surface 22b of the p-type compound semiconductor layer 22 based on a lift-off method.
- the pad electrode 44 is formed over the current confinement layer 43 from the p-side electrode 42 based on a known method. In this way, the structure shown in FIG.
- the second light reflecting layer 52 is formed on the p-side electrode 42 over the pad electrode 44 based on a known method.
- the n-side electrode 41 is formed on the other surface 11b of the substrate 11 based on a known method.
- the surface emitting laser element of Example 5 having the structure shown in FIG. 2A can be obtained.
- Step-540 Thereafter, the surface emitting laser element is separated by performing so-called element separation, and the side surface and the exposed surface of the multilayer structure 20 are covered with, for example, an insulating film made of SiO x . Then, in order to connect the n-side electrode 41 and the pad electrode 44 to an external circuit or the like, a terminal or the like is formed based on a well-known method, and packaged or sealed, thereby completing the surface emitting laser element of Example 5. .
- the n-type compound semiconductor layer 21 is formed on the substrate 11 on which the first light reflection layer 51 is formed by lateral growth based on a method of epitaxial growth in the lateral direction such as the ELO method, the first When the n-type compound semiconductor layer 21 epitaxially grows from the edge of the light reflecting layer 51 toward the center of the first light reflecting layer 51, many crystal defects may occur at the associated portion.
- the first normal LN 1 with respect to the first light reflecting layer 51 passing through the center of gravity of the area of the first light reflecting layer 51 is The area centroid of the two-light reflecting layer 52 does not exist.
- the area center of gravity of the active layer 23 does not exist on the normal LN 1 with respect to the first light reflecting layer 51 passing through the area center of gravity of the first light reflecting layer 51.
- the associated portion (specifically, located on or near the normal line LN 1 ) where there are many crystal defects is not located in the center of the element region, which adversely affects the characteristics of the surface emitting laser element. Will not occur, or adverse effects on the characteristics of the surface emitting laser element will be reduced.
- Example 6 is a modification of Example 5. As shown in FIG. 4A, which is a schematic partial cross-sectional view, the light generated in the active layer 23 in the surface emitting laser element of Example 6 is transmitted from the top surface of the n-type compound semiconductor layer 21 to the first light reflecting layer 51. It is emitted to the outside via That is, the surface emitting laser element of Example 6 is a first light reflecting layer emitting type surface emitting laser element.
- the second light reflection layer 52 was formed of a silicon semiconductor substrate via a bonding layer 45 made of a solder layer containing a gold (Au) layer or tin (Sn).
- the support substrate 46 is fixed based on a solder bonding method.
- Example 6 the active layer 23, the p-type compound semiconductor layer 22, the p-side electrode 42, and the second light reflecting layer 52 are sequentially formed on the n-type compound semiconductor layer 21, and then the second light reflecting layer.
- the substrate 11 is removed using the first light reflection layer 51 as a polishing stopper layer, and the n-type compound semiconductor layer 21 (the first surface 21a of the n-type compound semiconductor layer 21) and the first The light reflecting layer 51 is exposed.
- the n-side electrode 41 is formed on the n-type compound semiconductor layer 21 (the first surface 21a of the n-type compound semiconductor layer 21).
- the distance from the first light reflecting layer 51 to the second light reflecting layer 52 is not less than 0.15 ⁇ m and not more than 50 ⁇ m, and specifically, for example, 10 ⁇ m.
- the first light reflection layer 51 and the n-side electrode 41 are separated from each other, that is, have an offset, and the separation distance is within 1 mm, specifically, For example, the average is 0.05 mm.
- FIGS. 5A and 5B are schematic partial end views of the laminated structure and the like, a method for manufacturing the surface emitting laser element of Example 6 will be described.
- Step-600 First, steps similar to those in [Step-500] to [Step-530] in Example 5 are performed to obtain the structure shown in FIG. 2A. However, the n-side electrode 41 is not formed.
- Step-610 Thereafter, the second light reflecting layer 52 is fixed to the support substrate 46 through the bonding layer 45.
- the structure shown in FIG. 5A can be obtained.
- Step-620 Next, the substrate (GaN substrate) 11 is removed, and the first surface 21a of the n-type compound semiconductor layer 21 and the first light reflecting layer 51 are exposed. Specifically, first, the thickness of the substrate 11 is reduced based on the mechanical polishing method, and then the remaining portion of the substrate 11 is removed based on the CMP method. Thus, the first surface 21a of the n-type compound semiconductor layer 21 and the first light reflecting layer 51 are exposed, and the structure shown in FIG. 9B can be obtained.
- Step-630 Thereafter, the n-side electrode 41 is formed on the first surface 21a of the n-type compound semiconductor layer 21 based on a known method.
- the surface emitting laser element of Example 6 having the structure shown in FIG. 4A can be obtained.
- Step-640 the surface emitting laser element is separated by performing so-called element separation, and the side surface and the exposed surface of the multilayer structure 20 are covered with, for example, an insulating film made of SiO x . Then, in order to connect the n-side electrode 41 and the pad electrode 44 to an external circuit or the like, a terminal or the like is formed based on a well-known method, and packaged or sealed, thereby completing the surface emitting laser element of Example 6. .
- the substrate is removed in a state where the first light reflection layer is formed. Therefore, as a result of the first light reflecting layer functioning as a polishing stopper layer at the time of removing the substrate, it is possible to suppress the occurrence of variations in the removal of the substrate in the substrate surface and, further, the variation in the thickness of the n-type compound semiconductor layer. As a result, the length of the resonator can be made uniform, and as a result, the characteristics of the obtained surface-emitting laser element can be stabilized. Moreover, since the surface (flat surface) of the n-type compound semiconductor layer at the interface between the first light reflecting layer and the n-type compound semiconductor layer is flat, light scattering on the flat surface can be minimized. .
- the end of the n-side electrode 41 is separated from the first light reflecting layer 51.
- the end portion of the n-side electrode 41 extends to the outer edge of the first light reflecting layer 51.
- the n-side electrode may be formed so that the end of the n-side electrode is in contact with the first light reflecting layer.
- the seventh embodiment is a modification of the fifth to sixth embodiments.
- a schematic partial cross-sectional view of the surface emitting laser element of Example 7 is shown in FIG.
- the off-angle of the crystal orientation of the surface 11a of the GaN substrate 11 is within 0.4 degrees, preferably within 0.40 degrees, and the area of the GaN substrate 11 is defined as S 0.
- the area of the first light reflection layer 51 is 0.8 S 0 or less.
- 0.004 ⁇ S 0 can be exemplified as the lower limit value of the area of the first light reflecting layer 51.
- the thermal expansion relaxation film 53 is formed on the GaN substrate 11 as the lowermost layer of the first light reflecting layer 51, or the lowermost layer (thermal expansion of the first light reflecting layer 51 in contact with the GaN substrate 11).
- the linear thermal expansion coefficient CTE of the relaxation film 53 is 1 ⁇ 10 ⁇ 6 / K ⁇ CTE ⁇ 1 ⁇ 10 ⁇ 5 / K
- the thermal expansion relaxation film 53 (the lowermost layer of the first light reflection layer 51) having such a film thickness is transparent to light having a wavelength ⁇ 0 and does not have a function as a light reflection layer.
- the values of CTE of silicon nitride (SiN x ) and GaN substrate 11 are as shown in Table 6 below. The value of CTE is a value at 25 ° C.
- GaN substrate 5.59 ⁇ 10 ⁇ 6 / K
- the thermal expansion relaxation film 53 constituting the lowermost layer of the first light reflection layer 51 is formed, and further, a dielectric is formed on the thermal expansion relaxation film 53.
- the remainder of the first light reflecting layer 51 made of a multilayer film is formed.
- the 1st light reflection layer 51 is obtained by performing patterning. Thereafter, the same steps as [Step-510] to [Step-540] of the fifth embodiment may be performed.
- Example 7 the relationship between the off angle and the surface roughness Ra of the p-type compound semiconductor layer 22 was examined. The results are shown in Table 7 below. From Table 7, it can be seen that when the off-angle exceeds 0.4 degrees, the value of the surface roughness Ra of the p-type compound semiconductor layer 22 increases. That is, by setting the off angle to 0.4 degrees or less, preferably within 0.40 degrees, step bunching during the growth of the compound semiconductor layer can be suppressed, and the surface roughness Ra of the p-type compound semiconductor layer 22 can be suppressed. As a result, the second light reflecting layer 52 excellent in smoothness can be obtained, and variations in characteristics such as light reflectance are unlikely to occur.
- the surface roughness Ra of the p-type compound semiconductor layer 22 is preferably 1.0 nm or less.
- the lowermost layer of the first light reflection layer 51 is made of SiO x (CTE: 0.51 to 0.58 ⁇ 10 ⁇ 6 / K),
- the first light reflection layer 51 was peeled off from the GaN substrate 11 during the film formation of the multilayer structure 20 depending on the manufacturing conditions. There was a case. On the other hand, in Example 7, the first light reflection layer 51 did not peel from the GaN substrate 11 during the formation of the multilayer structure 20.
- the off-angle of the crystal orientation of the GaN substrate surface and the ratio of the area of the first light reflecting layer are defined.
- the surface roughness of the compound semiconductor layer can be reduced. That is, a p-type compound semiconductor layer having an excellent surface morphology can be formed.
- the second light reflecting layer having excellent smoothness can be obtained, so that a desired light reflectance can be obtained, and variations in the characteristics of the surface emitting laser element hardly occur.
- the thermal expansion relaxation film is formed or the value of CTE is defined, the GaN substrate is separated from the GaN substrate due to the difference between the linear thermal expansion coefficient of the GaN substrate and the linear thermal expansion coefficient of the first light reflecting layer.
- the occurrence of the problem that the first light reflection layer is peeled off can be avoided, and a surface emitting laser element having high reliability can be provided. Furthermore, since a GaN substrate is used, dislocations are unlikely to occur in the compound semiconductor layer, and problems such as an increase in the thermal resistance of the surface emitting laser element can be avoided, so that high reliability is imparted to the surface emitting laser element.
- the n-side electrode can be provided on the side different from the p-side electrode (the back side of the substrate) with respect to the GaN substrate.
- Example 8 is a modification of Example 6.
- the first surface 21 a of the n-type compound semiconductor layer 21 is provided with a convex portion 21 c, and the first light reflecting layer is formed.
- 51 is formed on the convex portion 21 c
- the n-side electrode 41 is formed in the concave portion 21 e around the convex portion 21 c formed on the first surface 21 a of the n-type compound semiconductor layer 21. That is, in Example 8, the n-type compound semiconductor layer 21 has a so-called mesa shape.
- the planar shape of the convex portion 21c is a circle.
- the light is dissipated out of the resonator when the light returns between the first light reflecting layer 51 and the second light reflecting layer 52.
- the possibility of causing problems such as an increase in operating voltage and a decrease in reliability is eliminated.
- the planar shape of the n-side electrode 41 is a ring (ring shape).
- the planar shape of the element region is circular, and the planar shape of the opening 43A provided in the first light reflecting layer 51, the second light reflecting layer 52, and the current confinement layer 43 is also circular.
- the height of the convex portion 21c is less than the thickness of the n-type compound semiconductor layer 21, and the height of the convex portion 21c is 1 ⁇ 10 ⁇ 8 m or more and 1 ⁇ 10 ⁇ 5 m or less, specifically, For example, 2 ⁇ 10 ⁇ 6 m can be exemplified.
- the size of the convex portion 21 c is larger than the first light reflecting layer 51 and larger than the element region.
- a dielectric layer 28 made of SiO 2 , SiN, AlN, ZrO 2 , Ta 2 O 5 or the like is formed on the side surface (side wall) 21d of the convex portion 21c.
- the refractive index value of the material constituting the dielectric layer 28 is preferably smaller than the average refractive index value of the material constituting the n-type compound semiconductor layer 21.
- Example 8 can be the same as the configuration and structure of the surface emitting laser element of Example 6, and thus detailed description thereof is omitted.
- FIGS. 8A, 8B, 8C, 9A, 9B, and 10 are schematic partial end views of a laminated structure and the like, a method for manufacturing the surface emitting laser element of Example 8 will be described.
- the laminated structure 20 is formed on the substrate 11.
- the first light reflection layer 51 is formed in a later step.
- Step-800 First, on a substrate 11 made of a GaN substrate, a first surface 21a, an n-type compound semiconductor layer 21 having a second surface facing the first surface 21a, and a GaN-based compound semiconductor are formed. , An active layer 23 in contact with the second surface 21b of the n-type compound semiconductor layer 21, a GaN-based compound semiconductor, a first surface 22a, and a second surface 22b facing the first surface 22a, A stacked structure 20 formed by stacking the p-type compound semiconductor layers 22 whose one surface 22a is in contact with the active layer 23 is formed based on a known MOCVD method. Next, a current confinement layer 43 having an opening 43A is formed on the p-type compound semiconductor layer 22 based on a known method. In this way, the structure shown in FIG. 8A can be obtained.
- the second light reflecting layer 52 including the p-side electrode 42 and the dielectric multilayer film is formed on the second surface 22 b of the p-type compound semiconductor layer 22.
- the p-side electrode 42 is formed from the second surface 22b of the p-type compound semiconductor layer 22 over the current confinement layer 43, and the p-side electrode 42 A pad electrode 44 is formed over the current confinement layer 43 from above based on a known method.
- the second light reflecting layer 52 is formed on the p-side electrode 42 over the pad electrode 44 based on a known method. In this way, the structure shown in FIG. 8C can be obtained.
- Step-820 Thereafter, the second light reflecting layer 52 is fixed to the support substrate 46 through the bonding layer 45. In this way, the structure shown in FIG. 9A can be obtained.
- the substrate 11 is removed to expose the first surface 21 a of the n-type compound semiconductor layer 21. Specifically, first, the thickness of the substrate 11 is reduced based on the mechanical polishing method, then the remaining portion of the substrate 11 is removed based on the CMP method, and the exposed n-type compound semiconductor layer 21 is further removed in the thickness direction. The first surface 21a of the n-type compound semiconductor layer 21 is partially removed and a mirror finishing process is performed. In this way, the structure shown in FIG. 9B can be obtained.
- Step-840 And the convex part 21c and the recessed part 21e are formed in the 1st surface 21a of the n-type compound semiconductor layer 21,
- the 1st light reflection layer 51 which consists of a dielectric multilayer film is formed on the convex part 21c,
- the convex part 21c and a recessed part
- the n-side electrode 41 is formed on 21e, and the dielectric layer 28 is formed on the side surface (side wall) 21d of the convex portion 21c.
- the exposed region of the n-type compound semiconductor layer 21 is By performing etching based on the RIE method, the convex portion 21c and the concave portion 21e are formed.
- the structure shown in FIG. 10 can be obtained.
- the dielectric layer 28 is formed on the side surface (side wall) 21d of the convex portion 21c by a known method.
- the first light reflecting layer 51 is formed on the convex portion 21c of the n-type compound semiconductor layer 21 based on a known method. Thereafter, the n-side electrode 41 is formed in the recess 21e of the n-type compound semiconductor layer 21 based on a known method.
- the surface emitting laser element of Example 8 having the structure shown in FIG. 7 can be obtained.
- the order of the formation of the convex portion 21c on the first surface 21a of the n-type compound semiconductor layer 21, the formation of the dielectric layer 28, the formation of the first light reflection layer 51, and the formation of the n-side electrode 41 is as follows.
- the first surface 21a is not limited to the order described above, such as the formation of the convex portion 21c, the formation of the dielectric layer 28, the formation of the first light reflection layer 51, and the formation of the n-side electrode 41.
- the formation of the light reflecting layer 51, the formation of the protrusion 21c on the first surface 21a of the n-type compound semiconductor layer 21, the formation of the dielectric layer 28, and the formation of the n-side electrode 41 may be performed in this order.
- 21 may be formed in the order of the formation of the convex portion 21c on the first surface 21a, the formation of the dielectric layer 28, the formation of the n-side electrode 41, and the formation of the first light reflection layer 51. Can be formed.
- Step-850 Thereafter, the surface emitting laser element is separated by performing so-called element separation, and the side surface and the exposed surface of the laminated structure are covered with an insulating film made of, for example, SiO 2 . Then, in order to connect the n-side electrode 41 and the pad electrode 44 to an external circuit or the like, a terminal or the like is formed based on a well-known method, and packaged or sealed, thereby completing the surface emitting laser element of Example 8. .
- the ninth embodiment is a modification of the eighth embodiment.
- an annular groove 21 f is formed so as to surround the first light reflecting layer 51 formed on the first surface 21 a of the n-type compound semiconductor layer 21.
- the groove portion 21f is filled with an insulating material. That is, an insulating material layer 29 made of SiO 2 , SiN, AlN, ZrO 2 , Ta 2 O 5 or the like is formed in the groove 21f.
- an insulating material layer 29 made of SiO 2 , SiN, AlN, ZrO 2 , Ta 2 O 5 or the like is formed in the groove 21f.
- the depth of the groove portion 21f is less than the thickness of the n-type compound semiconductor layer 21, and the depth of the groove portion 21f is 1 ⁇ 10 ⁇ 8 m or more and 1 ⁇ 10 ⁇ 5 m or less. An example is 2 ⁇ 10 ⁇ 6 m.
- the inner diameter of the groove 21f is larger than that of the first light reflecting layer 51 and larger than the element region.
- Example 9 can be the same as the configuration and structure of the surface emitting laser element of Example 6, and a detailed description thereof will be omitted.
- the surface emitting laser element of Example 9 is the same as [Step-840] in the surface emitting laser element of Example 8, instead of forming the convex portion 21c on the first surface 21a of the n-type compound semiconductor layer 21.
- the groove 21f may be formed, and the insulating material layer 29 may be formed in the groove 21f.
- a groove 21f is formed in the substrate (specifically, a GaN substrate) 11, an insulating material layer 29 is formed in the groove 21f, and then A first light reflecting layer 51 is formed on the substrate 11.
- the n-type compound semiconductor is formed on the entire surface, that is, on the insulating material layer 29 filled in the substrate 11, the first light reflecting layer 51, and the groove 21f.
- the insulating material layer 29 is a polishing stopper layer. Therefore, variation in the thickness direction of the n-type compound semiconductor layer 21 can be suppressed.
- the tenth embodiment is also a modification of the eighth to ninth embodiments.
- FIGS. 11A and 11B schematic partial cross-sectional views of the first light reflecting layer passing through the area center of gravity of the first light reflecting layer are used.
- the normal line LN 1 of the layer does not coincide with the normal line LN 2 of the second light reflecting layer passing through the center of gravity of the area of the second light reflecting layer facing the p-type compound semiconductor layer.
- the area centroid point of the active layer (specifically, the area centroid point of the active layer constituting the element region) is on the normal line LN 1 with respect to the first light reflecting layer passing through the area centroid point of the first light reflecting layer. ) Does not exist.
- 11A is a modification of the surface emitting laser element of Example 8 shown in FIG. 7A
- the surface emitting laser element shown in FIG. 11B is the surface of Example 9 shown in FIG. 7B. This is a modification of the light emitting laser element.
- the mode in which the light field intensity at the center of the resonator is the strongest, that is, the fundamental mode is often the most stable.
- the normal line LN 1 of the first light reflecting layer 51 passing through the center of gravity of the area of the first light reflecting layer 51 and the second light facing the p-type compound semiconductor layer 22 is often the most stable.
- the normal line LN 2 of the second light reflecting layer 52 passing through the area centroid of the portion of the reflecting layer 52 does not coincide, or alternatively, the first light reflecting layer passing through the area centroid of the first light reflecting layer 51
- the mesa-shaped central axis serving as a waveguide in the element region (current injection region) and the n-type compound semiconductor layer 21 is provided.
- the stability of the fundamental mode during high power operation can be lowered and kinks can be caused, and the upper limit of the light output of the surface emitting laser element can be lowered. Therefore, it is preferable to employ such a configuration when used for applications where it is desirable to limit the upper limit of output, such as irradiation of a living body with laser light.
- Examples of the deviation amount between the normal line LN 1 and the normal line LN 2 include 0.01R 0 to 0.25R 0 when the diameter when the planar shape of the element region is assumed to be a circle is R 0 .
- Example 10 can be the same as the structure and structure of the surface emitting laser elements of Example 8 to Example 9, and detailed description thereof is omitted. To do.
- the present disclosure has been described based on the preferred embodiments, the present disclosure is not limited to these embodiments.
- the configurations and structures of the light-emitting elements described in the examples are exemplifications, and can be changed as appropriate.
- the methods for manufacturing the light-emitting elements in the examples can also be changed as appropriate.
- this indication can also take the following structures.
- [A03] The optical semiconductor device according to [A01], wherein the thickness of the well layer adjacent to the p-type compound semiconductor layer is thicker than the thicknesses of the other well layers.
- [A04] The optical semiconductor device according to [A03], wherein the band gap energy of the well layer adjacent to the p-type compound semiconductor layer is smaller than the band gap energy of the other well layers.
- [A05] The optical semiconductor device according to any one of [A01] to [A04], wherein the tunnel barrier layer is formed between the well layer and the barrier layer.
- Optical Semiconductor Device Second Aspect >> An n-type compound semiconductor layer, an active layer, and a p-type compound semiconductor layer have a stacked structure in which the layers are stacked in this order, The active layer has a multiple quantum well structure having a tunnel barrier layer, An optical semiconductor device in which the band gap energy of the well layer adjacent to the p-type compound semiconductor layer is smaller than the band gap energy of the other well layers. [B02] The optical semiconductor device according to [B01], wherein the thickness of the well layer adjacent to the p-type compound semiconductor layer is thicker than the thicknesses of the other well layers.
- [B03] The optical semiconductor device according to [B01] or [B02], in which the tunnel barrier layer is formed between the well layer and the barrier layer.
- [C01] ⁇ Optical Semiconductor Device: Third Aspect >> An n-type compound semiconductor layer, an active layer, and a p-type compound semiconductor layer have a stacked structure in which the layers are stacked in this order, The active layer has a multiple quantum well structure having a tunnel barrier layer, An optical semiconductor device in which the thickness of the well layer adjacent to the p-type compound semiconductor layer is thicker than the thickness of the other well layers.
- [C02] The optical semiconductor device according to [C01], wherein the tunnel barrier layer is formed between the well layer and the barrier layer.
- [D04] The optical semiconductor device according to [D02] or [D03], wherein the n-type compound semiconductor layer is formed on the c-plane of the GaN substrate.
- a surface emitting laser element The off angle of the surface orientation of the GaN substrate surface is within 0.4 degrees, preferably within 0.40 degrees.
- the area of the GaN substrate is S 0
- the area of the first light reflecting layer is 0.8S 0 or less
- the optical semiconductor device according to [D03] or [D04] in which a thermal expansion relaxation film is formed on a GaN substrate as a lowermost layer of the first light reflection layer.
- the thermal expansion relaxation film is made of [E01] made of at least one material selected from the group consisting of silicon nitride, aluminum oxide, niobium oxide, tantalum oxide, titanium oxide, magnesium oxide, zirconium oxide, and aluminum nitride.
- the linear thermal expansion coefficient CTE of the lowermost layer of the first light reflecting layer in contact with the GaN substrate is 1 ⁇ 10 ⁇ 6 / K ⁇ CTE ⁇ 1 ⁇ 10 ⁇ 5 / K
- the lowermost layer of the first light reflecting layer is made of at least one material selected from the group consisting of silicon nitride, aluminum oxide, niobium oxide, tantalum oxide, titanium oxide, magnesium oxide, zirconium oxide, and aluminum nitride.
- t 1 the thickness of the lowermost layer of the first light reflecting layer
- the emission wavelength of the optical semiconductor device is ⁇ 0
- the refractive index of the lowermost layer of the first light reflecting layer is n 1
- t 1 ⁇ 0 / (2n 1 )
- SYMBOLS 11 Substrate (GaN substrate), 20 ... Multilayer structure, 21 ... n-type compound semiconductor layer, 21A ... n-cladding layer, 21B ... n-guide layer, 21a ... 1st surface of n-type compound semiconductor layer, 21b... 2nd surface of n-type compound semiconductor layer, 21c... convex portion provided on n-type compound semiconductor layer, 21d. ), 21e... Concave portions around the convex portions, 22... P-type compound semiconductor layer, 22A... Electron barrier layer, 22B... P-cladding layer, 22C. ... 1st surface of p-type compound semiconductor layer, 22b ...
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Abstract
Description
n型化合物半導体層、活性層、及び、p型化合物半導体層がこの順に積層された積層構造体を有し、
活性層は、トンネルバリア層を有する多重量子井戸構造を備えている。
1.本開示の第1の態様~第3の態様に係る光半導体デバイス、全般に関する説明
2.実施例1(本開示の第1の態様に係る光半導体デバイス、半導体レーザ素子)
3.実施例2(本開示の第2の態様に係る光半導体デバイス、半導体レーザ素子)
4.実施例3(本開示の第3の態様に係る光半導体デバイス、半導体レーザ素子)
5.実施例4(実施例1~実施例3の変形、発光ダイオード)
6.実施例5(実施例1~実施例3の変形、面発光レーザ素子)
7.実施例6(実施例5の変形)
8.実施例7(実施例5~実施例6の別の変形)
9.実施例8(実施例6の変形)
10.実施例9(実施例8の別の変形)
11.実施例10(実施例8~実施例9の変形)
12.その他
本開示の第1の態様~第3の態様に係る光半導体デバイスにおいて、活性層と接するn型化合物半導体層の面をn型化合物半導体層の第2面、この第2面と対向する面をn型化合物半導体層の第1面と呼ぶ。また、活性層と接するp型化合物半導体層の面をp型化合物半導体層の第1面、この第1面と対向する面をp型化合物半導体層の第2面と呼ぶ。
p側電極26 Pd/Au
p型化合物半導体層22
p-コンタクト層22C GaN(厚さ0.1μm)
p-クラッド層22B AlGaN(厚さ:0.3μm)
電子障壁層22A AlGaN
活性層23 表2を参照
n型化合物半導体層21
n-ガイド層21B InGaN(厚さ:0.1μm)
n-クラッド層21A AlGaN(厚さ:0.4μm)
基板11 GaN基板、c面
n側電極25 Ti/Pt/Au
活性層
第2の井戸層 In0.30Ga0.70N(厚さ:2.5nm)
第2のトンネルバリア層 GaN(厚さ:2.0nm)
障壁層 In0.05Ga0.95N(厚さ:4.0nm)
第1のトンネルバリア層 GaN(厚さ:2.0nm)
第1の井戸層 In0.30Ga0.70N(厚さ:2.5nm)
先ず、基板11上、具体的には、n型GaN基板の(0001)面上に、周知のMOCVD法に基づき、n型化合物半導体層21、活性層23及びp型化合物半導体層22が、順次、積層されて成る積層構造体20を形成する。そして、p型化合物半導体層22を厚さ方向に一部分エッチングすることで、リッジストライプ構造27を形成する。リッジストライプ構造27を構成するp型化合物半導体層22の部分の厚さを0.12μmとした。
その後、p型化合物半導体層22を覆うSiO2から成る絶縁層24を形成した後、絶縁層24上にSi層(図示せず)を形成する。そして、p側電極26を形成すべき絶縁層24及びSi層を除去した後、p型化合物半導体層22上にp側電極26を形成する。具体的には、真空蒸着法に基づきp側電極層を全面に成膜した後、p側電極層上にフォトリソグラフィ技術に基づきエッチング用レジスト層を形成する。そして、エッチング用レジスト層に覆われていないp側電極層をエッチング法に基づき除去した後、エッチング用レジスト層を除去する。リフトオフ法に基づき、p型化合物半導体層22上にp側電極26を形成してもよい。
次いで、基板11を裏面から研磨することで基板11の厚さを薄くし、その後、基板11の裏面にn側電極25を形成し、また、p側電極26にパッド電極を形成する。そして、基板11の劈開等を行い、積層構造体20の第1端面及び第2端面における光反射率の制御を行うために、第1端面に無反射コート層(AR)あるいは低反射コート層を形成し、第2端面に高反射コート層(HR)を形成する。そして、更に、パッケージ化を行うことで、光半導体デバイスを作製することができる。
活性層
第2の井戸層 In0.19Ga0.81N(厚さ:2.5nm)
第2のトンネルバリア層 GaN(厚さ:2.0nm)
障壁層 In0.04Ga0.96N(厚さ:4.0nm)
第1のトンネルバリア層 GaN(厚さ:2.0nm)
第1の井戸層 In0.18Ga0.82N(厚さ:2.5nm)
第2の井戸層312のバンドギャップエネルギー 2.695eV
第1の井戸層311のバンドギャップエネルギー 2.654eV
活性層
第2の井戸層 In0.18Ga0.82N(厚さ:2.8nm)
第2のトンネルバリア層 GaN(厚さ:2.0nm)
障壁層 In0.05Ga0.95N(厚さ:4.0nm)
第1のトンネルバリア層 GaN(厚さ:2.0nm)
第1の井戸層 In0.18Ga0.82N(厚さ:2.5nm)
第1光反射層51、
第1光反射層51上に形成されたn型化合物半導体層21、活性層23及びp型化合物半導体層22から成る積層構造体20、並びに、
p型化合物半導体層22上に形成されたp側電極42及び第2光反射層52、
を備えている。n型化合物半導体層21の第1面21a上に第1光反射層51が形成されており、p型化合物半導体層22の第2面22bの上方には、第2光反射層52が形成されている。そして、第2光反射層52は第1光反射層51と対向している。
S1>S2
を満足することが望ましいし、第2光反射層出射タイプの面発光レーザ素子の場合、
S1<S2
を満足することが望ましいが、これに限定するものではない。
S3>S4
を満足することが望ましいし、第2光反射層出射タイプの面発光レーザ素子の場合、
S3<S4
を満足することが望ましいが、これに限定するものではない。
GaN基板表面の面方位のオフ角は0.4度以内、好ましくは0.40度以内であり、
GaN基板の面積をS0としたとき、第1光反射層の面積は0.8S0以下であり、
第1光反射層の最下層として熱膨張緩和膜がGaN基板上に形成されており、あるいは又、GaN基板と接する第1光反射層の最下層の線熱膨張係数CTEは、
1×10-6/K≦CTE≦1×10-5/K
好ましくは、
1×10-6/K<CTE≦1×10-5/K
を満足することが好ましい。
t1=λ0/(4n1)
好ましくは、
t1=λ0/(2n1)
を満足することが望ましい。但し、熱膨張緩和膜の厚さt1の値は本質的に任意とすることができ、例えば、1×10-7m以下とすることができる。
t1=λ0/(4n1)
好ましくは、
t1=λ0/(2n1)
を満足することが望ましい。但し、第1光反射層の最下層の厚さt1の値は本質的に任意とすることができ、例えば、1×10-7m以下とすることができる。
GaN系化合物半導体から成り、第1面21a、及び、第1面21aと対向する第2面21bを有するn型化合物半導体層21、
GaN系化合物半導体から成り、n型化合物半導体層21の第2面21bと接する活性層(発光層)23、及び、
GaN系化合物半導体から成り、第1面22a、及び、第1面22aと対向する第2面22bを有し、第1面22aが活性層23と接するp型化合物半導体層22、
が積層されて成る。そして、p型化合物半導体層22の第2面22b上には、p側電極42及び誘電体多層膜から成る第2光反射層52が形成されており、積層構造体20が形成された基板11の表面11aと対向する基板11の他方の面11bにn側電極41が形成されている。誘電体多層膜から成る第1光反射層51は、基板11の表面11aに形成されているし、n型化合物半導体層21の第1面21aと接して形成されている。
基板(具体的には、GaN基板)11の上に第1光反射層51を形成する。具体的には、先ず、スパッタリング法に基づき全面に第1光反射層51を形成するための誘電体多層膜を基板11上に形成した後、フォトリソグラフィ技術及びドライエッチング技術に基づき誘電体多層膜をパターニングすることで、第1光反射層51を得ることができる(図3A参照)。
次に、全面にn型化合物半導体層21、活性層23及びp型化合物半導体層22を形成する。具体的には、ELO法といった横方向にエピタキシャル成長させるMOCVD法(TMGガス及びSiH4ガスを用いる)に基づき、全面にn型GaNから成るn型化合物半導体層21を形成する。引き続き、全面に活性層23及びp型化合物半導体層22を形成する。具体的には、エピタキシャル成長法に基づき、n型化合物半導体層21の上に、TMGガス及びTMIガスを用いて活性層23を形成した後、TMGガス、TMAガス、Cp2Mgガスを用いて電子障壁層を形成し、TMGガス、Cp2Mgガスを用いてp型GaN層を形成することで、p型化合物半導体層22を得る。以上の工程によって積層構造体20を得ることができる。即ち、第1光反射層51を含む基板(具体的には、GaN基板)11上に、
GaN系化合物半導体から成り、第1面21a、及び、第1面21aと対向する第2面21bを有するn型化合物半導体層21、
GaN系化合物半導体から成り、n型化合物半導体層21の第2面21bと接する活性層23、及び、
GaN系化合物半導体から成り、第1面22a、及び、第1面22aと対向する第2面22bを有し、第1面22aが活性層23と接するp型化合物半導体層22、
が積層されて成る積層構造体20をエピタキシャル成長させる。こうして、図3Bに示す構造を得ることができる。
次いで、p型化合物半導体層22の第2面22b上に、周知の方法に基づき、厚さ0.2μmの絶縁材料から成り、開口43Aを有する電流狭窄層43を形成する。
その後、p型化合物半導体層22上に、第1光反射層51と対向したp側電極及び第2光反射層を形成する。具体的には、p型化合物半導体層22の第2面22b上にp側電極42及び誘電体多層膜から成る第2光反射層52を形成する。より具体的には、例えば、リフトオフ法に基づき、p型化合物半導体層22の第2面22bの上から電流狭窄層43の上に亙り、厚さ50nmのITOから成るp側電極42を形成し、更に、p側電極42の上から電流狭窄層43の上に亙り、周知の方法に基づきパッド電極44を形成する。こうして、図3Cに示す構造を得ることができる。その後、p側電極42の上からパッド電極44の上に亙り、周知の方法に基づき第2光反射層52を形成する。一方、基板11の他方の面11bに、周知の方法に基づきn側電極41を形成する。こうして、図2Aに示した構造を有する実施例5の面発光レーザ素子を得ることができる。
その後、所謂素子分離を行うことで面発光レーザ素子を分離し、積層構造体20の側面や露出面を、例えば、SiOXから成る絶縁膜で被覆する。そして、n側電極41やパッド電極44を外部の回路等に接続するために端子等を周知の方法に基づき形成し、パッケージや封止することで、実施例5の面発光レーザ素子を完成させる。
先ず、実施例5の[工程-500]~[工程-530]と同様の工程を実行することで、図2Aに示した構造を得る。但し、n側電極41は形成しない。
その後、第2光反射層52を、接合層45を介して支持基板46に固定する。こうして、図5Aに示す構造を得ることができる。
次いで、基板(GaN基板)11を除去して、n型化合物半導体層21の第1面21a、第1光反射層51を露出させる。具体的には、先ず、機械研磨法に基づき基板11の厚さを薄くし、次いで、CMP法に基づき基板11の残部を除去する。こうして、n型化合物半導体層21の第1面21a、第1光反射層51を露出させ、図9Bに示す構造を得ることができる。
その後、n型化合物半導体層21の第1面21a上に、周知の方法に基づきn側電極41を形成する。こうして、図4Aに示す構造を有する実施例6の面発光レーザ素子を得ることができる。
そして、所謂素子分離を行うことで面発光レーザ素子を分離し、積層構造体20の側面や露出面を、例えば、SiOXから成る絶縁膜で被覆する。そして、n側電極41やパッド電極44を外部の回路等に接続するために端子等を周知の方法に基づき形成し、パッケージや封止することで、実施例6の面発光レーザ素子を完成させる。
1×10-6/K≦CTE≦1×10-5/K
好ましくは、
1×10-6/K<CTE≦1×10-5/K
を満足する。
t1=λ0/(2n1)
を満足する窒化ケイ素(SiNX)から成る。尚、このような膜厚を有する熱膨張緩和膜53(第1光反射層51の最下層)は、波長λ0の光に対して透明であり、光反射層としての機能は有していない。窒化ケイ素(SiNX)及びGaN基板11のCTEの値は以下の表6のとおりである。CTEの値は25゜Cにおける値である。
GaN基板 :5.59×10-6/K
窒化ケイ素(SiNX):2.6~3.5×10-6/K
オフ角(度) 表面粗さRa(nm)
0.35 0.87
0.38 0.95
0.43 1.32
0.45 1.55
0.50 2.30
第1光反射層51の面積 表面粗さRa(nm)
0.88S0 1.12
0.83S0 1.05
0.75S0 0.97
0.69S0 0.91
0.63S0 0.85
先ず、GaN基板から成る基板11上に、GaN系化合物半導体から成り、第1面21a、及び、第1面21aと対向する第2面を有するn型化合物半導体層21、GaN系化合物半導体から成り、n型化合物半導体層21の第2面21bと接する活性層23、及び、GaN系化合物半導体から成り、第1面22a、及び、第1面22aと対向する第2面22bを有し、第1面22aが活性層23と接するp型化合物半導体層22が積層されて成る積層構造体20を、周知のMOCVD法に基づき形成する。次いで、p型化合物半導体層22の上に、周知の方法に基づき、開口43Aを有する電流狭窄層43を形成する。こうして、図8Aに示す構造を得ることができる。
次に、p型化合物半導体層22の第2面22b上にp側電極42及び誘電体多層膜から成る第2光反射層52を形成する。具体的には、例えば、リフトオフ法に基づき、p型化合物半導体層22の第2面22bの上から電流狭窄層43の上に亙り、p側電極42を形成し、更に、p側電極42の上から電流狭窄層43の上に亙り、周知の方法に基づきパッド電極44を形成する。こうして、図8Bに示す構造を得ることができる。その後、p側電極42の上からパッド電極44の上に亙り、周知の方法に基づき第2光反射層52を形成する。こうして、図8Cに示す構造を得ることができる。
その後、第2光反射層52を、接合層45を介して支持基板46に固定する。こうして、図9Aに示す構造を得ることができる。
次いで、基板11を除去して、n型化合物半導体層21の第1面21aを露出させる。具体的には、先ず、機械研磨法に基づき基板11の厚さを薄くし、次いで、CMP法に基づき基板11の残部を除去し、更に、露出したn型化合物半導体層21を厚さ方向に部分的に除去し、n型化合物半導体層21の第1面21aに対する鏡面仕上げ処理を行う。こうして、図9Bに示す構造を得ることができる。
そして、n型化合物半導体層21の第1面21aに凸部21c、凹部21eを形成し、凸部21c上に誘電体多層膜から成る第1光反射層51を形成し、凸部21c及び凹部21eにn側電極41を形成し、凸部21cの側面(側壁)21dに誘電体層28を形成する。
その後、所謂素子分離を行うことで面発光レーザ素子を分離し、積層構造体の側面や露出面を、例えば、SiO2等から成る絶縁膜で被覆する。そして、n側電極41やパッド電極44を外部の回路等に接続するために端子等を周知の方法に基づき形成し、パッケージや封止することで、実施例8の面発光レーザ素子を完成させる。
[A01]《光半導体デバイス:第1の態様》
n型化合物半導体層、活性層、及び、p型化合物半導体層がこの順に積層された積層構造体を有し、
活性層は、トンネルバリア層を有する多重量子井戸構造を備えており、
p型化合物半導体層に隣接した井戸層の組成揺らぎは、他の井戸層の組成揺らぎよりも大きい光半導体デバイス。
[A02]p型化合物半導体層に隣接した井戸層のバンドギャップエネルギーは、他の井戸層のバンドギャップエネルギーよりも小さい[A01]に記載の光半導体デバイス。
[A03]p型化合物半導体層に隣接した井戸層の厚さは、他の井戸層の厚さよりも厚い[A01]に記載の光半導体デバイス。
[A04]p型化合物半導体層に隣接した井戸層のバンドギャップエネルギーは、他の井戸層のバンドギャップエネルギーよりも小さい[A03]に記載の光半導体デバイス。
[A05]トンネルバリア層は、井戸層と障壁層との間に形成されている[A01]乃至[A04]のいずれか1項に記載の光半導体デバイス。
[B01]《光半導体デバイス:第2の態様》
n型化合物半導体層、活性層、及び、p型化合物半導体層がこの順に積層された積層構造体を有し、
活性層は、トンネルバリア層を有する多重量子井戸構造を備えており、
p型化合物半導体層に隣接した井戸層のバンドギャップエネルギーは、他の井戸層のバンドギャップエネルギーよりも小さい光半導体デバイス。
[B02]p型化合物半導体層に隣接した井戸層の厚さは、他の井戸層の厚さよりも厚い[B01]に記載の光半導体デバイス。
[B03]トンネルバリア層は、井戸層と障壁層との間に形成されている[B01]又は[B02]に記載の光半導体デバイス。
[C01]《光半導体デバイス:第3の態様》
n型化合物半導体層、活性層、及び、p型化合物半導体層がこの順に積層された積層構造体を有し、
活性層は、トンネルバリア層を有する多重量子井戸構造を備えており、
p型化合物半導体層に隣接した井戸層の厚さは、他の井戸層の厚さよりも厚い光半導体デバイス。
[C02]トンネルバリア層は、井戸層と障壁層との間に形成されている[C01]に記載の光半導体デバイス。
[D01]トンネルバリア層の厚さは4nm以下である[A01]乃至[C02]のいずれか1項に記載の光半導体デバイス。
[D02]活性層は、AlInGaN系化合物半導体から成る[A01]乃至[D01]のいずれか1項に記載の光半導体デバイス。
[D03]トンネルバリア層はGaNから成る[D02]に記載の光半導体デバイス。
[D04]n型化合物半導体層は、GaN基板のc面上に形成されている[D02]又は[D03]に記載の光半導体デバイス。
[D05]発光波長は440nm以上である[D02]乃至[D04]のいずれか1項に記載の光半導体デバイス。
[E01]面発光レーザ素子から成り、
GaN基板表面の面方位のオフ角は0.4度以内、好ましくは0.40度以内であり、
GaN基板の面積をS0としたとき、第1光反射層の面積は0.8S0以下であり、
第1光反射層の最下層として熱膨張緩和膜がGaN基板上に形成されている[D03]又は[D04]に記載の光半導体デバイス。
[E02]熱膨張緩和膜は、窒化ケイ素、酸化アルミニウム、酸化ニオブ、酸化タンタル、酸化チタン、酸化マグネシウム、酸化ジルコニウム及び窒化アルミニウムから成る群から選択された少なくとも1種類の材料から成る[E01]に記載の光半導体デバイス。
[E03]熱膨張緩和膜の厚さをt1、光半導体デバイスの発光波長をλ0、熱膨張緩和膜の屈折率をn1としたとき、
t1=λ0/(2n1)
を満足する[E01]又は[E02]に記載の光半導体デバイス。
[E04]面発光レーザ素子から成り、
GaN基板表面の面方位のオフ角は0.4度以内、好ましくは0.40度以内であり、
GaN基板の面積をS0としたとき、第1光反射層の面積は0.8S0以下であり、
GaN基板と接する第1光反射層の最下層の線熱膨張係数CTEは、
1×10-6/K≦CTE≦1×10-5/K
好ましくは、
1×10-6/K<CTE≦1×10-5/K
を満足する[D03]又は[D04]に記載の光半導体デバイス。
[E05]第1光反射層の最下層は、窒化ケイ素、酸化アルミニウム、酸化ニオブ、酸化タンタル、酸化チタン、酸化マグネシウム、酸化ジルコニウム及び窒化アルミニウムから成る群から選択された少なくとも1種類の材料から成る[E04]に記載の光半導体デバイス。
[E06]第1光反射層の最下層の厚さをt1、光半導体デバイスの発光波長をλ0、第1光反射層の最下層の屈折率をn1としたとき、
t1=λ0/(2n1)
を満足する[E04]又は[E05]に記載の光半導体デバイス。
[E07]p型化合物半導体層の表面粗さRaは、1.0nm以下である[E01]乃至[E06]のいずれか1項に記載の光半導体デバイス。
[F01]面発光レーザ素子から成り、
活性層と対向するn型化合物半導体層の第1面には凸部が形成され、第1光反射層は凸部上に形成されており、n型化合物半導体層の第1面に形成された凸部周辺の凹部にn側電極が形成されている[D02]乃至[E07]のいずれか1項に記載の光半導体デバイス。
[F02]凸部の側面には誘電体層が形成されている[F01]に記載の光半導体デバイス。
[F03]誘電体層を構成する材料の屈折率の値は、n型化合物半導体層を構成する材料の平均屈折率の値よりも小さい[F02]に記載の光半導体デバイス。
[F04]面発光レーザ素子から成り、
活性層と対向するn型化合物半導体層の第1面上には第1光反射層が形成されており、
第1光反射層を取り囲むようにn型化合物半導体層の第1面には溝部が形成されており、
溝部は絶縁材料で充填されている[D02]乃至[E07]のいずれか1項に記載の光半導体デバイス。
[F05]面発光レーザ素子から成り、
第1光反射層の面積重心点を通る第1光反射層の法線と、p型化合物半導体層と対向する第2光反射層の部分の面積重心点を通る第2光反射層の法線とは、一致していない[D02]乃至[F04]のいずれか1項に記載の光半導体デバイス。
[F06]面発光レーザ素子から成り、
第1光反射層の面積重心点を通る第1光反射層に対する法線上に、活性層の面積重心点は存在しない[D02]乃至[F04]のいずれか1項に記載の光半導体デバイス。
Claims (15)
- n型化合物半導体層、活性層、及び、p型化合物半導体層がこの順に積層された積層構造体を有し、
活性層は、トンネルバリア層を有する多重量子井戸構造を備えており、
p型化合物半導体層に隣接した井戸層の組成揺らぎは、他の井戸層の組成揺らぎよりも大きい光半導体デバイス。 - p型化合物半導体層に隣接した井戸層のバンドギャップエネルギーは、他の井戸層のバンドギャップエネルギーよりも小さい請求項1に記載の光半導体デバイス。
- p型化合物半導体層に隣接した井戸層の厚さは、他の井戸層の厚さよりも厚い請求項1に記載の光半導体デバイス。
- p型化合物半導体層に隣接した井戸層のバンドギャップエネルギーは、他の井戸層のバンドギャップエネルギーよりも小さい請求項3に記載の光半導体デバイス。
- トンネルバリア層は、井戸層と障壁層との間に形成されている請求項1に記載の光半導体デバイス。
- n型化合物半導体層、活性層、及び、p型化合物半導体層がこの順に積層された積層構造体を有し、
活性層は、トンネルバリア層を有する多重量子井戸構造を備えており、
p型化合物半導体層に隣接した井戸層のバンドギャップエネルギーは、他の井戸層のバンドギャップエネルギーよりも小さい光半導体デバイス。 - p型化合物半導体層に隣接した井戸層の厚さは、他の井戸層の厚さよりも厚い請求項6に記載の光半導体デバイス。
- トンネルバリア層は、井戸層と障壁層との間に形成されている請求項6に記載の光半導体デバイス。
- n型化合物半導体層、活性層、及び、p型化合物半導体層がこの順に積層された積層構造体を有し、
活性層は、トンネルバリア層を有する多重量子井戸構造を備えており、
p型化合物半導体層に隣接した井戸層の厚さは、他の井戸層の厚さよりも厚い光半導体デバイス。 - トンネルバリア層は、井戸層と障壁層との間に形成されている請求項9に記載の光半導体デバイス。
- トンネルバリア層の厚さは4nm以下である請求項1、請求項6及び請求項9のいずれか1項に記載の光半導体デバイス。
- 活性層は、AlInGaN系化合物半導体から成る請求項1、請求項6及び請求項9のいずれか1項に記載の光半導体デバイス。
- トンネルバリア層はGaNから成る請求項12に記載の光半導体デバイス。
- n型化合物半導体層は、GaN基板のc面上に形成されている請求項12に記載の光半導体デバイス。
- 発光波長は440nm以上である請求項12に記載の光半導体デバイス。
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