WO2016101562A1 - 一种网络时钟同步装置及其工作方法 - Google Patents

一种网络时钟同步装置及其工作方法 Download PDF

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Publication number
WO2016101562A1
WO2016101562A1 PCT/CN2015/081973 CN2015081973W WO2016101562A1 WO 2016101562 A1 WO2016101562 A1 WO 2016101562A1 CN 2015081973 W CN2015081973 W CN 2015081973W WO 2016101562 A1 WO2016101562 A1 WO 2016101562A1
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clock
access device
recovery unit
data access
clock recovery
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PCT/CN2015/081973
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English (en)
French (fr)
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董超
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中兴通讯股份有限公司
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Publication of WO2016101562A1 publication Critical patent/WO2016101562A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

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  • This paper relates to the field of Internet technology, and in particular to a network clock synchronization device and a working method thereof.
  • Wireless applications require good synchronization of the clock frequency of the communication network.
  • the IP RAN (IP Radio Access Networks) frequency must be synchronized within a certain accuracy between different base stations, otherwise the service is switched at the base station. When there is a drop, it will affect the normal use of the application.
  • clock synchronization between synchronous Ethernet devices usually adopts a method of recovering a line clock from bit stream data of a port to implement clock transmission.
  • the port data connection is interrupted, the signal pin of the restored line clock is followed.
  • the clock whose output is the same as the normal line clock frequency but whose phase is offset needs to wait until the software query port is abnormal before switching the clock to other alternate sources according to the SSM (Synchronization Status Message) algorithm. Since the software operation is often in the millisecond level, the system will be in an asynchronous state during this time, which will have a serious impact on the synchronous service.
  • the embodiment of the invention provides a network clock synchronization device and a working method thereof, which are used to solve the problem that the network clock synchronization is poor when the external data is abnormally interrupted in the related art.
  • an embodiment of the present invention provides a network clock synchronization apparatus, including: a clock recovery unit and a clock gating unit, wherein the clock recovery unit has one end connected to the network data access device and the other end strobed with the clock. Connected to the line clock to recover the line clock by using the data incoming by the network data access device; the clock input unit has a first input end connected to the clock recovery unit, and a second input end and the network The data access device is connected, and the output end is connected to the phase locked loop, and is configured to: when the network data access device transmits data to the clock recovery unit, the line clock output by the clock recovery unit is directed to the lock Phase loop transmission; the network data access device is interrupted to the clock When the recovery unit transmits data, the line clock transmitted by the clock recovery unit to the phase locked loop is cut off so that the phase locked loop maintains the line clock before the data interruption.
  • the network data access device includes an optical module
  • the clock recovery unit includes a physical layer chip.
  • the second input end of the clock gating portion is connected to the signal loss LOS pin of the optical module.
  • the clock gating portion includes a detecting module and a gating module connected to each other, wherein the detecting module is connected to the network data access device, and the gating module is connected to the clock recovery portion.
  • the clock gating part is a combination logic circuit.
  • a frequency dividing portion is further disposed between the clock gating portion and the phase locked loop, and the clock gating portion is connected to the phase locked loop by the frequency dividing portion, and the frequency dividing portion is It is set to divide the clock output by the clock gating section.
  • a frequency dividing unit is further disposed between the clock recovery unit and the clock gating unit, and the clock recovery unit is connected to the clock gating unit by the frequency dividing unit, and the frequency dividing unit is The clock output from the clock recovery unit is divided and transmitted to the clock gating unit.
  • the embodiment of the present invention further provides a working method of the network clock synchronization apparatus, including: detecting whether the network data access apparatus transmits data to the clock recovery unit; and the network data access apparatus is When the clock recovery unit transmits data, the line clock output by the clock recovery unit is transmitted to the phase locked loop; when the network data access device interrupts transmission of data to the clock recovery unit, the clock is cut off The line clock that the recovery unit transmits to the phase locked loop by itself, so that the phase locked loop maintains the line clock before the data interruption.
  • the network data access device includes an optical module
  • the detecting, by the network data access device, whether the data is transmitted to the clock recovery unit includes: detecting a signal loss LOS pin detection device of the optical module Whether the network data access device transmits data to the clock recovery unit.
  • the clock recovery unit can The line clock is recovered by using the data transmitted by the network data access device; the clock gating unit can transmit the line clock outputted by the clock recovery unit to the phase locked loop when the network data access device transmits the data to the clock recovery unit.
  • the line clock that the clock recovery unit transmits to the phase locked loop is cut off, so that the phase locked loop maintains the line clock before the data interruption.
  • the clock gating unit Since the clock gating unit is directly connected to the network data access device, the data output state of the network data access device can be known in real time, so that the clock recovery unit can be cut off in time when the data output device of the network data access device is interrupted.
  • the wrong line clock transmitted by the phase-locked loop allows the phase-locked loop to continue to maintain the original clock output, avoiding the situation in which the phase-locked loop outputs an incorrect clock, effectively improving the synchronization of the network clock.
  • FIG. 1 is a schematic structural diagram of a network clock synchronization apparatus according to an embodiment of the present invention
  • FIG. 2 is another schematic structural diagram of a network clock synchronization apparatus according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another network clock synchronization apparatus according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of still another network clock synchronization apparatus according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a working method of a network clock synchronization apparatus according to an embodiment of the present invention
  • FIG. 6 is a detailed flowchart of a working method of a network clock synchronization apparatus according to an embodiment of the present invention.
  • an embodiment of the present invention provides a network clock synchronization apparatus, including: a clock recovery unit 11 and a clock gating unit 12;
  • the clock recovery unit 11 has one end connected to the network data access device 13 and the other end connected to the clock gating portion 12, which is configured to recover the line clock by using the data transmitted by the network data access device 13;
  • the clock gating portion 12 has a first input terminal connected to the clock recovery portion 11, a second input terminal connected to the network data access device 13, and an output terminal connected to the phase locked loop 14, which is set to: in the network data.
  • the access device 13 transmits data to the clock recovery unit 11
  • the line clock output from the clock recovery unit 11 is transmitted to the phase locked loop 14, and when the network data access device 13 interrupts transmission of data to the clock recovery unit 11, the clock recovery unit is cut off. 11
  • the wrong line clock is passed to the phase locked loop 14 by itself so that the phase locked loop 14 maintains the line clock before the data is interrupted.
  • the network clock synchronization apparatus includes a clock recovery unit 11 and a clock gating unit 12; wherein the clock recovery unit 11 can recover the line clock by using the data transmitted by the network data access device 13; the clock gating unit 12 can When the network data access device 13 transmits data to the clock recovery unit 11, the line clock output from the clock recovery unit 11 is transmitted to the phase locked loop 14, and is cut off when the network data access device 13 interrupts transmission of data to the clock recovery unit 11.
  • the clock recovery unit 11 self-transfers the line clock to the phase locked loop 14, thereby causing the phase locked loop 14 to maintain the line clock before the data is interrupted.
  • the clock gating portion 12 Since the clock gating portion 12 is directly connected to the network data access device 13, the data output state of the network data access device 13 can be known in real time, so that the clock can be cut off at the first time when the data output of the network data access device 13 is interrupted.
  • the line clock transmitted by the recovery unit 11 to the phase-locked loop 14 causes the phase-locked loop 14 to continue to maintain the original clock output, thereby avoiding the situation in which the phase-locked loop 14 outputs an erroneous clock, thereby effectively improving the synchronization of the network clock.
  • clock recovery can be performed by a circuit or chip of the physical layer, and therefore, the clock recovery section 11 can include a physical layer chip.
  • the network data access device 13 can be any device that accesses the external network to the local network.
  • the clock gating portion 12 can also be detected in time by being connected to multiple types of network data access devices 13. Is the corresponding data output normal?
  • the network data access device 13 may include an optical module configured to convert between the optical signal and the electrical signal. Since the optical module has a signal loss LOS pin, the output LOS signal is also common in the communication standard.
  • the second input end of the clock gating portion 12 can be lost with the optical module signal.
  • the LOS pins are connected.
  • the LOS signal output by the LOS pin can reflect the state of the optical signal received by the optical module in real time, and is reflected on the electrical interface of the optical module in the form of a level signal.
  • the low level represents the normal line optical signal, and the high level represents the alarm line light.
  • the signal is lost.
  • the LOS signal is a signal defined in the optical module standard. Many manufacturers have the same optical module definition. Therefore, using the optical module as the line condition monitoring module has the advantages of good versatility, simplicity and convenience.
  • the clock gating portion 12 can be composed of various forms of circuit structures or modules, and the circuit structure The simpler the response is, the more the line clock that the clock recovery unit 11 transmits to the phase locked loop 14 can be cut off in time when the network data access device 13 is interrupted.
  • the clock gating portion 12 may include a detecting module 121 and a gating module 122 connected to each other, wherein the detecting module 121 is connected to the network data access device 13, The gating module 122 is connected to the clock recovery unit 11.
  • the strobe module 122 is responsible for controlling the line recovery clock on and off, externally connecting one input clock signal, outputting one clock, and simultaneously connecting with the detection module, and the strobe module 122 remains in the on state when the line state is normal, when the external line
  • the gating module 122 can receive the notification from the detecting module 121 at the first time, and immediately cut off the clock, so that the system phase locked loop immediately enters the holding state.
  • the clock gating portion 12 can also be a combination logic circuit.
  • the LOS signal of the optical module and the line recovery clock signal output by the physical layer chip can be simultaneously connected to the CPLD (Complex Programmable Logic Device).
  • CPLD Complex Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • a frequency dividing unit 15 and a clock may be disposed between the clock gating portion 12 and the phase locked loop 14.
  • the gate portion 12 can be connected to the phase locked loop 14 via the frequency dividing portion 15.
  • the frequency dividing section 15 is provided to divide the clock output from the clock gate section 12.
  • the frequency dividing unit 15 may be disposed between the clock recovery unit 11 and the clock gating unit 12, and the clock recovery unit 11 is connected to the clock gating unit 12 by the frequency dividing unit 15 to divide the frequency.
  • the unit 15 is provided to divide the clock output from the clock recovery unit 11 and transmit it to the clock gate unit 12.
  • the line condition monitoring and the clock off are completely realized by hardware automatically, without software participation, and the speed is fast, from line interruption to off clock, the time is nanosecond, and the system can effectively make the system external.
  • the source is lost to switch to the new clock source and still works in the synchronous state, which improves the performance of the system.
  • an embodiment of the present invention further provides a working method of a network clock synchronization apparatus according to any of the foregoing embodiments, including:
  • the clock switching unit 12 can output the line clock outputted by the clock recovery unit 11 to the phase locked loop 14 when the network data access apparatus 13 transmits data to the clock recovery unit 11.
  • the line clock transmitted by the clock recovery unit 11 to the phase locked loop 14 is cut off, so that the phase locked loop 14 maintains the line clock before the data interruption. Since the clock gating portion 12 is directly connected to the network data access device 13, the data output state of the network data access device 13 can be known in real time, so that the clock can be cut off at the first time when the data output of the network data access device 13 is interrupted.
  • the line clock transmitted by the recovery unit 11 to the phase-locked loop 14 causes the phase-locked loop 14 to continue to maintain the original clock output, thereby avoiding the situation in which the phase-locked loop 14 outputs an erroneous clock, thereby effectively improving the synchronization of the network clock.
  • step S21 detecting whether the network data access device transmits data to the clock recovery unit includes: detecting a signal loss LOS tube of the optical module The foot detects whether the network data access device transmits data to the clock recovery unit.
  • the system For devices working in synchronous Ethernet, the system first selects the current port synchronization clock, and then through configuration selection, the system phase-locked loop locks the line recovery clock from the current port, and uses this as a reference to generate the system operating clock, when the current port is external.
  • the detection module of the clock gating section immediately informs the strobe module of the current port state in the form of a level signal after detecting the loss of the optical signal, and the strobe module cuts off the current interface after receiving the level change.
  • the physical layer chip line restores the clock output from the clock output pin.
  • the system phase-locked loop detects that the external clock is lost, enters the HOLDOVER hold mode, and the system management layer detects an abnormality of the external signal, and then switches the synchronization source to another clock through the SSM (Synchronization Status Message) algorithm.
  • SSM Synchronization Status Message
  • the above technical solution can greatly reduce the impact of external clock source anomalies on synchronous Ethernet devices. Improve the performance of the clock system, thereby improving the reliability of the entire clock synchronization network, and the method is simple, reliable and efficient, without adding additional hardware costs.
  • the network clock synchronization device and the working method thereof are provided by the embodiment of the present invention, and the clock recovery unit can recover the line clock by using the data transmitted by the network data access device; the clock gating unit can transmit the network data access device to the clock recovery unit.
  • the line clock outputted by the clock recovery unit is transmitted to the phase-locked loop, and when the network data access device interrupts the transmission of data to the clock recovery unit, the line clock transmitted by the clock recovery unit to the phase-locked loop is cut off, thereby locking the phase.
  • the loop keeps the line clock before the data is interrupted.
  • the clock gating unit Since the clock gating unit is directly connected to the network data access device, the data output state of the network data access device can be known in real time, so that the clock recovery unit can be cut off in time when the data output device of the network data access device is interrupted.
  • the wrong line clock transmitted by the phase-locked loop allows the phase-locked loop to continue to maintain the original clock output, avoiding the situation in which the phase-locked loop outputs an incorrect clock, effectively improving the synchronization of the network clock.

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Abstract

一种网络时钟同步装置及其工作方法，所述装置包括：时钟恢复部和时钟选通部，所述时钟恢复部，其一端与网络数据接入装置相连，另一端与所述时钟选通部相连，设置为利用所述网络数据接入装置传入的数据恢复出线路时钟；所述时钟选通部，其第一输入端与所述时钟恢复部相连，第二输入端与所述网络数据接入装置相连，输出端与锁相环相连，其设置为：在所述网络数据接入装置中断向所述时钟恢复部传输数据时，截断所述时钟恢复部自行向所述锁相环传递的线路时钟。

Description

一种网络时钟同步装置及其工作方法 技术领域
本文涉及互联网技术领域，尤其涉及一种网络时钟同步装置及其工作方法。
背景技术
无线应用需要通讯网络的时钟频率具有良好的同步性，例如，IP RAN(IP无线接入网络，IP Radio Access Networks)在不同基站之间的频率必须同步在一定精度之内，否则业务在基站切换时会出现掉线，影响应用正常使用。
相关技术中，同步以太网设备之间的时钟同步，通常采用从端口的比特流数据中恢复线路时钟的方法来实现时钟的传递，当端口数据连接中断时，恢复线路时钟的信号管脚会随之输出与正常线路时钟频率相同但相位产生偏移的时钟，需要等到软件查询端口异常后才能根据SSM(Synchronization Status Message，同步状态信息)算法将时钟切换到其他备用源。由于软件操作往往都是毫秒级，因此这段时间内，系统都会处于非同步状态，对同步业务会造成严重影响。
发明内容
本发明实施例提供一种网络时钟同步装置及其工作方法，用以解决相关技术中外部数据异常中断时网络时钟同步性差的问题。
一方面，本发明实施例提供一种网络时钟同步装置，包括：时钟恢复部和时钟选通部，所述时钟恢复部，其一端与网络数据接入装置相连，另一端与所述时钟选通部相连，设置为利用所述网络数据接入装置传入的数据恢复出线路时钟；所述时钟选通部，其第一输入端与所述时钟恢复部相连，第二输入端与所述网络数据接入装置相连，输出端与锁相环相连，其设置为：在所述网络数据接入装置向所述时钟恢复部传输数据时，将所述时钟恢复部输出的线路时钟向所述锁相环传递；在所述网络数据接入装置中断向所述时钟 恢复部传输数据时，截断所述时钟恢复部自行向所述锁相环传递的线路时钟，以使所述锁相环保持数据中断前的线路时钟。
可选的，所述网络数据接入装置包括光模块，所述时钟恢复部包括物理层芯片。
可选的，所述时钟选通部的第二输入端与所述光模块的信号丢失LOS管脚相连。
可选的，所述时钟选通部包括相互连接的检测模块和选通模块，其中，所述检测模块与所述网络数据接入装置相连，所述选通模块与所述时钟恢复部相连。
可选的，所述时钟选通部为组合逻辑电路。
可选的，所述时钟选通部和所述锁相环之间还设置有分频部，所述时钟选通部通过所述分频部与所述锁相环相连，所述分频部设置为，将所述时钟选通部输出的时钟分频。
可选的，所述时钟恢复部和所述时钟选通部之间还设置有分频部，所述时钟恢复部通过所述分频部与所述时钟选通部相连，所述分频部设置为，将所述时钟恢复部输出的时钟分频后传输给所述时钟选通部。
另一方面，本发明实施例还提供了所述网络时钟同步装置的工作方法，包括：检测所述网络数据接入装置是否向所述时钟恢复部传输数据；在所述网络数据接入装置向所述时钟恢复部传输数据时，将所述时钟恢复部输出的线路时钟向所述锁相环传递；在所述网络数据接入装置中断向所述时钟恢复部传输数据时，截断所述时钟恢复部自行向所述锁相环传递的线路时钟，以使所述锁相环保持数据中断前的线路时钟。
可选的，所述网络数据接入装置包括光模块；所述检测所述网络数据接入装置是否向所述时钟恢复部传输数据包括：通过检测所述光模块的信号丢失LOS管脚检测所述网络数据接入装置是否向所述时钟恢复部传输数据。
本发明实施例提供的网络时钟同步装置及其工作方法，时钟恢复部能够 利用网络数据接入装置传入的数据恢复出线路时钟；时钟选通部能够在网络数据接入装置向时钟恢复部传输数据时，将时钟恢复部输出的线路时钟向锁相环传递，在网络数据接入装置中断向时钟恢复部传输数据时，截断时钟恢复部自行向锁相环传递的线路时钟，从而使锁相环保持数据中断前的线路时钟。由于时钟选通部直接与网络数据接入装置相连，可以实时获知网络数据接入装置的数据输出状态，从而能够在网络数据接入装置数据输出中断的第一时间，及时截断时钟恢复部自行向锁相环传递的错误的线路时钟，使锁相环继续保持原来的时钟输出，避免了锁相环输出错误时钟的情况，有效提高了网络时钟的同步性。
附图概述
图1是本发明实施例提供的网络时钟同步装置的一种结构示意图；
图2是本发明实施例提供的网络时钟同步装置的另一种结构示意图；
图3是本发明实施例提供的网络时钟同步装置的又一种结构示意图；
图4是本发明实施例提供的网络时钟同步装置的又再一种结构示意图；
图5是本发明实施例提供的网络时钟同步装置的工作方法的一种流程图；
图6是本发明实施例提供的网络时钟同步装置的工作方法的一种详细流程图。
本发明的实施方式
如图1所示，本发明实施例提供一种网络时钟同步装置，包括：时钟恢复部11和时钟选通部12；其中：
时钟恢复部11，其一端与网络数据接入装置13相连，另一端与时钟选通部12相连，其设置为利用网络数据接入装置13传入的数据恢复出线路时钟；
时钟选通部12，其第一输入端与时钟恢复部11相连，第二输入端与网络数据接入装置13相连，输出端与锁相环14相连，其设置为：在网络数据 接入装置13向时钟恢复部11传输数据时，将时钟恢复部11输出的线路时钟向锁相环14传递；在网络数据接入装置13中断向时钟恢复部11传输数据时，截断时钟恢复部11自行向锁相环14传递的错误的线路时钟，以使锁相环14保持数据中断前的线路时钟。
本发明实施例提供的网络时钟同步装置包括时钟恢复部11和时钟选通部12；其中时钟恢复部11能够利用网络数据接入装置13传入的数据恢复出线路时钟；时钟选通部12能够在网络数据接入装置13向时钟恢复部11传输数据时，将时钟恢复部11输出的线路时钟向锁相环14传递，在网络数据接入装置13中断向时钟恢复部11传输数据时，截断时钟恢复部11自行向锁相环14传递的线路时钟，从而使锁相环14保持数据中断前的线路时钟。由于时钟选通部12直接与网络数据接入装置13相连，可以实时获知网络数据接入装置13的数据输出状态，从而能够在网络数据接入装置13数据输出中断的第一时间，及时截断时钟恢复部11自行向锁相环14传递的线路时钟，使锁相环14继续保持原来的时钟输出，避免了锁相环14输出错误时钟的情况，有效提高了网络时钟的同步性。
在网络通信协议中，时钟恢复可以由物理层的电路或芯片来完成，因此，时钟恢复部11可以包括物理层芯片。可选的，网络数据接入装置13可以为任何将外部网络接入到本地网络的设备，相应的，时钟选通部12也可以通过与多种类型的网络数据接入装置13相连而及时检测到相应的数据输出是否正常。例如，如果外部网络是通过光纤传入本地网络的，那么网络数据接入装置13可以包括光模块，其设置为光信号与电信号之间的相互转换。由于光模块中都具有信号丢失LOS管脚，其输出的LOS信号也是通信标准里通用的，为了加强通用性，可选的，时钟选通部12的第二输入端可以与光模块的信号丢失LOS管脚相连。LOS管脚输出的LOS信号可以实时反映光模块接收光信号的状态，并以电平信号的形式反映在光模块的电接口上，低电平代表线路光信号正常，高电平代表告警线路光信号丢失。LOS信号是光模块标准中定义的一个信号，许多厂家光模块定义都相同，因此使用光模块作为线路状态监测模块具有通用性好，简单方便的优点。
其中，时钟选通部12可以由多种形式的电路结构或模块组成，电路结构 越简单，反应越快，越能够在网络数据接入装置13中断时，及时截断时钟恢复部11自行向锁相环14传递的线路时钟。例如，如图2所示，在本发明的一个实施例中，时钟选通部12可以包括相互连接的检测模块121和选通模块122，其中，检测模块121与网络数据接入装置13相连，选通模块122与时钟恢复部11相连。选通模块122负责控制线路恢复时钟通断，外部连接了一路输入时钟信号，输出一路时钟，同时与检测模块相连，选通模块122在线路状态正常的情况下一直保持接通状态，当外部线路异常中断时，选通模块122能在第一时间收到来自检测模块121的通知，立刻切断时钟，让系统锁相环立刻进入保持状态。
在本发明的另一个实施例中，时钟选通部12还可以为组合逻辑电路，例如，可以将光模块的LOS信号，物理层芯片输出的线路恢复时钟信号同时接入CPLD(Complex Programmable Logic Device，复杂可编程逻辑器件)或FPGA(Field－Programmable Gate Array，现场可编程门阵列)，通过硬件描述语言将两个信号做一个简单的组合逻辑运算。
需要说明的是，为了适应系统中不同芯片、端口或电路对时钟频率的不同需求，如图3所示，时钟选通部12和锁相环14之间还可设置有分频部15，时钟选通部12可以通过分频部15与锁相环14相连。分频部15设置为将时钟选通部12输出的时钟分频。
可选的，如图4所示，分频部15还可以设置在时钟恢复部11和时钟选通部12之间，时钟恢复部11通过分频部15与时钟选通部12相连，分频部15设置为将时钟恢复部11输出的时钟分频后传输给时钟选通部12。
采用上述技术方案后，线路状态监测和时钟的关断完全通过硬件自动实现，无需软件参与，速度快，从线路中断到关断时钟，时间是纳秒级的，可以有效的使系统在外部时钟源丢失到切换新时钟源之间依旧工作在同步状态，提高了系统的性能。
相应的，如图5所示，本发明的实施例还提供一种前述实施例中任一种网络时钟同步装置的工作方法，包括：
S21，检测所述网络数据接入装置是否向所述时钟恢复部传输数据；
S22，在所述网络数据接入装置向所述时钟恢复部传输数据时，将所述时钟恢复部输出的线路时钟向所述锁相环传递；在所述网络数据接入装置中断向所述时钟恢复部传输数据时，截断所述时钟恢复部自行向所述锁相环传递的线路时钟，以使所述锁相环保持数据中断前的线路时钟。
本发明实施例提供的网络时钟同步装置的工作方法，时钟选通部12能够在网络数据接入装置13向时钟恢复部11传输数据时，将时钟恢复部11输出的线路时钟向锁相环14传递，在网络数据接入装置13中断向时钟恢复部11传输数据时，截断时钟恢复部11自行向锁相环14传递的线路时钟，从而使锁相环14保持数据中断前的线路时钟。由于时钟选通部12直接与网络数据接入装置13相连，可以实时获知网络数据接入装置13的数据输出状态，从而能够在网络数据接入装置13数据输出中断的第一时间，及时截断时钟恢复部11自行向锁相环14传递的线路时钟，使锁相环14继续保持原来的时钟输出，避免了锁相环14输出错误时钟的情况，有效提高了网络时钟的同步性。
可选的，当网络数据接入装置13包括光模块时，步骤S21中，检测所述网络数据接入装置是否向所述时钟恢复部传输数据包括：通过检测所述光模块的信号丢失LOS管脚检测所述网络数据接入装置是否向所述时钟恢复部传输数据。
下面通过应用示例、，对本发明实施例提供的网络时钟同步装置的工作方法进行详细说明。
工作在同步以太网中的设备，首先系统选择当前端口同步时钟，然后通过配置选择，系统锁相环锁定来自当前端口的线路恢复时钟，并以此为基准产生系统工作时钟，当当前端口的外部连接因为异常故障突然中断时，时钟选通部的检测模块检测到光信号丢失后立刻以电平信号形式把当前端口状态告知选通模块，选通模块在收到电平变换后，切断当前接口物理层芯片线路恢复时钟输出管脚输出的时钟。系统锁相环随即检测到外部时钟丢失，进入HOLDOVER保持模式，等系统管理层检测到外部信号异常，再通过SSM(Synchronization Status Message，同步状态信息)算法将同步源切换到其他时钟，详细流程可如图6所示。
采用上述技术方案可以大大降低外部时钟源异常对同步以太网设备的影 响，提高时钟系统性能，进而提高整个时钟同步网络的可靠性，且方法简单，可靠高效，无需增加额外的硬件成本。
工业实用性
本发明实施例提供的网络时钟同步装置及其工作方法，时钟恢复部能够利用网络数据接入装置传入的数据恢复出线路时钟；时钟选通部能够在网络数据接入装置向时钟恢复部传输数据时，将时钟恢复部输出的线路时钟向锁相环传递，在网络数据接入装置中断向时钟恢复部传输数据时，截断时钟恢复部自行向锁相环传递的线路时钟，从而使锁相环保持数据中断前的线路时钟。由于时钟选通部直接与网络数据接入装置相连，可以实时获知网络数据接入装置的数据输出状态，从而能够在网络数据接入装置数据输出中断的第一时间，及时截断时钟恢复部自行向锁相环传递的错误的线路时钟，使锁相环继续保持原来的时钟输出，避免了锁相环输出错误时钟的情况，有效提高了网络时钟的同步性。

Claims (9)

  1. 一种网络时钟同步装置，包括：时钟恢复部和时钟选通部，其中：
    所述时钟恢复部，其一端与网络数据接入装置相连，另一端与所述时钟选通部相连，设置为利用所述网络数据接入装置传入的数据恢复出线路时钟；
    所述时钟选通部，其第一输入端与所述时钟恢复部相连，第二输入端与所述网络数据接入装置相连，输出端与锁相环相连，其设置为：在所述网络数据接入装置向所述时钟恢复部传输数据时，将所述时钟恢复部输出的线路时钟向所述锁相环传递；在所述网络数据接入装置中断向所述时钟恢复部传输数据时，截断所述时钟恢复部自行向所述锁相环传递的线路时钟，以使所述锁相环保持数据中断前的线路时钟。
  2. 根据权利要求1所述的装置，其中，所述网络数据接入装置包括光模块，所述时钟恢复部包括物理层芯片。
  3. 根据权利要求2所述的装置，其中，所述时钟选通部的第二输入端与所述光模块的信号丢失LOS管脚相连。
  4. 根据权利要求1至3中任一项所述的装置，其中，所述时钟选通部包括相互连接的检测模块和选通模块，其中，所述检测模块与所述网络数据接入装置相连，所述选通模块与所述时钟恢复部相连。
  5. 根据权利要求1至3中任一项所述的装置，其中，所述时钟选通部为组合逻辑电路。
  6. 根据权利要求1至3中任一项所述的装置，所述时钟选通部和所述锁相环之间还设置有分频部，所述时钟选通部通过所述分频部与所述锁相环相连，所述分频部设置为，将所述时钟选通部输出的时钟分频。
  7. 根据权利要求1至3中任一项所述的装置，所述时钟恢复部和所述时钟选通部之间还设置有分频部，所述时钟恢复部通过所述分频部与所述时钟选通部相连，所述分频部设置为，将所述时钟恢复部输出的时钟分频后传输给所述时钟选通部。
  8. 一种根据权利要求1所述的网络时钟同步装置的工作方法，包括：
    检测所述网络数据接入装置是否向所述时钟恢复部传输数据；
    在所述网络数据接入装置向所述时钟恢复部传输数据时，将所述时钟恢复部输出的线路时钟向所述锁相环传递；在所述网络数据接入装置中断向所述时钟恢复部传输数据时，截断所述时钟恢复部自行向所述锁相环传递的线路时钟，以使所述锁相环保持数据中断前的线路时钟。
  9. 根据权利要求8所述的方法，其中，所述网络数据接入装置包括光模块；
    所述检测所述网络数据接入装置是否向所述时钟恢复部传输数据包括：
    通过检测所述光模块的信号丢失LOS管脚检测所述网络数据接入装置是否向所述时钟恢复部传输数据。
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