WO2016092987A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2016092987A1
WO2016092987A1 PCT/JP2015/081069 JP2015081069W WO2016092987A1 WO 2016092987 A1 WO2016092987 A1 WO 2016092987A1 JP 2015081069 W JP2015081069 W JP 2015081069W WO 2016092987 A1 WO2016092987 A1 WO 2016092987A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
transparent member
substrate
semiconductor element
semiconductor
Prior art date
Application number
PCT/JP2015/081069
Other languages
French (fr)
Japanese (ja)
Inventor
伸一 眞▲崎▼
Original Assignee
アオイ電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by アオイ電子株式会社 filed Critical アオイ電子株式会社
Priority to TW104141275A priority Critical patent/TW201633516A/en
Publication of WO2016092987A1 publication Critical patent/WO2016092987A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device in which a semiconductor element is sealed by a sealing member and a method for manufacturing the same.
  • a semiconductor element is mounted on a substrate, a gap is provided above the semiconductor element and covered with a lid, and a non-conductive resin is filled between the lid and the substrate.
  • a functional area such as an optical sensor
  • the lid that covers the upper portion of the semiconductor element is composed of a plurality of members such as a holder and a lens barrel, which increases the cost.
  • a semiconductor device includes a substrate having a terminal provided on the upper surface, a semiconductor element having an electrode disposed on the upper surface of the substrate and electrically connected to the terminal of the substrate, and a semiconductor element A transparent flat plate covering the upper portion of the substrate, and a transparent member integrally formed with a plurality of legs for providing a predetermined gap between the flat plate and the upper surface of the substrate, the upper surface of the substrate, and the upper surface of the substrate facing each other And a sealing member provided so as to surround the periphery of the semiconductor element between the lower surface of the transparent member.
  • the electrode of the semiconductor element is provided on the upper surface of the semiconductor element, and the electrode of the semiconductor element and the terminal of the substrate are electrically connected by the wire. It is preferable that According to the third aspect of the present invention, in the semiconductor device of the first or second aspect, it is preferable that the legs are bonded to the upper surface of the substrate.
  • the semiconductor element has a rectangular shape
  • the substrate has a rectangular shape larger than the semiconductor element
  • the transparent member includes:
  • the semiconductor element has a rectangular shape larger than the semiconductor element, and the semiconductor element is arranged in the center of the substrate with each side of the semiconductor element being inside each side of the substrate, and the legs are provided at the four corners of the transparent member.
  • the sealing member preferably seals between adjacent legs.
  • the outer peripheral side surface of the sealing member is preferably flush with each of the four side edges of the substrate.
  • the transparent member is preferably a plane whose upper surface and lower surface are parallel to each other.
  • a method for manufacturing a semiconductor device comprising: a material substrate having a plurality of semiconductor device formation regions on each of which a semiconductor device is formed; and a terminal formed in each semiconductor device formation region A step of arranging a semiconductor element having an electrode on the upper surface in each semiconductor device formation region of the material substrate, a step of wire bonding each electrode of the semiconductor element and a terminal formed on the material substrate, A transparent member having a plurality of legs and covering an upper portion of the semiconductor element is disposed in each semiconductor device forming region of the material substrate, and the transparent members disposed in each of the plurality of semiconductor device forming regions are separated from each other.
  • in the method of manufacturing a semiconductor device according to the seventh aspect in the step of providing the sealing resin between the upper surface of the material substrate and the lower surface of the transparent member facing the upper surface of the material substrate.
  • the sealing member is injected from between the transparent members disposed in the plurality of semiconductor device forming regions of the material substrate and spaced apart from each other, and the upper surface of the material substrate, the lower surface of the transparent member, and the side surfaces of the legs It is preferable to seal the opening surrounded by.
  • a step of preparing a transparent member material plate having an area capable of forming a plurality of transparent members, and a cutting tool are provided. By moving the cutting tool in a direction orthogonal to one direction, and forming a first groove having a width corresponding to the gap between the legs in the transparent member material plate.
  • the method further includes a step of manufacturing the transparent member including a step of cutting along the extending direction of the groove.
  • the present invention since the upper part of the semiconductor element is covered with the transparent member having a plurality of legs, an increase in the cost of the semiconductor device can be suppressed.
  • FIG. 1A is a perspective view schematically showing the appearance of a semiconductor device according to an embodiment
  • FIG. 1B is a semiconductor schematically showing an internal structure of the device observed through a transparent member
  • FIG. 2A is a plan view from above of the semiconductor device shown in FIG. 1, and FIG. 2B is a cross-sectional view taken along line IIb-IIb in FIG. 2A.
  • FIG. 3 is an external perspective view of a transparent member.
  • 4A to 4C are perspective views for explaining a method for producing a transparent member.
  • FIG. 5 is a plan view from above for explaining a method of manufacturing a semiconductor device, and shows a step of placing a semiconductor element on a substrate.
  • FIG. 6 is a diagram illustrating a process following FIG. 5.
  • FIG. 5 is a plan view schematically showing the appearance of a semiconductor device according to an embodiment
  • FIG. 1B is a semiconductor schematically showing an internal structure of the device observed through a transparent member.
  • FIG. 2A is a plan
  • FIG. 7 is a diagram showing a step following FIG.
  • FIG. 8 is a diagram showing a step following FIG.
  • FIG. 9 is a diagram showing a step following FIG. 10A and 10B are diagrams showing a modification.
  • FIGS. 11A and 11B are diagrams showing a modification.
  • FIG. 1A is a perspective view schematically showing the appearance of a semiconductor device according to an embodiment, and a description of a device internal structure observed through a transparent member described later is omitted.
  • FIG. 1B is a perspective view of a semiconductor device schematically showing the device internal structure observed through a transparent member described later.
  • FIG. 2A is a plan view from above of the semiconductor device shown in FIG. 1, and schematically shows the internal structure of the device observed through a transparent member.
  • FIG. 2B is a cross-sectional view taken along the line IIb-IIb in FIG.
  • FIG. 3 is an external perspective view of the transparent member.
  • the left-right direction, front-rear direction, and up-down direction of the semiconductor device are as illustrated.
  • a sealing member described later is shaded.
  • the semiconductor device 1 includes a substrate, that is, a circuit board 10, a semiconductor element 20, a transparent member 40, and a sealing member 50.
  • the semiconductor element 20 has a functional region 21 such as a light receiving region on the upper surface 20a, and is die-bonded on the upper surface 10a of the circuit board 10 (see FIG. 2B).
  • a plurality of electrodes 22 are arranged around the functional region 21 of the semiconductor element 20.
  • terminals 11 are arranged around the semiconductor element 20.
  • Each electrode 22 of the semiconductor element 20 is electrically connected to the terminal 11 of the circuit board 10 by a wire 23.
  • connection between the electrode 22 and the terminal 11 is based on a wire bonding method using a wire such as gold, silver, copper, or alloy.
  • a wire such as gold, silver, copper, or alloy.
  • external terminal portions 12 connected to the corresponding terminals 11 are formed through via holes (not shown).
  • the semiconductor element 20 has a rectangular shape in plan view, and the circuit board 10 has a rectangular shape that is slightly larger than the semiconductor element 20 in plan view.
  • the semiconductor element 20 is disposed substantially at the center of the circuit board 10, and the opposite sides of the semiconductor element 20 are respectively disposed on the inner side by an equal length from the corresponding side of the circuit board 10.
  • a transparent member 40 shown in FIG. 3 is disposed on the upper surface 10 a of the circuit board 10.
  • FIG. 3 shows the transparent member upside down.
  • the transparent member 40 includes a top plate 41 that is a rectangular flat plate and leg portions 42 that extend downward at the four corners of the top plate 41.
  • the leg portion 42 is formed integrally with the top plate 41. That is, the transparent member 40 is an integral member, and is not a combination of the top plate 41 and the leg portion 42 formed separately.
  • the shape and size of the transparent member 40 in plan view are the same as the shape and size of the circuit board 10. That is, the four side surfaces 40c and 40d (see FIG. 1A) of the transparent member 40 and the four side surfaces 10c and 10d of the circuit board 10 (see FIG. 1A) are flush with each other. .
  • the side forming the side surface 40c of the transparent member 40 is a long side, and the side forming the side surface 40d is a short side.
  • the transparent member 40 is formed of transparent resin such as transparent glass or acrylic resin. Therefore, in the transparent member 40, not only the top plate 41 but also the leg portion 42 is transparent. In FIG. 3, the leg portion 42 has a prismatic shape. However, the shape of the leg portion 42 may be a cylindrical shape, a truncated cone, a truncated pyramid, or the like.
  • the upper surface 41a and the lower surface 41b of the top plate 41 are formed flat over the entire surface.
  • the top surface 41a and the bottom surface 41b of the top plate 41 are parallel. That is, the top plate 41 is a parallel flat plate and has no positive or negative refractive power. Therefore, the top plate 41 does not converge or diverge light transmitted through the top plate 41.
  • the lower surface 42 a of the leg portion 42 is parallel to the upper surface 41 a and the lower surface 41 b of the top plate 41.
  • the side surface facing the adjacent leg portions 42 is referred to as an inner side surface 42 b.
  • each leg portion 42 is bonded to the upper surface 10a of the circuit board 10 with an adhesive (not shown).
  • the height (length in the vertical direction) from the lower surface 42a of the leg portion 42 to the lower surface 41b of the top plate 41, that is, the leg length h of the leg portion 42 is determined by connecting the terminal 11 and the electrode 22 as shown in FIG. It is formed larger than the height of the wire 23 to be connected. That is, the lower surface 41 b of the top plate 41 is located above the maximum height portion 23 a of the wire 23 protruding from the upper surface 20 a of the semiconductor element 20.
  • the transparent member 40 is disposed in the center of the circuit board 10 in the left-right direction and the front-rear direction, and covers the entire semiconductor element 20. As shown in FIG. 2B, a gap S is formed between the upper surface 20 a of the semiconductor element 20 and the lower surface 41 b of the top plate 41 of the transparent member 40.
  • each leg portion 42 is disposed outside the semiconductor element 20 in a plan view. Further, as shown in FIG. 2B, the terminals 11 formed on the upper surface 10 a of the circuit board 10 are located between the adjacent leg portions 42.
  • the sealing member 50 is formed on the upper surface 10 a of the circuit board 10 so as to surround the outer periphery of the semiconductor element 20, and seals the opening on the side surface of the semiconductor device 1.
  • the sealing member 50 is a space surrounded by the adjacent leg portions 42, that is, the upper surface 10 a of the circuit board 10, the lower surface 41 b of the top plate 41, and the inner side surface 42 b of the leg portion 42. Is sealed. A method for forming the sealing member 50 will be described later.
  • the sealing member 50 is provided between the upper surface 10 a of the circuit board 10 and the lower surface 41 b of the top plate 41.
  • the sealing member 50 covers a predetermined range on the terminal 11 side of the terminal 11 of the circuit board 10 and the wire 23.
  • the inner peripheral side surface 50 a of the sealing member 50 facing the side surface of the semiconductor element 20 is not in contact with the side surface of the semiconductor element 20, but may be in contact with the side surface of the semiconductor element 20.
  • the sealing member 50 does not cover the predetermined length on the electrode 22 side of the electrode 22 and the wire 23 formed on the upper surface 20 a of the semiconductor element 20.
  • the sealing member 50 may be configured to cover the electrode 22 and the predetermined range on the electrode 22 side of the wire 23 as long as the functional region 21 of the semiconductor element 20 is not covered.
  • a plurality of semiconductor devices 1 shown in FIGS. The circuit board 10, the semiconductor element 20, and the transparent member 40 are individually manufactured. Below, an example of the method of manufacturing several transparent member 40 with sufficient productivity and low cost is demonstrated.
  • FIG. 3 and FIGS. 4A to 4C a method for manufacturing the transparent member 40 in the case where the four semiconductor elements 20 are manufactured at once will be described as an example.
  • dimensions of each part of the transparent member 40 are determined as shown in FIG. That is, the height of the transparent member 40 is H, the leg length of the leg part 42 is h as described above, the dimension of the leg part 42 in the left-right direction is d1, and the dimension of the leg part 42 in the front-rear direction is d2.
  • the interval between the inner side surfaces 42b of the left and right leg portions 42 is W1, and the interval between the inner side surfaces 42b of the front and rear leg portions 42 is W2.
  • the thickness of the transparent member material plate is the same as the height H (vertical length) of the transparent member 40 shown in FIG.
  • a rectangular transparent member material plate is processed to form a plurality of grooves 32 extending in the front-rear direction, as shown in FIG.
  • the width of the groove 32 is the same as the interval W ⁇ b> 1 between the inner side surfaces 42 b of the left and right leg portions 42 of the transparent member 40.
  • the width of the groove 32 is the same as the gap between the left and right leg portions 42 of the transparent member 40.
  • the depth of the groove 32 is the same as the leg length h of the leg portion 42.
  • the grooves 32 adjacent to each other on the left and right are formed in parallel so as to be separated by twice (2d1) the dimension d1 in the left-right direction of the leg portion 42 of the transparent member 40. That is, each groove 32 is processed such that a groove unprocessed portion 31 having a length of 2 d 1 is formed between adjacent grooves 32.
  • the groove 32 is formed, for example, by moving the cutting tool in the front-rear direction.
  • the groove 32 is positioned such that the length from the left and right side surfaces 37 to the end portion of the groove 32 is the same as the dimension d1 of the leg portion 42 of the transparent member 40 Is provided. That is, when the groove 32 is formed, walls KBL and KBR having a width d1 are formed at the left and right edges of the transparent member material plate, and a wall KBC having a width of d1 ⁇ 2 is provided at the center of the transparent member material plate. That is, the above-described groove unprocessed portion 31 is formed.
  • grooves 34 each having a length W2 in the front-rear direction, that is, a width W2 are formed at two positions in the front-rear direction of the left and right walls KBL, KBR and the central wall KBC, as shown in FIG.
  • the groove 34 is formed by moving the cutting tool in the left-right direction, for example, similarly to the case where the groove 32 is formed.
  • the protrusions 42Xa at the four corners of the transparent member material plate are rectangular cross sections having the same length d1 ⁇ d2 as the leg portions 42 in FIG.
  • the central protrusion 42Xb has a rectangular cross section of length (2 ⁇ d1) ⁇ (2 ⁇ d2).
  • the protrusions 42Xc at the front and rear ends sandwiching the central protrusion 42Xb in the front-rear direction have a rectangular cross section of d2 ⁇ (2 ⁇ d1).
  • the left and right protrusions 42Xd sandwiching the central protrusion 42Xb in the left-right direction have a rectangular cross section of d1 ⁇ (2 ⁇ d2).
  • the groove 34 is formed at a position where the above-described dimensions are set.
  • the width W ⁇ b> 2 of the groove 34 is an interval W ⁇ b> 2 between the inner side surfaces 42 b of the front and rear legs 42 of the transparent member 40.
  • the depth of the groove 34 is the same as the leg length h of the leg portion 42. In this way, the transparent member intermediate assembly plate 30P shown in FIGS. 4B and 4C is formed from the transparent member material plate.
  • the left and right side surfaces 37 may be cut so that the width of the walls KBL and KBR is d1 after the width of the left and right walls KBL and KBR is made larger than d1 and the groove 32 is formed.
  • the length in the front-rear direction of the protrusions 42Xc at both front and rear ends is made larger than d2, and after forming the groove 34, the front and rear side surfaces 37 are arranged so that the length in the front-rear direction of the protrusions 42Xc is d2. You may cut.
  • the transparent member intermediate assembly plate 30P After forming the transparent member intermediate assembly plate 30P, the transparent member intermediate assembly plate 30P is cut at a cutting position indicated by a two-dot chain line in FIG. This cutting position is an intermediate position between adjacent grooves 32 and an intermediate position between adjacent grooves 34. Thereby, the some transparent member 40 can be produced efficiently.
  • the case where two grooves 32 and 34 are formed on the transparent member material plate is illustrated.
  • This is an example of manufacturing four transparent members 40 used for four semiconductor devices at a time.
  • you may increase the number of the grooves 32 and 34 formed in a transparent member raw material board.
  • only one groove 32 may be formed on the transparent member material plate, and the transparent member 40 may be obtained by cutting at an intermediate position between adjacent grooves 34.
  • This is an example of manufacturing two transparent members 40 used for two semiconductor devices at a time.
  • the manufacturing method of the said transparent member 40 is suitable when forming the transparent member 40 with glass.
  • the transparent member intermediate assembly plate 30P in which the grooves 32 and 34 shown in FIG. 4B are formed may be formed by a molding method or the like.
  • a method for manufacturing a semiconductor device will be described with reference to FIGS.
  • a material circuit board (material substrate) 10P for forming a plurality of semiconductor device forming regions 1r is prepared.
  • each semiconductor device formation region is denoted by reference numeral 1r.
  • the terminal 11 and the external terminal portion 12 are formed in each semiconductor device formation region 1r of the material circuit board 10P.
  • the terminal 11 and the external terminal portion 12 are formed in each semiconductor device formation region 1r of the material circuit board 10P.
  • four semiconductor devices 1 in the left and right direction ⁇ 3 in the front and rear direction are formed on the material circuit board 10P will be described as an example, but more or less semiconductors are formed on the material circuit board 10P.
  • the device 1 can be formed.
  • each semiconductor device formation region 1r is the same as the size and shape of the semiconductor device 1 in plan view. That is, each semiconductor device formation region 1r is a region surrounded by two long sides extending in the left-right direction and two short sides extending in the front-rear direction.
  • the semiconductor element 20 is die-bonded to each semiconductor device formation region 1r to fix the semiconductor element 20 to the material substrate, that is, the material circuit board 10P. Then, the electrodes 22 of the semiconductor element 20 and the terminals 11 formed in the semiconductor device formation region 1r of the material circuit board 10P are connected by wire bonding.
  • the transparent member 40 is fixed in each semiconductor device formation region 1r.
  • the transparent member 40 is fixed by adhering the lower surface 42a (see FIG. 3) of the leg portion 42 to the material circuit board 10P with an adhesive (not shown).
  • a gap is provided between the transparent members 40 adjacent to each other in the front-rear direction and the left-right direction.
  • semiconductor device formation between the semiconductor device forming regions 1r adjacent in the left-right direction, that is, between the transparent members 40 adjacent in the left-right direction, and the left end side and the right end side is formed.
  • a liquid resin material 50p is injected into one side edge of the region 1r.
  • the resin material 50p is the sealing member 50 before being solidified.
  • the resin material 50p wets and spreads on the upper surface of the material circuit board 10P, the lower surface 41b of the top plate 41 (see FIG. 2B), and the inner side surface 42b of the leg portion 42 (see FIG. 2B). It flows from the outer side of the short side of the transparent member 40 toward the inner side of the semiconductor device forming region 1r.
  • a liquid resin material 50p is injected into one side edge of the formation region 1r.
  • the resin material 50p spreads over the upper surface of the material circuit board 10P, the lower surface 41b of the top plate 41, and the inner side surface 42b of the leg portion 42, and extends from the outside of the long side of the transparent member 40 to the semiconductor device forming region 1r. Flows inward.
  • a gap S (see FIG. 2B) is formed between the upper surface 20a of the semiconductor element 20 and the lower surface 41b of the top plate 41 of the transparent member 40.
  • an epoxy resin or a silicone resin can be used as the resin material 50p.
  • a filler such as glass fiber may be dispersed in the resin.
  • the resin material 50p is cured by heat or ultraviolet rays. Then, as shown in FIG. 9, the material circuit board 10 ⁇ / b> P is cut in the left-right direction and the front-back direction at the position of the cutting line indicated by the two-dot chain line.
  • the cutting line indicated by the two-dot chain line in FIG. 9 overlaps the boundary line of each semiconductor device formation region 1r. By this cutting, the outer peripheral side surface of the sealing member 50 is flush with the four side surfaces of the circuit board 10.
  • a plurality of semiconductor devices 1 shown in FIG. 1 can be formed by the steps described above.
  • the transparent member that covers the upper portion of the semiconductor element 20 is the transparent member 40 in which a plurality of leg portions 42 that are placed on the upper surface 10a of the circuit board 10 are integrally formed.
  • the leg portion 42 is formed integrally with the top plate 41. For this reason, it is not necessary to align each of the four spacers as compared with a structure in which the member corresponding to the top plate 41 portion is supported by four spacers that are members different from the member. The manufacturing cost can be reduced.
  • a material circuit board (material) having a plurality of semiconductor device forming regions 1 r on which the semiconductor devices 1 are respectively formed on the upper surface, and terminals 11 are formed in each semiconductor device forming region 1 r Substrate) 10P was prepared.
  • the semiconductor element 20 which has the electrode 22 on the upper surface 20a was arrange
  • the electrodes 22 of the semiconductor elements 20 and the terminals 11 formed on the material circuit board 10P were connected by wire bonding.
  • a plurality of transparent members 40 each having a plurality of leg portions 42 and covering the upper portion of the semiconductor element 20 are arranged in the respective semiconductor device forming regions 1r of the material circuit board 10P so as to be separated from each other.
  • the sealing member 50 is provided between the upper surface of the material circuit board 10P and the lower surface of the transparent member 40 facing the upper surface of the material circuit board 10P, that is, the lower surface 41b of the top plate 41. Then, the material circuit board 10P was separated for each semiconductor device formation region 1r. Thereby, positioning of the transparent member 40 and attachment to the material circuit board 10P can be performed easily and efficiently, and the manufacturing process of the semiconductor device 1 can be simplified. In addition, an increase in manufacturing cost of the semiconductor device 1 can be suppressed.
  • the sealing member 50 In the step of providing the sealing member 50 between the upper surface of the material circuit board 10P and the lower surface of the transparent member 40 facing the upper surface of the material circuit board 10P, that is, the lower surface 41b of the top plate 41, the material circuit board 10P.
  • the resin material 50p is injected from between the transparent members 40 spaced apart from each other in each semiconductor device forming region 1r, and the upper surface of the material circuit board 10P and the lower surface of the transparent member 40, that is, the top plate 41
  • the opening surrounded by the lower surface 41b and the inner side surface 42b of the leg portion 42 is sealed.
  • a transparent member material plate having an area where a plurality of transparent members 40 can be formed was prepared.
  • channel 32 which has the width W1 for the clearance gap between the leg parts 42 was formed in the transparent member raw material board.
  • a groove 34 having a width W2 corresponding to the gap between the leg portions 42 and orthogonal to the groove 32 was formed on the transparent member material plate.
  • the transparent member material plate was cut along the extending direction of the grooves 32 and 34. That is, the process of manufacturing the transparent member 40 includes the steps of preparing a transparent member material plate having an area where a plurality of transparent members 40 can be formed, and moving the cutting tool in one direction to form a transparent member material plate.
  • channel 32 in a transparent member raw material board is not formed by moving a cutting tool in the direction orthogonal to one direction 31, a step of forming a groove 34 having a width W2 corresponding to the gap of the leg portion 42 and orthogonal to the groove 32, and cutting the transparent member material plate along the extending direction of the grooves 32 and 34.
  • the transparent member 40 can be manufactured at low cost, and the increase in the manufacturing cost of the semiconductor device 1 can be suppressed.
  • the leg part 42 is formed integrally with the top plate 41, the strength of the transparent member 40 is improved. Therefore, since the thickness of the top plate 41 can be reduced, the semiconductor device 1 can be miniaturized.
  • the four side surfaces 40c and 40d of the transparent member 40 are respectively It is considered to be the same. That is, in the above description, the shape and size of the transparent member 40 in plan view are the same as the shape and size of the circuit board 10. However, the present invention is not limited to this.
  • the size of the transparent member 40 in plan view may be smaller than the size of the circuit board 10 as in the semiconductor device 1A shown in the perspective view of FIG. That is, the dimension of the transparent member 40 in plan view may be smaller than the dimension of the semiconductor device formation region 1r (see FIG. 5). In this case, as shown in FIG.
  • the upper surface of the sealing member 50 may be lower than the top plate 41 of the transparent member 40, and the semiconductor device shown in the perspective view of FIG. As in 1B, the top surface of the sealing member 50 may be flush with the top plate 41 of the transparent member 40.
  • the upper surface of the sealing member 50 may be higher than the top plate 41 of the transparent member 40.
  • the sealing member 50 may not cover the top plate 41 of the transparent member 40.
  • the sealing member 50 may cover a part of the top surface of the top plate 41 of the transparent member 40, for example, the periphery of the top surface of the top plate 41.
  • the functional region 21 see FIG. 1B
  • sealing is performed so as not to block incident light to the functional region 21.
  • the member 50 needs to be provided.
  • the functional area 21 of the semiconductor element 20 is exemplified as the light receiving area.
  • the semiconductor element 20 may be an imaging element.
  • the present invention can also be applied to a semiconductor element 20 having a function other than light reception, such as a light emitting element, such as an acceleration sensor.
  • the gap S is sealed with the sealing member 50, but the present invention is not limited to this.
  • the gap portion S may not be sealed with the sealing member 50.
  • the functional region 21 may be exposed to the external atmosphere of the semiconductor device 1 by providing an opening or the like in a part of the transparent member 40.
  • the semiconductor element 20 has been described as a quad type in which the electrodes 22 are arranged on four sides.
  • the present invention can also be applied to the dual-type semiconductor element 20 in which the electrodes 22 are arranged only on a pair of opposite sides.
  • the semiconductor device of the present invention can be variously modified and configured within the scope of the invention.
  • a transparent flat plate covering the upper part of the semiconductor element, a flat plate, and an upper surface of the substrate.
  • a transparent member Surrounding the periphery of the semiconductor element is a transparent member integrally formed with a plurality of legs for providing a predetermined gap between the upper surface of the substrate, and an upper surface of the substrate and a lower surface of the transparent member facing the surface. What is necessary is just to be provided with the sealing member provided in.

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Abstract

This semiconductor device is provided with: a substrate which is provided with a terminal on the upper surface; a semiconductor element which is arranged on the upper surface of the substrate and has an electrode that is electrically connected to the terminal of the substrate; a transparent member which is obtained by integrally forming a transparent flat plate that covers the upper part of the semiconductor element with a plurality of leg parts for providing a predetermined gap between the flat plate and the upper surface of the substrate; and a sealing member which is arranged so as to surround the semiconductor element between the upper surface of the substrate and the lower surface of the transparent member, said lower surface facing the upper surface of the substrate.

Description

半導体デバイスおよびその製造方法Semiconductor device and manufacturing method thereof
　この発明は、半導体素子が封止部材により封止された半導体デバイスおよびその製造方法に関する。 The present invention relates to a semiconductor device in which a semiconductor element is sealed by a sealing member and a method for manufacturing the same.
　光学センサ等の機能領域を有する半導体デバイスにおいて、半導体素子を基板上に搭載し、半導体素子の上部に空隙を設けて蓋体で覆い、蓋体と基板との間に非導電性の樹脂を充填したものが知られている（特許文献１参照）。 In a semiconductor device having a functional area such as an optical sensor, a semiconductor element is mounted on a substrate, a gap is provided above the semiconductor element and covered with a lid, and a non-conductive resin is filled between the lid and the substrate. Is known (see Patent Document 1).
日本国特開２００６－２７８７２６号公報Japanese Unexamined Patent Publication No. 2006-278726
　特許文献１に記載された発明では、半導体素子の上部を覆う蓋体がホルダやレンズバレルなどの複数の部材から構成されており、コストが高くなる。 In the invention described in Patent Document 1, the lid that covers the upper portion of the semiconductor element is composed of a plurality of members such as a holder and a lens barrel, which increases the cost.
　本発明の第１の態様によると、半導体デバイスは、上面に端子が設けられた基板と、基板の上面に配置され、基板の端子に電気的に接続された電極を有する半導体素子と、半導体素子の上部を覆う透明な平板と、平板と基板の上面との間に所定の空隙を設けるための複数の脚部とが一体に形成された透明部材と、基板の上面と、基板の上面と対向する透明部材の下面との間で、半導体素子の周囲を囲んで設けられた封止部材と、を備える。
　本発明の第２の態様によると、第１の態様の半導体デバイスにおいて、半導体素子の電極は、半導体素子の上面に設けられ、半導体素子の電極と基板の端子とは、ワイヤにより電気的に接続されていることが好ましい。
　本発明の第３の態様によると、第１または第２の態様の半導体デバイスにおいて、脚部は、基板の上面に接着されていることが好ましい。
　本発明の第４の態様によると、第１から３のいずれか１態様の半導体デバイスにおいて、半導体素子は矩形形状を有し、基板は、半導体素子より大きい矩形形状を有し、透明部材は、半導体素子より大きい矩形形状を有し、半導体素子は、基板の中央部に、半導体素子の各側辺を基板の各側辺の内側にして配置され、脚部は、透明部材の四隅に設けられ、封止部材は、隣り合う脚部の間を封止することが好ましい。
　本発明の第５の態様によると、第３または第４の態様の半導体デバイスにおいて、封止部材の外周側面は、基板の４つの側辺のそれぞれに面一であることが好ましい。
　本発明の第６の態様によると、第１から５のいずれか１態様の半導体デバイスにおいて、透明部材は、上面および下面が互いに平行な平面であることが好ましい。
　本発明の第７の態様によると、半導体デバイスの製造方法は、半導体デバイスがそれぞれ形成される複数の半導体デバイス形成領域を上面に有し、各半導体デバイス形成領域内に端子が形成された素材基板を準備する工程と、素材基板の各半導体デバイス形成領域内に、上面に電極を有する半導体素子を配置する工程と、半導体素子それぞれの電極と素材基板に形成された端子をワイヤボンディングする工程と、複数の脚部を有し、半導体素子の上部を覆う透明部材を、素材基板の各半導体デバイス形成領域内に配置し、複数の半導体デバイス形成領域のそれぞれに配置された前記透明部材が相互に離間した工程と、素材基板の上面と、素材基板の上面と対向する透明部材の下面との間に封止部材を設ける工程と、素材基板を各半導体デバイス形成領域毎に分離する工程と、を含む。
　本発明の第８の態様によると、第７の態様の半導体デバイスの製造方法において、素材基板の上面と、素材基板の上面と対向する透明部材の下面との間に封止樹脂を設ける工程では、素材基板の複数の半導体デバイス形成領域のそれぞれに配置されて相互に離間した透明部材同士の間から封止部材を注入して、素材基板の上面と、透明部材の下面と、脚部の側面とで囲まれた開口を封止することが好ましい。
　本発明の第９の態様によると、第７または第８の態様の半導体デバイスの製造方法において、複数の透明部材を形成可能な面積を有する透明部材素材板を準備する工程と、切削工具を一の方向に移動させることで、透明部材素材板に、脚部の間隙分の幅を有する第１の溝を形成する工程と、切削工具を一の方向と直交する方向に移動させることで、透明部材素材板における第１の溝が形成されない未加工部に対して、脚部の間隙分の幅を有し、第１の溝と直交する第２の溝を形成する工程と、透明部材素材板を、溝の延在方向に沿って切断する工程と、を含み前記透明部材を製造する工程をさらに備えることが好ましい。 According to the first aspect of the present invention, a semiconductor device includes a substrate having a terminal provided on the upper surface, a semiconductor element having an electrode disposed on the upper surface of the substrate and electrically connected to the terminal of the substrate, and a semiconductor element A transparent flat plate covering the upper portion of the substrate, and a transparent member integrally formed with a plurality of legs for providing a predetermined gap between the flat plate and the upper surface of the substrate, the upper surface of the substrate, and the upper surface of the substrate facing each other And a sealing member provided so as to surround the periphery of the semiconductor element between the lower surface of the transparent member.
According to the second aspect of the present invention, in the semiconductor device of the first aspect, the electrode of the semiconductor element is provided on the upper surface of the semiconductor element, and the electrode of the semiconductor element and the terminal of the substrate are electrically connected by the wire. It is preferable that
According to the third aspect of the present invention, in the semiconductor device of the first or second aspect, it is preferable that the legs are bonded to the upper surface of the substrate.
According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the semiconductor element has a rectangular shape, the substrate has a rectangular shape larger than the semiconductor element, and the transparent member includes: The semiconductor element has a rectangular shape larger than the semiconductor element, and the semiconductor element is arranged in the center of the substrate with each side of the semiconductor element being inside each side of the substrate, and the legs are provided at the four corners of the transparent member. The sealing member preferably seals between adjacent legs.
According to the fifth aspect of the present invention, in the semiconductor device of the third or fourth aspect, the outer peripheral side surface of the sealing member is preferably flush with each of the four side edges of the substrate.
According to the sixth aspect of the present invention, in the semiconductor device according to any one of the first to fifth aspects, the transparent member is preferably a plane whose upper surface and lower surface are parallel to each other.
According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a material substrate having a plurality of semiconductor device formation regions on each of which a semiconductor device is formed; and a terminal formed in each semiconductor device formation region A step of arranging a semiconductor element having an electrode on the upper surface in each semiconductor device formation region of the material substrate, a step of wire bonding each electrode of the semiconductor element and a terminal formed on the material substrate, A transparent member having a plurality of legs and covering an upper portion of the semiconductor element is disposed in each semiconductor device forming region of the material substrate, and the transparent members disposed in each of the plurality of semiconductor device forming regions are separated from each other. A sealing member between the upper surface of the material substrate and the lower surface of the transparent member facing the upper surface of the material substrate; and And a step of separating each formation region.
According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh aspect, in the step of providing the sealing resin between the upper surface of the material substrate and the lower surface of the transparent member facing the upper surface of the material substrate. The sealing member is injected from between the transparent members disposed in the plurality of semiconductor device forming regions of the material substrate and spaced apart from each other, and the upper surface of the material substrate, the lower surface of the transparent member, and the side surfaces of the legs It is preferable to seal the opening surrounded by.
According to a ninth aspect of the present invention, in the method for manufacturing a semiconductor device according to the seventh or eighth aspect, a step of preparing a transparent member material plate having an area capable of forming a plurality of transparent members, and a cutting tool are provided. By moving the cutting tool in a direction orthogonal to one direction, and forming a first groove having a width corresponding to the gap between the legs in the transparent member material plate. Forming a second groove perpendicular to the first groove having a width corresponding to the gap between the leg portions with respect to an unprocessed portion in which the first groove is not formed in the member material plate; and a transparent member material plate It is preferable that the method further includes a step of manufacturing the transparent member including a step of cutting along the extending direction of the groove.
　この発明によれば、複数の脚部を有する透明部材で半導体素子の上部を覆うようにしたので、半導体デバイスのコスト増を抑制できる。 According to the present invention, since the upper part of the semiconductor element is covered with the transparent member having a plurality of legs, an increase in the cost of the semiconductor device can be suppressed.
図１（ａ）は、一実施の形態の半導体デバイスの外観を模式的に示した斜視図、図１（ｂ）は、透明部材を介して観察されるデバイス内部構造を模式的に表した半導体デバイスの斜視図。FIG. 1A is a perspective view schematically showing the appearance of a semiconductor device according to an embodiment, and FIG. 1B is a semiconductor schematically showing an internal structure of the device observed through a transparent member. FIG. 図２（ａ）は、図１に示す半導体デバイスの上方からの平面図、図２（ｂ）は図２（ａ）のＩＩｂ－ＩＩｂ線断面図。2A is a plan view from above of the semiconductor device shown in FIG. 1, and FIG. 2B is a cross-sectional view taken along line IIb-IIb in FIG. 2A. 図３は、透明部材の外観斜視図。FIG. 3 is an external perspective view of a transparent member. 図４（ａ）～（ｃ）は、透明部材の製造方法を説明するための斜視図。4A to 4C are perspective views for explaining a method for producing a transparent member. 図５は、半導体デバイスの製造方法を説明するための上方からの平面図であり、基板上に半導体素子を載置する工程を示す。FIG. 5 is a plan view from above for explaining a method of manufacturing a semiconductor device, and shows a step of placing a semiconductor element on a substrate. 図６は、図５に続く工程を示す図。FIG. 6 is a diagram illustrating a process following FIG. 5. 図７は、図６に続く工程を示す図。FIG. 7 is a diagram showing a step following FIG. 図８は、図７に続く工程を示す図。FIG. 8 is a diagram showing a step following FIG. 図９は、図８に続く工程を示す図。FIG. 9 is a diagram showing a step following FIG. 図１０（ａ）（ｂ）は、変形例を示す図。10A and 10B are diagrams showing a modification. 図１１（ａ）（ｂ）は、変形例を示す図。FIGS. 11A and 11B are diagrams showing a modification.
［半導体デバイスの構造］
　以下、この発明の半導体デバイスの一実施の形態を図面と共に説明する。
　図１（ａ）は、一実施の形態の半導体デバイスの外観を模式的に示した斜視図であり、後述する透明部材を介して観察されるデバイス内部構造の記載を省略している。図１（ｂ）は、後述する透明部材を介して観察されるデバイス内部構造を模式的に表した半導体デバイスの斜視図である。図２（ａ）は、図１に示す半導体デバイスの上方からの平面図であり、透明部材を介して観察されるデバイス内部構造を模式的に表している。図２（ｂ）は、図２（ａ）のＩＩｂ－ＩＩｂ線断面図である。また、図３は、透明部材の外観斜視図である。
　説明の便宜上、半導体デバイスの左右方向、前後方向および上下方向を図示の通りとする。なお、図２（ａ）では、後述する封止部材に網掛けを施している。 [Structure of semiconductor device]
Hereinafter, an embodiment of a semiconductor device of the present invention will be described with reference to the drawings.
FIG. 1A is a perspective view schematically showing the appearance of a semiconductor device according to an embodiment, and a description of a device internal structure observed through a transparent member described later is omitted. FIG. 1B is a perspective view of a semiconductor device schematically showing the device internal structure observed through a transparent member described later. FIG. 2A is a plan view from above of the semiconductor device shown in FIG. 1, and schematically shows the internal structure of the device observed through a transparent member. FIG. 2B is a cross-sectional view taken along the line IIb-IIb in FIG. FIG. 3 is an external perspective view of the transparent member.
For convenience of explanation, the left-right direction, front-rear direction, and up-down direction of the semiconductor device are as illustrated. In FIG. 2A, a sealing member described later is shaded.
　半導体デバイス１は、基板すなわち回路基板１０と、半導体素子２０と、透明部材４０と、封止部材５０とを備えている。
　半導体素子２０は上面２０ａに、例えば、受光領域などの機能領域２１を有し、回路基板１０の上面１０ａ（図２（ｂ）参照）上にダイボンディングされている。半導体素子２０の機能領域２１の周囲には、複数の電極２２が配列されている。回路基板１０の上面１０ａには、半導体素子２０の周囲に端子１１（図２（ｂ）参照）が配列されている。半導体素子２０の各電極２２は、回路基板１０の端子１１にワイヤ２３により電気的に接続されている。電極２２と端子１１との接続は、金、銀、銅、合金などのワイヤを用いたワイヤボンディング法によるものである。回路基板１０の下面１０ｂ（図２（ｂ）参照）には、不図示のビアホールを介して、それぞれ、対応する端子１１に接続された外部端子部１２が形成されている。 The semiconductor device 1 includes a substrate, that is, a circuit board 10, a semiconductor element 20, a transparent member 40, and a sealing member 50.
The semiconductor element 20 has a functional region 21 such as a light receiving region on the upper surface 20a, and is die-bonded on the upper surface 10a of the circuit board 10 (see FIG. 2B). A plurality of electrodes 22 are arranged around the functional region 21 of the semiconductor element 20. On the upper surface 10 a of the circuit board 10, terminals 11 (see FIG. 2B) are arranged around the semiconductor element 20. Each electrode 22 of the semiconductor element 20 is electrically connected to the terminal 11 of the circuit board 10 by a wire 23. The connection between the electrode 22 and the terminal 11 is based on a wire bonding method using a wire such as gold, silver, copper, or alloy. On the lower surface 10b (see FIG. 2B) of the circuit board 10, external terminal portions 12 connected to the corresponding terminals 11 are formed through via holes (not shown).
　半導体素子２０は平面視で矩形形状を有しており、回路基板１０は、平面視で、半導体素子２０より一回り大きい矩形形状を有している。半導体素子２０は、回路基板１０のほぼ中央に配置されており、半導体素子２０の相対向する側辺は、それぞれ、回路基板1０の対応する側辺から等しい長さだけ内側に配置されている。 The semiconductor element 20 has a rectangular shape in plan view, and the circuit board 10 has a rectangular shape that is slightly larger than the semiconductor element 20 in plan view. The semiconductor element 20 is disposed substantially at the center of the circuit board 10, and the opposite sides of the semiconductor element 20 are respectively disposed on the inner side by an equal length from the corresponding side of the circuit board 10.
　回路基板１０の上面１０ａには、図３に示す透明部材４０が配置されている。説明の便宜上、図３では、透明部材の上下を逆さまにして図示している。透明部材４０は、矩形形状の平板である天板４１と、天板４１の四隅で下方に延在する脚部４２とを備える。脚部４２は、天板４１と一体に形成されている。すなわち透明部材４０は一体ものであり、それぞれ別々に形成された天板４１と脚部４２とを組み合わせたものではない。 A transparent member 40 shown in FIG. 3 is disposed on the upper surface 10 a of the circuit board 10. For convenience of explanation, FIG. 3 shows the transparent member upside down. The transparent member 40 includes a top plate 41 that is a rectangular flat plate and leg portions 42 that extend downward at the four corners of the top plate 41. The leg portion 42 is formed integrally with the top plate 41. That is, the transparent member 40 is an integral member, and is not a combination of the top plate 41 and the leg portion 42 formed separately.
　本実施の形態では、平面視における透明部材４０の形状寸法は、回路基板１０の形状寸法と同一である。すなわち、透明部材４０の４つの側面４０ｃ，４０ｄ（図１（ａ）参照）と、回路基板１０の４つの側面１０ｃ，１０ｄ（図１（ａ）参照）とは、それぞれ面一とされている。なお、透明部材４０の側面４０ｃを形成する辺は長辺、側面４０ｄを形成する辺は短辺である。透明部材４０は、透明なガラスまたはアクリル樹脂等の透明な樹脂により形成される。したがって、透明部材４０では、天板４１だけではなく、脚部４２も透明である。図３では、脚部４２は、角柱形状とされている。しかし、脚部４２の形状は、円柱形状あるいは円錐台、角錐台等であってもよい。 In the present embodiment, the shape and size of the transparent member 40 in plan view are the same as the shape and size of the circuit board 10. That is, the four side surfaces 40c and 40d (see FIG. 1A) of the transparent member 40 and the four side surfaces 10c and 10d of the circuit board 10 (see FIG. 1A) are flush with each other. . The side forming the side surface 40c of the transparent member 40 is a long side, and the side forming the side surface 40d is a short side. The transparent member 40 is formed of transparent resin such as transparent glass or acrylic resin. Therefore, in the transparent member 40, not only the top plate 41 but also the leg portion 42 is transparent. In FIG. 3, the leg portion 42 has a prismatic shape. However, the shape of the leg portion 42 may be a cylindrical shape, a truncated cone, a truncated pyramid, or the like.
　天板４１の上面４１ａおよび下面４１ｂは、全面に亘り平坦に形成されている。天板４１の上面４１ａと下面４１ｂとは平行である。すなわち、天板４１は平行平面板であり、正や負の屈折力をもたない。したがって、天板４１は、天板４１を透過する光を収れんさせず、発散させない。脚部４２の下面４２ａは、天板４１の上面４１ａおよび下面４１ｂと平行である。説明の便宜上、脚部４２の側面のうち、隣り合う脚部４２同士で向かい合う側面を内側側面４２ｂと呼ぶ。 The upper surface 41a and the lower surface 41b of the top plate 41 are formed flat over the entire surface. The top surface 41a and the bottom surface 41b of the top plate 41 are parallel. That is, the top plate 41 is a parallel flat plate and has no positive or negative refractive power. Therefore, the top plate 41 does not converge or diverge light transmitted through the top plate 41. The lower surface 42 a of the leg portion 42 is parallel to the upper surface 41 a and the lower surface 41 b of the top plate 41. For convenience of explanation, of the side surfaces of the leg portions 42, the side surface facing the adjacent leg portions 42 is referred to as an inner side surface 42 b.
　各脚部４２の下面４２ａ（図３参照）が不図示の接着剤により回路基板１０の上面１０ａに接着されている。脚部４２の下面４２ａから天板４１の下面４１ｂまでの高さ（上下方向の長さ）、すなわち脚部４２の脚長ｈは、図２（ｂ）に示すように、端子１１と電極２２を接続するワイヤ２３の高さより大きく形成されている。すなわち、天板４１の下面４１ｂは、ワイヤ２３における、半導体素子２０の上面２０ａから突出する最大の高さの部分２３ａの上方に位置している。このように、透明部材４０は、回路基板１０の左右方向および前後方向の中央に配置されて、半導体素子２０全体を覆っている。図２（ｂ）に示すように、半導体素子２０の上面２０ａと透明部材４０の天板４１の下面４１ｂとの間には空隙部Ｓが形成されている。 The lower surface 42a (see FIG. 3) of each leg portion 42 is bonded to the upper surface 10a of the circuit board 10 with an adhesive (not shown). The height (length in the vertical direction) from the lower surface 42a of the leg portion 42 to the lower surface 41b of the top plate 41, that is, the leg length h of the leg portion 42 is determined by connecting the terminal 11 and the electrode 22 as shown in FIG. It is formed larger than the height of the wire 23 to be connected. That is, the lower surface 41 b of the top plate 41 is located above the maximum height portion 23 a of the wire 23 protruding from the upper surface 20 a of the semiconductor element 20. Thus, the transparent member 40 is disposed in the center of the circuit board 10 in the left-right direction and the front-rear direction, and covers the entire semiconductor element 20. As shown in FIG. 2B, a gap S is formed between the upper surface 20 a of the semiconductor element 20 and the lower surface 41 b of the top plate 41 of the transparent member 40.
　図２（ａ）によく示すように、各脚部４２は、平面視において半導体素子２０の外側に配置されている。また、図２（ｂ）に示すように、隣り合う脚部４２の間に、回路基板１０の上面１０ａに形成された端子１１が位置する。 2A, each leg portion 42 is disposed outside the semiconductor element 20 in a plan view. Further, as shown in FIG. 2B, the terminals 11 formed on the upper surface 10 a of the circuit board 10 are located between the adjacent leg portions 42.
　封止部材５０は、回路基板１０の上面１０ａ上に、半導体素子２０の外周を囲むように形成されていて、半導体デバイス１の側面の開口を封止する。具体的には、封止部材５０は、隣り合う脚部４２の間、すなわち、回路基板１０の上面１０ａと、天板４１の下面４１ｂと、脚部４２の内側側面４２ｂとで囲まれた空間を封止する。封止部材５０の形成方法ついては、後述する。 The sealing member 50 is formed on the upper surface 10 a of the circuit board 10 so as to surround the outer periphery of the semiconductor element 20, and seals the opening on the side surface of the semiconductor device 1. Specifically, the sealing member 50 is a space surrounded by the adjacent leg portions 42, that is, the upper surface 10 a of the circuit board 10, the lower surface 41 b of the top plate 41, and the inner side surface 42 b of the leg portion 42. Is sealed. A method for forming the sealing member 50 will be described later.
　図２（ｂ）によく示すように、封止部材５０は、回路基板１０の上面１０ａと天板４１の下面４１ｂとの間に設けられている。封止部材５０は、回路基板１０の端子１１およびワイヤ２３の端子１１側の所定範囲を覆っている。本実施の形態では、半導体素子２０の側面と対向する封止部材５０の内周側面５０ａは、半導体素子２０の側面と接触していないが、半導体素子２０の側面と接触してもよい。本実施の形態では、封止部材５０は、半導体素子２０の上面２０ａに形成された電極２２およびワイヤ２３の電極２２側の所定長を覆っていない。しかし、封止部材５０は、半導体素子２０の機能領域２１を覆わなければ、ワイヤ２３の電極２２側の所定範囲および電極２２を覆うように構成してもよい。
　図１，２に示す半導体デバイス１は、複数個まとめて製造する。回路基板１０、半導体素子２０、透明部材４０は、それぞれ個別に製造する。以下では、複数の透明部材４０を生産性よく、かつ、低コストで製造する方法の一例を説明する。 As well shown in FIG. 2B, the sealing member 50 is provided between the upper surface 10 a of the circuit board 10 and the lower surface 41 b of the top plate 41. The sealing member 50 covers a predetermined range on the terminal 11 side of the terminal 11 of the circuit board 10 and the wire 23. In the present embodiment, the inner peripheral side surface 50 a of the sealing member 50 facing the side surface of the semiconductor element 20 is not in contact with the side surface of the semiconductor element 20, but may be in contact with the side surface of the semiconductor element 20. In the present embodiment, the sealing member 50 does not cover the predetermined length on the electrode 22 side of the electrode 22 and the wire 23 formed on the upper surface 20 a of the semiconductor element 20. However, the sealing member 50 may be configured to cover the electrode 22 and the predetermined range on the electrode 22 side of the wire 23 as long as the functional region 21 of the semiconductor element 20 is not covered.
A plurality of semiconductor devices 1 shown in FIGS. The circuit board 10, the semiconductor element 20, and the transparent member 40 are individually manufactured. Below, an example of the method of manufacturing several transparent member 40 with sufficient productivity and low cost is demonstrated.
［透明部材の製造方法］
　図３および図４（ａ）～（ｃ）を参照して、４つの半導体素子２０を一度に製造する場合の透明部材４０の製造方法を一例として説明する。説明の便宜上、透明部材４０の各部の寸法を図３に示すように定める。すなわち、透明部材４０の高さをＨとし、脚部４２の脚長を上述したようにｈとし、脚部４２の左右方向の寸法をｄ１とし、脚部４２の前後方向の寸法をｄ２とする。左右の脚部４２の内側側面４２ｂ同士の間隔をＷ１とし、前後の脚部４２の内側側面４２ｂ同士の間隔をＷ２とする。 [Method for producing transparent member]
With reference to FIG. 3 and FIGS. 4A to 4C, a method for manufacturing the transparent member 40 in the case where the four semiconductor elements 20 are manufactured at once will be described as an example. For convenience of explanation, dimensions of each part of the transparent member 40 are determined as shown in FIG. That is, the height of the transparent member 40 is H, the leg length of the leg part 42 is h as described above, the dimension of the leg part 42 in the left-right direction is d1, and the dimension of the leg part 42 in the front-rear direction is d2. The interval between the inner side surfaces 42b of the left and right leg portions 42 is W1, and the interval between the inner side surfaces 42b of the front and rear leg portions 42 is W2.
　複数の透明部材４０を形成可能な面積を有する不図示の平板、すなわち矩形の透明部材素材板を準備する。透明部材素材板の厚さは、図３に図示する透明部材４０の高さＨ（上下方向の長さ）と同一である。 A flat plate (not shown) having an area where a plurality of transparent members 40 can be formed, that is, a rectangular transparent member material plate is prepared. The thickness of the transparent member material plate is the same as the height H (vertical length) of the transparent member 40 shown in FIG.
　矩形の透明部材素材板を加工して、図４（ａ）に示すように、前後方向に延在する複数の溝３２を形成する。溝３２の幅は、透明部材４０の左右の脚部４２の内側側面４２ｂ同士の間隔Ｗ１と同じである。換言すれば、溝３２の幅は、透明部材４０の左右の脚部４２の間隙と同じである。溝３２の深さは、脚部４２の脚長ｈと同じである。左右で隣り合う各溝３２は、透明部材４０の脚部４２の左右方向の寸法ｄ１の２倍（２ｄ１）離間するように平行に形成する。つまり、各溝３２は、隣接する溝３２間に長さ２ｄ１の溝未加工部３１が形成されるよう加工される。溝３２は、たとえば切削工具を前後方向に移動させることで形成される。 A rectangular transparent member material plate is processed to form a plurality of grooves 32 extending in the front-rear direction, as shown in FIG. The width of the groove 32 is the same as the interval W <b> 1 between the inner side surfaces 42 b of the left and right leg portions 42 of the transparent member 40. In other words, the width of the groove 32 is the same as the gap between the left and right leg portions 42 of the transparent member 40. The depth of the groove 32 is the same as the leg length h of the leg portion 42. The grooves 32 adjacent to each other on the left and right are formed in parallel so as to be separated by twice (2d1) the dimension d1 in the left-right direction of the leg portion 42 of the transparent member 40. That is, each groove 32 is processed such that a groove unprocessed portion 31 having a length of 2 d 1 is formed between adjacent grooves 32. The groove 32 is formed, for example, by moving the cutting tool in the front-rear direction.
　透明部材素材板の左右方向の両側部において、溝３２は、左右の側面３７から溝３２の端部までの長さが、透明部材４０の脚部４２の左右方向の寸法ｄ１と同一となる位置に設けられる。すなわち、溝３２を形成すると、透明部材素材板の左右両端縁には、幅がｄ１である壁ＫＢＬ，ＫＢＲが形成され、透明部材素材板の中央部にはｄ１×２の幅を有する壁ＫＢＣ、すなわち上述の溝未加工部３１が形成される。 On both side portions of the transparent member material plate in the left-right direction, the groove 32 is positioned such that the length from the left and right side surfaces 37 to the end portion of the groove 32 is the same as the dimension d1 of the leg portion 42 of the transparent member 40 Is provided. That is, when the groove 32 is formed, walls KBL and KBR having a width d1 are formed at the left and right edges of the transparent member material plate, and a wall KBC having a width of d1 × 2 is provided at the center of the transparent member material plate. That is, the above-described groove unprocessed portion 31 is formed.
　次いで、左右の壁ＫＢＬ，ＫＢＲと中央の壁ＫＢＣの前後方向２カ所に、前後方向の長さがＷ２、すなわち幅がＷ２の溝３４を形成すると、図４（ｂ）に示すように、透明部材素材板の表面に９個の突部４２Ｘａ～４２Ｘｄが形成される。溝３４は、たとえば溝３２を形成した場合と同様に、切削工具を左右方向に移動させることで形成される。
　透明部材素材板の四隅の突部４２Ｘａは図３の脚部４２と同様の長さｄ１×ｄ２の矩形断面である。中央部の突部４２Ｘｂは長さ（２×ｄ１）×（２×ｄ２）の矩形断面である。中央の突部４２Ｘｂを前後方向に挟む前後両端の突部４２Ｘｃはｄ２×（２×ｄ１）の矩形断面である。中央の突部４２Ｘｂを左右方向に挟む左右両端の突部４２Ｘｄはｄ１×（２×ｄ２）の矩形断面である。溝３４は以上の各部寸法が設定される位置で形成される。溝３４の幅Ｗ２は、透明部材４０の前後の脚部４２の内側側面４２ｂ同士の間隔Ｗ２である。溝３４の深さは、脚部４２の脚長ｈと同じである。
　このようにして、透明部材素材板から図４（ｂ），（ｃ）に示す透明部材中間集合板３０Ｐが形成される。 Next, when grooves 34 each having a length W2 in the front-rear direction, that is, a width W2, are formed at two positions in the front-rear direction of the left and right walls KBL, KBR and the central wall KBC, as shown in FIG. Nine protrusions 42Xa to 42Xd are formed on the surface of the member material plate. The groove 34 is formed by moving the cutting tool in the left-right direction, for example, similarly to the case where the groove 32 is formed.
The protrusions 42Xa at the four corners of the transparent member material plate are rectangular cross sections having the same length d1 × d2 as the leg portions 42 in FIG. The central protrusion 42Xb has a rectangular cross section of length (2 × d1) × (2 × d2). The protrusions 42Xc at the front and rear ends sandwiching the central protrusion 42Xb in the front-rear direction have a rectangular cross section of d2 × (2 × d1). The left and right protrusions 42Xd sandwiching the central protrusion 42Xb in the left-right direction have a rectangular cross section of d1 × (2 × d2). The groove 34 is formed at a position where the above-described dimensions are set. The width W <b> 2 of the groove 34 is an interval W <b> 2 between the inner side surfaces 42 b of the front and rear legs 42 of the transparent member 40. The depth of the groove 34 is the same as the leg length h of the leg portion 42.
In this way, the transparent member intermediate assembly plate 30P shown in FIGS. 4B and 4C is formed from the transparent member material plate.
　なお、左右の壁ＫＢＬ，ＫＢＲの幅をｄ１より大きくしておき、溝３２を形成した後、壁ＫＢＬ，ＫＢＲの幅がｄ１となるように、左右の側面３７を切削してもよい。また、前後両端の突部４２Ｘｃの前後方向の長さをｄ２より大きくしておき、溝３４を形成した後、突部４２Ｘｃの前後方向の長さがｄ２となるように、前後の側面３７を切削してもよい。 It should be noted that the left and right side surfaces 37 may be cut so that the width of the walls KBL and KBR is d1 after the width of the left and right walls KBL and KBR is made larger than d1 and the groove 32 is formed. In addition, the length in the front-rear direction of the protrusions 42Xc at both front and rear ends is made larger than d2, and after forming the groove 34, the front and rear side surfaces 37 are arranged so that the length in the front-rear direction of the protrusions 42Xc is d2. You may cut.
　透明部材中間集合板３０Ｐを形成した後、図４（ｃ）において２点鎖線で示した切断位置で透明部材中間集合板３０Ｐを切断する。この切断位置は、隣り合う溝３２同士の中間位置、および、隣り合う溝３４同士の中間位置である。これにより、複数の透明部材４０を効率的に作製することができる。 After forming the transparent member intermediate assembly plate 30P, the transparent member intermediate assembly plate 30P is cut at a cutting position indicated by a two-dot chain line in FIG. This cutting position is an intermediate position between adjacent grooves 32 and an intermediate position between adjacent grooves 34. Thereby, the some transparent member 40 can be produced efficiently.
　上記では、透明部材素材板に溝３２，３４をそれぞれ２つ形成する場合で例示した。これは、４個の半導体デバイスに使用する４個の透明部材４０を一度に製造する一例である。さらに、透明部材素材板に形成する溝３２，３４の数を増やしてもよい。また、透明部材素材板に形成する溝３２を１つだけとし、隣り合う溝３４同士の中間位置で切断することにより、透明部材４０を得るようにしてもよい。これは、２個の半導体デバイスに使用する２個の透明部材４０を一度に製造する一例である。
　上記透明部材４０の製造方法は、透明部材４０を、ガラスにより形成する場合に適する。透明部材４０を樹脂により形成する場合には、図４（ｂ）に示す、溝３２，３４が形成された透明部材中間集合板３０Ｐをモールド法等により形成してもよい。 In the above, the case where two grooves 32 and 34 are formed on the transparent member material plate is illustrated. This is an example of manufacturing four transparent members 40 used for four semiconductor devices at a time. Furthermore, you may increase the number of the grooves 32 and 34 formed in a transparent member raw material board. Alternatively, only one groove 32 may be formed on the transparent member material plate, and the transparent member 40 may be obtained by cutting at an intermediate position between adjacent grooves 34. This is an example of manufacturing two transparent members 40 used for two semiconductor devices at a time.
The manufacturing method of the said transparent member 40 is suitable when forming the transparent member 40 with glass. When the transparent member 40 is formed of resin, the transparent member intermediate assembly plate 30P in which the grooves 32 and 34 shown in FIG. 4B are formed may be formed by a molding method or the like.
［半導体デバイスの製造方法］
　図５～９を参照して、半導体デバイスの製造方法を説明する。
　複数の半導体デバイス形成領域１ｒを形成するための素材回路基板（素材基板）１０Ｐを準備する。図５では、１つ１つの半導体デバイス形成領域を符号１ｒで示している。素材回路基板１０Ｐの各半導体デバイス形成領域１ｒ内には、端子１１および端子１１にビアホールを介して接続された外部端子部１２（図２（ｂ）参照）が形成されている。
　なお、以下では、素材回路基板１０Ｐ上に、左右方向４×前後方向３個の半導体デバイス１を形成する場合として例示するが、素材回路基板１０Ｐ上には、これ以上またはこれ以下の数の半導体デバイス１を形成することが可能である。各半導体デバイス形成領域１ｒの平面形状は、半導体デバイス１を平面視した大きさおよび形状と同一である。すなわち、各半導体デバイス形成領域１ｒは、左右方向に延在する２つの長辺と、前後方向に延在する２つの短辺とで囲まれた領域である。 [Method for Manufacturing Semiconductor Device]
A method for manufacturing a semiconductor device will be described with reference to FIGS.
A material circuit board (material substrate) 10P for forming a plurality of semiconductor device forming regions 1r is prepared. In FIG. 5, each semiconductor device formation region is denoted by reference numeral 1r. In each semiconductor device formation region 1r of the material circuit board 10P, the terminal 11 and the external terminal portion 12 (see FIG. 2B) connected to the terminal 11 via a via hole are formed.
In the following, a case where four semiconductor devices 1 in the left and right direction × 3 in the front and rear direction are formed on the material circuit board 10P will be described as an example, but more or less semiconductors are formed on the material circuit board 10P. The device 1 can be formed. The planar shape of each semiconductor device formation region 1r is the same as the size and shape of the semiconductor device 1 in plan view. That is, each semiconductor device formation region 1r is a region surrounded by two long sides extending in the left-right direction and two short sides extending in the front-rear direction.
　図５に示すように、各半導体デバイス形成領域１ｒに、半導体素子２０をダイボンディングして素材基板、すなわち素材回路基板１０Ｐに半導体素子２０を固定する。そして、ワイヤボンディングにより、半導体素子２０の電極２２と素材回路基板１０Ｐの半導体デバイス形成領域１ｒに形成された端子１１とを接続する。 As shown in FIG. 5, the semiconductor element 20 is die-bonded to each semiconductor device formation region 1r to fix the semiconductor element 20 to the material substrate, that is, the material circuit board 10P. Then, the electrodes 22 of the semiconductor element 20 and the terminals 11 formed in the semiconductor device formation region 1r of the material circuit board 10P are connected by wire bonding.
　図６に示すように、各半導体デバイス形成領域１ｒ内に、透明部材４０を固定する。透明部材４０は、不図示の接着剤により、脚部４２の下面４２ａ（図３参照）が素材回路基板１０Ｐに接着されて固定される。前後および左右で隣り合う透明部材４０同士の間には、隙間が設けられている。 As shown in FIG. 6, the transparent member 40 is fixed in each semiconductor device formation region 1r. The transparent member 40 is fixed by adhering the lower surface 42a (see FIG. 3) of the leg portion 42 to the material circuit board 10P with an adhesive (not shown). A gap is provided between the transparent members 40 adjacent to each other in the front-rear direction and the left-right direction.
　図７に示すように、ディスペンサを前後方向に移動しながら、左右方向に隣接する半導体デバイス形成領域１ｒ間、すなわち左右で隣り合う透明部材４０同士の間、および左端側と右端側の半導体デバイス形成領域１ｒの一側縁側に、液状の樹脂材料５０ｐを注入する。樹脂材料５０ｐは、固化する前の封止部材５０である。樹脂材料５０ｐは、素材回路基板１０Ｐの上面と、天板４１の下面４１ｂ（図２（ｂ）参照）と、脚部４２の内側側面４２ｂ（図２（ｂ）参照）とに濡れ広がりながら、透明部材４０の短辺の外方から半導体デバイス形成領域１ｒの内方側に向かって流動する。 As shown in FIG. 7, while moving the dispenser in the front-rear direction, semiconductor device formation between the semiconductor device forming regions 1r adjacent in the left-right direction, that is, between the transparent members 40 adjacent in the left-right direction, and the left end side and the right end side is formed. A liquid resin material 50p is injected into one side edge of the region 1r. The resin material 50p is the sealing member 50 before being solidified. The resin material 50p wets and spreads on the upper surface of the material circuit board 10P, the lower surface 41b of the top plate 41 (see FIG. 2B), and the inner side surface 42b of the leg portion 42 (see FIG. 2B). It flows from the outer side of the short side of the transparent member 40 toward the inner side of the semiconductor device forming region 1r.
　図８に示すように、ディスペンサを左右方向に移動しながら、前後方向に隣接する半導体デバイス形成領域１ｒ間、すなわち前後で隣り合う透明部材４０同士の間、および前端側と後端側の半導体デバイス形成領域１ｒの一側縁側に、液状の樹脂材料５０ｐを注入する。樹脂材料５０ｐは、素材回路基板１０Ｐの上面と、天板４１の下面４１ｂと、脚部４２の内側側面４２ｂとに濡れ広がりながら、透明部材４０の長辺の外方から半導体デバイス形成領域１ｒの内方側に向かって流動する。 As shown in FIG. 8, while moving the dispenser in the left-right direction, between the semiconductor device forming regions 1r adjacent in the front-rear direction, that is, between the transparent members 40 adjacent in the front-rear direction, and the semiconductor devices on the front end side and the rear end side A liquid resin material 50p is injected into one side edge of the formation region 1r. The resin material 50p spreads over the upper surface of the material circuit board 10P, the lower surface 41b of the top plate 41, and the inner side surface 42b of the leg portion 42, and extends from the outside of the long side of the transparent member 40 to the semiconductor device forming region 1r. Flows inward.
　このように樹脂材料５０ｐを注入することで、半導体素子２０の上面２０ａと透明部材４０の天板４１の下面４１ｂとの間に空隙部Ｓ（図２（ｂ）参照）が形成される。
　なお、樹脂材料５０ｐとしては、例えば、エポキシ樹脂、シリコーン樹脂を用いることができる。樹脂中にガラス繊維などのフィラを分散してもよい。 By injecting the resin material 50p in this way, a gap S (see FIG. 2B) is formed between the upper surface 20a of the semiconductor element 20 and the lower surface 41b of the top plate 41 of the transparent member 40.
For example, an epoxy resin or a silicone resin can be used as the resin material 50p. A filler such as glass fiber may be dispersed in the resin.
　樹脂材料５０ｐの注入が完了したら、樹脂材料５０ｐを熱や紫外線により、硬化させる。
　そして、図９に示すように、二点鎖線で示す切断線の位置で、素材回路基板１０Ｐを左右方向および前後方向に切断する。図９で二点鎖線で示した切断線は、各半導体デバイス形成領域１ｒの境界線と重なる。この切断によって、封止部材５０の外周側面が回路基板１０の４つの側面とそれぞれ面一となる。上述した工程によって、図１に示す半導体デバイス１を複数形成できる。 When the injection of the resin material 50p is completed, the resin material 50p is cured by heat or ultraviolet rays.
Then, as shown in FIG. 9, the material circuit board 10 </ b> P is cut in the left-right direction and the front-back direction at the position of the cutting line indicated by the two-dot chain line. The cutting line indicated by the two-dot chain line in FIG. 9 overlaps the boundary line of each semiconductor device formation region 1r. By this cutting, the outer peripheral side surface of the sealing member 50 is flush with the four side surfaces of the circuit board 10. A plurality of semiconductor devices 1 shown in FIG. 1 can be formed by the steps described above.
　上記一実施の形態によれば、下記の効果を奏する。
（１）半導体素子２０の上部を覆う透明な部材は、回路基板１０の上面１０ａに載置される複数の脚部４２が一体に形成された透明部材４０である。これにより、半導体素子２０の上部を覆う透明部材４０の構造を簡略化できるので、半導体デバイス１のコスト増を抑制できる。また、回路基板１０の上面１０ａの四隅にスペーサを配置し、当該スペーサの上に平板状の部材を載置することによって半導体デバイス１を製造する場合と比べて、透明部材４０の位置決めおよび回路基板１０への取り付けを容易、かつ、能率的に行うことができる。 According to the one embodiment, the following effects are obtained.
(1) The transparent member that covers the upper portion of the semiconductor element 20 is the transparent member 40 in which a plurality of leg portions 42 that are placed on the upper surface 10a of the circuit board 10 are integrally formed. Thereby, since the structure of the transparent member 40 which covers the upper part of the semiconductor element 20 can be simplified, the increase in the cost of the semiconductor device 1 can be suppressed. Further, compared with the case where the semiconductor device 1 is manufactured by placing spacers at the four corners of the upper surface 10a of the circuit board 10 and placing flat members on the spacers, the positioning of the transparent member 40 and the circuit board are compared. 10 can be easily and efficiently attached.
（２）透明部材４０は、脚部４２が天板４１と一体に形成されている。このため、天板４１部分に相当する部材が、当該部材とは異なる部材である４つのスペーサで支持される構造に比し、４つのスペーサのそれぞれの位置合わせを行う必要がないので、組み立て工数を削減でき、製造コストを低減できる。 (2) In the transparent member 40, the leg portion 42 is formed integrally with the top plate 41. For this reason, it is not necessary to align each of the four spacers as compared with a structure in which the member corresponding to the top plate 41 portion is supported by four spacers that are members different from the member. The manufacturing cost can be reduced.
（３）半導体デバイス１の製造にあたり、半導体デバイス１がそれぞれ形成される複数の半導体デバイス形成領域１ｒを上面に有し、各半導体デバイス形成領域１ｒ内に端子１１が形成された素材回路基板（素材基板）１０Ｐを準備した。そして、素材回路基板１０Ｐの各半導体デバイス形成領域１ｒ内に、上面２０ａに電極２２を有する半導体素子２０を配置した。半導体素子２０それぞれの電極２２と素材回路基板１０Ｐに形成された端子１１をワイヤボンディングにより接続した。それぞれが複数の脚部４２を有し、半導体素子２０の上部を覆う複数の透明部材４０を、素材回路基板１０Ｐの各半導体デバイス形成領域１ｒ内に相互に離間して配置した。素材回路基板１０Ｐの上面と、素材回路基板１０Ｐの上面と対向する透明部材４０の下面、すなわち天板４１の下面４１ｂとの間に封止部材５０を設けた。そして、素材回路基板１０Ｐを半導体デバイス形成領域１ｒ毎に分離した。
　これにより、透明部材４０の位置決めおよび素材回路基板１０Ｐへの取り付けを容易、かつ、能率的に行うことができ、半導体デバイス１の製造工程を簡略化できる。また、半導体デバイス１の製造コストの増加を抑制できる。 (3) In manufacturing the semiconductor device 1, a material circuit board (material) having a plurality of semiconductor device forming regions 1 r on which the semiconductor devices 1 are respectively formed on the upper surface, and terminals 11 are formed in each semiconductor device forming region 1 r Substrate) 10P was prepared. And the semiconductor element 20 which has the electrode 22 on the upper surface 20a was arrange | positioned in each semiconductor device formation area 1r of the raw circuit board 10P. The electrodes 22 of the semiconductor elements 20 and the terminals 11 formed on the material circuit board 10P were connected by wire bonding. A plurality of transparent members 40 each having a plurality of leg portions 42 and covering the upper portion of the semiconductor element 20 are arranged in the respective semiconductor device forming regions 1r of the material circuit board 10P so as to be separated from each other. The sealing member 50 is provided between the upper surface of the material circuit board 10P and the lower surface of the transparent member 40 facing the upper surface of the material circuit board 10P, that is, the lower surface 41b of the top plate 41. Then, the material circuit board 10P was separated for each semiconductor device formation region 1r.
Thereby, positioning of the transparent member 40 and attachment to the material circuit board 10P can be performed easily and efficiently, and the manufacturing process of the semiconductor device 1 can be simplified. In addition, an increase in manufacturing cost of the semiconductor device 1 can be suppressed.
（４）素材回路基板１０Ｐの上面と、素材回路基板１０Ｐの上面と対向する透明部材４０の下面、すなわち天板４１の下面４１ｂとの間に封止部材５０を設ける工程では、素材回路基板１０Ｐの各半導体デバイス形成領域１ｒ内に相互に離間して配置された透明部材４０同士の間から樹脂材料５０ｐを注入して、素材回路基板１０Ｐの上面と、透明部材４０の下面、すなわち天板４１の下面４１ｂと、脚部４２の内側側面４２ｂとで囲まれた開口を封止するようにした。これにより、複数の半導体デバイス１における封止部材５０による封止を能率的に行うことができ、半導体デバイス１の製造工程を簡略化できる。また、半導体デバイス１の製造コストの増加を抑制できる。 (4) In the step of providing the sealing member 50 between the upper surface of the material circuit board 10P and the lower surface of the transparent member 40 facing the upper surface of the material circuit board 10P, that is, the lower surface 41b of the top plate 41, the material circuit board 10P. The resin material 50p is injected from between the transparent members 40 spaced apart from each other in each semiconductor device forming region 1r, and the upper surface of the material circuit board 10P and the lower surface of the transparent member 40, that is, the top plate 41 The opening surrounded by the lower surface 41b and the inner side surface 42b of the leg portion 42 is sealed. Thereby, the sealing by the sealing member 50 in the plurality of semiconductor devices 1 can be efficiently performed, and the manufacturing process of the semiconductor device 1 can be simplified. In addition, an increase in manufacturing cost of the semiconductor device 1 can be suppressed.
（５）透明部材４０の製造に当たり、複数の透明部材４０を形成可能な面積を有する透明部材素材板を準備した。そして、透明部材素材板に、脚部４２の間隙分の幅Ｗ１を有する溝３２を形成した。透明部材素材板に、脚部４２の間隙分の幅Ｗ２を有し、溝３２と直交する溝３４を形成した。そして、この透明部材素材板を、溝３２，３４の延在方向に沿って切断した。すなわち、透明部材４０を製造する工程は、複数の透明部材４０を形成可能な面積を有する透明部材素材板を準備する工程と、切削工具を一の方向に移動させることで、透明部材素材板に、脚部４２の間隙分の幅Ｗ１を有する溝３２を形成する工程と、切削工具を一の方向と直交する方向に移動させることで、透明部材素材板における溝３２が形成されない溝未加工部３１に対して、脚部４２の間隙分の幅Ｗ２を有し、溝３２と直交する溝３４を形成する工程と、透明部材素材板を、溝３２，３４の延在方向に沿って切断する工程とを含む。
　これにより、透明部材４０を安価に製造でき、半導体デバイス１の製造コストの増加を抑制できる。また、脚部４２が天板４１と一体に形成されるので、透明部材４０の強度が向上する。したがって、天板４１の厚さを薄くすることができるので、半導体デバイス１を小型化できる。 (5) In manufacturing the transparent member 40, a transparent member material plate having an area where a plurality of transparent members 40 can be formed was prepared. And the groove | channel 32 which has the width W1 for the clearance gap between the leg parts 42 was formed in the transparent member raw material board. A groove 34 having a width W2 corresponding to the gap between the leg portions 42 and orthogonal to the groove 32 was formed on the transparent member material plate. The transparent member material plate was cut along the extending direction of the grooves 32 and 34. That is, the process of manufacturing the transparent member 40 includes the steps of preparing a transparent member material plate having an area where a plurality of transparent members 40 can be formed, and moving the cutting tool in one direction to form a transparent member material plate. The process of forming the groove | channel 32 which has the width W1 for the gap | interval of the leg part 42, and the groove | channel unprocessed part in which the groove | channel 32 in a transparent member raw material board is not formed by moving a cutting tool in the direction orthogonal to one direction 31, a step of forming a groove 34 having a width W2 corresponding to the gap of the leg portion 42 and orthogonal to the groove 32, and cutting the transparent member material plate along the extending direction of the grooves 32 and 34. Process.
Thereby, the transparent member 40 can be manufactured at low cost, and the increase in the manufacturing cost of the semiconductor device 1 can be suppressed. Moreover, since the leg part 42 is formed integrally with the top plate 41, the strength of the transparent member 40 is improved. Therefore, since the thickness of the top plate 41 can be reduced, the semiconductor device 1 can be miniaturized.
［変形例］
（１）上述の説明では、透明部材４０の４つの側面４０ｃ，４０ｄ（図１（ａ）参照）と、回路基板１０の４つの側面１０ｃ，１０ｄ（図１（ａ）参照）とが、それぞれ面一とされている。すなわち、上述の説明では、平面視における透明部材４０の形状寸法が、回路基板１０の形状寸法と同一である。しかし、本発明はこれに限定されない。たとえば、図１０（ａ）の斜視図で示した半導体デバイス１Ａのように、平面視における透明部材４０の寸法が、回路基板１０の寸法よりも小さくてもよい。すなわち、平面視における透明部材４０の寸法が、半導体デバイス形成領域１ｒ（図５参照）の寸法よりも小さくてもよい。
　この場合には、図１０（ａ）に示すように、封止部材５０の上面が、透明部材４０の天板４１よりも低くてもよく、図１０（ｂ）の斜視図で示した半導体デバイス１Ｂのように、封止部材５０の上面が、透明部材４０の天板４１と面一であってもよい。 [Modification]
(1) In the above description, the four side surfaces 40c and 40d of the transparent member 40 (see FIG. 1A) and the four side surfaces 10c and 10d of the circuit board 10 (see FIG. 1A) are respectively It is considered to be the same. That is, in the above description, the shape and size of the transparent member 40 in plan view are the same as the shape and size of the circuit board 10. However, the present invention is not limited to this. For example, the size of the transparent member 40 in plan view may be smaller than the size of the circuit board 10 as in the semiconductor device 1A shown in the perspective view of FIG. That is, the dimension of the transparent member 40 in plan view may be smaller than the dimension of the semiconductor device formation region 1r (see FIG. 5).
In this case, as shown in FIG. 10A, the upper surface of the sealing member 50 may be lower than the top plate 41 of the transparent member 40, and the semiconductor device shown in the perspective view of FIG. As in 1B, the top surface of the sealing member 50 may be flush with the top plate 41 of the transparent member 40.
　また、図１１（ａ），（ｂ）に示すように、封止部材５０の上面が、透明部材４０の天板４１よりも高くてもよい。この場合には、図１１（ａ）の斜視図で示した半導体デバイス１Ｃのように、封止部材５０が、透明部材４０の天板４１を覆わないようにしてもよく、図１１（ｂ）の斜視図で示した半導体デバイス１Ｄのように、封止部材５０が、透明部材４０の天板４１の上面の一部、たとえば天板４１の上面の周縁を覆うようにしてもよい。なお、図１１（ｂ）に示す場合において、たとえば半導体素子２０の機能領域２１（図１（ｂ）参照）が受光領域等であれば、機能領域２１への入射光を遮らないように封止部材５０を設ける必要がある。 Further, as shown in FIGS. 11A and 11B, the upper surface of the sealing member 50 may be higher than the top plate 41 of the transparent member 40. In this case, like the semiconductor device 1C shown in the perspective view of FIG. 11A, the sealing member 50 may not cover the top plate 41 of the transparent member 40. FIG. As in the semiconductor device 1D shown in the perspective view, the sealing member 50 may cover a part of the top surface of the top plate 41 of the transparent member 40, for example, the periphery of the top surface of the top plate 41. In the case shown in FIG. 11B, for example, if the functional region 21 (see FIG. 1B) of the semiconductor element 20 is a light receiving region or the like, sealing is performed so as not to block incident light to the functional region 21. The member 50 needs to be provided.
（２）上述の説明では、半導体素子２０の機能領域２１を受光領域として例示したが、半導体素子２０が撮像素子であってもよい。また、本発明は、発光素子等、受光以外の他の機能を有する半導体素子２０、たとえば加速度センサ等に対しても適用することができる。 (2) In the above description, the functional area 21 of the semiconductor element 20 is exemplified as the light receiving area. However, the semiconductor element 20 may be an imaging element. The present invention can also be applied to a semiconductor element 20 having a function other than light reception, such as a light emitting element, such as an acceleration sensor.
（３）上述の説明では、空隙部Ｓが封止部材５０で密閉されるように構成したが、本発明はこれに限定されない。たとえば、ＭＥＭＳ圧力センサのように、機能領域２１が半導体デバイス１の外部雰囲気に暴露される必要がある場合には、空隙部Ｓが封止部材５０で密閉されていなくてもよい。また、透明部材４０の一部に開口等を設けることで、機能領域２１が半導体デバイス１の外部雰囲気に暴露されるようにしてもよい。 (3) In the above description, the gap S is sealed with the sealing member 50, but the present invention is not limited to this. For example, when the functional region 21 needs to be exposed to the external atmosphere of the semiconductor device 1 like a MEMS pressure sensor, the gap portion S may not be sealed with the sealing member 50. Further, the functional region 21 may be exposed to the external atmosphere of the semiconductor device 1 by providing an opening or the like in a part of the transparent member 40.
（４）上述の説明では、半導体素子２０は、４つの側辺に電極２２が配列されたクワッド型として説明した。しかし、本発明は、相対向する一対の側辺のみに電極２２が配列されたデュアル型の半導体素子２０に対しても適用することができる。 (4) In the above description, the semiconductor element 20 has been described as a quad type in which the electrodes 22 are arranged on four sides. However, the present invention can also be applied to the dual-type semiconductor element 20 in which the electrodes 22 are arranged only on a pair of opposite sides.
　その他、本発明の半導体デバイスは、発明の趣旨の範囲内において、種々、変形して構成することが可能であり、要は、半導体素子の上部を覆う透明な平板と、平板と基板の上面との間に所定の空隙を設けるための複数の脚部とが一体に形成された透明部材と、基板の上面と、その面と対向する透明部材の下面との間で、半導体素子の周囲を囲んで設けられた封止部材が設けられたものであればよい。 In addition, the semiconductor device of the present invention can be variously modified and configured within the scope of the invention. In short, a transparent flat plate covering the upper part of the semiconductor element, a flat plate, and an upper surface of the substrate. Surrounding the periphery of the semiconductor element is a transparent member integrally formed with a plurality of legs for providing a predetermined gap between the upper surface of the substrate, and an upper surface of the substrate and a lower surface of the transparent member facing the surface. What is necessary is just to be provided with the sealing member provided in.
　次の優先権基礎出願の開示内容は引用文としてここに組み込まれる。
　日本国特許出願２０１４年第２５２０６５号（２０１４年１２月１２日出願） The disclosure of the following priority application is hereby incorporated by reference.
Japanese Patent Application 2014-252065 (filed on December 12, 2014)
１、１Ａ～１Ｄ；半導体デバイス、１ｒ；半導体デバイス形成領域、１０；回路基板（基板）、１０Ｐ；素材回路基板（素材基板）、１１；端子、２０；半導体素子、２２；電極、３０Ｐ；透明部材中間集合板、３２，３４；溝、４０；透明部材、４１；天板、４２；脚部、５０；封止部材、５０ｐ；樹脂材料、Ｓ；空隙部 DESCRIPTION OF SYMBOLS 1, 1A-1D; Semiconductor device, 1r; Semiconductor device formation area, 10: Circuit board (substrate), 10P; Material circuit board (material substrate), 11; Terminal, 20; Semiconductor element, 22; Electrode, 30P; Member intermediate assembly plate, 32, 34; groove, 40; transparent member, 41; top plate, 42; leg portion, 50; sealing member, 50p; resin material, S;

Claims (9)

  1. 　上面に端子が設けられた基板と、
    　前記基板の上面に配置され、前記基板の前記端子に電気的に接続された電極を有する半導体素子と、
    　前記半導体素子の上部を覆う透明な平板と、前記平板と前記基板の上面との間に所定の空隙を設けるための複数の脚部とが一体に形成された透明部材と、
    　前記基板の上面と、前記基板の上面と対向する前記透明部材の下面との間で、前記半導体素子の周囲を囲んで設けられた封止部材と、を備える半導体デバイス。     A substrate provided with terminals on the upper surface;
    A semiconductor element having an electrode disposed on an upper surface of the substrate and electrically connected to the terminal of the substrate;
    A transparent flat plate covering the upper part of the semiconductor element, and a transparent member integrally formed with a plurality of legs for providing a predetermined gap between the flat plate and the upper surface of the substrate;
    A semiconductor device comprising: an upper surface of the substrate; and a sealing member provided surrounding the semiconductor element between the lower surface of the transparent member facing the upper surface of the substrate.
  2. 　請求項１に記載の半導体デバイスにおいて、
    　前記半導体素子の前記電極は、前記半導体素子の上面に設けられ、前記半導体素子の前記電極と前記基板の前記端子とは、ワイヤにより電気的に接続されている半導体デバイス。     The semiconductor device according to claim 1,
    The electrode of the semiconductor element is provided on an upper surface of the semiconductor element, and the electrode of the semiconductor element and the terminal of the substrate are electrically connected by a wire.
  3. 　請求項１または請求項２に記載の半導体デバイスにおいて、
    　前記脚部は、前記基板の上面に接着されている半導体デバイス。     The semiconductor device according to claim 1 or claim 2,
    The leg is a semiconductor device bonded to the upper surface of the substrate.
  4. 　請求項１から３のいずれか１項に記載の半導体デバイスにおいて、
    　前記半導体素子は矩形形状を有し、
    　前記基板は、前記半導体素子より大きい矩形形状を有し、
    　前記透明部材は、前記半導体素子より大きい矩形形状を有し、
    　前記半導体素子は、前記基板の中央部に、前記半導体素子の各側辺を前記基板の各側辺の内側にして配置され、
    　前記脚部は、前記透明部材の四隅に設けられ、
    　前記封止部材は、隣り合う前記脚部の間を封止する半導体デバイス。     The semiconductor device according to any one of claims 1 to 3,
    The semiconductor element has a rectangular shape,
    The substrate has a rectangular shape larger than the semiconductor element;
    The transparent member has a rectangular shape larger than the semiconductor element,
    The semiconductor element is disposed in a central portion of the substrate with each side of the semiconductor element inside each side of the substrate.
    The leg portions are provided at the four corners of the transparent member,
    The sealing member is a semiconductor device that seals between adjacent leg portions.
  5. 　請求項３または請求項４に記載の半導体デバイスにおいて、
    　前記封止部材の外周側面は、前記基板の４つの側辺のそれぞれに面一である半導体デバイス。     The semiconductor device according to claim 3 or claim 4,
    The outer peripheral side surface of the sealing member is a semiconductor device that is flush with each of the four side sides of the substrate.
  6. 　請求項１から５のいずれか１項に記載の半導体デバイスにおいて、
    　前記透明部材は、上面および下面が互いに平行な平面である半導体デバイス。     The semiconductor device according to any one of claims 1 to 5,
    The transparent member is a semiconductor device in which an upper surface and a lower surface are planes parallel to each other.
  7. 　半導体デバイスがそれぞれ形成される複数の半導体デバイス形成領域を上面に有し、各半導体デバイス形成領域内に端子が形成された素材基板を準備する工程と、
    　前記素材基板の前記各半導体デバイス形成領域内に、上面に電極を有する半導体素子を配置する工程と、
    　前記半導体素子それぞれの前記電極と前記素材基板に形成された前記端子をワイヤボンディングする工程と、
    　複数の脚部を有し、前記半導体素子の上部を覆う透明部材を、前記素材基板の前記各半導体デバイス形成領域内に配置し、前記複数の半導体デバイス形成領域のそれぞれに配置された前記透明部材が相互に離間した工程と、
    　前記素材基板の上面と、前記素材基板の上面と対向する前記透明部材の下面との間に封止部材を設ける工程と、
    　前記素材基板を前記各半導体デバイス形成領域毎に分離する工程と、を含む半導体デバイスの製造方法。     A step of preparing a material substrate having a plurality of semiconductor device formation regions on which the semiconductor devices are respectively formed on the upper surface and terminals are formed in each semiconductor device formation region;
    A step of disposing a semiconductor element having an electrode on the upper surface in each semiconductor device formation region of the material substrate;
    Wire bonding the electrodes of each of the semiconductor elements and the terminals formed on the material substrate;
    A transparent member having a plurality of legs and covering an upper portion of the semiconductor element is disposed in each semiconductor device formation region of the material substrate, and the transparent member is disposed in each of the plurality of semiconductor device formation regions. Processes separated from each other,
    Providing a sealing member between the upper surface of the material substrate and the lower surface of the transparent member facing the upper surface of the material substrate;
    Separating the material substrate for each semiconductor device formation region.
  8. 　請求項７に記載の半導体デバイスの製造方法において、
    　前記素材基板の上面と、前記素材基板の上面と対向する前記透明部材の下面との間に封止樹脂を設ける工程では、前記素材基板の前記複数の半導体デバイス形成領域のそれぞれに配置されて相互に離間した前記透明部材同士の間から前記封止部材を注入して、前記素材基板の上面と、前記透明部材の下面と、前記脚部の側面とで囲まれた開口を封止する半導体デバイスの製造方法。     In the manufacturing method of the semiconductor device according to claim 7,
    In the step of providing the sealing resin between the upper surface of the material substrate and the lower surface of the transparent member facing the upper surface of the material substrate, the sealing resin is disposed in each of the plurality of semiconductor device forming regions of the material substrate and mutually A semiconductor device that injects the sealing member from between the transparent members separated from each other to seal an opening surrounded by the upper surface of the material substrate, the lower surface of the transparent member, and the side surface of the leg portion Manufacturing method.
  9. 　請求項７または請求項８に記載の半導体デバイスの製造方法において、
    　複数の透明部材を形成可能な面積を有する透明部材素材板を準備する工程と、
    　切削工具を一の方向に移動させることで、前記透明部材素材板に、前記脚部の間隙分の幅を有する第１の溝を形成する工程と、
    　前記切削工具を前記一の方向と直交する方向に移動させることで、前記透明部材素材板における前記第１の溝が形成されない未加工部に対して、前記脚部の間隙分の幅を有し、前記第１の溝と直交する第２の溝を形成する工程と、
    　前記透明部材素材板を、前記溝の延在方向に沿って切断する工程と、を含み前記透明部材を製造する工程をさらに備える半導体デバイスの製造方法。     In the manufacturing method of the semiconductor device according to claim 7 or 8,
    Preparing a transparent member material plate having an area capable of forming a plurality of transparent members;
    Forming a first groove having a width corresponding to the gap between the legs in the transparent member material plate by moving the cutting tool in one direction;
    By moving the cutting tool in a direction perpendicular to the one direction, a width corresponding to a gap of the leg portion is formed with respect to an unprocessed portion where the first groove is not formed in the transparent member material plate. Forming a second groove orthogonal to the first groove;
    Cutting the transparent member material plate along the extending direction of the groove, and further comprising the step of manufacturing the transparent member.
PCT/JP2015/081069 2014-12-12 2015-11-04 Semiconductor device and method for manufacturing same WO2016092987A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278726A (en) * 2005-03-29 2006-10-12 Sharp Corp Semiconductor device module and its manufacturing method
JP2008035014A (en) * 2006-07-27 2008-02-14 Fujifilm Corp Imaging device
JP2014120635A (en) * 2012-12-18 2014-06-30 Seiko Instruments Inc Optical device and method of manufacturing optical device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278726A (en) * 2005-03-29 2006-10-12 Sharp Corp Semiconductor device module and its manufacturing method
JP2008035014A (en) * 2006-07-27 2008-02-14 Fujifilm Corp Imaging device
JP2014120635A (en) * 2012-12-18 2014-06-30 Seiko Instruments Inc Optical device and method of manufacturing optical device

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