WO2016090959A1 - 开关电源双脉冲脉宽限制电路及其实现方法 - Google Patents

开关电源双脉冲脉宽限制电路及其实现方法 Download PDF

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Publication number
WO2016090959A1
WO2016090959A1 PCT/CN2015/088098 CN2015088098W WO2016090959A1 WO 2016090959 A1 WO2016090959 A1 WO 2016090959A1 CN 2015088098 W CN2015088098 W CN 2015088098W WO 2016090959 A1 WO2016090959 A1 WO 2016090959A1
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Prior art keywords
circuit
pulse
pin
pulse width
electronic switch
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PCT/CN2015/088098
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English (en)
French (fr)
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姚敦平
范家闩
廖仕明
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深圳市科陆电子科技股份有限公司
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0029—Circuits or arrangements for limiting the slope of switching signals, e.g. slew rate

Definitions

  • the invention belongs to the technical field of pulse width control of a switching power supply, and particularly relates to a double pulse pulse width limiting circuit of a switching power supply and an implementation method thereof.
  • switching power supply has become an indispensable electronic device for people's work and life. It has been applied to the field of electronic information with its characteristics of small size, light weight and high efficiency.
  • the pulse of the driving switch tube in the switching power supply has single pulse, double pulse and even multiple pulses. Most of the pulses that drive the switching transistors in the switching power supply are implemented by using a special PWM control chip.
  • a PWM chip with dead time control it can be configured into two types: fixed dead time and dead time.
  • the control chip CM6900 series the dead time is fixed at 400 nanoseconds.
  • the dead time of the control chip SG3525 series can be configured according to external resistors and capacitors.
  • the former is not convenient for flexible configuration of the pulse width, and neither of them is suitable for the requirement of the pulse width limitation of the digital switching power supply in hardware.
  • the independent pulse width limiting circuit such as the Chinese utility model patent application (patent application number: 201220684107.9, utility model name: a pulse width limiting circuit of an LED driver)
  • the circuit is disclosed by using a differential circuit composed of a resistor and a capacitor to realize the pulse. Wide limit.
  • the reliability of limiting the pulse width by this method is not high, and the triode in the circuit is easily mis-conducted, and is more suitable for the pulse width limitation of a single pulse.
  • Another example is the Chinese invention patent application (patent application number: 201410396623.5, The invention name: a pulse width limiting circuit of an inverter power supply) applies for a circuit for limiting the pulse width by controlling the current injected into the PWM regulating terminal of the PWM control chip.
  • this method relies too much on the PWM control chip and cannot be digitalized. Switching power supplies require a pulse width limit on the hardware.
  • the main object of the present invention is to provide a switching power supply double pulse pulse width limiting circuit, which solves the problem of pulse width limitation of double pulses, achieves the limitation of being independent of the two-way pulse generating source, and can flexibly set the controlled two-way pulse.
  • the technical effect of the pulse width is to provide a switching power supply double pulse pulse width limiting circuit, which solves the problem of pulse width limitation of double pulses, achieves the limitation of being independent of the two-way pulse generating source, and can flexibly set the controlled two-way pulse.
  • the present invention provides a switching power supply dual pulse pulse width limiting circuit including a pulse width limiting circuit and an electronic switching circuit, the pulse width limiting circuit being coupled to the electronic switching circuit.
  • the pulse width limiting circuit is coupled to an external double pulse generating circuit for generating two complementary symmetric, dead time initial pulse signals, the pulse width limiting circuit for using the initial pulse
  • the signal is converted into two complementary drive pulse signals of a preset pulse width, and the generated pulse control signal is sent to the electronic switch circuit.
  • the electronic switch circuit is configured to select an output channel according to the pulse control signal, and output two complementary driving pulse signals of the preset pulse width.
  • the switching power supply double pulse pulse width limiting circuit further includes a power on reset circuit, and the power on reset circuit is respectively connected to the pulse width limiting circuit and the electronic switch circuit.
  • the power-on reset circuit is configured to control the electronic switch circuit to output two complementary drive pulse signals of the preset pulse width after the power-on power is delayed for a preset period of time.
  • the switching power supply double pulse pulse width limiting circuit further comprises a full cycle control circuit and a doze control circuit, wherein the full cycle control circuit is connected to the external double pulse generating circuit and connected to the electronic switch circuit;
  • the snoring control circuit is externally connected to the control loop, and the control loop is configured to detect whether the switching power supply has an effective signal of a snoring phenomenon, and the snoring control circuit is respectively connected to the pulse width limiting circuit and the electronic switching circuit.
  • the full cycle control circuit is configured to detect, by any one of the initial pulse signals, whether the switching power supply has a snoring phenomenon, and generate a snoring trigger pulse signal, and output the signal to the electronic switch circuit.
  • the snoring control circuit is configured to collect an effective signal of the control loop and output the signal to the electronic switch circuit, and to control the pulse width limiting circuit according to a snoring control signal provided by the electronic switch circuit, so that The pulse width limiting circuit outputs a pulse control signal, and the electronic switch circuit selects an output channel according to the pulse control signal, and outputs an initial pulse signal.
  • the electronic switch circuit is configured to generate a doze control signal according to the hiccup trigger pulse signal and the valid signal.
  • the pulse width limiting circuit is connected to the first signal input end and the second signal input end of the external double pulse generating circuit, and the first signal input end is connected to the anode of the first diode, a second signal input terminal is coupled to the anode of the second diode, and a third pin of the first Schmitt trigger is respectively connected to a cathode of the first diode, a cathode of the second diode, and a
  • the second resistor is connected to one end of the second capacitor, and is grounded via the second resistor
  • the fourth pin of the first Schmitt trigger is respectively connected to the anode of the third diode, the third resistor and the second capacitor
  • the other end is connected to the fifth pin of the second Schmitt trigger, the anode of the fourth diode, and the ninth pin of the third Schmitt trigger via the third resistor, the second dense
  • the fifth pin of the special trigger is connected to the cathode of the third diode, and the sixth pin of the second
  • the electronic switch circuit has an electronic switch, and the VEE pin and the VSS pin of the electronic switch and one end of the fourth capacitor are grounded, and the VDD pin and the INH pin of the electronic switch and the fourth capacitor are further One end is connected to the power-on reset circuit, and the C pin and the B pin of the electronic switch are connected to a tenth pin of a fourth Schmitt trigger of the pulse width limiting circuit, and the A pin of the electronic switch
  • the whole period control circuit is connected, and the X pin and the X0 pin of the electronic switch are respectively connected to the snoring control circuit, the Z1 pin and the Y1 pin of the electronic switch are grounded, and the Z pin of the electronic switch is
  • the PDRA is connected, its Y pin is connected to PDRB, its Z0 pin is connected to OUTA, and its Y0 pin is connected to OUTB.
  • the power-on reset circuit has a power source, and the power source is respectively connected to a VDD pin of the electronic switch circuit, and a fourth capacitor end and an end of the fifth capacitor, the fifth power The other end of the capacitor is respectively connected to the INH pin of the electronic switch circuit, the cathode of the fifth diode, and the ground through the sixth resistor, and the anode of the fifth diode is grounded.
  • the full cycle control circuit has a fifth Schmitt trigger, a first pin of the fifth Schmitt trigger is connected to one end of the first capacitor, and is grounded via a first resistor, the first a second pin of the Schmitt trigger is connected to the A pin of the electronic switch circuit, and a fourteenth pin of the fifth Schmitt trigger is connected to the power source, the fifth Schmitt trigger
  • the seventh pin of the device is grounded, and the other end of the first capacitor is connected to any one of the first signal input end and the second signal input end of the double pulse generating circuit.
  • the snoring control circuit comprises a second MOS transistor and a sixth Schmitt trigger
  • the thirteenth pin of the sixth Schmitt trigger acquires an effective signal of an external control loop via the seventh resistor
  • a twelfth pin of the sixth Schmitt trigger is connected to an X pin of the electronic switch circuit
  • a gate of the second MOS transistor is connected to an X0 pin of the electronic switch circuit
  • the first pole of the second MOS transistor is grounded
  • the drain of the second MOS transistor is respectively associated with a fourth Schmitt trigger of the pulse width limiting circuit
  • the eleven pin, one end of the third capacitor, one end of the fifth resistor, and the drain of the first MOS transistor are connected.
  • the present invention also provides a method for implementing a dual-pulse pulse width limiting circuit of a switching power supply, and constructing a double pulse generating circuit, a pulse width limiting circuit, an electronic switching circuit, and the pulse respectively connected in sequence a power-on reset circuit connected to the wide limit circuit and the electronic switch circuit;
  • the double pulse generating circuit generates two complementary symmetric, initial time signals with dead time, and sends the initial pulse signal to the pulse width limiting circuit;
  • the pulse width limiting circuit converts the initial pulse signal into two complementary driving pulse signals of a preset pulse width, and sends the generated pulse control signal to the electronic switching circuit;
  • the electronic switch circuit selects an output channel according to the received pulse control signal, and outputs two complementary drive pulse signals of the preset pulse width;
  • the power-on reset circuit controls the electronic switch circuit to output two complementary drive pulse signals of the preset pulse width after the power-on power is delayed for a preset period of time.
  • the switching power supply double pulse pulse width limiting circuit further comprises a full cycle control circuit and a doze control circuit;
  • the full cycle control circuit detects that the switching power supply is snoring according to any one of the initial pulse signals, the snoring trigger pulse signal is sent to the electronic switch circuit;
  • the snoring control circuit collects an effective signal of an external control loop and transmits the valid signal to the electronic switch circuit;
  • the electronic switch circuit generates a doze control signal according to the doze trigger pulse signal and the valid signal, and sends the doze control signal to the doze control circuit;
  • the snoring control circuit controls the pulse width limiting circuit according to the snoring control signal, so that the pulse width limiting circuit outputs a pulse control signal, and the electronic switching circuit selects an output channel according to the pulse control signal, and outputs an initial pulse signal.
  • the invention solves the problem of the pulse width limitation of the double pulse through the pulse width limiting circuit and the electronic switching circuit, and achieves the technical effect that the pulse width of the controlled two-way pulse can be flexibly set without being restricted by the two-way pulse generating source. . That is, whether the double pulse generated by the integrated chip or the double pulse generated by the controller, the present invention can flexibly set the pulse width of the controlled double pulse.
  • the invention limits the width of the driving pulse by the pulse width limiting circuit, so that the switching tube works in the safe current region, increases the service life of the switching tube, reduces the maintenance cost of the switching tube, and improves the reliability of the switching power supply.
  • Embodiment 1 is a circuit diagram of Embodiment 1 of a switching power supply double pulse pulse width limiting circuit according to the present invention
  • FIG. 2 is a timing diagram of key signals of the first embodiment of the switching power supply double pulse pulse width limiting circuit of the present invention
  • Embodiment 3 is a circuit diagram of Embodiment 2 of a switching power supply double pulse pulse width limiting circuit according to the present invention
  • Embodiment 4 is a flowchart of Embodiment 3 of a switching power supply double pulse pulse width limiting circuit according to the present invention.
  • FIG. 5 is a flowchart of Embodiment 4 of a switching power supply double pulse pulse width limiting circuit according to the present invention.
  • FIG. 1 is a circuit diagram of Embodiment 1 of a dual-pulse pulse width limiting circuit for a switching power supply according to the present invention
  • FIG. 2 is a timing diagram of key signals of Embodiment 1 of a dual-pulse pulse width limiting circuit for a switching power supply according to the present invention.
  • the present invention provides a switching power supply double pulse pulse width limiting circuit including a pulse width limiting circuit 4 and an electronic switching circuit 5, the pulse width limiting circuit 4 and the electronic opening Close circuit 5 connection;
  • the pulse width limiting circuit 4 is coupled to an external double pulse generating circuit for generating two complementary symmetric, dead time initial pulse signals, the pulse width limiting circuit 4 for The initial pulse signal is converted into two complementary drive pulse signals of a preset pulse width, and the generated pulse control signal is sent to the electronic switch circuit 5;
  • the electronic switch circuit 5 is configured to select an output channel according to the pulse control signal, and output two complementary drive pulse signals of the preset pulse width.
  • the double pulse generating circuit may be an oscillating circuit formed by an integrated chip (for example, 555), or an oscillating circuit composed of a special PWM control chip (such as SG3525), or a pulse generated by a controller (for example, DSP) control. Circuit. That is, the present invention can be implemented as long as it can generate a two-way complementary circuit with a pulse signal having a small dead time, and is within the protection scope of the present invention.
  • the pulse width limiting circuit 4 of the present invention generates a double pulse strobe trigger signal of a certain width by using two complementary symmetry of the dual pulse generating circuit and the dead time of the initial pulse signal with dead time, and strobes the double pulse
  • the trigger signal is sent to the electronic switch circuit 5.
  • the switching power supply double pulse pulse width limiting circuit further includes a power on reset circuit 1 , and the power on reset circuit 1 is respectively connected to the pulse width limiting circuit 4 and the electronic switch circuit 5;
  • the power-on reset circuit 1 is configured to control the electronic switch circuit to output two complementary drive pulse signals of the preset pulse width after the power-on power is delayed for a preset period of time.
  • the two complementary driving pulse signals of the preset pulse width are output to the switch tube, so that the power-on power is delayed for a preset period of time and then the preset pulse width is output.
  • the two complementary drive pulse signals are output to the switch tube, so that the power-on power is delayed for a preset period of time and then the preset pulse width is output.
  • the pulse width limiting circuit 4 is connected to the first signal input end and the second signal input end of the external double pulse generating circuit, and the first signal input end is connected to the anode of the first diode.
  • the second signal input end is connected to the anode of the second diode
  • the third pin of the first Schmitt trigger is respectively connected to the cathode of the first diode, the cathode of the second diode, Connected to one end of the second capacitor via the second resistor, and grounded via the second resistor, the fourth pin of the first Schmitt trigger and the anode of the third diode, the third resistor and the second
  • the other end of the capacitor is connected to the fifth pin of the second Schmitt trigger, the anode of the fourth diode, and the ninth pin of the third Schmitt trigger via the third resistor
  • the second application a fifth pin of the Mitt trigger is connected to a cathode of the third diode, and a sixth pin of the second Schmitt trigger
  • the input of the double pulse generating circuit is the pin OUTA and the pin OUTB, the pin OUTA is connected to the anode of the first diode, the pin OUTB is connected to the anode of the second diode, and the cathode of the first diode is a cathode of the second diode, a segment of the second resistor is connected to the third pin of the first Schmitt trigger, and the other end of the second resistor is grounded, the fourth pin of the first Schmitt trigger One end of the three resistor, the anode of the third diode, the anode of the fourth diode, and the ninth pin of the third Schmitt trigger, and the other end of the third resistor is connected to one end of the second capacitor, The cathode of the three diode is connected to the fifth pin of the second Schmitt trigger, and the other end of the second capacitor is grounded; the sixth pin of the second Schmitt trigger is connected to one end of the fourth resistor, The other end of the fourth
  • the first diode and the second diode perform anti-reverse acquisition on the pulses at the OUTA and OUTB inputs, and the pulse width limiting circuit 4 of the present invention inputs the OUTA and OUTB inputs due to the dead zone of the pulses input at the OUTA and OUTB inputs.
  • the pulse width limiting circuit 4 of the present invention inputs the OUTA and OUTB inputs due to the dead zone of the pulses input at the OUTA and OUTB inputs.
  • the narrow pulse at V1 quickly charges the second capacitor through the third diode.
  • the second capacitor begins to discharge through the third resistor, and the voltage V2 gradually decreases, and the waveform is as shown in the V2 timing in FIG.
  • the time constant t3 determined by the second capacitance and the third resistance determines the pulse width.
  • the second Schmitt trigger, the fourth resistor, the fourth diode, the third Schmitt trigger, the first MOS transistor and the fifth resistor constitute a pulse shaping circuit, and the pulse waveform after forming is as shown in FIG.
  • the V3 timing is shown.
  • the pulse width t1 of the pulse voltage V3 (t3 ⁇ 3 * t1, the actual value is subject to the measurement result).
  • the third capacitance value is small and is used to filter out interference.
  • the fourth diode is a clamping diode to ensure the stability of the low voltage V1.
  • the electronic switch circuit 5 has an electronic switch, and the VEE pin and the VSS pin of the electronic switch and one end of the fourth capacitor are grounded, and the VDD pin and the INH pin and the fourth capacitor of the electronic switch The other end is connected to the power-on reset circuit, and the C pin and the B pin of the electronic switch are connected to the tenth pin of the fourth Schmitt trigger of the pulse width limiting circuit, and the A pin of the electronic switch Connected to the full cycle control circuit, the X pin and the X0 pin of the electronic switch are respectively connected to the doze control circuit, the Z1 pin and the Y1 pin of the electronic switch are grounded, and the Z pin of the electronic switch Connected to PDRA, its Y pin is connected to PDRB, its Z0 pin is connected to OUTA, and its Y0 pin is connected to OUTB.
  • the double pulse after the pulse width limitation of the present invention outputs the driving circuit from the Z pin and the Y pin of the electronic switch.
  • the VEE pin of the electronic switch, the VSS pin of the electronic switch, and the end of the fourth capacitor are grounded.
  • the VDD pin of the electronic switch and the other end of the fourth capacitor are connected to the power supply at the same time.
  • the Y1 pin of the electronic switch is grounded, and the Y0 of the electronic switch The pin is connected to OUTB, the Z1 pin of the electronic switch is grounded, the Z0 pin of the electronic switch is connected to OUTA, the Z pin of the electronic switch is connected to PDRA, and the Y pin of the electronic switch is connected to PDRB.
  • the electronic switch When the C and B pins of the electronic switch are high, the electronic switch strobes low to connect to PDRA and PDRB, and conversely, keeps the OUTA and OUTB pulse outputs unchanged.
  • the electronic switch keeps the OUTA and OUTB pulse outputs unchanged.
  • the power-on reset circuit 1 has a power source, and the power source is respectively connected to a VDD pin of the electronic switch circuit, a fourth capacitor end, and a fifth capacitor, and the other end of the fifth capacitor is respectively The INH pin of the electronic switch circuit, the cathode of the fifth diode are connected, and the sixth resistor is grounded, and the anode of the fifth diode is grounded.
  • the input end of the power-on reset circuit 1 is connected to the power source, and the output end thereof is connected to the INH pin of the electronic switch of the electronic switch circuit 5, and the power source is connected to one end of the fifth capacitor.
  • the other end of the fifth capacitor is connected to the INH pin of the electronic switch, one end of the sixth resistor, and the cathode of the second diode, the other end of the sixth resistor is grounded, and the anode of the fifth diode is also grounded.
  • the fifth capacitor and the sixth resistor constitute a differential circuit.
  • the voltage V6 of the INH pin of the electronic switch will rise instantaneously.
  • the electronic switch does not work, no drive output, and then slowly discharges through the sixth resistor.
  • the voltage V6 drops to a low level, the electronic switch starts to work, and the electronic switch has a pulse output.
  • the fifth diode is a clamp diode.
  • V6 When the power is turned off, the voltage V6 is clamped to a low level, which avoids the failure of the next power-on reset.
  • the invention solves the problem of the pulse width limitation of the double pulse through the pulse width limiting circuit 4 and the electronic switching circuit 5, and achieves the limitation of the source of the controlled two-way pulse without being restricted by the source of the two-way pulse.
  • Technical effects That is, whether the double pulse generated by the integrated chip or the double pulse generated by the controller, the present invention can flexibly set the pulse width of the controlled double pulse.
  • the invention limits the width of the driving pulse by the pulse width limiting circuit 4, so that the switching tube operates in the safe current region, increases the service life of the switching tube, reduces the maintenance cost of the switching tube, and improves the reliability of the switching power supply.
  • FIG. 3 is a circuit diagram of Embodiment 2 of a dual-pulse pulse width limiting circuit for a switching power supply according to the present invention.
  • the circuit structure is substantially the same as that of the above embodiment, except that the switching power supply double pulse pulse width limiting circuit further includes a full cycle control circuit 2 and a doze control circuit 3, and the whole cycle control circuit 2, the double pulse generating circuit is externally connected to the electronic switch circuit 5; the hiccup control circuit 3 is externally connected to the control loop, and the control loop is used for detecting whether the switching power supply has a valid signal of snoring, The snoring control circuit 3 is connected to the pulse width limiting circuit 4 and the electronic switching circuit 5, respectively;
  • the full cycle control circuit 2 is configured to detect whether the switching power supply has a snoring phenomenon by using any one of the initial pulse signals, and generate a snoring trigger pulse signal;
  • the snoring control circuit 3 is configured to collect an effective signal of the control loop, and control the pulse width limiting circuit 4 according to the snoring control signal, so that the pulse width limiting circuit 4 outputs a pulse control Making a signal, the electronic switch circuit 5 selects an output channel according to a pulse control signal, and outputs an initial pulse signal;
  • the electronic switch circuit 5 is configured to generate a doze control signal according to the hiccup trigger pulse signal and the valid signal.
  • the full cycle control circuit 3 has a fifth Schmitt trigger, the first pin of the fifth Schmitt trigger is connected to one end of the first capacitor, and the first resistor is grounded, a second pin of the fifth Schmitt trigger is connected to the A pin of the electronic switch circuit, and a fourteenth pin of the fifth Schmitt trigger is connected to the power source, the fifth Schmidt The seventh pin of the flip-flop is grounded, and the other end of the first capacitor is connected to any one of the first signal input end and the second signal input end of the double pulse generating circuit.
  • the whole cycle control circuit 3 includes a first capacitor, one end of which is connected to OUTA or OUTB of the double pulse generating circuit, and the other end of the first flashlight and the first pin of the fifth Schmitt trigger, the first One end of the resistor is connected, the other end of the first resistor is grounded, the seventh pin of the first Schmitt trigger is grounded, and the fourteenth pin of the first Schmitt trigger is connected to the power source, the first Schmitt trigger
  • the second pin of the device is connected to the A pin of the electronic switch of the electronic switch circuit 5.
  • the first resistor and the first capacitor constitute a differential circuit, and the working principle is the same as the differential circuit of the power-on reset circuit 1.
  • the full cycle control circuit 3 adds a fifth Schmitt trigger, which is a flip of the input narrow pulse signal.
  • a fifth Schmitt trigger which is a flip of the input narrow pulse signal.
  • the snoring control circuit includes a second MOS transistor and a sixth Schmitt trigger
  • the thirteenth pin of the sixth Schmitt trigger acquires an effective signal of an external control loop via the seventh resistor
  • a twelfth pin of the sixth Schmitt trigger is connected to an X pin of the electronic switch circuit
  • a gate of the second MOS transistor is connected to an X0 pin of the electronic switch circuit
  • the first pole of the second MOS transistor is grounded
  • the drain of the second MOS transistor is respectively associated with a fourth Schmitt trigger of the pulse width limiting circuit
  • the eleven pin, one end of the third capacitor, one end of the fifth resistor, and the drain of the first MOS transistor are connected.
  • the hiccup control circuit 3 acquires an effective signal of the external control loop (high level is normal), BURST is connected to one end of the seventh resistor, and the other end of the seventh resistor and the thirteenth pin of the sixth Schmitt trigger Connection, the twelfth pin of the sixth Schmitt trigger and the electrical of the electronic switch circuit 5
  • the X pin of the sub-switch is connected, one end of the eighth resistor is connected to one end of the sixth capacitor, the gate of the second MOS transistor, the X0 pin of the electronic switch of the electronic switch circuit, and the other end of the eighth resistor and the sixth capacitor
  • the other end is connected, and the other end of the eighth resistor is grounded, the first MOS transistor is grounded, and the drain of the second MOS transistor is connected to the pulse width limiting circuit.
  • the signal BURST is low level
  • the sixth Schmitt trigger is turned over, it is at a high level
  • the A pin of the electronic switch is also at a high level, so that the electron
  • the X0 pin and the X pin of the electronic switch of the switch circuit 5 are turned on, the second MOS transistor is turned on, the voltage V3 is turned to a low level, and after the fourth Schmitt trigger is turned over, the high level is performed, and finally the electronic switch
  • the hiccup control is achieved by maintaining the output pulses OUTA and OUTB to the drive circuit.
  • the pulse width of the pulse of the double pulse generating circuit is relatively small, and the pulse width limitation is not required, and the pulse can be directly output.
  • the sixth capacitor and the eighth resistor function to prevent mis-conduction of the second MOS transistor.
  • the invention solves the problem of snoring of a wide range of input voltage switching power supply by the added full cycle control circuit 2 and the snoring control circuit 3.
  • FIG. 4 is a flowchart of Embodiment 3 of a dual-pulse pulse width limiting circuit for a switching power supply according to the present invention.
  • Embodiment 3 of the present invention further provides an implementation method of a switching power supply double pulse pulse width limiting circuit, and constructs a double pulse generating circuit, a pulse width limiting circuit, an electronic switching circuit, and the respectively described a pulse width limiting circuit and a power-on reset circuit connected to the electronic switch circuit, comprising the following steps;
  • step S10 the double pulse generating circuit generates two complementary symmetrical initial pulse signals with dead time, and sends the initial pulse signals to the pulse width limiting circuit.
  • the double pulse generating circuit generates two complementary symmetrical initial pulse signals with a small dead time, and then outputs the initial pulse signals to the pulse width limiting circuit through the two input terminals OUTA and OUTB, respectively.
  • Step S11 the pulse width limiting circuit converts the initial pulse signal into two complementary driving pulse signals of a preset pulse width, and sends the generated pulse control signal to the electronic switching circuit.
  • Step S12 the electronic switch circuit selects an output channel according to the received pulse control signal, and outputs two complementary drive pulse signals of the preset pulse width.
  • Step S13 the power-on reset circuit controls the electronic switch circuit to output two complementary drive pulse signals of the preset pulse width after the power-on power-on delay for a preset period of time.
  • the invention solves the problem of the pulse width limitation of the double pulse through the pulse width limiting circuit 4 and the electronic switching circuit 5, and achieves the limitation of the source of the controlled two-way pulse without being restricted by the source of the two-way pulse.
  • Technical effects That is, whether the double pulse generated by the integrated chip or the double pulse generated by the controller, the present invention can flexibly set the pulse width of the controlled double pulse.
  • the invention limits the width of the driving pulse by the pulse width limiting circuit 4, so that the switching tube operates in the safe current region, increases the service life of the switching tube, reduces the maintenance cost of the switching tube, and improves the reliability of the switching power supply.
  • the two complementary driving pulse signals of the preset pulse width are output to the switch tube, so that the power-on power is delayed for a preset period of time and then the preset pulse width is output.
  • the two complementary drive pulse signals are output to the switch tube, so that the power-on power is delayed for a preset period of time and then the preset pulse width is output.
  • FIG. 5 is a flowchart of Embodiment 4 of a dual-pulse pulse width limiting circuit for a switching power supply according to the present invention.
  • the steps of the above embodiment are basically the same, except that the switching power supply double pulse pulse width limiting circuit further includes a full cycle control circuit and a doze control circuit, and the switching power supply double pulse pulse width limitation
  • the implementation method of the circuit further includes the following steps;
  • Step S20 when the whole cycle control circuit detects that the switching power supply is snoring according to any one of the initial pulse signals, the snoring trigger pulse signal is sent to the electronic switch circuit;
  • Step S21 the hiccup control circuit collects an effective signal of an external control loop, and sends the valid signal to the electronic switch circuit;
  • Step S22 the electronic switch circuit generates a doze control signal according to the doze trigger pulse signal and the valid signal, and sends the doze control signal to the doze control circuit;
  • Step S23 the snoring control circuit controls the pulse width limiting circuit according to the snoring control signal, so that the pulse width limiting circuit outputs a pulse control signal, and the electronic switch circuit selects an output channel according to the pulse control signal, and outputs an initial pulse. signal.
  • the invention solves the problem of snoring of a wide range of input voltage switching power supply by the added full cycle control circuit 2 and the snoring control circuit 3.

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Abstract

一种开关电源双脉冲脉宽限制电路及其实现方法。开关电源双脉冲脉宽限制电路包括脉宽限制电路（4）和电子开关电路（5）。脉宽限制电路与电子开关电路连接。脉宽限制电路与外部双脉冲发生电路连接。双脉冲发生电路用于生成两路互补对称、带死区时间的初始脉冲信号（OUTA，OUTB）。脉宽限制电路用于将初始脉冲信号转换为预设脉宽的两路互补的驱动脉冲信号（PDRA，PDRB），并将生成的脉冲控制信号发送至电子开关电路。电子开关电路用于根据脉冲控制信号选择输出通道，将预设脉宽的两路互补的驱动脉冲信号输出。开关电源双脉冲脉宽限制电路解决了双脉冲的脉宽限制的问题，其不受双路脉冲发生源的限制，并且能灵活设置双路脉冲脉宽。

Description

开关电源双脉冲脉宽限制电路及其实现方法 技术领域
本发明属于开关电源脉宽控制技术领域，尤其涉及一种开关电源双脉冲脉宽限制电路及其实现方法。
背景技术
随着电力电子技术的飞速发展，开关电源已成为人们的工作、生活中不可缺少的电子设备，它以小型、轻便和高效率的特点应用到了电子信息领域。
根据拓扑结构、控制方式的不同，开关电源中驱动开关管的脉冲有单脉冲、双脉冲，甚至多脉冲。而开关电源中驱动开关管的脉冲大多都采用专门的PWM控制芯片来实现。
而现有的大、中功率的开关电源，常见的是采用全桥拓扑结构。但是，全桥拓扑结构的电路要求控制相邻桥臂上的开关管轮流导通，因此，就需要互补对称的双脉冲来控制，脉冲的最大占空比为50％。当负载变化或控制电路异常时，电源长时间工作在PWM芯片的最大输出脉宽附近，开关管处于长时间导通状态，严重时可能导致相邻桥臂上的开关管电流不对称，甚至同时导通的情况，从而烧坏开关管，以致造成损失。为了避免此问题的发生，可行的解决办法是限制PWM控制芯片的最大输出脉宽，使开关管工作在安全电流区域内。
现有限制脉冲宽度的方法有很多，比较常见的是包括自带死区时间控制的PWM芯片和独立的脉宽限制电路。
对于带死区时间控制的PWM芯片，其分为固定死区时间和死区时间可配置两种。例如：控制芯片CM6900系列，死区时间固定为400纳秒。控制芯片SG3525系列的死区时间可根据外接电阻和电容来配置。但是，前者不便于脉冲宽度的灵活配置，而且，两者都不适用数字化开关电源在硬件上对脉宽限制的需求。
对于独立的脉宽限制电路，如中国实用新型专利申请(专利申请号：201220684107.9，实用新型名称：一种LED驱动器的脉宽限制电路)公示的电路，采用电阻、电容构成的微分电路来实现脉宽限制。但是，通过此方法实现脉宽的限制的可靠性不高，电路中的三极管易误导通，且较适用单脉冲的脉宽限制。又如中国发明专利申请(专利申请号：201410396623.5， 发明名称：一种逆变电源的脉宽限制电路)申请公示的电路，该电路通过控制注入PWM控制芯片的PWM调节端的电流来限制脉宽，但是，此方法过于依赖PWM控制芯片，无法适用数字化开关电源在硬件上对脉宽限制的需求。
然而，在大、中功率等级开关电源应用场合中使用双脉冲驱动较多。因此，如何解决双脉冲的脉宽限制问题，是当前亟待解决的技术问题。
发明内容
本发明的主要目的在于提供一种开关电源双脉冲脉宽限制电路，解决了双脉冲的脉宽限制的问题，达到了不受双路脉冲发生源的限制，且能灵活设置被控双路脉冲的脉宽的技术效果。
为实现上述目的，本发明提供了一种开关电源双脉冲脉宽限制电路，其包括脉宽限制电路和电子开关电路，所述脉宽限制电路与所述电子开关电路连接。
所述脉宽限制电路与外部双脉冲发生电路连接，所述双脉冲发生电路用于生成两路互补对称、带死区时间的初始脉冲信号，所述脉宽限制电路用于将所述初始脉冲信号转换为预设脉宽的两路互补的驱动脉冲信号，并将生成脉冲控制信号发送至电子开关电路。
所述电子开关电路用于根据所述脉冲控制信号选择输出通道，将所述预设脉宽的两路互补的驱动脉冲信号输出。
优选地，所述开关电源双脉冲脉宽限制电路还包括开机复位电路，所述开机复位电路分别与脉宽限制电路、电子开关电路连接。
所述开机复位电路用于控制所述电子开关电路，在开机上电延迟预设时间段后，输出所述预设脉宽的两路互补的驱动脉冲信号。
优选地，所述开关电源双脉冲脉宽限制电路还包括整周期控制电路和打嗝控制电路，所述整周期控制电路与所述外部双脉冲发生电路连接，并与所述电子开关电路连接；所述打嗝控制电路外接控制环路，所述控制环路用于检测开关电源是否出现打嗝现象的有效信号，所述打嗝控制电路分别与所述脉宽限制电路、电子开关电路连接。
所述整周期控制电路，用于通过所述初始脉冲信号中任意一个脉冲信号检测开关电源是否出现打嗝现象，以及生成打嗝触发脉冲信号，并输出到所述电子开关电路。
所述打嗝控制电路，用于采集所述控制环路的有效信号并输出到所述电子开关电路，以及用于根据所述电子开关电路提供的打嗝控制信号控制所述脉宽限制电路，以致所述脉宽限制电路输出脉冲控制信号，所述电子开关电路根据脉冲控制信号选择输出通道，输出初始脉冲信号。
所述电子开关电路，用于根据打嗝触发脉冲信号和有效信号生成打嗝控制信号。
优选地，所述脉宽限制电路与所述外部双脉冲发生电路的第一信号输入端和第二信号输入端连接，所述第一信号输入端与第一二极管的阳极连接，所述第二信号输入端与所述第二二极管的阳极连接，所述第一施密特触发器的第三引脚分别与第一二极管的阴极、第二二极管的阴极、经第二电阻与第二电容的一端连接，以及经第二电阻接地，所述第一施密特触发器的第四引脚分别与第三二极管的阳极、经第三电阻与第二电容的另一端、经第三电阻与第二施密特触发器的第五引脚、第四二极管的阳极、第三施密特触发器的第九引脚连接，所述第二施密特触发器的第五引脚与第三二极管的阴极连接，所述第二施密特触发器的第六引脚经第四电阻分别与第四二极管的阴极、第一MOS管的栅极连接，所述第三施密特触发器的第九引脚与第四二极管的阳极连接，所述第三施密特触发器的第八引脚经第五电阻分别与第一MOS管的漏极、第三电容的一端、第四施密特触发器的第十一引脚、所述打嗝控制电路连接，所述第一MOS管的原极接地，所述第三电容的另一端接地，所述第四施密特触发器的第十引脚与所述电子开关电路连接。
优选地，所述电子开关电路具有电子开关，所述电子开关的VEE引脚和VSS引脚以及第四电容的一端接地，所述电子开关的VDD引脚和INH引脚、第四电容的另一端与所述开机复位电路连接，所述电子开关的C引脚和B引脚与脉宽限制电路的第四施密特触发器的第十引脚连接，所述电子开关的A引脚与整周期控制电路连接，所述电子开关的X引脚和X0引脚分别与所述打嗝控制电路连接，所述电子开关的Z1引脚和Y1引脚接地，所述电子开关的Z引脚与PDRA连接，其Y引脚与PDRB连接，其Z0引脚与OUTA连接，其Y0引脚与OUTB连接。
优选地，所述开机复位电路具有一个电源，所述电源分别与所述电子开关电路的VDD引脚和第四电容一端、第五电容的一端连接，所述第五电 容的另一端分别与所述电子开关电路的INH引脚、第五二极管的阴极连接，以及经第六电阻接地，所述第五二极管的阳极接地。
优选地，所述整周期控制电路具有第五施密特触发器，所述第五施密特触发器的第一引脚与第一电容的一端连接，以及经第一电阻接地，所述第五施密特触发器的第二引脚与所述电子开关电路的A引脚连接，所述第五施密特触发器的第十四引脚与电源连接，所述第五施密特触发器的第七引脚接地，所述第一电容的另一端与双脉冲发生电路的第一信号输入端和第二信号输入端中任意一个输入端连接。
优选地，所述打嗝控制电路包括第二MOS管和第六施密特触发器，所述第六施密特触发器的第十三引脚经第七电阻采集外部的控制环路的有效信号，所述第六施密特触发器的第十二引脚与所述电子开关电路的X引脚连接，所述第二MOS管的栅极与所述电子开关电路的X0引脚连接，以及经第六电容接地、经第八电阻接地，所述第二MOS管的原极接地，所述第二MOS管的漏极分别与所述脉宽限制电路的第四施密特触发器的第十一引脚、第三电容的一端、第五电阻的一端、第一MOS管的漏极连接。
此外，为实现上述目的，本发明还提供了一种开关电源双脉冲脉宽限制电路的实现方法，构建依次连接的双脉冲发生电路、脉宽限制电路、电子开关电路，以及分别与所述脉宽限制电路、电子开关电路连接的开机复位电路；
双脉冲发生电路生成两路互补对称、带死区时间的初始脉冲信号，并将所述初始脉冲信号发送至所述脉宽限制电路；
脉宽限制电路将所述初始脉冲信号转换为预设脉宽的两路互补的驱动脉冲信号，并将生成的脉冲控制信号发送至电子开关电路；
所述电子开关电路根据接收到的所述脉冲控制信号选择输出通道，将所述预设脉宽的两路互补的驱动脉冲信号输出；
所述开机复位电路控制所述电子开关电路，在开机上电延迟预设时间段后，输出所述预设脉宽的两路互补的驱动脉冲信号。
优选地，所述开关电源双脉冲脉宽限制电路还包括整周期控制电路和打嗝控制电路；
当所述整周期控制电路根据所述初始脉冲信号中任意一个脉冲信号检测到开关电源出现打嗝现象时，发出打嗝触发脉冲信号至电子开关电路；
所述打嗝控制电路采集到外部的控制环路的有效信号，并将所述有效信号发送至所述电子开关电路；
所述电子开关电路根据所述打嗝触发脉冲信号和所述有效信号生成打嗝控制信号，并将所述打嗝控制信号发送至所述打嗝控制电路；
所述打嗝控制电路根据所述打嗝控制信号控制所述脉宽限制电路，以致所述脉宽限制电路输出脉冲控制信号，所述电子开关电路根据脉冲控制信号选择输出通道，输出初始脉冲信号。
本发明通过脉宽限制电路和电子开关电路，解决了双脉冲的脉宽限制的问题，达到了不受双路脉冲发生源的限制，而能灵活设置被控双路脉冲的脉宽的技术效果。即无论是集成芯片产生的双脉冲，还是控制器产生的双脉冲，本发明均能够灵活的设置被控双脉冲的脉宽。
本发明通过脉宽限制电路来限制驱动脉冲的宽度，以致开关管工作在安全电流区域内，增长了开关管的使用寿命，降低了开关管的维护成本、以及提高了开关电源的可靠性。
说明书附图
图1为本发明开关电源双脉冲脉宽限制电路实施例1的电路图；
图2为本发明开关电源双脉冲脉宽限制电路实施例1的关键信号时序图；
图3为本发明开关电源双脉冲脉宽限制电路实施例2的电路图；
图4为本发明开关电源双脉冲脉宽限制电路实施例3的流程图；
图5为本发明开关电源双脉冲脉宽限制电路实施例4的流程图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用来限定本发明。
实施例1
参见图1和图2，图1为本发明开关电源双脉冲脉宽限制电路实施例1的电路图；图2为本发明开关电源双脉冲脉宽限制电路实施例1的关键信号时序图。
在实施例1中，本发明提供了一种开关电源双脉冲脉宽限制电路，其包括脉宽限制电路4和电子开关电路5，所述脉宽限制电路4与所述电子开 关电路5连接；
所述脉宽限制电路4与外部双脉冲发生电路连接，所述双脉冲发生电路用于生成两路互补对称、带死区时间的初始脉冲信号，所述脉宽限制电路4用于将所述初始脉冲信号转换为预设脉宽的两路互补的驱动脉冲信号，并将生成的脉冲控制信号发送至电子开关电路5；
所述电子开关电路5用于根据所述脉冲控制信号选择输出通道，将所述预设脉宽的两路互补的驱动脉冲信号输出。
本发明中双脉冲发生电路可以是集成芯片(例如555)构成的振荡电路，或者是专门的PWM控制芯片(如SG3525)构成的振荡电路，或者是控制器(例如：DSP)控制产生的脉冲发生电路。即只要能够产生两路互补，且带有较小的死区时间的脉冲信号的双脉冲发生电路，均能够实现本发明，均在本发明的保护范围以内。
本发明的脉宽限制电路4利用双脉冲发生电路的两路互补对称、带死区时间的初始脉冲信号的死区时间，产生一定宽度的双脉冲选通触发信号，并将该双脉冲选通触发信号发送至电子开关电路5。
进一步地，所述开关电源双脉冲脉宽限制电路还包括开机复位电路1，所述开机复位电路1分别与脉宽限制电路4、电子开关电路5连接；
所述开机复位电路1用于控制所述电子开关电路，在开机上电延迟预设时间段后，输出所述预设脉宽的两路互补的驱动脉冲信号。
本发明为了确保辅助电源以及其他的控制电路正常工作后，再输出预设脉宽的两路互补的驱动脉冲信号至开关管，因此，开机上电延迟预设时间段后再输出预设脉宽的两路互补的驱动脉冲信号。
进一步地，所述脉宽限制电路4与所述外部双脉冲发生电路的第一信号输入端和第二信号输入端连接，所述第一信号输入端与第一二极管的阳极连接，所述第二信号输入端与所述第二二极管的阳极连接，所述第一施密特触发器的第三引脚分别与第一二极管的阴极、第二二极管的阴极、经第二电阻与第二电容的一端连接，以及经第二电阻接地，所述第一施密特触发器的第四引脚分别与第三二极管的阳极、经第三电阻与第二电容的另一端、经第三电阻与第二施密特触发器的第五引脚、第四二极管的阳极、第三施密特触发器的第九引脚连接，所述第二施密特触发器的第五引脚与第三二极管的阴极连接，所述第二施密特触发器的第六引脚经第四电阻分 别与第四二极管的阴极、第一MOS管的栅极连接，所述第三施密特触发器的第九引脚与第四二极管的阳极连接，所述第三施密特触发器的第八引脚经第五电阻分别与第一MOS管的漏极、第三电容的一端、第四施密特触发器的第十一引脚、所述打嗝控制电路连接，所述第一MOS管的原极接地，所述第三电容的另一端接地，所述第四施密特触发器的第十引脚与所述电子开关电路连接。
双脉冲发生电路的输入端为引脚OUTA和引脚OUTB，引脚OUTA与第一二极管的阳极连接，引脚OUTB与第二二极管的阳极连接，第一二极管的阴极和第二二极管的阴极、第二电阻的一段和第一施密特触发器的第三引脚连接，第二电阻的另一端接地，第一施密特触发器的第四引脚与第三电阻的一端、第三二极管的阳极、第四二极管的阳极和第三施密特触发器的第九引脚连接，第三电阻的另一端与第二电容的一端连接，第三二极管的阴极与第二施密特触发器的第五引脚连接，第二电容的另一端接地；第二施密特触发器的第六引脚与第四电阻的一端连接，第四电阻的另一端与第四二极管的阴极、第一MOS管的漏极连接，第一MOS管的原极接地，第三施密特触发器的第八引脚与第五电阻的一端连接，第五电阻的另一端与第一MOS管的漏极连接，第三电容的一端、第四施密特触发器的第十一引脚连接，第三电容的另一端接地，第四施密特触发器的第十引脚与电子开关电路的C引脚和B引脚连接。
第一二极管和第二二极管对OUTA和OUTB输入端的脉冲进行防反采集，由于OUTA和OUTB输入端输入的脉冲存在死区，本发明的脉宽限制电路4对OUTA和OUTB输入端的脉冲混合采用后，经过第一施密特触发器翻转后生成窄脉冲，其脉宽等于死区时间t，波形如图2中的V1时序所示。
V1处的窄脉冲通过第三二极管对第二电容进行快速充电，第二电容值越小，所需死区时间就越短。
窄脉冲过后，第二电容通过第三电阻开始放电，电压V2逐渐下降，波形如图2中的V2时序。
第二电容和第三电阻确定的时间常数t3决定了脉冲脉宽。
第二施密特触发器、第四电阻、第四二极管、第三施密特触发器、第一MOS管和第五电阻构成了脉冲成形电路，成形后的脉冲波形如图2中的 V3时序所示。脉冲电压V3的脉宽t1(t3≈3*t1,实际值以测量结果为准)。
第三电容值很小，用来滤除干扰。
第四二极管为钳位二极管，保证电压V1低电平的稳定性。
电压V3经过第四施密特触发器翻转后，得到脉宽一定触发脉冲，该第四施密特触发器将该触发脉冲发送至电子开关电路的C引脚和B引脚。
进一步地，所述电子开关电路5具有电子开关，所述电子开关的VEE引脚和VSS引脚以及第四电容的一端接地，所述电子开关的VDD引脚和INH引脚、第四电容的另一端与所述开机复位电路连接，所述电子开关的C引脚和B引脚与脉宽限制电路的第四施密特触发器的第十引脚连接，所述电子开关的A引脚与整周期控制电路连接，所述电子开关的X引脚和X0引脚分别与所述打嗝控制电路连接，所述电子开关的Z1引脚和Y1引脚接地，所述电子开关的Z引脚与PDRA连接，其Y引脚与PDRB连接，其Z0引脚与OUTA连接，其Y0引脚与OUTB连接。
本发明的脉宽限制后的双脉冲是从电子开关的Z引脚和Y引脚输出驱动电路的。
电子开关的VEE引脚、电子开关的VSS引脚和第四电容的一端接地，电子开关的VDD引脚、第四电容的另一端同时接电源，电子开关的Y1引脚接地，电子开关的Y0引脚接OUTB，电子开关的Z1引脚接地，电子开关的Z0引脚接OUTA，电子开关的Z引脚接PDRA，电子开关的Y引脚接PDRB。
当电子开关的C引脚和B引脚为高电平时，电子开关选通低电平连接到PDRA和PDRB，反之，保持OUTA和OUTB脉冲输出不变。
值得说明的是，如果本发明的开关电源出现打嗝现象时，电子开关保持OUTA和OUTB脉冲输出不变。
由于C引脚和B引脚输入如图2中V3时序翻转后的脉冲控制，由此电子开关输出的双脉冲的时序波形图如图2中的PDRA和PDRB所示，其中，脉冲的宽度为t2，且满足t2＝T-t1，即输出脉冲宽度得到限制。
进一步地，所述开机复位电路1具有一个电源，所述电源分别与所述电子开关电路的VDD引脚和第四电容一端、第五电容的一端连接，所述第五电容的另一端分别与所述电子开关电路的INH引脚、第五二极管的阴极连接，以及经第六电阻接地，所述第五二极管的阳极接地。
开机复位电路1的输入端连接电源，其输出端连接到电子开关电路5的电子开关的INH引脚，电源连接第五电容的一端，。第五电容的另一端与电子开关的INH引脚、第六电阻的一端和第二二极管的阴极连接，第六电阻的另一端接地，第五二极管的阳极也接地。
第五电容和第六电阻构成了微分电路，上电的瞬间，电子开关的INH引脚的电压V6会瞬间上升，此时电子开关不工作，无驱动输出，之后通过第六电阻慢慢放电，电压V6下降至低电平，电子开关开始工作，电子开关有脉冲输出。
第五二极管为钳位二极管，掉电后将电压V6钳位至低电平，避免了下次开机复位失败。
本发明通过脉宽限制电路4和电子开关电路5，解决了双脉冲的脉宽限制的问题，达到了不受双路脉冲发生源的限制，而能灵活设置被控双路脉冲的脉宽的技术效果。即无论是集成芯片产生的双脉冲，还是控制器产生的双脉冲，本发明均能够灵活的设置被控双脉冲的脉宽。
本发明通过脉宽限制电路4来限制驱动脉冲的宽度，以致开关管工作在安全电流区域内，增长了开关管的使用寿命，降低了开关管的维护成本、以及提高了开关电源的可靠性。
实施例2
参见图3，图3为本发明开关电源双脉冲脉宽限制电路实施例2的电路图。
在实施例2中，与上述实施例的电路结构基本相同，不同之处在于，所述开关电源双脉冲脉宽限制电路还包括整周期控制电路2和打嗝控制电路3，所述整周期控制电路2外接所述双脉冲发生电路，并与所述电子开关电路5连接；所述打嗝控制电路3外接控制环路，所述控制环路用于检测开关电源是否出现打嗝现象的有效信号，所述打嗝控制电路3分别与所述脉宽限制电路4、电子开关电路5连接；
所述整周期控制电路2，用于通过述初始脉冲信号中任意一个脉冲信号检测开关电源是否出现打嗝现象，以及生成打嗝触发脉冲信号；
所述打嗝控制电路3，用于采集所述控制环路的有效信号，以及根据打嗝控制信号控制所述脉宽限制电路4，以致所述脉宽限制电路4输出脉冲控 制信号，所述电子开关电路5根据脉冲控制信号选择输出通道，输出初始脉冲信号；
所述电子开关电路5，用于根据打嗝触发脉冲信号和有效信号生成打嗝控制信号。
进一步地，所述整周期控制电路3具有第五施密特触发器，所述第五施密特触发器的第一引脚与第一电容的一端连接，以及经第一电阻接地，所述第五施密特触发器的第二引脚与所述电子开关电路的A引脚连接，所述第五施密特触发器的第十四引脚与电源连接，所述第五施密特触发器的第七引脚接地，所述第一电容的另一端与双脉冲发生电路的第一信号输入端和第二信号输入端中任意一个输入端连接。
整周期控制电路3包括第一电容，该第一电容的一端与双脉冲发生电路的OUTA或者OUTB连接，该第一电筒的另一端与第五施密特触发器的第一引脚、第一电阻的一端连接，第一电阻的另一端接地，第一施密特触发器的第七引脚接地，第一施密特触发器的第十四引脚与电源连接，第一施密特触发器的第二引脚与电子开关电路5的电子开关的A引脚。
第一电阻和第一电容构成微分电路，工作原理与开机复位电路1的微分电路一样。
整周期控制电路3增加了一个第五施密特触发器，第五施密特触发器是实现输入窄脉冲信号的翻转。当检测到UOTA或者OUTB有上升沿时，即不打嗝，电子开关电路5的电子开关的X0引脚和X引脚不接通，反之，电子开关的X0引脚和X引脚接通，即需要进行打嗝控制。
进一步地，所述打嗝控制电路包括第二MOS管和第六施密特触发器，所述第六施密特触发器的第十三引脚经第七电阻采集外部的控制环路的有效信号，所述第六施密特触发器的第十二引脚与所述电子开关电路的X引脚连接，所述第二MOS管的栅极与所述电子开关电路的X0引脚连接，以及经第六电容接地、经第八电阻接地，所述第二MOS管的原极接地，所述第二MOS管的漏极分别与所述脉宽限制电路的第四施密特触发器的第十一引脚、第三电容的一端、第五电阻的一端、第一MOS管的漏极连接。
打嗝控制电路3采集外接的控制环路的有效信号(高电平为正常)，BURST与第七电阻的一端连接，第七电阻的另一端与第六施密特触发器的第十三引脚连接，第六施密特触发器的第十二引脚与电子开关电路5的电 子开关的X引脚连接，第八电阻的一端与第六电容的一端、第二MOS管的栅极、电子开关电路的电子开关的X0引脚连接，第八电阻的另一端与第六电容的另一端连接，以及第八电阻的另一端接地，第二MOS管的原极接地，第二MOS管的漏极与脉宽限制电路连接。
当开关电源出现了打嗝现象时，信号BURST为低电平，经过第六施密特触发器翻转后，呈高电平，而此时，电子开关的A引脚也为高电平，以致电子开关电路5的电子开关的X0引脚和X引脚接通，第二MOS管导通，电压V3变为低电平，第四施密特触发器翻转后，呈高电平，最终电子开关保持输出脉冲OUTA和OUTB至驱动电路，即实现了打嗝控制。
当开关电源出现打嗝现象时，双脉冲发生电路的脉冲的脉宽比较小，不需要进行脉宽限制，可以直接输出。
第六电容和第八电阻的作用是，防止第二MOS管的误导通。
本发明通过增加的整周期控制电路2和打嗝控制电路3，解决了宽范围输入电压开关电源的打嗝问题。
对于宽范围输入电压开关电源，当输入电压高于额定值，电源空载时，常出现打嗝现象。
实施例3
参见图4，图4为本发明开关电源双脉冲脉宽限制电路实施例3的流程图。
为实现上述目的，本发明实施例3还提供了一种开关电源双脉冲脉宽限制电路的实现方法，构建依次连接的双脉冲发生电路、脉宽限制电路、电子开关电路，以及分别与所述脉宽限制电路、电子开关电路连接的开机复位电路，其包括如下步骤；
步骤S10，双脉冲发生电路生成两路互补对称、带死区时间的初始脉冲信号，并将所述初始脉冲信号发送至所述脉宽限制电路。
双脉冲发生电路生成两路互补对称、带很小的死区时间的初始脉冲信号之后，再通过OUTA和OUTB两个输入端分别将初始脉冲信号输出至脉宽限制电路。
步骤S11，脉宽限制电路将所述初始脉冲信号转换为预设脉宽的两路互补的驱动脉冲信号，并将生成的脉冲控制信号发送至电子开关电路。
步骤S12，所述电子开关电路根据接收到的所述脉冲控制信号选择输出通道，将所述预设脉宽的两路互补的驱动脉冲信号输出。
步骤S13，所述开机复位电路控制所述电子开关电路，在开机上电延迟预设时间段后，输出所述预设脉宽的两路互补的驱动脉冲信号。
本发明通过脉宽限制电路4和电子开关电路5，解决了双脉冲的脉宽限制的问题，达到了不受双路脉冲发生源的限制，而能灵活设置被控双路脉冲的脉宽的技术效果。即无论是集成芯片产生的双脉冲，还是控制器产生的双脉冲，本发明均能够灵活的设置被控双脉冲的脉宽。
本发明通过脉宽限制电路4来限制驱动脉冲的宽度，以致开关管工作在安全电流区域内，增长了开关管的使用寿命，降低了开关管的维护成本、以及提高了开关电源的可靠性。
本发明为了确保辅助电源以及其他的控制电路正常工作后，再输出预设脉宽的两路互补的驱动脉冲信号至开关管，因此，开机上电延迟预设时间段后再输出预设脉宽的两路互补的驱动脉冲信号。
实施例4
参见图5，图5为本发明开关电源双脉冲脉宽限制电路实施例4的流程图。
在实施例4中，与上述实施例的步骤基本相同，不同之处在于，所述开关电源双脉冲脉宽限制电路还包括整周期控制电路和打嗝控制电路，所述开关电源双脉冲脉宽限制电路的实现方法还包括如下步骤；
步骤S20，当所述整周期控制电路根据所述初始脉冲信号中任意一个脉冲信号检测到开关电源出现打嗝现象时，发出打嗝触发脉冲信号至电子开关电路；
步骤S21，所述打嗝控制电路采集到外部的控制环路的有效信号，并将所述有效信号发送至所述电子开关电路；
步骤S22，所述电子开关电路根据所述打嗝触发脉冲信号和所述有效信号生成打嗝控制信号，并将所述打嗝控制信号发送至所述打嗝控制电路；
步骤S23，所述打嗝控制电路根据所述打嗝控制信号控制所述脉宽限制电路，以致所述脉宽限制电路输出脉冲控制信号，所述电子开关电路根据脉冲控制信号选择输出通道，输出初始脉冲信号。
对于宽范围输入电压开关电源，当输入电压高于额定值，电源空载时，常出现打嗝现象。
本发明通过增加的整周期控制电路2和打嗝控制电路3，解决了宽范围输入电压开关电源的打嗝问题。
以上对发明的具体实施方式进行了详细说明，但其只作为范例，本发明并不限制与以上描述的具体实施方式。对于本领域的技术人员而言，任何对该发明进行的等同修改或替代也都在本发明的范畴之中，因此，在不脱离本发明的精神和原则范围下所作的均等变换和修改、改进等，都应涵盖在本发明的范围内。

Claims (10)

  1. 一种开关电源双脉冲脉宽限制电路，其特征在于，其包括脉宽限制电路和电子开关电路，所述脉宽限制电路与所述电子开关电路连接；
    所述脉宽限制电路与外部双脉冲发生电路连接，所述外部双脉冲发生电路用于生成两路互补对称、带死区时间的初始脉冲信号，所述脉宽限制电路用于将所述初始脉冲信号转换为预设脉宽的两路互补的驱动脉冲信号，并将生成的脉冲控制信号发送至电子开关电路；
    所述电子开关电路用于根据所述脉冲控制信号选择输出通道，将所述预设脉宽的两路互补的驱动脉冲信号输出。
  2. 根据权利要求1所述的开关电源双脉冲脉宽限制电路，其特征在于，所述开关电源双脉冲脉宽限制电路还包括开机复位电路，所述开机复位电路分别与所述脉宽限制电路、所述电子开关电路连接；
    所述开机复位电路用于控制所述电子开关电路在开机上电延迟预设时间段后，再将所述预设脉宽的两路互补的驱动脉冲信号输出。
  3. 根据权利要求2所述的开关电源双脉冲脉宽限制电路，其特征在于，所述开关电源双脉冲脉宽限制电路还包括整周期控制电路和打嗝控制电路，所述整周期控制电路与所述外部双脉冲发生电路连接，并与所述电子开关电路连接；所述打嗝控制电路与外部控制环路连接，所述外部控制环路用于检测外部开关电源是否出现打嗝现象的有效信号，所述打嗝控制电路分别与所述脉宽限制电路、所述电子开关电路连接；
    所述整周期控制电路，用于通过所述初始脉冲信号中任意一个脉冲信号检测所述外部开关电源是否出现打嗝现象，以及用于生成打嗝触发脉冲信号，并输出到所述电子开关电路；
    所述打嗝控制电路，用于采集所述外部控制环路的有效信号并输出到所述电子开关电路，以及用于根据所述电子开关电路提供的打嗝控制信号控制所述脉宽限制电路；
    所述电子开关电路，用于根据打嗝触发脉冲信号和有效信号生成打嗝控制信号。
  4. 根据权利要求3所述的开关电源双脉冲脉宽限制电路，其特征在于，所述脉宽限制电路与所述外部双脉冲发生电路的第一信号输入端和第二信号输入端连接，所述第一信号输入端与第一二极管的阳极连接，所述第二信号输入端与所述第二二极管的阳极连接，所述第一施密特触发器的第三 引脚分别与第一二极管的阴极、第二二极管的阴极、经第二电阻与第二电容的一端连接，以及经第二电阻接地，所述第一施密特触发器的第四引脚分别与第三二极管的阳极、经第三电阻与第二电容的另一端、经第三电阻与第二施密特触发器的第五引脚、第四二极管的阳极、第三施密特触发器的第九引脚连接，所述第二施密特触发器的第五引脚与第三二极管的阴极连接，所述第二施密特触发器的第六引脚经第四电阻分别与第四二极管的阴极、第一MOS管的栅极连接，所述第三施密特触发器的第九引脚与第四二极管的阳极连接，所述第三施密特触发器的第八引脚经第五电阻分别与第一MOS管的漏极、第三电容的一端、第四施密特触发器的第十一引脚、所述打嗝控制电路连接，所述第一MOS管的原极接地，所述第三电容的另一端接地，所述第四施密特触发器的第十引脚与所述电子开关电路连接。
  5. 根据权利要求4所述的开关电源双脉冲脉宽限制电路，其特征在于，所述电子开关电路具有电子开关，所述电子开关的VEE引脚和VSS引脚以及第四电容的一端接地，所述电子开关的VDD引脚和INH引脚、第四电容的另一端与所述开机复位电路连接，所述电子开关的C引脚和B引脚与脉宽限制电路的第四施密特触发器的第十引脚连接，所述电子开关的A引脚与整周期控制电路连接，所述电子开关的X引脚和X0引脚分别与所述打嗝控制电路连接，所述电子开关的Z1引脚和Y1引脚接地，所述电子开关的Z引脚与PDRA连接，其Y引脚与PDRB连接，其Z0引脚与OUTA连接，其Y0引脚与OUTB连接。
  6. 根据权利要求5所述的开关电源双脉冲脉宽限制电路，其特征在于，所述开机复位电路具有一个电源，所述电源分别与所述电子开关电路的VDD引脚和第四电容一端、第五电容的一端连接，所述第五电容的另一端分别与所述电子开关电路的INH引脚、第五二极管的阴极连接，以及经第六电阻接地，所述第五二极管的阳极接地。
  7. 根据权利要求6所述的开关电源双脉冲脉宽限制电路，其特征在于，所述整周期控制电路具有第五施密特触发器，所述第五施密特触发器的第一引脚与第一电容的一端连接，以及经第一电阻接地，所述第五施密特触发器的第二引脚与所述电子开关电路的A引脚连接，所述第五施密特触发器的第十四引脚与电源连接，所述第五施密特触发器的第七引脚接地，所述第一电容的另一端与双脉冲发生电路的第一信号输入端和第二信号输入 端中任意一个输入端连接。
  8. 根据权利要求6所述的开关电源双脉冲脉宽限制电路，其特征在于，所述打嗝控制电路包括第二MOS管和第六施密特触发器，所述第六施密特触发器的第十三引脚经第七电阻采集外部的控制环路的有效信号，所述第六施密特触发器的第十二引脚与所述电子开关电路的X引脚连接，所述第二MOS管的栅极与所述电子开关电路的X0引脚连接，以及经第六电容接地、经第八电阻接地，所述第二MOS管的原极接地，所述第二MOS管的漏极分别与所述脉宽限制电路的第四施密特触发器的第十一引脚、第三电容的一端、第五电阻的一端、第一MOS管的漏极连接。
  9. 一种开关电源双脉冲脉宽限制电路的实现方法，其特征在于，构建依次连接的双脉冲发生电路、脉宽限制电路、电子开关电路，以及分别与所述脉宽限制电路、电子开关电路连接的开机复位电路,其包括如下步骤:
    双脉冲发生电路生成两路互补对称、带死区时间的初始脉冲信号，并将所述初始脉冲信号发送至所述脉宽限制电路；
    脉宽限制电路将所述初始脉冲信号转换为预设脉宽的两路互补的驱动脉冲信号，并将生成的脉冲控制信号发送至电子开关电路；
    所述电子开关电路根据接收到的所述脉冲控制信号选择输出通道，将所述预设脉宽的两路互补的驱动脉冲信号输出；
    所述开机复位电路控制所述电子开关电路，在开机上电延迟预设时间段后，输出所述预设脉宽的两路互补的驱动脉冲信号。
  10. 根据权利要求9所述的开关电源双脉冲脉宽限制电路的实现方法，其特征在于，所述开关电源双脉冲脉宽限制电路还包括整周期控制电路和打嗝控制电路,所述开关电源双脉冲脉宽限制电路的实现方法还包括如下步骤:
    当所述整周期控制电路根据所述初始脉冲信号中任意一个脉冲信号检测到开关电源出现打嗝现象时，发出打嗝触发脉冲信号至电子开关电路；
    所述打嗝控制电路采集到外部的控制环路的有效信号，并将所述有效信号发送至所述电子开关电路；
    所述电子开关电路根据所述打嗝触发脉冲信号和所述有效信号生成打嗝控制信号，并将所述打嗝控制信号发送至所述打嗝控制电路；
    所述打嗝控制电路根据所述打嗝控制信号控制所述脉宽限制电路，以 致所述脉宽限制电路输出脉冲控制信号，所述电子开关电路根据脉冲控制信号选择输出通道，输出初始脉冲信号。
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