WO2016090682A1 - 覆晶薄膜单元 - Google Patents

覆晶薄膜单元 Download PDF

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Publication number
WO2016090682A1
WO2016090682A1 PCT/CN2014/094884 CN2014094884W WO2016090682A1 WO 2016090682 A1 WO2016090682 A1 WO 2016090682A1 CN 2014094884 W CN2014094884 W CN 2014094884W WO 2016090682 A1 WO2016090682 A1 WO 2016090682A1
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WIPO (PCT)
Prior art keywords
circuit module
driving circuit
signal
flip chip
chip unit
Prior art date
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Ceased
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PCT/CN2014/094884
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English (en)
French (fr)
Inventor
扶伟
陈宥烨
陈胤宏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/416,679 priority Critical patent/US9780023B2/en
Publication of WO2016090682A1 publication Critical patent/WO2016090682A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a flip chip unit.
  • the flip chip (COF, English full name Chip On Flex or Chip On Film) is widely used in the field of liquid crystal display technology. It mainly refers to the die-bonding technology of the die to fix the integrated circuit on the flexible circuit board, and uses the soft additional circuit board as the package chip carrier to bond the chip and the flexible substrate circuit.
  • FIG. 1 shows a flip chip unit of the prior art.
  • a driving circuit module is usually provided in a flip chip unit.
  • the flip chip unit of the prior art comprises a soft dielectric layer 1 and a driving circuit module 2 on the soft dielectric layer 1.
  • the drive circuit module 2 there are corresponding input signals 3 and output signals 4, respectively. Since all the signal channels of the flip chip unit are located in one driving circuit module 2, heat dissipation is very difficult, and the temperature drop is difficult, which is disadvantageous for the maintenance and maintenance of the flip chip unit.
  • the flip-chip thin film unit has difficulty in heat dissipation and cooling, and the present invention proposes an improved flip chip unit, which effectively solves the above problems and brings about new beneficial effects.
  • the present invention provides a flip chip unit comprising: a soft dielectric layer; a plurality of pins for inputting signals on the soft dielectric layer; and a first driving circuit module and a second driving circuit a module, wherein the first driving circuit module is connected to at least a portion of the pin for inputting a signal, and a cascaded trace is disposed between the first driving circuit module and the second driving circuit module In both Establish a cascade signal.
  • the number of signal channels of each driving circuit module can be half of the required number of signal channels of the entire flip chip unit, so that the signal channels can be dispersed on multiple driving circuit modules, which greatly improves the heat dissipation efficiency.
  • the number of the first driving circuit modules is one. Of course this is not limiting.
  • all of the pins for inputting signals are connected to the first driving circuit module to input an input signal into the first driving circuit module, and the input signal passes through the first A cascade signal between the driving circuit module and the second driving circuit module is transmitted to the second driving circuit module.
  • each driver circuit module can receive all the input signals required to complete the function, and output the output signals separately.
  • the input signal and the cascade signal each comprise a power signal, a data signal and a control signal.
  • the input signal comprises a power signal, a data signal and a control signal.
  • the pins for the data signal and the control signal in the input signal are only connected to the first driving circuit module, and the first driving circuit module and the second driving circuit module are both used for a pin of the power signal in the input signal is connected, and a data signal and a control signal in the input signal are transmitted to the The second drive circuit module.
  • each driving circuit module can receive all the input signals required to complete the function, and output the output signals separately; in addition, the power signals in the input signals are separately presented and sent to the first driving circuit module respectively.
  • the second driving circuit module the temperature of the two driving circuit modules can be kept consistent.
  • the cascaded signal comprises a data signal and a control signal. This is because the first driving circuit module and the second driving circuit module have respectively received the power signals in the input signals, and there is no need to transmit the power signals through the cascaded wires.
  • the number of the second driving circuit modules is one.
  • the first driving circuit module and the second driving circuit module are both configured in the form of a chip, and the chip passes through a bump provided on a surface thereof facing the soft dielectric layer side.
  • the pins for the input signal are connected.
  • the cascade of traces is on the soft dielectric layer.
  • the flip chip unit according to the present invention due to the first driving circuit module and the second driving circuit
  • the cascading signals are cleverly set between the circuit modules, which greatly reduces the number of pins, so that the width of each pin can be wider, making the pins stronger, improving the heat dissipation efficiency and reducing the risk of pin breakage. , effectively guarantee the quality of the produced flip chip unit.
  • the problem of temperature unevenness of different drive circuit modules is also solved in particular, ensuring temperature uniformity throughout the flip chip unit.
  • Figure 1 shows a flip chip unit of the prior art
  • Figure 2 shows a first embodiment of a flip chip unit in accordance with the present invention
  • Figure 3 shows a second embodiment of a flip chip unit in accordance with the present invention
  • Figure 4 shows a comparative example of the design to illustrate the advantages of the flip chip unit in accordance with the present invention.
  • Fig. 2 shows a flip chip unit 10 according to the present invention in the first embodiment.
  • the flip chip unit 10 first includes a soft dielectric layer 11.
  • the soft dielectric layer 11 is a flexible carrier, and the material thereof may be, for example, polyimide.
  • a plurality of pins (not shown) for inputting signals are disposed on the flexible dielectric layer 11, and the soft dielectric layer 11 can be used as a carrier film for these pins to facilitate tape and tape transfer.
  • Two driving circuit modules are further disposed on the soft dielectric layer 11, which are a first driving circuit module 12.1 and a second driving circuit module 12.2, respectively.
  • the first drive circuit module 12.1 and the second drive circuit module 12.2 are separated by a certain distance, which can be determined according to the process and the size of the flexible dielectric layer 11.
  • the number of signal channels of each driving circuit module can be half of the number of signal channels required for the entire flip chip unit 10, so that the signal channels can be dispersed on multiple driving circuit modules, thereby greatly improving the heat dissipation efficiency.
  • the flip-chip unit 10 Compared with the prior art design in which only one driving circuit module is disposed on a soft dielectric layer, the flip-chip unit 10 according to the present invention is provided with two driving circuit modules, wherein each driving circuit module
  • the number of signal channels of the block can be half of that of the prior art drive circuit modules (when the signal transmission functions are the same). In this way, the requirements of the signal output can be satisfied, and the driving circuits are respectively arranged in the two modules, and a gap is provided in the middle, thereby improving the heat dissipation efficiency of the entire flip chip unit 10, which is improved compared with the design method in the prior art.
  • the heat dissipation effect is provided with the prior art design in which only one driving circuit module is disposed on a soft dielectric layer.
  • the first driving circuit module 12.1 is connected to all pins (not shown) for inputting signals, and a cascaded trace 15 is disposed between the first driving circuit module 12.1 and the second driving circuit module 12.2. To establish a cascade signal between the two.
  • the cascading traces 15 can be located on the soft dielectric layer 11.
  • the second driver circuit module 12.2 is not connected to the pin.
  • first drive circuit module 12.1 and one second drive circuit block 12.2 are provided.
  • this is merely exemplary, and is used to illustrate the technical effect of increasing the heat dissipation efficiency of the entire flip chip unit by the distributed arrangement of the driving circuit modules of the solution of the present invention.
  • the number of drive circuit modules is not limiting.
  • the first driving circuit module 12.1 and the second driving circuit module 12.2 may each be plural, and the cascade wiring 15 may have different configurations.
  • each of the driving circuit modules can receive all the input signals required to complete the function, and output the output signals 14 respectively.
  • the specific connection manner of the pin for the input signal 13 and the first driving circuit module 12.1 is not shown in FIG. 2, it is easy to understand according to the transmission mode of the input signal 13 and the output signal 14 shown in FIG.
  • the pins for the input signal 13 are all connected to the first driving circuit module 12.1 and not to the second driving circuit module 12.2.
  • the input signals received by the second driver circuit module 12.2 are all from the cascade traces 15 between the first driver circuit module 12.1 and the second driver circuit module 12.2.
  • the input signal 13 and the concatenated signal may include a power supply signal (VAA/VDD/VGM, etc.), a data signal, and a control signal (DIO/POL, etc.).
  • VAA/VDD/VGM power supply signal
  • DIO/POL control signal
  • first driving circuit module 12.1 and the second driving circuit module 12.2 may each be configured in the form of a chip, and the chip may pass through a bump provided on a surface thereof facing the side of the soft dielectric layer 11 and used for inputting The pins of the incoming signal 13 are connected.
  • the chip and the soft dielectric layer 11 can be fixed to each other by a filling glue.
  • Fig. 3 shows a flip chip unit 20 according to the present invention in the second embodiment.
  • the flip chip unit 20 first includes a soft dielectric layer 21.
  • a plurality of pins (not shown) for inputting signals are disposed on the flexible dielectric layer 21, and the soft dielectric layer 21 can be used as a carrier film for these pins.
  • Two driving circuit modules are further disposed on the soft dielectric layer 21, which are a first driving circuit module 22.1 and a second driving circuit module 22.2, respectively.
  • the first driving circuit module 22.1 and the second driving circuit module 22.2 are separated by a certain distance.
  • a cascaded trace 25 is provided between the first driver circuit module 22.1 and the second driver circuit module 22.2 to establish a cascade signal therebetween.
  • the cascading traces 25 can be located on the soft dielectric layer 21.
  • first drive circuit module 22.1 and one second drive circuit block 22.2 are provided in the second embodiment shown in Fig. 3.
  • the first driving circuit module 22.1 and the second driving circuit module 22.2 may each be plural, and the cascaded wires 25 may have different configurations.
  • the input signals include a power supply signal (VAA/VDD/VGM, etc.), a data signal, and a control signal (DIO/POL, etc.).
  • VAA/VDD/VGM power supply signal
  • DIO/POL control signal
  • the data signal and the control signal 23 in the input signal are only input to the first driving circuit module 22.1, and the power signals 23, 26 in the input signal are input to the first driving circuit module 22.1 and the second, respectively.
  • Drive circuit module 22.2 The data signal and the control signal in the input signal are passed to the second driver circuit module 22.2 through the cascade signal between the first driver circuit module 22.1 and the second driver circuit module 22.2.
  • the pins for the data signal and the control signal in the input signal are only connected to the first driver circuit module 22.1, and the first driver circuit module 22.1 and the second driver circuit module 22.2. They are connected to different pins for the power signal in the input signal.
  • a cascaded trace 25 is provided between the first driver circuit module 22.1 and the second driver circuit module 22.2 to establish a cascade signal between the two.
  • the cascade signal established between the first driving circuit module 22.1 and the second driving circuit module 22.2 mainly includes a data signal and a control signal because the first driving circuit module 22.1 and the second driving circuit module 22.2 have respectively received the input signals.
  • the power signal does not need to pass the cascaded trace 25 to pass the signal.
  • the data signal and the control signal received by the first driving circuit module 22.1 are transmitted to the second driving power through the cascaded trace 25 between the first driving circuit module 22.1 and the second driving circuit module 22.2.
  • each driving circuit module can receive all the input signals required to complete the function, and output the output signals 24 respectively.
  • the first driving circuit module 22.1 and the second driving circuit module 22.2 are both configured in the form of a chip, and the chip can be designed
  • the bumps on the surface thereof facing the side of the soft dielectric layer 21 are connected to the leads for the input signals 23, 26.
  • the chip and the soft dielectric layer 21 can be fixed to each other by a filling glue.
  • the main difference of the second embodiment is that the power signals in the input signals are separately presented and delivered to the first driving circuit module 22.1 and the second driving circuit module 22.2, respectively.
  • the first driving circuit module 12.1 receives the power supply signal, that is, only the first driving circuit module 12.1 is connected to the power supply pin, and the second driving circuit module 12.2 is not connected to the power supply pin, which causes The temperature of the first driving circuit module 12.1 is higher than that of the second driving circuit module 12.2, resulting in uneven temperature in the entire flip chip unit 10.
  • the second embodiment is further improved on this problem, and the power signals in the input signal are separately presented and sent to the first driving circuit module 22.1 and the second driving circuit module 22.2, respectively, so that the two driving The temperature balance of the circuit module.
  • the flip chip unit 20 of the second embodiment still achieves the advantages of increasing heat dissipation efficiency and improving the temperature lowering effect, compared to the prior art flip chip unit described in the background section.
  • FIG. 4 shows a comparative example of a flip chip unit 30 designed to illustrate the advantages of a flip chip unit in accordance with the present invention.
  • the flip chip unit 30 in the comparative example first includes the soft dielectric layer 31.
  • a plurality of pins (not shown) for inputting signals are disposed on the flexible dielectric layer 31.
  • Two driving circuit modules are further disposed on the soft dielectric layer 31, which are a first driving circuit module 32.1 and a second driving circuit module 32.2, respectively.
  • the first driving circuit module 32.1 and the second driving circuit module 32.2 are separated by a certain distance.
  • the first driving circuit module 32.1 and the second driving circuit module 32.2 of the flip-chip unit 30 in the comparative example are both for the pins for all input signals (Fig. Connected in the middle, and no cascaded traces are provided between the first drive circuit module 32.1 and the second drive circuit module 32.2.
  • the first drive circuit module 32.1 and the second drive circuit module 32.2 independently receive all of the input signals 33, respectively.
  • input signal 33 may include a power signal, a data signal, and a control signal.
  • the first drive circuit module 32.1 and the second drive circuit module 32.2 independently output the output signal 34, respectively.
  • the dispersed driving circuit module is provided (with the same signal transmission function, each of the comparative examples)
  • the number of signal channels of the driving circuit module is also half of that in the prior art), and the problem of difficulty in cooling and cooling is solved, but since the two driving circuit modules require two sets of input signals, the ratio of the flip chip unit 30 is required.
  • the number of pins for the input signal is twice that of the flip chip unit 10 (shown in FIG. 2) of the first embodiment of the present invention, because in the first embodiment, all input signals are cascaded.
  • the signal is input to the second drive circuit block 12.2, not through the pin.
  • the number of pins for the input signal required by the flip chip unit 30 of the comparative example is also much larger, and the extra number corresponds to the data signal in one input signal and The number of pins corresponding to the control signal is because they are input to the second drive circuit block 22.2 through the cascade signal instead of the pass pins in the second embodiment.
  • the flip chip unit 10, 20 of the present invention since the cascading signal is skillfully set between the first driving circuit module and the second driving circuit module, the number of pins is greatly reduced with respect to the contrast ratio, thereby The width of each pin can be wider, which makes the pins stronger, which improves the heat dissipation efficiency and reduces the risk of pin breakage, thus ensuring the quality of the flip chip unit produced.
  • the second embodiment according to a further improvement of the present invention in particular, also solves the problem of temperature unevenness of different driving circuit modules, ensuring temperature uniformity in the entire flip chip unit.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种覆晶薄膜单元（10），包括：软质介电层（11）；位于软质介电层（11）上的多个用于输入信号的引脚；以及第一驱动电路模块（12.1）和第二驱动电路模块（12.2），第一驱动电路模块（12.1）与至少一部分用于输入信号的引脚相连，且在第一驱动电路模块（12.1）和第二驱动电路模块（12.2）之间设置有级联走线（15）以在二者之间建立级联信号。每个驱动电路模块（12.1，12.2）的信号通道数量可以为整个覆晶薄膜单元（10）信号通道需求数量的一半，如此可以将信号通道分散在多个驱动电路模块（12.1，12.2）上，大大提升了散热效率。

Description

覆晶薄膜单元
相关申请的交叉引用
本申请要求享有于2014年12月10日提交的名称为“覆晶薄膜单元”的中国专利申请CN201410751795.X的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种覆晶薄膜单元。
背景技术
覆晶薄膜(COF，英文全称为Chip On Flex或Chip On Film)广泛地应用于液晶显示技术领域。其主要指将集成电路固定于柔性线路板上的晶粒软膜构装技术，运用软质附加电路板作封装芯片载体，从而将芯片与软性基板电路接合。
图1显示了现有技术中的覆晶薄膜单元。在现有技术中，通常在一个覆晶薄膜单元中设置一个驱动电路模块。然而这种情况不利于散热降温。如图1所示，现有技术中的覆晶薄膜单元包括一个软质介电层1，以及位于软质介电层1上的驱动电路模块2。针对该驱动电路模块2，相应地有输入信号3和输出信号4。由于该覆晶薄膜单元的全部的信号通道都位于一个驱动电路模块2中，散热非常困难，降温难度大，不利于覆晶薄膜单元的保持与维护。
发明内容
针对现有技术中的覆晶薄膜单元散热降温困难的缺陷，本发明提出了一种改进的覆晶薄膜单元，有效解决了上述问题，同时还带来了新的有益效果。
本发明提出了一种覆晶薄膜单元，包括：软质介电层；位于所述软质介电层上的多个用于输入信号的引脚；以及第一驱动电路模块和第二驱动电路模块，其中，所述第一驱动电路模块与至少一部分所述用于输入信号的引脚相连，且在所述第一驱动电路模块和所述第二驱动电路模块之间设置有级联走线以在二者之 间建立级联信号。
每个驱动电路模块的信号通道数量可以为整个覆晶薄膜单元信号通道需求数量的一半，如此可以将信号通道分散在多个驱动电路模块上，大大提升了散热效率。
优选地，所述第一驱动电路模块的数量为一个。当然这并非限定性的。
优选地，全部的所述用于输入信号的引脚均与所述第一驱动电路模块相连，以将输入信号输入到所述第一驱动电路模块中，同时所述输入信号通过所述第一驱动电路模块和所述第二驱动电路模块之间的级联信号传递至所述第二驱动电路模块。如此可实现每个驱动电路模块都可以接收到完成功能所需的全部输入信号，并分别输出输出信号。
优选地，所述输入信号和所述级联信号均包括电源信号、数据信号和控制信号。
优选地，所述输入信号包括电源信号、数据信号和控制信号。优选地，用于所述输入信号中的数据信号和控制信号的引脚仅与所述第一驱动电路模块相连，而所述第一驱动电路模块和所述第二驱动电路模块均和用于所述输入信号中的电源信号的引脚相连，所述输入信号中的数据信号和控制信号通过所述第一驱动电路模块和所述第二驱动电路模块之间的级联信号传递至所述第二驱动电路模块。如此地，首先可以实现每个驱动电路模块都可以接收到完成功能所需的全部输入信号，并分别输出输出信号；另外，将输入信号中的电源信号单独提出来分别输送到第一驱动电路模块和第二驱动电路模块中，可以使得两个驱动电路模块的温度保持一致。
优选地，所述级联信号包括数据信号和控制信号。这是因为第一驱动电路模块和第二驱动电路模块已经分别接收了输入信号中的电源信号，不需要再通过级联走线传递电源信号。
优选地，所述第二驱动电路模块的数量为一个。
优选地，所述第一驱动电路模块和所述第二驱动电路模块均构造为芯片的形式，且所述芯片通过设于其朝向所述软质介电层一侧的表面上的凸块与所述用于输入信号的引脚相连。
优选地，所述级联走线位于所述软质介电层上。
另外，根据本发明的覆晶薄膜单元，由于在第一驱动电路模块和第二驱动电 路模块之间巧妙地设置了级联信号，大大降低了引脚的数量，从而每个引脚的宽度可以更宽，使得引脚更加牢固，在提升散热效率的同时降低了引脚断裂的风险，有效保证了所生产的覆晶薄膜单元的品质。同时，根据本发明的进一步的改进，尤其还解决了不同的驱动电路模块温度不均的问题，保证了整个覆晶薄膜单元内的温度均匀性。
上述技术特征可以各种适合的方式组合或由等效的技术特征来替代，只要能够达到本发明的目的。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1显示了现有技术中的覆晶薄膜单元；
图2显示了根据本发明的覆晶薄膜单元的第一实施例；
图3显示了根据本发明的覆晶薄膜单元的第二实施例；以及
图4显示了设计的对比例，用以说明根据本发明的覆晶薄膜单元的优点。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例绘制。
具体实施方式
下面将结合附图对本发明作进一步说明。
图2显示了第一实施例中的根据本发明的覆晶薄膜单元10。通过图2可明显看出，覆晶薄膜单元10首先包括软质介电层11。软质介电层11为柔性载体，其材质例如可为聚酰亚胺。
在软质介电层11上设置有多个用于输入信号的引脚(图中未示出)，软质介电层11可用来作为这些引脚的载膜，以利于卷带式传输。
在软质介电层11上还设置有两个驱动电路模块，分别为第一驱动电路模块12.1和第二驱动电路模块12.2。第一驱动电路模块12.1和第二驱动电路模块12.2之间相隔一定距离，这可以根据工艺和软质介电层11的尺寸来决定。每个驱动电路模块的信号通道数量可以为整个覆晶薄膜单元10信号通道需求数量的一半，如此可以将信号通道分散在多个驱动电路模块上，大大提升了散热效率。
相比于现有技术中在一块软质介电层上仅设置一个驱动电路模块的设计，根据本发明的覆晶薄膜单元10中设置有两个驱动电路模块，其中每个驱动电路模 块的信号通道数量可为现有技术中的驱动电路模块的一半(信号传输功能相同的情况下)。如此既能够满足信号输出的需求，同时将驱动电路分别布置在两个模块中，并在中间设置间隙，提高了整个覆晶薄膜单元10的散热效率，与现有技术中的设计方式相比提升了散热效果。
第一驱动电路模块12.1与所有的用于输入信号的引脚(图中未示出)相连，且在第一驱动电路模块12.1和第二驱动电路模块12.2之间设置有级联走线15，以在二者之间建立级联信号。级联走线15可以位于软质介电层11上。第二驱动电路模块12.2不与引脚相连。
在图2所示的第一实施例中，仅设置了一个第一驱动电路模块12.1和一个第二驱动电路模块12.2。当然，这仅仅为示例性的，用来说明本发明的方案的通过分散布置的驱动电路模块来增加整个覆晶薄膜单元的散热效率的技术效果。驱动电路模块的数量并非限定性的。只要技术条件适合，且软质介电层11的尺寸适合，第一驱动电路模块12.1和第二驱动电路模块12.2均可以为多个，级联走线15也可以有不同的构造。
在图2所示的覆晶薄膜单元10中，全部的用于输入信号13的引脚均与第一驱动电路模块12.1相连。这样做的目的是，将输入信号13输入到第一驱动电路模块12.1中，同时该输入信号13通过位于第一驱动电路模块12.1和第二驱动电路模块12.2之间的级联信号传递至第二驱动电路模块12.2。具体地，可通过走线15来实现该级联信号。如此可实现，每个驱动电路模块都可以接收到完成功能所需的全部输入信号，并分别输出输出信号14。
另外，虽然图2中并未显示出用于输入信号13的引脚与第一驱动电路模块12.1的具体连接方式，但是根据图2所示的输入信号13和输出信号14的传递方式，容易理解，用于输入信号13的引脚均全部与第一驱动电路模块12.1相连，而不与第二驱动电路模块12.2相连。换言之，第二驱动电路模块12.2所接收到的输入信号全部来自第一驱动电路模块12.1和第二驱动电路模块12.2之间的级联走线15。
具体地，输入信号13和该级联信号可包括电源信号(VAA/VDD/VGM等)、数据信号和控制信号(DIO/POL等)。
另外，第一驱动电路模块12.1和第二驱动电路模块12.2均可构造为芯片的形式，且该芯片可通过设于其朝向软质介电层11一侧的表面上的凸块与用于输 入信号13的引脚相连。芯片和软质介电层11之间可通过填充胶彼此固定。
图3显示了第二实施例中的根据本发明的覆晶薄膜单元20。通过图3可明显看出，覆晶薄膜单元20首先包括软质介电层21。在软质介电层21上设置有多个用于输入信号的引脚(图中未示出)，软质介电层21可用来作为这些引脚的载膜。
在软质介电层21上还设置有两个驱动电路模块，分别为第一驱动电路模块22.1和第二驱动电路模块22.2。第一驱动电路模块22.1和第二驱动电路模块22.2之间相隔一定距离。
第一驱动电路模块22.1和第二驱动电路模块22.2之间设置有级联走线25，以在二者之间建立级联信号。级联走线25可以位于软质介电层21上。
在图3所示的第二实施例中，仅设置了一个第一驱动电路模块22.1和一个第二驱动电路模块22.2。当然，这仅仅为示例性的，并非限定性的。只要技术条件适合，且软质介电层21的尺寸适合，第一驱动电路模块22.1和第二驱动电路模块22.2均可以为多个，级联走线25也可以有不同的构造。
在图3所示的覆晶薄膜单元20中，输入信号包括电源信号(VAA/VDD/VGM等)、数据信号和控制信号(DIO/POL等)。其中如图所示，输入信号中的数据信号和控制信号23仅输入到第一驱动电路模块22.1中，而输入信号中的电源信号23、26则分别输入到第一驱动电路模块22.1和第二驱动电路模块22.2中。输入信号中的数据信号和控制信号通过第一驱动电路模块22.1和第二驱动电路模块22.2之间的级联信号传递至第二驱动电路模块22.2。
从结构上讲，上述技术方案可以有许多具体的实施方式。在图3所示的第二实施例中，用于输入信号中的数据信号和控制信号的引脚仅与第一驱动电路模块22.1相连，而第一驱动电路模块22.1和第二驱动电路模块22.2分别与不同的用于输入信号中的电源信号的引脚相连。同时在第一驱动电路模块22.1和第二驱动电路模块22.2之间设置有级联走线25，以在二者之间建立级联信号。
第一驱动电路模块22.1和第二驱动电路模块22.2之间设立的级联信号主要包括数据信号和控制信号，因为第一驱动电路模块22.1和第二驱动电路模块22.2已经分别接收了输入信号中的电源信号，不需要再通过级联走线25来传递信号。如此地，第一驱动电路模块22.1所接收到的数据信号和控制信号通过位于第一驱动电路模块22.1和第二驱动电路模块22.2之间的级联走线25传递至第二驱动电 路模块22.2中，以实现每个驱动电路模块都可以接收到完成功能所需的全部输入信号，并分别输出输出信号24。
类似于图2所示的第一实施例，在图3所示的第二实施例中，第一驱动电路模块22.1和第二驱动电路模块22.2均构造为芯片的形式，且该芯片可通过设于其朝向软质介电层21一侧的表面上的凸块与用于输入信号23、26的引脚相连。芯片和软质介电层21之间可通过填充胶彼此固定。
与第一实施例相比，第二实施例主要的不同之处是将输入信号中的电源信号单独提出来，分别输送到第一驱动电路模块22.1和第二驱动电路模块22.2中。
在第一实施例中，仅仅第一驱动电路模块12.1接收到电源信号，即仅第一驱动电路模块12.1与电源引脚相连，而第二驱动电路模块12.2不与电源引脚相连，这会造成第一驱动电路模块12.1的温度高于第二驱动电路模块12.2，从而造成整个覆晶薄膜单元10内温度不均匀。而第二实施例正是针对此问题作了进一步的改进，将输入信号中的电源信号单独提出来，分别输送到第一驱动电路模块22.1和第二驱动电路模块22.2中，以使得两个驱动电路模块的温度平衡。同时，相对于背景技术部分所介绍的现有技术中的覆晶薄膜单元而言，第二实施例中的覆晶薄膜单元20仍然实现了增加散热效率、提高降温效果的优点。
图4显示了设计的对比例的覆晶薄膜单元30，用来说明根据本发明的覆晶薄膜单元的优点。从图4可明显看出，对比例中的覆晶薄膜单元30首先包括软质介电层31。在软质介电层31上设置有多个用于输入信号的引脚(图中未示出)。
在软质介电层31上还设置有两个驱动电路模块，分别为第一驱动电路模块32.1和第二驱动电路模块32.2。第一驱动电路模块32.1和第二驱动电路模块32.2之间相隔一定距离。
与本发明的覆晶薄膜单元10、20不同的是，对比例中的覆晶薄膜单元30的第一驱动电路模块32.1和第二驱动电路模块32.2均与用于全部输入信号的引脚(图中未示出)相连，且在第一驱动电路模块32.1和第二驱动电路模块32.2之间未设置有级联走线。
在对比例中，第一驱动电路模块32.1和第二驱动电路模块32.2分别独立地接收全部的输入信号33。具体地，输入信号33可包括电源信号、数据信号和控制信号。同时，第一驱动电路模块32.1和第二驱动电路模块32.2分别独立地输出输出信号34。
通过对比可以发现，在对比例的覆晶薄膜单元30中，相对于现有技术的覆晶薄膜单元，虽然也通过设置分散的驱动电路模块(具有同等信号输送功能的条件下，对比例中每个驱动电路模块的信号通道数量也是现有技术中的一半)而解决了散热降温困难的问题，但是由于其两个驱动电路模块需要两组输入信号，因此对比例的覆晶薄膜单元30所需要的用于输入信号的引脚数量是本发明的第一实施例的覆晶薄膜单元10(图2所示)的两倍，因为在第一实施例中，所有的输入信号都是通过级联信号输入到第二驱动电路模块12.2的，而非通过引脚。同理地，相比于第二实施例，对比例的覆晶薄膜单元30所需要的用于输入信号的引脚数量也多出许多，多出的数量对应于一份输入信号中数据信号和控制信号所对应的引脚数，因为在第二实施例中它们是通过级联信号输入到第二驱动电路模块22.2的，而非通过引脚。
在有限空间的软质介电层上，引脚的数量越多，意味着每个引脚的宽度就必须越短。引脚的宽度变短，会相应增加引脚断裂的风险，因为在运输或组装的过程中，振动或拉扯都有造成引脚断裂的可能性。
而反观根据本发明的覆晶薄膜单元10、20，由于在第一驱动电路模块和第二驱动电路模块之间巧妙地设置了级联信号，相对于对比例大大降低了引脚的数量，从而每个引脚的宽度可以更宽，使得引脚更加牢固，在提升散热效率的同时降低了引脚断裂的风险，有效保证了所生产的覆晶薄膜单元的品质。同时，根据本发明的进一步改进的第二实施例尤其还解决了不同的驱动电路模块温度不均的问题，保证了整个覆晶薄膜单元内的温度均匀性。
虽然已经参考优选实施例对本发明进行了描述，但在不脱离本发明的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (16)

  1. 覆晶薄膜单元，其中，包括：
    软质介电层；
    位于所述软质介电层上的多个用于输入信号的引脚；以及
    第一驱动电路模块和第二驱动电路模块，
    其中，所述第一驱动电路模块与至少一部分所述用于输入信号的引脚相连，且在所述第一驱动电路模块和所述第二驱动电路模块之间设置有级联走线以在二者之间建立级联信号。
  2. 根据权利要求1所述的覆晶薄膜单元，其中，所述第一驱动电路模块的数量为一个。
  3. 根据权利要求2所述的覆晶薄膜单元，其中，全部的所述用于输入信号的引脚均与所述第一驱动电路模块相连，以将输入信号输入到所述第一驱动电路模块中，同时所述输入信号通过所述第一驱动电路模块和所述第二驱动电路模块之间的级联信号传递至所述第二驱动电路模块。
  4. 根据权利要求3所述的覆晶薄膜单元，其中，所述输入信号和所述级联信号均包括电源信号、数据信号和控制信号。
  5. 根据权利要求2所述的覆晶薄膜单元，其中，所述输入信号包括电源信号、数据信号和控制信号。
  6. 根据权利要求5所述的覆晶薄膜单元，其中，用于所述输入信号中的数据信号和控制信号的引脚仅与所述第一驱动电路模块相连，而所述第一驱动电路模块和所述第二驱动电路模块均和用于所述输入信号中的电源信号的引脚相连，所述输入信号中的数据信号和控制信号通过所述第一驱动电路模块和所述第二驱动电路模块之间的级联信号传递至所述第二驱动电路模块。
  7. 根据权利要求6所述的覆晶薄膜单元，其中，所述级联信号包括数据信号和控制信号。
  8. 根据权利要求1所述的覆晶薄膜单元，其中，所述第二驱动电路模块的数量为一个。
  9. 根据权利要求3所述的覆晶薄膜单元，其中，所述第二驱动电路模块的数量为一个。
  10. 根据权利要求5所述的覆晶薄膜单元，其中，所述第二驱动电路模块的数量为一个。
  11. 根据权利要求1所述的覆晶薄膜单元，其中，所述第一驱动电路模块和所述第二驱动电路模块均构造为芯片的形式，且所述芯片通过设于其朝向所述软质介电层一侧的表面上的凸块与所述用于输入信号的引脚相连。
  12. 根据权利要求3所述的覆晶薄膜单元，其中，所述第一驱动电路模块和所述第二驱动电路模块均构造为芯片的形式，且所述芯片通过设于其朝向所述软质介电层一侧的表面上的凸块与所述用于输入信号的引脚相连。
  13. 根据权利要求5所述的覆晶薄膜单元，其中，所述第一驱动电路模块和所述第二驱动电路模块均构造为芯片的形式，且所述芯片通过设于其朝向所述软质介电层一侧的表面上的凸块与所述用于输入信号的引脚相连。
  14. 根据权利要求1所述的覆晶薄膜单元，其中，所述级联走线位于所述软质介电层上。
  15. 根据权利要求3所述的覆晶薄膜单元，其中，所述级联走线位于所述软质介电层上。
  16. 根据权利要求5所述的覆晶薄膜单元，其中，所述级联走线位于所述软质介电层上。
PCT/CN2014/094884 2014-12-10 2014-12-25 覆晶薄膜单元 Ceased WO2016090682A1 (zh)

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