WO2016090621A1 - Procédé et dispositif de stockage de données - Google Patents

Procédé et dispositif de stockage de données Download PDF

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Publication number
WO2016090621A1
WO2016090621A1 PCT/CN2014/093653 CN2014093653W WO2016090621A1 WO 2016090621 A1 WO2016090621 A1 WO 2016090621A1 CN 2014093653 W CN2014093653 W CN 2014093653W WO 2016090621 A1 WO2016090621 A1 WO 2016090621A1
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data
target
ber
written
page
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PCT/CN2014/093653
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English (en)
Chinese (zh)
Inventor
徐君
杨伟
刘海燕
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华为技术有限公司
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Priority to CN201480036916.0A priority Critical patent/CN106415502B/zh
Priority to PCT/CN2014/093653 priority patent/WO2016090621A1/fr
Publication of WO2016090621A1 publication Critical patent/WO2016090621A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes

Definitions

  • the present invention relates to the field of data storage and, more particularly, to a method and apparatus for data storage.
  • SSDs solid state drives
  • SLC single-level storage unit
  • MLC multi-state storage unit
  • MSB Most Significant Bit
  • LSB Least Significant Bit
  • Flash memory represents stored data based on how much electrons are stored in its floating gate electrode.
  • the data states exhibited by the memory cells are "00", “01", “10” and “11", respectively.
  • the error rate of the flash memory is related to the data state represented in the memory unit of the flash memory, that is, the different data states exhibited by the memory cells have different bit error rates (BER), and the main causes of the bit error rate are also Not the same.
  • the flash page in flash memory is a read-write unit, and the types of flash pages include MSB pages and LSB pages.
  • the existing data storage method writes data written to a flash page based on an Error Correction Code (ECC) algorithm, and corrects errors in the data according to the ECC algorithm.
  • ECC Error Correction Code
  • the method uses a fixed ECC algorithm and error correction bits to correct the errored data and uses fixed ECC error correction capability. This method cannot match the appropriate error correction capability, which causes the error correction capability of the ECC algorithm to be wasted, thus resulting in a large amount of calculation of the error correction.
  • Embodiments of the present invention provide a data storage method and apparatus, which can reduce the calculation amount of data error correction on the basis of ensuring data correctness.
  • a method of data storage is provided, the method being applied to a non-volatile memory
  • the method includes: receiving a write request, the write request including data to be written and an address; determining a type of the target flash page according to the address, wherein the target flash page stores the to-be-written in the non-volatile memory a flash page of data; calculating a predicted bit error rate BER of the target flash page according to the determined type of the target flash page and the data to be written; determining a target of the data to be written according to the predicted BER of the target flash page
  • the error correction code ECC algorithm and the target error correction bit number; the data to be written is written to the target flash page according to the determined target ECC algorithm and the target error correction bit number.
  • the target error correction code ECC algorithm and the target error correction bit number of the data to be written are determined according to the predicted BER of the target flash page, including Determining the target ECC algorithm of the data to be written and the target error correction bit according to the predicted BER of the target flash page and the preset correspondence between the predicted BER of the target flash page and the error correction capability information,
  • the error correction capability information includes an ECC algorithm and an error correction bit number.
  • the predicted bit error rate BER of the target flash page includes: calculating a predicted BER of the target flash page according to a type of the target flash page and the to-be-written data by using a BER calculation method corresponding to the type of the target flash page.
  • the BER is calculated as: The B MSB is the predicted BER of the MSB page; the P 00 is the proportion of the 00 in the data to be written; the P 10 is the proportion of 10 in the data to be written; The BER of the left-biased error for the preset write 00; A BER with a right-biased error occurs for a preset write of 10.
  • the BER is calculated as: The B LSB is the predicted BER of the LSB page; the P 11 is the proportion of the 11 to be written data; the P 10 is the proportion of the 10 to be written data; the P 00 is the waiting The proportion of 00 in the written data; the P 01 is the proportion of 01 in the data to be written; The BER of the right-biased error occurs for the preset write 11; a BER that causes a left-biased error for a preset write of 10; The BER of the right-biased error occurs for the preset write 00; The BER of the left-biased error occurs for the preset write 01.
  • the data to be written is written to the target flash page according to the determined target ECC algorithm and the target error correction bit number
  • the method includes: recording the target ECC algorithm and the target error correction bit number.
  • a device configured to apply to a non-volatile memory, comprising: a receiving module, configured to receive a write request, the write request includes data and an address to be written; and a type determining module, configured to The address determines a type of the target flash page, wherein the target flash page is a flash page in the non-volatile memory that stores the data to be written; and a calculation module, configured to determine, according to the type, the target flash page determined by the module Type and the data to be written, calculating a predicted bit error rate BER of the target flash page; an algorithm determining module, configured to determine a target error correction code ECC algorithm and target of the to-be-written data according to the predicted BER of the target flash page An error correction bit; a writing module, configured to write the data to be written to the target flash page according to the target ECC algorithm determined by the algorithm determining module and the target error correction bit number.
  • a receiving module configured to receive a write request, the write request includes data and an address to be written
  • the algorithm determining module is specifically configured to: predict a BER according to the target flash page, and predict BER and error correction according to the preset target flash page Corresponding relationship of the capability information, the target ECC algorithm of the data to be written and the target error correction bit number are determined, and the error correction capability information includes an ECC algorithm and an error correction bit number.
  • the calculating module is specifically configured to: according to the type of the target flash page and the to-be-written The incoming data is calculated by the BER calculation method corresponding to the type of the target flash page, and the predicted BER of the target flash page is calculated.
  • the calculating module is specifically configured to: calculate according to the BER the way: Calculating a predicted BER of the target flash page, wherein the B MSB is a predicted BER of the MSB page; the P 00 is a proportion of 00 in the to-be-written data; the P 10 is 10 of the to-be-written data Ratio The BER of the left-biased error for the preset write 00; A BER with a right-biased error occurs for a preset write of 10.
  • the calculating module is specifically configured to: calculate according to the BER the way: Calculating a predicted BER of the target flash page, wherein the B LSB is a predicted BER of the LSB page; the P 11 is a proportion of the 11 to be written data; the P 10 is 10 of the to-be-written data ratio; P 00 the proportion of the write data to be for 00; P 01 for the data to be written to the proportion of 01; the The BER of the right-biased error occurs for the preset write 11; a BER that causes a left-biased error for a preset write of 10; The BER of the right-biased error occurs for the preset write 00; The BER of the left-biased error occurs for the preset write 01.
  • the fifth possible implementation manner of the second aspect further includes: a recording module, Used to record the target ECC algorithm and the target number of error correction bits.
  • the bit error rate is predicted for the data to be written to the flash page, the appropriate ECC algorithm and the number of error correction bits are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data entered into the flash page is written to the flash page to facilitate error correction of the data in which the error occurred.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, thereby saving the error correction capability of the ECC algorithm and reducing the calculation amount of error correction on the basis of ensuring the correctness of the data.
  • FIG. 1 is a schematic diagram of an error model of a data state of a flash memory cell of the present invention.
  • FIG. 2 is a schematic flow chart of a method of data storage according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a method for data storage according to another embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method of data storage according to an embodiment of the present invention.
  • FIG. 5 is a schematic block diagram of an apparatus in accordance with one embodiment of the present invention.
  • Figure 6 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention.
  • FIG. 1 is a schematic diagram of an error model of a data state of a flash memory cell of the present invention.
  • the flash memory represents the stored data according to the amount of electrons stored in its floating gate electrode. of.
  • the data states exhibited by the memory cells are "00", “01", “10” and “11", respectively.
  • the error rate of the flash memory is related to the data state represented in the memory unit of the flash memory, that is, the different data states exhibited by the memory cells have different bit error rates (BER), and the main causes of the bit error rate are also Not the same.
  • the flash page in flash memory is a read-write unit, and the types of flash pages include MSB pages and LSB pages.
  • the two main errors are errors and programming errors caused by leakage.
  • the abscissa V is a voltage value expressed by a memory cell
  • the ordinate P is a distribution of cells.
  • the leakage error will cause the electrons in the memory cell to leak, causing the voltage to drop, causing the data state to shift to the left.
  • This error is a left-biased error. Due to the repeated program erase of the flash chip and the programming operation of the nearby chip, the electrons in the flash memory chip rise, and the data state is right-biased. This error is a right-bias error.
  • FIG. 2 is a schematic flow chart of a method of data storage according to an embodiment of the present invention.
  • the method of Figure 2 can be performed by the apparatus shown in Figure 5, which can be a non-volatile memory.
  • the method includes:
  • 201 Receive a write request, where the write request includes data to be written and an address.
  • Flash memory pages are used to read data or write data.
  • a write request can be received, which can include data to be written and an address.
  • the target flash page is a flash page in the non-volatile memory that stores the data to be written.
  • the data to be written can be written to different types of flash pages according to the address in the write request.
  • the types of flash pages include MSB pages and LSB pages.
  • An error may occur during the writing process, which may be a left-biased error or a right-biased error.
  • the written data should be "10".
  • a right-biased error occurs, the written data becomes "00", that is, the data "1" written to the MSB page is changed to a right-off error to become "0".
  • the type of target flash page may be a flash page for storing different bit data.
  • the type of the target flash page is related to the number of bit data storable by each storage unit in the target flash page. If the bit data storable by each storage unit in the target flash page is 2-bit data, the data to be written is
  • the bit data respectively written in each storage unit of the target flash page may include high-order bit data, that is, Most Significant Bit (MSB) data and low-order bit data, that is, Least Significant Bit (referred to as Least Significant Bit). LSB).
  • the type of the target flash page may include an MSB page for storing MSB data and an LSB page for storing LSB data.
  • bit data that can be stored in each storage unit of the target flash page is data of 4 or more bits
  • the bit data of each storage unit in the target flash page respectively written in the data to be written may further include other Bit data of the bit, correspondingly, the type of the target flash page may further include a flash page for storing the other bit data.
  • the type of flash page can be determined based on the address in the write request.
  • the bit error rate (BER) of this type of flash page can be predicted based on the type of flash page determined by the data and address to be written.
  • the predicted bit error rate of the flash page can be the predicted bit error rate of the MSB page or the predicted bit error rate of the LSB page.
  • the different types of flash pages may correspond to different computing methods.
  • the different calculation methods are divided into a calculation method of the prediction bit error rate corresponding to the MSB page and a calculation method of the prediction bit error rate corresponding to the LSB page.
  • the BER of the target flash page is calculated according to the type of the target flash page and the data to be written. For example, according to the type of the target flash page, combined with the specific content of the data to be written, the calculation is performed.
  • the BER of the target flash page may be a distribution of different data types in the data to be written, and the different data types may be different bit data, such as a specific distribution of 0 and 1.
  • the BER of the target flash page may also be a Content Dependent Bit Error Rate (CDBER).
  • CDBER Content Dependent Bit Error Rate
  • the BER of the target flash page may be calculated, for example, according to the type of the target flash page and the distribution of different types of data in the data to be written, such as the distribution of 11, 10, 01, and 00. .
  • the target flash page is an MSB page, it can be based on The predicted bit error rate of the MSB page selects the target ECC algorithm corresponding to the MSB page and the target error correction bit number; if the target flash page is an LSB page, the target ECC algorithm corresponding to the LSB page may be selected based on the predicted bit error rate of the LSB page and The number of target error corrections.
  • the ECC algorithm may be a BCH (Bose Ray-Chaudhuri Hocquenghem) algorithm, and the error correction bit number may be N bits, and N is a positive integer greater than or equal to 1.
  • BCH Bit-Chaudhuri Hocquenghem
  • the data to be written to the MSB page can be written to the MSB page according to the target ECC algorithm corresponding to the MSB page and the target number of error correction bits. And correcting the error data; if the target flash page is an LSB page, the data to be written to the LSB page can be written into the LSB page according to the target ECC algorithm corresponding to the LSB page and the target error correction bit number, and Error data occurred for error correction. That is to say, the operation of the flash page in the embodiment of the present invention may operate on the MSB page, and may also operate on the LSB page, and the present invention is not limited thereto.
  • the ECC algorithm and the number of error correction bits are selected for error correction.
  • the write error can be a Content Dependent Bit Error Rate (CDBER).
  • the embodiments of the present invention may be applied to a non-volatile memory, and may also be applied to a memory using a flash memory granule as a storage medium, such as a solid-state hard disk SSD, a flash memory card capable memory.
  • a flash memory granule as a storage medium, such as a solid-state hard disk SSD, a flash memory card capable memory.
  • the bit error rate is predicted for the data to be written to the flash page, the appropriate ECC algorithm and the number of error correction bits are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data of the flash page is written to the flash page to facilitate error correction of the data in which the error occurred.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, and save the error correction capability of the ECC algorithm, thereby reducing the amount of error correction calculation.
  • the predicted BER of the target flash page may be calculated according to the type of the target flash page and the data to be written, using a BER calculation manner corresponding to the type of the target flash page.
  • the type of the target flash page is divided into an MSB page and an LBS page, and the MSB page and the LSB page respectively correspond to different BER calculation modes.
  • the ratio of the four data states to the write data can be obtained.
  • the proportion of different data states in the write data and the BER of the preset write data Ability to calculate the predicted bit error rate of a flash page.
  • the BER of the preset write data can be obtained based on experimental data and empirical values.
  • the flash page includes the MSB page and the LSB page
  • the method of calculating the predicted bit error rate of the flash page is also applicable to the MSB page and the LSB page. That is, the flash page in the embodiment of the present invention can be replaced with an MSB page or an LSB page. In this way, the predicted bit error rate of the MSB page and the LSB page can be separately calculated, and the ECC algorithm and the error correction bit number can be respectively selected, thereby respectively correcting the write data of the MSB page and the LSB page.
  • the BER calculation manner may be:
  • B MSB is the predicted BER of the MSB page
  • P 00 is the proportion of 00 in the data to be written
  • P 10 is the proportion of 10 in the data to be written
  • the BER of the left-biased error occurs for the preset write 00
  • a BER with a right-biased error occurs for a preset write of 10.
  • the BER is calculated as:
  • B LSB is the predicted BER of the LSB page;
  • P 11 is the proportion of 11 in the data to be written;
  • P 10 is the proportion of 10 in the data to be written;
  • P 00 is the proportion of 00 in the data to be written.
  • P 01 is the proportion of 01 in the data to be written;
  • the BER of the right-biased error occurs for the preset write 11;
  • the BER of the left-biased error occurs for the preset write 10;
  • the BER of the right-biased error occurs for the preset write 00;
  • the BER of the left-biased error occurs for the preset write 01.
  • the proportion of the data state to which the data belongs can be obtained.
  • the proportions of the four data states be P 11 , P 10 , P 00 , P 01 , respectively .
  • P 11 represents the proportion of “11” in the data to be written
  • P 10 represents the proportion of “10” in the data to be written
  • P 00 represents the proportion of “00” in the data to be written
  • P 01 represents the proportion of "01" in the data to be written.
  • the BER of the preset data written to the flash page may include a left-biased error and a right-biased error.
  • Left-handed errors can include: among them, The BER of the left-biased error occurs for the preset write 11 For the default write of 10, the BER of the left-biased error occurs. The BER of the left-biased error occurs for the preset write 00, The BER of the left-biased error occurs for the preset write 01.
  • Right deviation errors can include: among them, The BER of the right-biased error occurs for the preset write 11 The BER of the right-biased error occurs for the default write of 10, The BER of the right-biased error occurs for the preset write 00, The BER of the right-biased error occurs for the preset write 01. Can be drawn from Figure 1
  • the formula for calculating the predicted bit error rate of the MSB page and the LSB page can be as follows:
  • the embodiment of the present invention may determine, according to the predicted BER of the target flash page and the correspondence between the predicted BER and the error correction capability information of the preset target flash page, to be written.
  • the target ECC algorithm of the data and the target error correction bit number, and the error correction capability information includes the ECC algorithm and the number of error correction bits.
  • the error correction capability information of the ECC algorithm has a correspondence relationship with the predicted BER of the flash page.
  • the error correction capability of the ECC algorithm indicates that the ECC algorithm and the number of error correction bits can correct a range of bit error rates. Different ECC algorithms and error correction bits can correct a range of bit error rates. That is, there is a correspondence between different ECC algorithms and the number of error correction bits and the bit error rate.
  • the correspondence between the predicted BER of the preset target flash page and the error correction capability information may be set according to empirical data.
  • the preset ECC algorithm and the correspondence between the number of error correction bits and the predicted BER of the target flash page can achieve the purpose of ensuring data reliability and minimizing the computational overhead of the ECC.
  • the page theoretical minimum error rate and the page theoretical maximum error rate of the flash page may be set first, and the range of the set page theoretical minimum BER to the page theoretical maximum BER bit error rate is divided into multiple bit error rates. of range.
  • the range of different bit error rates may correspond to different error correction capability information. That is to say, the range of the bit error rate that can be corrected by the ECC algorithm and the number of error correction bits is the range of the bit error rate corresponding to the ECC algorithm and the number of error correction bits.
  • the embodiment of the present invention may determine N error rate ranges corresponding to N error correction capability information, where N is greater than or equal to 1; and determine, from the N bit error rate ranges, a predicted bit error rate of the flash page.
  • the target bit error rate range; the ECC algorithm and the number of error correction bits corresponding to the target bit error rate range are determined as the target ECC algorithm and the target error correction bit number.
  • the correctable bit error rate of the ECC algorithm and the error correction bit number selected by the embodiment of the present invention is greater than the predicted bit error rate of the flash page, and the ECC error correction capability can be saved on the basis of ensuring data reliability, thereby reducing calculation. Volume, improve system performance and space utilization.
  • the correspondence between the error correction capability information of the ECC algorithm and the bit error rate of the flash page may be expressed as the error correction capability information of the ECC algorithm corresponding to a certain bit error rate range.
  • the N error correction capability information may correspond to an N bit error rate range. If the predicted bit error rate of the target flash page belongs to the target bit error rate range in the N bit error rate range, the ECC algorithm corresponding to the target bit error rate range and the error correction bit number may be used to write the data information of the flash page. Make corrections.
  • the flash page in embodiments of the present invention may be replaced with an MSB page or an LSB page.
  • the minimum and maximum values of the bit error rate in the N bit error rate ranges are determined based on the predicted bit error rate of the target flash page.
  • the minimum value of the bit error rate is the page theoretical minimum BER
  • the maximum value of the bit error rate is the page theoretical maximum BER.
  • the correspondence between the N error correction capability information and the N bit error rate ranges can be established as follows according to the above description.
  • the bit error rate range of the moderately divided table 1 corresponds to the corresponding ECC algorithm and the number of error correction bits, and the ECC algorithm and the number of error correction bits are set to an error correction level.
  • the correspondence between the error correction capability information of the ECC algorithm and the bit error rate will be described in detail in conjunction with Table 1 below.
  • CDBER min is the page theory minimum bit error rate
  • CDBER max is the page theoretical maximum bit error rate.
  • the embodiment of the present invention may use the CDBER min corresponding to the MSB page and the smaller CDBER min corresponding to the LSB page as the CDBER in the correspondence table of Table 1.
  • min i.e. the theoretical minimum bit error rate p
  • the MSB page and the LSB page use the same correspondence table in common.
  • the ECC algorithm in the embodiment of the present invention selects the BCH algorithm, and other ECC algorithms may also be used, and the embodiment of the present invention is not limited thereto.
  • the bit error rate range is the same. That is, the range of CDBER min -CDBER 1 can be the same as the range of CDBER 1-CDBER 2. If the number of N error correction bits is non-equal, the range of bit error rates is also different. For example, when the error correction level is 0, the bit error rate range corresponding to 1 bit of the error correction bit number is CDBER min -CDBER 1, and when the error correction level is 1, the bit error rate range corresponding to 3 bits of the error correction bit number is 2 Double CDBER min -CDBER 1.
  • the embodiment of the present invention may look up Table 1 and determine the bit error rate range in which the calculated predicted BER of the target flash page falls, and select the bit error rate.
  • the range corresponding ECC algorithm and the number of error correction bits write the data to be written to the flash memory, and correct the errored data according to the selected ECC algorithm and the number of error correction bits. For example, if the predicted bit error rate of the MSB page is within the bit error rate range corresponding to the error correction level of 1, the BCH algorithm and the 2 bit error correction bit number are selected to write the data to the MSB page.
  • FIG. 3 is a schematic flowchart of a method for data storage according to another embodiment of the present invention.
  • the same steps in Fig. 3 as those in Fig. 2 are given the same reference numerals.
  • the method can be performed by the apparatus shown in FIG. 5, and the method can further include:
  • a data prediction bit error rate is written for a flash memory page, an appropriate ECC algorithm and an error correction bit number are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data of the flash page is written to the flash memory to facilitate correction of the data in which the error occurred.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, and save the error correction capability of the ECC algorithm, thereby reducing the calculation amount of the error correction process.
  • the target ECC algorithm and the target error correction bit number may be recorded, and the corresponding error correction level may also be recorded.
  • the embodiment of the present invention may call the error correction level, and perform error correction using the ECC algorithm corresponding to the error correction level and the number of error correction bits.
  • FIG. 4 is a schematic flow chart of a method of data storage according to an embodiment of the present invention. The process can be performed by the apparatus shown in FIG. 5, which can be a solid state drive SSD, the method comprising:
  • the type of the flash page is determined based on the address in the write request.
  • the types of flash pages are divided into MSB pages and LSB pages.
  • the flash page is an MSB page
  • the data to be written may be data of one flash page in the flash memory.
  • a flash page can be 4KB or 8KB in size.
  • the embodiment of the present invention does not limit the size of the flash page.
  • the proportion of the data state to which the data belongs can be obtained.
  • the proportions of the four data states be P 11 , P 10 , P 00 , P 01 , respectively .
  • P 11 represents the proportion of “11” in the data to be written
  • P 10 represents the proportion of “10” in the data to be written
  • P 00 represents the proportion of “00” in the data to be written
  • P 01 represents the proportion of "01" in the data to be written.
  • the BER of the preset data written to the flash page may include a left-biased error and a right-biased error.
  • the left bias error to include: among them, The BER of the left-biased error occurs for the preset write 11 For the default write of 10, the BER of the left-biased error occurs. The BER of the left-biased error occurs for the preset write 00, The BER of the left-biased error occurs for the preset write 01. Can be drawn from Figure 1
  • the BER of the right-biased error occurs for the preset write 11
  • the BER of the right-biased error occurs for the default write of 10
  • the BER of the right-biased error occurs for the preset write 00
  • the BER of the right-biased error occurs for the preset write 01.
  • the predicted BER of the LSB page is calculated according to the proportion of the four data states in the data to be written and the BER of the preset write data.
  • the error correction capability information includes an ECC algorithm and an error correction bit number.
  • the correspondence between the error correction capability information of the ECC algorithm and the bit error rate of the flash page may be expressed as the error correction capability information of the ECC algorithm corresponding to a certain bit error rate range.
  • the N error correction capability information may correspond to an N bit error rate range. If the predicted bit error rate of the target flash page belongs to the target bit error rate range in the N bit error rate range, the ECC algorithm corresponding to the target bit error rate range and the error correction bit number may be used to write the data information of the flash page. Make corrections.
  • the minimum and maximum values of the bit error rate in the N bit error rate ranges are determined based on the predicted bit error rate of the target flash page.
  • the minimum value of the BER corresponding to the MSB page and the minimum value of the BER corresponding to the LSB page may be used as the page theoretical minimum bit error rate; and the maximum value of the BER corresponding to the MSB page corresponds to the LSB page.
  • the larger of the maximum values of BER is used as the page theoretical maximum bit error rate.
  • the MSB page and the LSB page use the same correspondence table in common.
  • the ECC algorithm and the number of error correction bits may correspond to an error correction level.
  • the error correction level can also be recorded in the embodiment of the present invention.
  • the embodiment of the present invention may call the error correction level of the record, and use the ECC algorithm corresponding to the error correction level and the number of error correction bits to correct the error data in the data written in the flash page. wrong.
  • the embodiment of the present invention may perform error correction on data that is erroneous in the data written in the MSB page according to the ECC algorithm and the number of error correction bits selected by the predicted bit error rate of the MSB page, or may be based on the predicted bit of the LSB page.
  • the error rate selected ECC algorithm and the number of error correction bits correct the error data in the data written to the LSB page.
  • the bit error rate is predicted for the data to be written to the flash page, the appropriate ECC algorithm and the number of error correction bits are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data of the flash page is written to the flash page to facilitate error correction of the data in which the error occurred.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, and save the error correction capability of the ECC algorithm, thereby reducing the amount of error correction calculation.
  • FIG. 5 is a schematic block diagram of an apparatus in accordance with one embodiment of the present invention.
  • the apparatus shown in FIG. 5 can implement the methods of FIGS. 2 and 3 described above and the process of FIG.
  • the device can be a non-volatile memory, and the device 50 includes:
  • the receiving module 51 is configured to receive a write request, where the write request includes data to be written and an address;
  • the type determining module 52 is configured to determine a type of the target flash page according to the address, wherein the target flash page is a flash page in the non-volatile memory that stores the data to be written;
  • the calculating module 53 is configured to calculate a predicted bit error rate BER of the target flash page according to the type of the target flash page determined by the type determining unit and the data to be written;
  • the algorithm determining module 54 is configured to determine a target error correction code ECC algorithm and a target error correction bit number of the data to be written according to the predicted BER of the target flash page;
  • a writing module 55 configured to determine, according to an algorithm, a target ECC algorithm and target error correction determined by the module The number of bits writes the data to be written to the target flash page.
  • the bit error rate is predicted for the data to be written to the flash page, the appropriate ECC algorithm and the number of error correction bits are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data of the flash page is written to the flash page to facilitate error correction of the data in which the error occurred.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, and save the error correction capability of the ECC algorithm, thereby reducing the amount of error correction calculation.
  • the algorithm determining module 54 may determine the target ECC of the data to be written according to the predicted BER of the target flash page and the corresponding relationship between the predicted BER and the error correction capability information of the preset target flash page.
  • the algorithm and the target error correction bit number, the error correction capability information includes the ECC algorithm and the number of error correction bits.
  • the calculating module 53 may calculate the predicted BER of the target flash page according to the type of the target flash page and the data to be written, using a BER calculation manner corresponding to the type of the target flash page.
  • the calculation module 53 may calculate according to the BER:
  • B MSB is the predicted BER of the MSB page
  • P 00 is the proportion of 00 in the data to be written
  • P 10 is the proportion of 10 in the data to be written
  • the BER of the left-biased error occurs for the preset write 00
  • a BER with a right-biased error occurs for a preset write of 10.
  • the calculation module 53 may calculate according to the BER:
  • B LSB is the predicted BER of the LSB page
  • P 11 is the proportion of 11 in the data to be written
  • P 10 is the proportion of 10 in the data to be written
  • P 00 is The proportion of 00 to be written in the data
  • P 01 is the proportion of 01 in the data to be written
  • the BER of the right-biased error occurs for the preset write 11
  • the BER of the left-biased error occurs for the preset write 10
  • the BER of the right-biased error occurs for the preset write 00
  • the BER of the left-biased error occurs for the preset write 01.
  • the apparatus 50 may further include a recording module 56 for recording the target ECC algorithm and the target error correction bit number.
  • FIG. 6 is a schematic block diagram of an apparatus in accordance with another embodiment of the present invention.
  • the apparatus 60 of FIG. 6 can be used to implement the steps and methods of the above method embodiments.
  • the apparatus of FIG. 6 includes a processor 61 and a memory 62.
  • the processor 61 and the memory 62 are connected by a bus system 69.
  • the processor 61 controls the operation of the device 60.
  • Memory 62 can include read only memory and random access memory and provides instructions and data to processor 61.
  • a portion of memory 62 may also include non-volatile line random access memory (NVRAM).
  • NVRAM non-volatile line random access memory
  • the various components of device 60 are coupled together by a bus system 69, which in addition to the data bus includes a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as bus system 69 in the figure.
  • Processor 61 may be an integrated circuit chip with signal processing capabilities.
  • the processor 61 described above may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or discrete hardware. Component.
  • the methods, steps, and logical block diagrams disclosed in the embodiments of the present invention may be implemented or carried out.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the processor 61 reads the information in the memory 62 in conjunction with the various components of its hardware control device 60.
  • device 60 performs the following operations:
  • the target flash page is a flash page in the non-volatile memory that stores the data to be written
  • the data to be written is written to the target flash page according to the determined target ECC algorithm and the target number of error correction bits.
  • the bit error rate is predicted for the data to be written to the flash page
  • the appropriate ECC algorithm and the number of error correction bits are selected according to the predicted bit error rate, and the selected ECC algorithm and the number of error correction bits are to be written.
  • the data of the flash page is written to the flash page to correct the data with errors. wrong.
  • the method can select an appropriate ECC algorithm and the number of error correction bits, and save the error correction capability of the ECC algorithm, thereby reducing the amount of error correction calculation.
  • the processor 61 may determine a target ECC algorithm to be written according to a predicted BER of the target flash page and a corresponding relationship between the predicted BER of the target flash page and the error correction capability information. And the target error correction bit number, the error correction capability information includes the ECC algorithm and the number of error correction bits.
  • the processor 61 may calculate the predicted BER of the target flash page according to the type of the target flash page and the data to be written, using a BER calculation manner corresponding to the type of the target flash page.
  • the BER is calculated as: Wherein, B MSB is the predicted BER of the MSB page; P 00 is the proportion of 00 in the data to be written; P 10 is the proportion of 10 in the data to be written; The BER of the left-biased error occurs for the preset write 00; A BER with a right-biased error occurs for a preset write of 10.
  • the BER is calculated as: Among them, B LSB is the predicted BER of the LSB page; P 11 is the proportion of 11 in the data to be written; P 10 is the proportion of 10 in the data to be written; P 00 is the proportion of 00 in the data to be written. Ratio; P 01 is the proportion of 01 in the data to be written; The BER of the right-biased error occurs for the preset write 11; The BER of the left-biased error occurs for the preset write 10; The BER of the right-biased error occurs for the preset write 00; The BER of the left-biased error occurs for the preset write 01.
  • the processor 61 may also record the target ECC algorithm and the target number of error correction bits.
  • system and “network” are used interchangeably herein.
  • the word “and/or” is merely an association relationship describing the associated object, indicating that there may be three relationships, for example, A and/or B, which may indicate that A exists separately, A and B exist simultaneously, and B exists separately. three situations.
  • the character “/” in this article generally indicates that the contextual object is an "or" relationship.
  • B corresponding to A means that B is associated with A, and B can be determined according to A.
  • determining B from A does not mean that B is only determined based on A, and that B can also be determined based on A and/or other information.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or software. The form of the functional unit is implemented.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure.
  • connection may suitably be a computer readable medium.
  • the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
  • coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixing of the associated media.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.
  • CD compact disc
  • DVD digital versatile disc
  • floppy disk a compact disc
  • Blu-ray disc wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data.

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  • Quality & Reliability (AREA)
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  • General Engineering & Computer Science (AREA)
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  • Read Only Memory (AREA)

Abstract

Des modes de réalisation de l'invention concernent un procédé et un dispositif de stockage de données. Le procédé consiste à : recevoir une demande d'écriture comprenant des données à écrire et une adresse ; déterminer le type d'une page de mémoire flash cible en fonction de l'adresse ; calculer un BER prédit de la page de mémoire flash cible en fonction du type de la page de mémoire flash cible et des données à écrire ; déterminer un algorithme ECC cible et un nombre de bits de correction d'erreur cible des données à écrire conformément au BER prédit de la page de mémoire flash cible ; et écrire les données à écrire dans la page de mémoire flash cible en fonction de l'algorithme ECC cible et du nombre de bits de correction d'erreur cible. Dans les modes de réalisation de l'invention, un taux d'erreur de bit est prédit pour les données à écrire dans une page de mémoire flash, un algorithme ECC approprié et un nombre de bits de correction d'erreur approprié sont sélectionnés en fonction du taux d'erreur de bit prédit, et les données à écrire dans la page de mémoire flash sont écrites dans la page de mémoire flash au moyen de l'algorithme ECC et du nombre de bits de correction d'erreur de façon à pouvoir effectuer une correction d'erreur sur des données lorsqu'une erreur se produit. Le procédé permet de sélectionner un algorithme ECC approprié et un nombre de bits de correction d'erreur approprié, d'économiser la capacité de correction d'erreur de l'algorithme ECC, et de réduire ainsi la quantité de calculs dans la correction d'erreur.
PCT/CN2014/093653 2014-12-12 2014-12-12 Procédé et dispositif de stockage de données WO2016090621A1 (fr)

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CN107861835A (zh) * 2017-11-22 2018-03-30 深圳忆联信息系统有限公司 一种提升闪存编码率的方法及闪存
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CN106484629A (zh) * 2016-10-18 2017-03-08 深圳大学 一种感知制程变异的三维闪存读写控制方法及其系统
CN106484629B (zh) * 2016-10-18 2019-06-25 深圳大学 一种感知制程变异的三维闪存读写控制方法及其系统
CN107861835A (zh) * 2017-11-22 2018-03-30 深圳忆联信息系统有限公司 一种提升闪存编码率的方法及闪存
CN107861835B (zh) * 2017-11-22 2021-11-16 深圳忆联信息系统有限公司 一种提升闪存编码率的方法及闪存
CN107977282A (zh) * 2017-12-20 2018-05-01 北京兆易创新科技股份有限公司 一种SPI-Nand读取数据页的方法及装置
CN107977282B (zh) * 2017-12-20 2021-01-26 北京兆易创新科技股份有限公司 一种SPI-Nand读取数据页的方法及装置
CN108683425A (zh) * 2018-05-18 2018-10-19 中国科学院微电子研究所 一种bch译码器
CN108683426A (zh) * 2018-05-18 2018-10-19 中国科学院微电子研究所 一种基于bch码的ecc系统及存储器
CN111130568A (zh) * 2018-10-31 2020-05-08 中国科学院微电子研究所 一种bch译码器及其译码方法、ecc系统
CN111130568B (zh) * 2018-10-31 2023-05-23 中国科学院微电子研究所 一种bch译码器及其译码方法、ecc系统
CN112597488A (zh) * 2020-12-30 2021-04-02 海光信息技术股份有限公司 页表完整性保护方法、装置和设备

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