WO2016076162A1 - Composite electronic component, circuit module, and dc-dc converter module - Google Patents

Composite electronic component, circuit module, and dc-dc converter module Download PDF

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Publication number
WO2016076162A1
WO2016076162A1 PCT/JP2015/080984 JP2015080984W WO2016076162A1 WO 2016076162 A1 WO2016076162 A1 WO 2016076162A1 JP 2015080984 W JP2015080984 W JP 2015080984W WO 2016076162 A1 WO2016076162 A1 WO 2016076162A1
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Prior art keywords
chip
connection terminal
semiconductor chip
component
support material
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PCT/JP2015/080984
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French (fr)
Japanese (ja)
Inventor
村瀬元規
Original Assignee
株式会社村田製作所
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Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN201590001032.1U priority Critical patent/CN207217523U/en
Priority to JP2016558988A priority patent/JP6414602B2/en
Publication of WO2016076162A1 publication Critical patent/WO2016076162A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the present invention relates to a composite electronic component in which a plurality of elements including a semiconductor chip are mounted on a substrate or a lead frame.
  • the composite electronic component facilitates downsizing and high performance, a circuit module including the composite electronic component, and DCDC.
  • the converter module is configured to convert a signal to a signal.
  • Japanese Patent Application Laid-Open No. 2005-228867 discloses a composite electronic component (hybrid integrated circuit device) configured to fix a semiconductor chip and a chip component on a substrate and connect the electrode of the chip component to the electrode on the substrate by wire bonding. Has been.
  • Patent Document 2 discloses an interposer in which a plurality of chip capacitors are provided inside and a plurality of semiconductor chips are mounted on the surface.
  • FIG. 19 is a cross-sectional view of a composite electronic component in which the semiconductor chip 21 and the chip component 30 are die-bonded to the lead frame 11.
  • the composite electronic component having the structure as shown in FIG. 19 has the following problems.
  • Patent Document 2 a composite electronic component having an interposer in which a chip component is provided and a semiconductor chip is mounted on the surface requires a very low-profile chip component, resulting in component cost and manufacturing. Cost increases.
  • An object of the present invention includes a composite electronic component capable of improving the compatibility when a semiconductor chip and other chip components are contained in one package, and reducing the size and improving the electrical characteristics, and the composite electronic component. It is to provide a circuit module and a DCDC converter.
  • the composite electronic component of the present invention is configured as follows.
  • Have The semiconductor chip is mounted on the support material with the connection terminal on the upper surface side,
  • the chip component has a first connection terminal on the upper surface and a second connection terminal on the lower surface,
  • the chip component is mounted on the support material with the first connection terminal on the upper surface side, and the second connection terminal is connected to the support material,
  • the connection terminal of the semiconductor chip and the first connection terminal of the chip component are directly connected via a wire without the support material, It is characterized by that.
  • connection structure for the first and second connection terminals of the chip component becomes rational, the resistance value of the current path becomes smaller, and the power loss can be reduced.
  • the composite electronic component of the present invention is configured as follows.
  • Have The semiconductor chip is mounted on the support material with the connection terminal on the upper surface side,
  • the chip component has a first connection terminal on the upper surface and a second connection terminal on the end,
  • the chip component is mounted on the support material with the first connection terminal on the upper surface side, and the second connection terminal is connected to the support material,
  • the connection terminal of the semiconductor chip and the first connection terminal of the chip component are directly connected via a wire without the support material, It is characterized by that.
  • the support member can be easily connected by the second connection terminal formed at the end portion, and the first connection terminal can be easily connected by wire.
  • the semiconductor chip and the chip component are mounted on a common electrode. This increases the cross-sectional area of the heat dissipation path, so that the heat dissipation performance of the chip component and the semiconductor chip is enhanced.
  • the support material is a lead frame;
  • the semiconductor chip and the chip component are preferably mounted on a die pad (common frame) of the lead frame. This does not complicate the lead frame pattern. Moreover, the heat dissipation of chip components and semiconductor chips is enhanced.
  • a DCDC converter module of the present invention includes the composite electronic component according to any one of (1) to (4) above,
  • the composite electronic component has a power input terminal, a power output terminal and a ground terminal,
  • the semiconductor chip is a switching power supply IC including a switching element and a switching control circuit,
  • the chip component is an inductance element, and at least a first end of the chip component is connected to the switching element.
  • the resistance value of the current path is reduced, power loss can be reduced, and high power conversion efficiency can be obtained. Further, the distance between the semiconductor chip and the chip component can be shortened, and the whole can be miniaturized. Moreover, since an island-like isolated terminal is unnecessary, high heat dissipation can be maintained.
  • the composite electronic component of this invention is comprised as follows.
  • the semiconductor chip is mounted on the support material with the connection terminal on the upper surface side,
  • the chip component is mounted on the support material such that the connection terminal is located at least on the upper surface,
  • the connection terminal of the semiconductor chip and the connection terminal of the chip component are directly connected via a wire without the support material, It is characterized by that.
  • the shape of the lead frame can be simplified even when a semiconductor chip and chip parts are mounted on the lead frame.
  • the resistance value of the current path is reduced, and power loss can be reduced.
  • the distance between the semiconductor chip and the chip component can be shortened, the entire composite electronic component can be reduced in size, and the resistance of the die bond can be reduced to improve the efficiency.
  • a die pad isolated in an island shape is unnecessary, high heat dissipation can be maintained.
  • the chip component since the chip component is provided inside and the interposer on which the semiconductor chip is mounted is not provided on the surface, the chip component can be applied as long as it is the same size as the semiconductor chip, and the component cost and the manufacturing cost are reduced.
  • a circuit module of the present invention includes the composite electronic component according to (6) above, It has a power supply terminal and a ground terminal,
  • the chip component is a decoupling capacitor element connected between the power supply terminal and the ground terminal.
  • FIG. 1 is a cross-sectional view of the main part of a composite electronic component 101 according to the first embodiment.
  • FIG. 2 is a plan view of the composite electronic component 101 without a mold resin.
  • 3A is a perspective view of the chip component 31
  • FIG. 3B is a cross-sectional view of the chip component 31
  • FIG. 3C is a perspective view showing a structure of a conductor portion of the chip component 31.
  • FIG. 4 is a circuit diagram of the composite electronic component 101 of this embodiment.
  • FIG. 5 is a cross-sectional view of the main part of the composite electronic component 102 according to the second embodiment.
  • FIG. 6 is a cross-sectional view of the main part of the composite electronic component 103 according to the third embodiment.
  • FIG. 7 is a plan view of the composite electronic component 103 without a mold resin.
  • FIG. 8A is a perspective view of the chip component 32
  • FIG. 8B is a cross-sectional view of the chip component 32.
  • FIG. 9 is a circuit diagram of the composite electronic component 103 of the present embodiment.
  • FIG. 10 is a cross-sectional view of the main part of the composite electronic component 104 according to the fourth embodiment.
  • FIG. 11 is a plan view of the composite electronic component 104 without a mold resin.
  • 12A is a perspective view of the chip component 31,
  • FIG. 12B is a cross-sectional view of the chip component 31, and
  • FIG. 12C is a perspective view showing the structure of the conductor portion of the chip component 31.
  • FIG. 13 is a circuit diagram of the composite electronic component 104 of this embodiment.
  • FIG. 14 is a cross-sectional view of the main part of the composite electronic component 105 according to the fifth embodiment.
  • FIG. 15 is a plan view of the composite electronic component 105 without a mold resin.
  • 16A is a perspective view of the chip component 31
  • FIG. 16B is a cross-sectional view of the chip component 31
  • FIG. 16C is a perspective view showing a structure of a conductor portion of the chip component 31.
  • FIG. 17 is a plan view of the composite electronic component 106 according to the sixth embodiment in the absence of mold resin.
  • FIG. 18 is a circuit diagram of the composite electronic component 106 of this embodiment.
  • FIG. 19 is a cross-sectional view of a composite electronic component in which the semiconductor chip 21 and the chip component 30 are die-bonded to the lead frame 11.
  • FIG. 1 is a cross-sectional view of the main part of a composite electronic component 101 according to the first embodiment.
  • FIG. 2 is a plan view of the composite electronic component 101 without a mold resin.
  • FIG. 1 is a schematic cross-sectional view taken along line AA in FIG.
  • the composite electronic component 101 includes a lead frame (11a to 11f, 11P, etc.), a semiconductor chip 21 and a chip component 31, which are examples of support materials.
  • the semiconductor chip 21 and the chip component 31 are mounted close to each other on the die pad 11P of the lead frame.
  • the chip component 31 has connection terminals (pads) 31P1 and 31P2 on one main surface.
  • the semiconductor chip 21 is mounted on the die pad 11P of the lead frame with the connection terminal on the upper surface side, and the chip component 31 is die-bonded on the die pad 11P with the connection terminals 31P1 and 31P2 on the upper surface side.
  • the lead frame includes terminals 11a, 11b, 11c, 11d, 11e, 11f and a die pad 11P.
  • the semiconductor chip 21 includes a plurality of connection terminals, and predetermined terminals of the semiconductor chip 21 are connected to terminals 11a, 11b, 11d, 11e, and 11f of the lead frame via wires W1, W2, W5, W6, and W7, respectively.
  • the predetermined terminal of the semiconductor chip 21 is directly connected to the connection terminals 31P1 and 31P2 of the chip component 31 via the wires W3 and W4 without the support material.
  • connection terminal 31P1 of the chip component 31 is connected to the terminal 11c of the lead frame via the wire W8. Since there are two wires W8, the line resistance between the chip component 31 and the terminal 11c is reduced.
  • the upper part of the lead frame is molded with a mold resin 40 such as an epoxy resin.
  • a mold resin 40 such as an epoxy resin.
  • the composite electronic component 101 is packaged in a QFN (Quad Flat Non-Leaded Package) or SON (Small Outline Non-Leaded Package) type.
  • the composite electronic component 101 is mounted on a printed wiring board as a surface mount type electronic component.
  • FIG. 3A is a perspective view of the chip component 31,
  • FIG. 3B is a cross-sectional view of the chip component 31, and
  • FIG. 3C is a perspective view showing a structure of a conductor portion of the chip component 31.
  • FIG. The chip component 31 is a laminate of a plurality of insulator layers including an insulator layer on which a plurality of conductor patterns are formed.
  • the chip component 31 of this embodiment is an inductance element.
  • the chip component 31 includes a coil conductor 31L and via conductors 31V1 and 31V2.
  • the coil conductor 31L is a rectangular helical conductor pattern including a plurality of conductor patterns along the insulator layer and a plurality of interlayer connection conductors.
  • the via conductor 31V2 passes through the coil winding range.
  • FIG. 4 is a circuit diagram of the composite electronic component 101 of the present embodiment.
  • the composite electronic component 101 of the present embodiment is a DCDC converter module used for a DCDC converter.
  • the composite electronic component 101 includes a semiconductor chip 21 and a chip component 31.
  • the semiconductor chip 21 includes switching elements Q1 and Q2 and a switching control circuit 21C.
  • a series circuit of the switching elements Q1, Q2 is connected between the power input terminal IN of the composite electronic component 101 and the ground terminal GND.
  • One end of the chip component 31 which is an inductance element is connected to the connection point of the switching elements Q1 and Q2, and the other end is connected to the output terminal OUT of the composite electronic component 101.
  • the enable terminal of the switching control circuit 21C is connected to the EN terminal of the composite electronic component 101.
  • the power supply E and the input capacitor Ci are connected to the power input terminal IN of the composite electronic component 101.
  • An output capacitor Co is connected to the output terminal of the composite electronic component 101.
  • the voltage of the output capacitor Co is supplied to the load.
  • the output voltage is input to the feedback terminal FB of the switching control circuit 21C.
  • the lead frame only includes the terminals 11a to 11f arranged around the package and the die pad 11P at the center, the shape of the lead frame can be simplified.
  • the chip component 31 can be applied as long as it has the same size as the semiconductor chip 21, and the component cost and manufacturing cost are reduced.
  • Second Embodiment an example of a composite electronic component packaged in an FBGA (Fine pitch Ball Grid Array) type is shown.
  • FBGA Full pitch Ball Grid Array
  • FIG. 5 is a cross-sectional view of the main part of the composite electronic component 102 according to the second embodiment.
  • the composite electronic component 102 includes a laminated substrate 12, a semiconductor chip 21, and a chip component 31.
  • the semiconductor chip 21 and the chip component 31 are mounted in the vicinity of the common electrode 12P formed on the laminated substrate 12.
  • the chip component 31 has connection terminals (pads) 31P1 and 31P2 on one main surface.
  • the laminated substrate 12 is a printed laminated substrate, and a plurality of connection terminals 12a, 12b and the like are formed on the upper surface. A plurality of lands are formed on the lower surface, and solder balls SB are provided on the lands.
  • the semiconductor chip 21 is mounted on the common electrode 12P with the connection terminal on the upper surface side, and the chip component 31 is die-bonded on the common electrode 12P with the connection terminals 31P1 and 31P2 on the upper surface side.
  • Wire bonding to the connection terminals 12a, 12b, etc. on the laminated substrate 12 is the same as that of the lead frame type composite electronic component 101 shown in the first embodiment. In this way, an FBGA type composite electronic component can also be configured.
  • the third embodiment includes not only an inductance element but also a capacitance element.
  • FIG. 6 is a cross-sectional view of the main part of the composite electronic component 103 according to the third embodiment.
  • the composite electronic component 103 includes a lead frame (11m, 11d, 11P, etc.) that is an example of a support material, a semiconductor chip 21, and chip components 31, 32.
  • the semiconductor chip 21 and the chip components 31 and 32 are mounted close to each other on the die pad 11P of the lead frame.
  • the chip component 31 has connection terminals 31P1 and 31P2 on one main surface.
  • the chip component 32 has connection terminals 32P1 and 32P2 on one main surface.
  • the semiconductor chip 21 is mounted on the die pad 11P of the lead frame with the connection terminal on the upper surface side, and the chip component 31 is die-bonded on the die pad 11P with the connection terminals 31P1 and 31P2 on the upper surface side. Are die-bonded on the die pad 11P with the connection terminals 32P1 and 32P2 on the upper surface side.
  • the lead frame includes terminals 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i, 11j, 11k, 11m and a die pad 11P.
  • the semiconductor chip 21 has a plurality of connection terminals, and predetermined terminals of the semiconductor chip 21 are wires W5, W6, W10, W13, W7, W1 to terminals 11a, 11b, 11c, 11g, 11h, 11i, 11j of the lead frame, respectively. , W2 are connected. Predetermined terminals of the semiconductor chip 21 are directly connected to the connection terminals 31P1 and 31P2 of the chip component 31 via the wires W3 and W4 without the support material.
  • connection terminals 31P1 and 31P2 of the chip component 31 are connected to the terminals 11d, 11e, and 11f of the lead frame via wires W8, W11, and W12.
  • connection terminals 32P1 and 32P2 of the chip component 32 are connected to the terminals 11m and 11k of the lead frame via wires W14 and W9.
  • FIG. 8A is a perspective view of the chip part 32
  • FIG. 8B is a cross-sectional view of the chip part 32.
  • FIG. The chip component 32 is a laminate of a plurality of insulator layers including an insulator layer on which a plurality of conductor patterns are formed.
  • the chip component 32 of this embodiment is a capacitance element.
  • the chip component 32 includes planar conductors 32E1 and 32E2 and via conductors 32C1 and 32C2. Capacitances are formed in the opposing portions of the planar conductors 32E1 and 32E2, and are commonly connected by the via conductors 32C1 and 32C2.
  • FIG. 9 is a circuit diagram of the composite electronic component 103 of the present embodiment.
  • the composite electronic component 103 is a DCDC converter module incorporating an input capacitor.
  • the chip component 32 of the composite electronic component 103 functions as an input capacitor connected between the power input terminal IN and the ground terminal GND. Therefore, the input capacitor Ci as shown in FIG. 4 is not required outside the composite electronic component 103.
  • Other configurations are the same as those of the composite electronic component 101 shown in FIG. 4 in the first embodiment.
  • FIG. 10 is a cross-sectional view of the main part of the composite electronic component 104 according to the fourth embodiment.
  • FIG. 11 is a plan view of the composite electronic component 104 without a mold resin.
  • FIG. 10 is a cross-sectional view taken along line AA in FIG.
  • the composite electronic component 104 includes a lead frame (11a to 11m, 11P, etc.) as an example of a support material, a semiconductor chip 21, and chip components 31 and 32.
  • the semiconductor chip 21 and the chip components 31 and 32 are mounted close to each other on the die pad 11P of the lead frame.
  • the chip component 32 has two connection terminals on the upper surface.
  • the chip component 31 has a connection terminal 31P1 on the upper surface and a connection terminal 31P2 on the lower surface.
  • the center of the connection terminal 31P1 and the center of the connection terminal 31P2 are in positions that do not overlap in plan view.
  • the lead frame includes terminals 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i, 11j, 11k, 11m and a die pad 11P.
  • the semiconductor chip 21 includes a plurality of connection terminals, and the predetermined terminals of the semiconductor chip 21 are connected to the terminals 11a, 11b, 11d, 11g, 11h, 11i, 11j, 11k, and 11m of the lead frame via wires.
  • the predetermined terminal of the semiconductor chip 21 is directly connected to the connection terminal 31P1 of the chip component 31 through the wire W4 without the support material. Since there are two wires W4, the line resistance between the chip component 31 and the terminal of the semiconductor chip 21 is reduced.
  • the chip component 32 is connected between one terminal of the semiconductor chip 21 and the terminal 11c of the lead frame via a wire.
  • connection terminal 31P2 of the chip component 31 is die-bonded to the terminals 11e and 11f of the lead frame.
  • FIG. 12A is a perspective view of the chip component 31,
  • FIG. 12B is a cross-sectional view of the chip component 31, and
  • FIG. 12C is a perspective view showing a structure of a conductor portion of the chip component 31.
  • FIG. The chip component 31 is a laminate of a plurality of insulator layers including an insulator layer on which a plurality of conductor patterns are formed.
  • the chip component 31 of this embodiment is an inductance element.
  • the chip component 31 includes a coil conductor 31L and via conductors 31V1 and 31V2.
  • the coil conductor 31L is a rectangular helical conductor pattern including a plurality of conductor patterns along the insulator layer and a plurality of interlayer connection conductors. Unlike the example shown in FIGS.
  • the upper end of the rectangular helical conductor pattern is connected to the terminal 31P1 on the upper surface via the via conductor 31V1, and the rectangular helical
  • the lower end of the conductor pattern is connected to the lower terminal 31P2 via the via conductor 31V2.
  • the conductor portion that does not contribute much to the inductance is shortened, and the DCR (Direct Current Current) is small.
  • the DCR Direct Current Current
  • the die bond connection on the terminal 31P1 side can be eliminated as compared with the conventional example of FIG. 19, the DCR can be reduced correspondingly, and the efficiency of the DCDC converter is improved.
  • FIG. 13 is a circuit diagram of the composite electronic component 104 of the present embodiment.
  • the composite electronic component 104 is a DCDC converter module that incorporates an input capacitor.
  • the basic circuit configuration is the same as that shown in FIG. 9 in the third embodiment.
  • a highly efficient DCDC converter is configured.
  • FIG. 14 is a cross-sectional view of the main part of the composite electronic component 105 according to the fifth embodiment.
  • FIG. 15 is a plan view of the composite electronic component 105 without a mold resin.
  • 14 is a cross-sectional view taken along line AA in FIG. The structure of the chip component 31 is different from that of the fourth embodiment.
  • FIG. 16A is a perspective view of the chip component 31
  • FIG. 16B is a cross-sectional view of the chip component 31
  • FIG. 16C is a perspective view showing the structure of the conductor portion of the chip component 31.
  • the chip component 31 is a laminate of a plurality of insulator layers including an insulator layer on which a plurality of conductor patterns are formed.
  • the chip component 31 includes a coil conductor 31L and a via conductor 31V1.
  • the chip component 31 includes a terminal 31P1 on the upper surface and a terminal 31P2 on one end. Unlike the example shown in FIGS. 10 and 12 in the fourth embodiment, the terminal 31P2 is formed on the five surfaces of one end of the laminate.
  • the coil conductor 31L is a rectangular helical conductor pattern including a plurality of conductor patterns along the insulator layer and a plurality of interlayer connection conductors.
  • the upper end of the rectangular helical conductor pattern is connected to the upper terminal 31P1 via the via conductor 31V1, and the lower end of the rectangular helical conductor pattern is connected to the terminal 31P2.
  • the conductor portion that does not contribute much to the inductance is shortened, and the DCR is small.
  • the connection cross-sectional area between the terminal 31P2 and the lead frame is increased, the resistance value of the die bonding portion can be reduced, and the DCR of the die bonding portion can be reduced.
  • FIG. 17 is a plan view of the composite electronic component 106 according to the sixth embodiment in the absence of mold resin.
  • the composite electronic component 106 includes a lead frame (11a to 11f, 11P, etc.) that is an example of a support material, a semiconductor chip 21, and a chip component 32.
  • the semiconductor chip 21 and the chip component 32 are mounted close to the die pad 11P of the lead frame.
  • the chip component 32 has connection terminals (pads) 32P1 and 32P2 on one main surface.
  • the semiconductor chip 21 is mounted on the die pad 11P of the lead frame with the connection terminal on the upper surface side, and the chip component 31 is die-bonded on the die pad 11P with the connection terminals 32P1 and 32P2 on the upper surface side.
  • predetermined terminals of the semiconductor chip 21 are connected to terminals 11a, 11b, 11c, 11e, and 11f of the lead frame via wires W1, W2, W3, W6, and W7, respectively.
  • the predetermined terminal of the semiconductor chip 21 is directly connected to the connection terminal 32P1 of the chip component 32 through the wire W4 without the support material.
  • the connection terminal 32P2 of the chip component 32 is connected to the terminal 11d of the lead frame via a wire W5.
  • FIG. 18 is a circuit diagram of the composite electronic component 106 of the present embodiment.
  • the composite electronic component 106 is a circuit module used for an AD conversion circuit.
  • the semiconductor chip 21 converts the voltage of the signal input terminal SIN into a digital value of a predetermined number of bits, and outputs the AD conversion value to an external circuit via the serial data communication signal lines SCL and SDA.
  • the chip part 32 is a capacitance element. One end of the chip component 32 is connected to the power supply line of the semiconductor chip 21 and the other end is a decoupling capacitor connected to the ground.
  • the equivalent series inductance (ESL) is small and the noise reduction effect is high.
  • the ESL of the capacitor alone need not be so small.
  • the semiconductor chip and the chip component are disposed adjacent to each other on the support material.
  • the semiconductor chip and the chip component to be wire-connected are close to each other and between the semiconductor chip and the chip component.
  • Other chip parts may be arranged on the board.
  • step-down converter is illustrated in FIGS. 4, 9, and 13, it can be similarly applied to a step-up converter and a step-up / step-down converter.

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Abstract

The present invention has: a semiconductor chip (21) mounted on a support material of a lead frame (11a, 11d, 11P, etc.), the semiconductor chip having connection terminals on one main surface thereof; and a chip component (31) mounted in a position on a die pad (11P) near the semiconductor chip (21), the chip component having connection terminals on one main surface thereof. The semiconductor chip (21) has the connection terminals on the upper surface side, and is mounted on the support material. The chip component (31) has connection terminals (31P1, 31P2) on the upper surface side, and is mounted on the die pad (11P). A connection terminal of the semiconductor chip (21) and a connection terminal of the chip component (31) are directly connected via a wire (W4) without the lead frame being interposed therebetween.

Description

複合電子部品、回路モジュールおよびＤＣＤＣコンバータモジュールComposite electronic components, circuit modules and DCDC converter modules
　本発明は、基板やリードフレームに、半導体チップを含む複数の素子を搭載した複合電子部品に関し、特に小型化、高性能化を容易にした複合電子部品、その複合電子部品を含む回路モジュールおよびＤＣＤＣコンバータモジュールに関する。 The present invention relates to a composite electronic component in which a plurality of elements including a semiconductor chip are mounted on a substrate or a lead frame. In particular, the composite electronic component facilitates downsizing and high performance, a circuit module including the composite electronic component, and DCDC. The converter module.
　従来、基板上に半導体チップとチップ部品とを固定し、チップ部品の電極を基板上の電極にワイヤーボンディングにより接続するように構成された複合電子部品（混成集積回路装置）が特許文献１に示されている。 Japanese Patent Application Laid-Open No. 2005-228867 discloses a composite electronic component (hybrid integrated circuit device) configured to fix a semiconductor chip and a chip component on a substrate and connect the electrode of the chip component to the electrode on the substrate by wire bonding. Has been.
　また、内部に複数のチップコンデンサが設けられ、表面に複数の半導体チップが搭載される、インターポーザが特許文献２に示されている。 Moreover, Patent Document 2 discloses an interposer in which a plurality of chip capacitors are provided inside and a plurality of semiconductor chips are mounted on the surface.
特開平３－５２２６０号公報JP-A-3-52260 特開２０１４－１１２８４号公報JP 2014-11284 A
　特許文献１に示されるように、ワイヤーボンディングにより接続する構造では、ワイヤーボンディングする電極にＮｉ／Ａｕなどの組成で厚メッキしておく必要がある。そのため、一般的なチップ部品の端子にワイヤーを直接接続することはできない。例えば図１９に示されるような構造となる。図１９は、リードフレーム１１に半導体チップ２１およびチップ部品３０がダイボンディングされた複合電子部品の断面図である。 As shown in Patent Document 1, in the structure of connecting by wire bonding, the electrode to be wire bonded needs to be thickly plated with a composition such as Ni / Au. Therefore, a wire cannot be directly connected to a terminal of a general chip component. For example, the structure is as shown in FIG. FIG. 19 is a cross-sectional view of a composite electronic component in which the semiconductor chip 21 and the chip component 30 are die-bonded to the lead frame 11.
　ところが、図１９に示されるような構造の複合電子部品には次のような課題がある。 However, the composite electronic component having the structure as shown in FIG. 19 has the following problems.
（ａ）半導体チップ（ダイ）２１が搭載されるリードフレーム１１にチップ部品３０をダイボンディングする構造では、リードフレーム１１の一部で配線パターンを形成することになるので、リードフレーム１１の形状が複雑になる。そのため、高コストになる、良品率が下がる等の問題が生じる。 (A) In the structure in which the chip component 30 is die-bonded to the lead frame 11 on which the semiconductor chip (die) 21 is mounted, a wiring pattern is formed by a part of the lead frame 11, so that the shape of the lead frame 11 is It becomes complicated. Therefore, problems such as high cost and a decrease in the non-defective product rate occur.
（ｂ）チップ部品３０を搭載した状態で、信頼性確保のためのフィレットＦＬが形成されることが好ましいが、そのために工程コストを生じる。また、チップ部品３０をリードフレーム１１にダイボンディングすると、ダイボンド用導電材の接続抵抗が大きい場合、比較的大電流が流れる個所に使用すると、電力効率が悪化する。 (B) While the fillet FL for ensuring reliability is preferably formed in a state where the chip component 30 is mounted, this causes a process cost. Further, when the chip component 30 is die-bonded to the lead frame 11, when the connection resistance of the die-bonding conductive material is large, the power efficiency is deteriorated when the chip component 30 is used at a location where a relatively large current flows.
（ｃ）図１９に示される絶縁領域Ｓを確保する必要があるだけでなく、ワイヤーＷの接続領域Ｃを確保する必要もあるので、半導体チップ２１とチップ部品３０との間隔を短くできず、複合電子部品全体が大きくなる。 (C) Since it is necessary not only to secure the insulating region S shown in FIG. 19 but also to secure the connection region C of the wire W, the interval between the semiconductor chip 21 and the chip component 30 cannot be shortened, The entire composite electronic component becomes larger.
（ｄ）チップ部品３０が搭載されるリードフレーム端子は島状に孤立した端子（接続不可のNC端子）になるため、パッケージ裏面の放熱性に劣る。また、実装不良の懸念を生ずる。 (D) Since the lead frame terminal on which the chip component 30 is mounted becomes an island-like isolated terminal (non-connectable NC terminal), the heat dissipation on the back surface of the package is inferior. In addition, there is a concern of mounting defects.
　また、特許文献２に示されるように、内部にチップ部品が設けられ、表面に半導体チップが搭載されるインターポーザを備える複合電子部品では、非常に低背なチップ部品が必要となり、部品コストおよび製造コストが嵩む。 Further, as shown in Patent Document 2, a composite electronic component having an interposer in which a chip component is provided and a semiconductor chip is mounted on the surface requires a very low-profile chip component, resulting in component cost and manufacturing. Cost increases.
　本発明の目的は、半導体チップと、それ以外のチップ部品とを１つのパッケージに収める場合の適合性を高めて、小型化、電気的特性の向上を図れる複合電子部品、その複合電子部品を含む回路モジュールおよびＤＣＤＣコンバータを提供することにある。 SUMMARY OF THE INVENTION An object of the present invention includes a composite electronic component capable of improving the compatibility when a semiconductor chip and other chip components are contained in one package, and reducing the size and improving the electrical characteristics, and the composite electronic component. It is to provide a circuit module and a DCDC converter.
（１）本発明の複合電子部品は次のように構成される。 (1) The composite electronic component of the present invention is configured as follows.
　支持材上に搭載され、一方主面に接続端子を有する半導体チップと、
　前記支持材上の、前記半導体チップに近接する位置に搭載され、一方主面に接続端子を有するチップ部品と、
を有し、
　前記半導体チップは、前記接続端子を上面側にして、前記支持材上に搭載され、
　前記チップ部品は、上面に第１接続端子、下面に第２接続端子をそれぞれ有し、
　前記チップ部品は、前記第１接続端子を上面側にして、前記支持材上に搭載されて、前記第２接続端子が前記支持材に接続され、
　前記半導体チップの前記接続端子と前記チップ部品の前記第１接続端子とは、前記支持材を介さずにワイヤーを介して直接接続されている、
　ことを特徴とする。 A semiconductor chip mounted on a support material and having a connection terminal on one main surface;
A chip component mounted on the support material at a position close to the semiconductor chip and having a connection terminal on one main surface;
Have
The semiconductor chip is mounted on the support material with the connection terminal on the upper surface side,
The chip component has a first connection terminal on the upper surface and a second connection terminal on the lower surface,
The chip component is mounted on the support material with the first connection terminal on the upper surface side, and the second connection terminal is connected to the support material,
The connection terminal of the semiconductor chip and the first connection terminal of the chip component are directly connected via a wire without the support material,
It is characterized by that.
　上記構成により、チップ部品の第１、第２の接続端子に対する接続構造が合理的になり、電流経路の抵抗値がより小さくなって電力損失を低減できる。 With the above configuration, the connection structure for the first and second connection terminals of the chip component becomes rational, the resistance value of the current path becomes smaller, and the power loss can be reduced.
（２）また、本発明の複合電子部品は次のように構成される。 (2) The composite electronic component of the present invention is configured as follows.
　支持材上に搭載され、一方主面に接続端子を有する半導体チップと、
　前記支持材上の、前記半導体チップに近接する位置に搭載され、一方主面に接続端子を有するチップ部品と、
を有し、
　前記半導体チップは、前記接続端子を上面側にして、前記支持材上に搭載され、
　前記チップ部品は、上面に第１接続端子、端部に第２接続端子をそれぞれ有し、
　前記チップ部品は、前記第１接続端子を上面側にして、前記支持材上に搭載されて、前記第２接続端子が前記支持材に接続され、
　前記半導体チップの前記接続端子と前記チップ部品の前記第１接続端子とは、前記支持材を介さずにワイヤーを介して直接接続されている、
　ことを特徴とする。 A semiconductor chip mounted on a support material and having a connection terminal on one main surface;
A chip component mounted on the support material at a position close to the semiconductor chip and having a connection terminal on one main surface;
Have
The semiconductor chip is mounted on the support material with the connection terminal on the upper surface side,
The chip component has a first connection terminal on the upper surface and a second connection terminal on the end,
The chip component is mounted on the support material with the first connection terminal on the upper surface side, and the second connection terminal is connected to the support material,
The connection terminal of the semiconductor chip and the first connection terminal of the chip component are directly connected via a wire without the support material,
It is characterized by that.
　上記構成により、支持材に対しては端部に形成された第２接続端子で容易に接続でき、第１接続端子に対しては容易にワイヤー接続できる。 With the above configuration, the support member can be easily connected by the second connection terminal formed at the end portion, and the first connection terminal can be easily connected by wire.
（３）上記（１）または（２）に記載の複合電子部品において、前記半導体チップおよび前記チップ部品は、共通の電極上に搭載されることが好ましい。このことにより、放熱経路の断面積が大きくなるため、チップ部品および半導体チップの放熱性が高まる。 (3) In the composite electronic component according to (1) or (2), it is preferable that the semiconductor chip and the chip component are mounted on a common electrode. This increases the cross-sectional area of the heat dissipation path, so that the heat dissipation performance of the chip component and the semiconductor chip is enhanced.
（４）上記（１）～（３）のいずれかに記載の複合電子部品において、
　前記支持材はリードフレームであり、
　前記半導体チップおよび前記チップ部品は、前記リードフレームのダイパッド（共通フレーム）に搭載されることが好ましい。このことにより、リードフレームのパターンが複雑化しない。また、チップ部品および半導体チップの放熱性が高まる。 (4) In the composite electronic component according to any one of (1) to (3) above,
The support material is a lead frame;
The semiconductor chip and the chip component are preferably mounted on a die pad (common frame) of the lead frame. This does not complicate the lead frame pattern. Moreover, the heat dissipation of chip components and semiconductor chips is enhanced.
（５）本発明のＤＣＤＣコンバータモジュールは、上記（１）～（４）のいずれかに記載の複合電子部品を備え、
　前記複合電子部品は、電源入力端子、電源出力端子およびグランド端子を有し、
　前記半導体チップはスイッチング素子およびスイッチング制御回路を含むスイッチング電源用ＩＣであり、
　前記チップ部品はインダクタンス素子であり、前記チップ部品の少なくとも第１端は前記スイッチング素子に接続されることを特徴とする。 (5) A DCDC converter module of the present invention includes the composite electronic component according to any one of (1) to (4) above,
The composite electronic component has a power input terminal, a power output terminal and a ground terminal,
The semiconductor chip is a switching power supply IC including a switching element and a switching control circuit,
The chip component is an inductance element, and at least a first end of the chip component is connected to the switching element.
　上記構成により、電流経路の抵抗値が小さくなって電力損失を低減でき、高い電力変換効率が得られる。また、半導体チップとチップ部品との間隔を短くでき、全体を小型化できる。また、島状に孤立した端子が不要であるため、高い放熱性が維持できる。 With the above configuration, the resistance value of the current path is reduced, power loss can be reduced, and high power conversion efficiency can be obtained. Further, the distance between the semiconductor chip and the chip component can be shortened, and the whole can be miniaturized. Moreover, since an island-like isolated terminal is unnecessary, high heat dissipation can be maintained.
（６）また、本発明の複合電子部品は次のように構成される。 (6) Moreover, the composite electronic component of this invention is comprised as follows.
　支持材（基板、リードフレーム等）上に搭載され、一方主面に接続端子（パッド）を有する半導体チップと、
　前記支持材上の、前記半導体チップに近接する位置に搭載され、一方主面に接続端子を有するチップ部品と、
を有し、
　前記半導体チップは、前記接続端子を上面側にして、前記支持材上に搭載され、
　前記チップ部品は、少なくとも上面に接続端子が位置するように、前記支持材上に搭載され、
　前記半導体チップの前記接続端子と前記チップ部品の前記接続端子とは、前記支持材を介さずにワイヤーを介して直接接続されている、
　ことを特徴とする。 A semiconductor chip mounted on a support material (substrate, lead frame, etc.) and having a connection terminal (pad) on one main surface;
A chip component mounted on the support material at a position close to the semiconductor chip and having a connection terminal on one main surface;
Have
The semiconductor chip is mounted on the support material with the connection terminal on the upper surface side,
The chip component is mounted on the support material such that the connection terminal is located at least on the upper surface,
The connection terminal of the semiconductor chip and the connection terminal of the chip component are directly connected via a wire without the support material,
It is characterized by that.
　上記構成により、リードフレームに半導体チップおよびチップ部品を搭載する場合でも、リードフレームの形状が簡素化できる。また、電流経路の抵抗値が小さくなって電力損失を低減できる。また、半導体チップとチップ部品との間隔を短くでき、複合電子部品全体を小型化できるとともに、ダイボンド分の抵抗を低減でき効率が向上する。また、島状に孤立したダイパッドが不要であるため、高い放熱性が維持できる。さらに、内部にチップ部品が設けられ、表面に半導体チップが搭載されるインターポーザを備えないので、チップ部品は半導体チップと同程度のサイズであれば適用でき、部品コストおよび製造コストは低減される。 With the above configuration, the shape of the lead frame can be simplified even when a semiconductor chip and chip parts are mounted on the lead frame. In addition, the resistance value of the current path is reduced, and power loss can be reduced. In addition, the distance between the semiconductor chip and the chip component can be shortened, the entire composite electronic component can be reduced in size, and the resistance of the die bond can be reduced to improve the efficiency. In addition, since a die pad isolated in an island shape is unnecessary, high heat dissipation can be maintained. Furthermore, since the chip component is provided inside and the interposer on which the semiconductor chip is mounted is not provided on the surface, the chip component can be applied as long as it is the same size as the semiconductor chip, and the component cost and the manufacturing cost are reduced.
（７）本発明の回路モジュールは、上記（６）に記載の複合電子部品を備え、
　電源端子およびグランド端子を有し、
　前記チップ部品は、前記電源端子と前記グランド端子との間に接続される、デカップリング用のコンデンサ素子であることを特徴とする。 (7) A circuit module of the present invention includes the composite electronic component according to (6) above,
It has a power supply terminal and a ground terminal,
The chip component is a decoupling capacitor element connected between the power supply terminal and the ground terminal.
　上記構成により、半導体チップからデカップリング用のコンデンサ素子までの電流経路長が短いので、等価直列インダクタンス（ESL）が小さく、ノイズ低減効果が高い。また、その分、コンデンサ単体でのESLがそれほど小さくなくてよい。 With the above configuration, since the current path length from the semiconductor chip to the decoupling capacitor element is short, the equivalent series inductance (ESL) is small and the noise reduction effect is high. In addition, the ESL of the capacitor alone need not be so small.
　本発明によれば、半導体チップと、それ以外のチップ部品とを１つのパッケージに収める場合の適合性が高まり、小型で電気的特性の高い複合電子部品、その複合電子部品を含む回路モジュールおよびＤＣＤＣコンバータが得られる。 ADVANTAGE OF THE INVENTION According to this invention, the compatibility in the case of accommodating a semiconductor chip and other chip components in one package is improved, and a small-sized composite electronic component having high electrical characteristics, a circuit module including the composite electronic component, and DCDC A converter is obtained.
図１は第１の実施形態に係る複合電子部品１０１の主要部の断面図である。FIG. 1 is a cross-sectional view of the main part of a composite electronic component 101 according to the first embodiment. 図２は複合電子部品１０１の、モールド樹脂の無い状態での平面図である。FIG. 2 is a plan view of the composite electronic component 101 without a mold resin. 図３（Ａ）はチップ部品３１の斜視図、図３（Ｂ）はチップ部品３１の断面図、図３（Ｃ）はチップ部品３１の導体部分の構造を示す斜視図である。3A is a perspective view of the chip component 31, FIG. 3B is a cross-sectional view of the chip component 31, and FIG. 3C is a perspective view showing a structure of a conductor portion of the chip component 31. 図４は本実施形態の複合電子部品１０１の回路図である。FIG. 4 is a circuit diagram of the composite electronic component 101 of this embodiment. 図５は第２の実施形態に係る複合電子部品１０２の主要部の断面図である。FIG. 5 is a cross-sectional view of the main part of the composite electronic component 102 according to the second embodiment. 図６は第３の実施形態に係る複合電子部品１０３の主要部の断面図である。FIG. 6 is a cross-sectional view of the main part of the composite electronic component 103 according to the third embodiment. 図７は複合電子部品１０３の、モールド樹脂の無い状態での平面図である。FIG. 7 is a plan view of the composite electronic component 103 without a mold resin. 図８（Ａ）はチップ部品３２の斜視図、図８（Ｂ）はチップ部品３２の断面図である。FIG. 8A is a perspective view of the chip component 32, and FIG. 8B is a cross-sectional view of the chip component 32. 図９は本実施形態の複合電子部品１０３の回路図である。FIG. 9 is a circuit diagram of the composite electronic component 103 of the present embodiment. 図１０は第４の実施形態に係る複合電子部品１０４の主要部の断面図である。FIG. 10 is a cross-sectional view of the main part of the composite electronic component 104 according to the fourth embodiment. 図１１は複合電子部品１０４の、モールド樹脂の無い状態での平面図である。FIG. 11 is a plan view of the composite electronic component 104 without a mold resin. 図１２（Ａ）はチップ部品３１の斜視図、図１２（Ｂ）はチップ部品３１の断面図、図１２（Ｃ）はチップ部品３１の導体部分の構造を示す斜視図である。12A is a perspective view of the chip component 31, FIG. 12B is a cross-sectional view of the chip component 31, and FIG. 12C is a perspective view showing the structure of the conductor portion of the chip component 31. 図１３は本実施形態の複合電子部品１０４の回路図である。FIG. 13 is a circuit diagram of the composite electronic component 104 of this embodiment. 図１４は第５の実施形態に係る複合電子部品１０５の主要部の断面図である。FIG. 14 is a cross-sectional view of the main part of the composite electronic component 105 according to the fifth embodiment. 図１５は複合電子部品１０５の、モールド樹脂の無い状態での平面図である。FIG. 15 is a plan view of the composite electronic component 105 without a mold resin. 図１６（Ａ）はチップ部品３１の斜視図、図１６（Ｂ）はチップ部品３１の断面図、図１６（Ｃ）はチップ部品３１の導体部分の構造を示す斜視図である。16A is a perspective view of the chip component 31, FIG. 16B is a cross-sectional view of the chip component 31, and FIG. 16C is a perspective view showing a structure of a conductor portion of the chip component 31. 図１７は第６の実施形態に係る複合電子部品１０６の、モールド樹脂の無い状態での平面図である。FIG. 17 is a plan view of the composite electronic component 106 according to the sixth embodiment in the absence of mold resin. 図１８は本実施形態の複合電子部品１０６の回路図である。FIG. 18 is a circuit diagram of the composite electronic component 106 of this embodiment. 図１９は、リードフレーム１１に半導体チップ２１およびチップ部品３０がダイボンディングされた複合電子部品の断面図である。FIG. 19 is a cross-sectional view of a composite electronic component in which the semiconductor chip 21 and the chip component 30 are die-bonded to the lead frame 11.
　以降、図を参照して幾つかの具体的な例を挙げて、本発明を実施するための複数の形態を示す。各図中には同一箇所に同一符号を付す。第２の実施形態以降では第１の実施形態と共通の事柄についての記述を省略し、異なる点について説明する。特に、同様の構成による同様の作用効果については実施形態毎には逐次言及しない。 Hereinafter, several specific examples will be given with reference to the drawings to show a plurality of modes for carrying out the present invention. In the drawings, the same reference numerals are given to the same portions. In the second and subsequent embodiments, description of matters common to the first embodiment is omitted, and different points will be described. In particular, the same operation effect by the same configuration will not be sequentially described for each embodiment.
《第１の実施形態》
　第１の実施形態では、ＤＣＤＣコンバータモジュールである複合電子部品の例を示す。図１は第１の実施形態に係る複合電子部品１０１の主要部の断面図である。図２は複合電子部品１０１の、モールド樹脂の無い状態での平面図である。図１は、図２におけるＡ－Ａラインでの模式的な断面図である。 << First Embodiment >>
In 1st Embodiment, the example of the composite electronic component which is a DCDC converter module is shown. FIG. 1 is a cross-sectional view of the main part of a composite electronic component 101 according to the first embodiment. FIG. 2 is a plan view of the composite electronic component 101 without a mold resin. FIG. 1 is a schematic cross-sectional view taken along line AA in FIG.
　複合電子部品１０１は、支持材の例であるリードフレーム（１１ａ～１１ｆ，１１Ｐ等）、半導体チップ２１およびチップ部品３１を備える。半導体チップ２１およびチップ部品３１は、リードフレームのダイパッド１１Ｐ上に近接して搭載される。チップ部品３１は一方主面に接続端子（パッド）３１Ｐ１，３１Ｐ２を有する。 The composite electronic component 101 includes a lead frame (11a to 11f, 11P, etc.), a semiconductor chip 21 and a chip component 31, which are examples of support materials. The semiconductor chip 21 and the chip component 31 are mounted close to each other on the die pad 11P of the lead frame. The chip component 31 has connection terminals (pads) 31P1 and 31P2 on one main surface.
　半導体チップ２１は、接続端子を上面側にして、リードフレームのダイパッド１１Ｐ上に搭載され、チップ部品３１は、接続端子３１Ｐ１，３１Ｐ２を上面側にして、ダイパッド１１Ｐ上にダイボンディングされる。 The semiconductor chip 21 is mounted on the die pad 11P of the lead frame with the connection terminal on the upper surface side, and the chip component 31 is die-bonded on the die pad 11P with the connection terminals 31P1 and 31P2 on the upper surface side.
　図２に表れるように、リードフレームは端子１１ａ，１１ｂ，１１ｃ，１１ｄ，１１ｅ，１１ｆおよびダイパッド１１Ｐを備える。半導体チップ２１は複数の接続端子を備え、半導体チップ２１の所定の端子はリードフレームの端子１１ａ，１１ｂ，１１ｄ，１１ｅ，１１ｆにそれぞれワイヤーＷ１，Ｗ２，Ｗ５，Ｗ６，Ｗ７を介して接続される。また、半導体チップ２１の所定の端子はチップ部品３１の接続端子３１Ｐ１，３１Ｐ２に、支持材を介さずにワイヤーＷ３，Ｗ４を介して直接接続される。 As shown in FIG. 2, the lead frame includes terminals 11a, 11b, 11c, 11d, 11e, 11f and a die pad 11P. The semiconductor chip 21 includes a plurality of connection terminals, and predetermined terminals of the semiconductor chip 21 are connected to terminals 11a, 11b, 11d, 11e, and 11f of the lead frame via wires W1, W2, W5, W6, and W7, respectively. . In addition, the predetermined terminal of the semiconductor chip 21 is directly connected to the connection terminals 31P1 and 31P2 of the chip component 31 via the wires W3 and W4 without the support material.
　チップ部品３１の接続端子３１Ｐ１はリードフレームの端子１１ｃにワイヤーＷ８を介して接続される。このワイヤーＷ８は２本であるので、チップ部品３１と端子１１ｃ間の線路抵抗は低減される。 The connection terminal 31P1 of the chip component 31 is connected to the terminal 11c of the lead frame via the wire W8. Since there are two wires W8, the line resistance between the chip component 31 and the terminal 11c is reduced.
　リードフレームの上部は、例えばエポキシ樹脂等のモールド樹脂４０でモールドされている。これにより、複合電子部品１０１は、QFN（Quad Flat Non-Leaded Package）またはSON（Small Outline Non-Leaded Package）型にパッケージ化される。この複合電子部品１０１は表面実装型の電子部品として、プリント配線基板に実装される。 The upper part of the lead frame is molded with a mold resin 40 such as an epoxy resin. Thereby, the composite electronic component 101 is packaged in a QFN (Quad Flat Non-Leaded Package) or SON (Small Outline Non-Leaded Package) type. The composite electronic component 101 is mounted on a printed wiring board as a surface mount type electronic component.
　図３（Ａ）は上記チップ部品３１の斜視図、図３（Ｂ）はチップ部品３１の断面図、図３（Ｃ）はチップ部品３１の導体部分の構造を示す斜視図である。チップ部品３１は複数の導体パターンが形成された絶縁体層を含む複数の絶縁体層の積層体である。本実施形態のチップ部品３１はインダクタンス素子である。チップ部品３１の内部にはコイル導体３１Ｌ、およびビア導体３１Ｖ１，３１Ｖ２を備える。コイル導体３１Ｌは、絶縁体層に沿った複数の導体パターンと複数の層間接続導体とで構成される矩形ヘリカル状の導体パターンである。ビア導体３１Ｖ２はコイルの巻回範囲内を通っている。 3A is a perspective view of the chip component 31, FIG. 3B is a cross-sectional view of the chip component 31, and FIG. 3C is a perspective view showing a structure of a conductor portion of the chip component 31. FIG. The chip component 31 is a laminate of a plurality of insulator layers including an insulator layer on which a plurality of conductor patterns are formed. The chip component 31 of this embodiment is an inductance element. The chip component 31 includes a coil conductor 31L and via conductors 31V1 and 31V2. The coil conductor 31L is a rectangular helical conductor pattern including a plurality of conductor patterns along the insulator layer and a plurality of interlayer connection conductors. The via conductor 31V2 passes through the coil winding range.
　図４は本実施形態の複合電子部品１０１の回路図である。本実施形態の複合電子部品１０１はＤＣＤＣコンバータに用いられるＤＣＤＣコンバータモジュールである。この複合電子部品１０１は半導体チップ２１とチップ部品３１とを備える。半導体チップ２１は、スイッチング素子Ｑ１，Ｑ２およびスイッチング制御回路２１Ｃを備える。スイッチング素子Ｑ１，Ｑ２の直列回路は、複合電子部品１０１の電源入力端子ＩＮとグランド端子ＧＮＤとの間に接続される。インダクタンス素子であるチップ部品３１の一端はスイッチング素子Ｑ１，Ｑ２の接続点に接続され、他端は複合電子部品１０１の出力端子ＯＵＴに接続される。スイッチング制御回路２１Ｃのイネーブル端子は複合電子部品１０１のＥＮ端子に接続される。 FIG. 4 is a circuit diagram of the composite electronic component 101 of the present embodiment. The composite electronic component 101 of the present embodiment is a DCDC converter module used for a DCDC converter. The composite electronic component 101 includes a semiconductor chip 21 and a chip component 31. The semiconductor chip 21 includes switching elements Q1 and Q2 and a switching control circuit 21C. A series circuit of the switching elements Q1, Q2 is connected between the power input terminal IN of the composite electronic component 101 and the ground terminal GND. One end of the chip component 31 which is an inductance element is connected to the connection point of the switching elements Q1 and Q2, and the other end is connected to the output terminal OUT of the composite electronic component 101. The enable terminal of the switching control circuit 21C is connected to the EN terminal of the composite electronic component 101.
　複合電子部品１０１の電源入力端子ＩＮには電源Ｅおよび入力コンデンサＣｉが接続される。複合電子部品１０１の出力端子には出力コンデンサＣｏが接続される。この出力コンデンサＣｏの電圧が負荷へ供給される。また、出力電圧はスイッチング制御回路２１Ｃのフィードバック端子ＦＢに入力される。 The power supply E and the input capacitor Ci are connected to the power input terminal IN of the composite electronic component 101. An output capacitor Co is connected to the output terminal of the composite electronic component 101. The voltage of the output capacitor Co is supplied to the load. The output voltage is input to the feedback terminal FB of the switching control circuit 21C.
　本実施形態によれば、次のような効果を奏する。 According to this embodiment, the following effects can be obtained.
（ａ）リードフレームは、パッケージの周囲に配置される端子１１ａ～１１ｆ、中央にダイパッド１１Ｐを備えるだけであるのでリードフレームの形状が簡素化できる。 (A) Since the lead frame only includes the terminals 11a to 11f arranged around the package and the die pad 11P at the center, the shape of the lead frame can be simplified.
（ｂ）インダクタンス素子であるチップ部品３１の一端とスイッチング素子Ｑ１，Ｑ２の接続点との間はワイヤーＷ４で直接接続され、チップ部品３１の他端と出力端子ＯＵＴとの間にワイヤーＷ８で接続される（図２参照）。そのため、最も電流量の大きな経路での導体損失が抑制される。 (B) One end of the chip component 31 which is an inductance element and the connection point of the switching elements Q1 and Q2 are directly connected by a wire W4, and the other end of the chip component 31 and the output terminal OUT are connected by a wire W8. (See FIG. 2). Therefore, the conductor loss in the path with the largest current amount is suppressed.
（ｃ）半導体チップ２１とチップ部品３１との間隔を短くでき、複合電子部品１０１全体を小型化できる。 (C) The distance between the semiconductor chip 21 and the chip component 31 can be shortened, and the entire composite electronic component 101 can be reduced in size.
（ｄ）半導体チップ２１とチップ部品３１とで島状に孤立したダイパッドが不要であるため、高い放熱性が維持できる。 (D) Since a die pad isolated in an island shape between the semiconductor chip 21 and the chip component 31 is not required, high heat dissipation can be maintained.
（ｅ）インターポーザを備えないので、チップ部品３１は半導体チップ２１と同程度のサイズであれば適用でき、部品コストおよび製造コストが低減される。 (E) Since no interposer is provided, the chip component 31 can be applied as long as it has the same size as the semiconductor chip 21, and the component cost and manufacturing cost are reduced.
《第２の実施形態》
　第２の実施形態では、FBGA（Fine pitch Ball Grid Array）型にパッケージ化された複合電子部品の例を示す。 << Second Embodiment >>
In the second embodiment, an example of a composite electronic component packaged in an FBGA (Fine pitch Ball Grid Array) type is shown.
　図５は第２の実施形態に係る複合電子部品１０２の主要部の断面図である。この複合電子部品１０２は、積層基板１２、半導体チップ２１およびチップ部品３１を備える。半導体チップ２１およびチップ部品３１は、積層基板１２上に形成されている共通電極１２Ｐに近接して搭載される。チップ部品３１は一方主面に接続端子（パッド）３１Ｐ１，３１Ｐ２を有する。 FIG. 5 is a cross-sectional view of the main part of the composite electronic component 102 according to the second embodiment. The composite electronic component 102 includes a laminated substrate 12, a semiconductor chip 21, and a chip component 31. The semiconductor chip 21 and the chip component 31 are mounted in the vicinity of the common electrode 12P formed on the laminated substrate 12. The chip component 31 has connection terminals (pads) 31P1 and 31P2 on one main surface.
　積層基板１２は、プリント積層基板であり、上面に複数の接続端子１２ａ，１２ｂ等が形成される。下面には複数のランドが形成され、それらランドにはんだボールＳＢが設けられる。 The laminated substrate 12 is a printed laminated substrate, and a plurality of connection terminals 12a, 12b and the like are formed on the upper surface. A plurality of lands are formed on the lower surface, and solder balls SB are provided on the lands.
　半導体チップ２１は、接続端子を上面側にして、共通電極１２Ｐ上に搭載され、チップ部品３１は、接続端子３１Ｐ１，３１Ｐ２を上面側にして、共通電極１２Ｐ上にダイボンディングされる。 The semiconductor chip 21 is mounted on the common electrode 12P with the connection terminal on the upper surface side, and the chip component 31 is die-bonded on the common electrode 12P with the connection terminals 31P1 and 31P2 on the upper surface side.
　積層基板１２上の接続端子１２ａ，１２ｂ等へのワイヤーボンディングは、第１の実施形態で示したリードフレームタイプの複合電子部品１０１の場合と同様である。このように、FBGA型の複合電子部品も構成できる。 Wire bonding to the connection terminals 12a, 12b, etc. on the laminated substrate 12 is the same as that of the lead frame type composite electronic component 101 shown in the first embodiment. In this way, an FBGA type composite electronic component can also be configured.
《第３の実施形態》
　第３の実施形態は、第１の実施形態と異なり、インダクタンス素子だけでなく、キャパシタンス素子も備える。 << Third Embodiment >>
Unlike the first embodiment, the third embodiment includes not only an inductance element but also a capacitance element.
　図６は第３の実施形態に係る複合電子部品１０３の主要部の断面図である。図７は複合電子部品１０３の、モールド樹脂の無い状態での平面図である。図６は、図７におけるＡ－Ａラインでの断面図である。 FIG. 6 is a cross-sectional view of the main part of the composite electronic component 103 according to the third embodiment. FIG. 7 is a plan view of the composite electronic component 103 without a mold resin. 6 is a cross-sectional view taken along line AA in FIG.
　複合電子部品１０３は、支持材の例であるリードフレーム（１１ｍ，１１ｄ，１１Ｐ等）、半導体チップ２１およびチップ部品３１，３２を備える。半導体チップ２１およびチップ部品３１，３２は、リードフレームのダイパッド１１Ｐ上に近接して搭載される。チップ部品３１は一方主面に接続端子３１Ｐ１，３１Ｐ２を有する。チップ部品３２は一方主面に接続端子３２Ｐ１，３２Ｐ２を有する。 The composite electronic component 103 includes a lead frame (11m, 11d, 11P, etc.) that is an example of a support material, a semiconductor chip 21, and chip components 31, 32. The semiconductor chip 21 and the chip components 31 and 32 are mounted close to each other on the die pad 11P of the lead frame. The chip component 31 has connection terminals 31P1 and 31P2 on one main surface. The chip component 32 has connection terminals 32P1 and 32P2 on one main surface.
　半導体チップ２１は、接続端子を上面側にして、リードフレームのダイパッド１１Ｐ上に搭載され、チップ部品３１は、接続端子３１Ｐ１，３１Ｐ２を上面側にして、ダイパッド１１Ｐ上にダイボンディングされ、チップ部品３２は、接続端子３２Ｐ１，３２Ｐ２を上面側にして、ダイパッド１１Ｐ上にダイボンディングされる。 The semiconductor chip 21 is mounted on the die pad 11P of the lead frame with the connection terminal on the upper surface side, and the chip component 31 is die-bonded on the die pad 11P with the connection terminals 31P1 and 31P2 on the upper surface side. Are die-bonded on the die pad 11P with the connection terminals 32P1 and 32P2 on the upper surface side.
　図７に表れるように、リードフレームは端子１１ａ，１１ｂ，１１ｃ，１１ｄ，１１ｅ，１１ｆ，１１ｇ，１１ｈ，１１ｉ，１１ｊ，１１ｋ，１１ｍおよびダイパッド１１Ｐを備える。半導体チップ２１は複数の接続端子を備え、半導体チップ２１の所定の端子はリードフレームの端子１１ａ，１１ｂ，１１ｃ，１１ｇ，１１ｈ，１１ｉ，１１ｊにそれぞれワイヤーＷ５，Ｗ６，Ｗ１０，Ｗ１３，Ｗ７，Ｗ１，Ｗ２を介して接続される。半導体チップ２１の所定の端子はチップ部品３１の接続端子３１Ｐ１，３１Ｐ２に、支持材を介さずにワイヤーＷ３，Ｗ４を介して直接接続される。 As shown in FIG. 7, the lead frame includes terminals 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i, 11j, 11k, 11m and a die pad 11P. The semiconductor chip 21 has a plurality of connection terminals, and predetermined terminals of the semiconductor chip 21 are wires W5, W6, W10, W13, W7, W1 to terminals 11a, 11b, 11c, 11g, 11h, 11i, 11j of the lead frame, respectively. , W2 are connected. Predetermined terminals of the semiconductor chip 21 are directly connected to the connection terminals 31P1 and 31P2 of the chip component 31 via the wires W3 and W4 without the support material.
　チップ部品３１の接続端子３１Ｐ１，３１Ｐ２はリードフレームの端子１１ｄ，１１ｅ，１１ｆにワイヤーＷ８，Ｗ１１，Ｗ１２を介して接続される。 The connection terminals 31P1 and 31P2 of the chip component 31 are connected to the terminals 11d, 11e, and 11f of the lead frame via wires W8, W11, and W12.
　チップ部品３２の接続端子３２Ｐ１，３２Ｐ２はリードフレームの端子１１ｍ，１１ｋにワイヤーＷ１４，Ｗ９を介して接続される。 The connection terminals 32P1 and 32P2 of the chip component 32 are connected to the terminals 11m and 11k of the lead frame via wires W14 and W9.
　図８（Ａ）は上記チップ部品３２の斜視図、図８（Ｂ）はチップ部品３２の断面図である。チップ部品３２は複数の導体パターンが形成された絶縁体層を含む複数の絶縁体層の積層体である。本実施形態のチップ部品３２はキャパシタンス素子である。チップ部品３２の内部には平面導体３２Ｅ１，３２Ｅ２、およびビア導体３２Ｃ１，３２Ｃ２を備える。平面導体３２Ｅ１，３２Ｅ２の対向部分に容量が形成され、ビア導体３２Ｃ１，３２Ｃ２でそれぞれ共通接続される。 8A is a perspective view of the chip part 32, and FIG. 8B is a cross-sectional view of the chip part 32. FIG. The chip component 32 is a laminate of a plurality of insulator layers including an insulator layer on which a plurality of conductor patterns are formed. The chip component 32 of this embodiment is a capacitance element. The chip component 32 includes planar conductors 32E1 and 32E2 and via conductors 32C1 and 32C2. Capacitances are formed in the opposing portions of the planar conductors 32E1 and 32E2, and are commonly connected by the via conductors 32C1 and 32C2.
　図９は本実施形態の複合電子部品１０３の回路図である。本実施形態では、複合電子部品１０３は、入力コンデンサを内蔵するＤＣＤＣコンバータモジュールである。この複合電子部品１０３のチップ部品３２は、電源入力端子ＩＮとグランド端子ＧＮＤとの間に接続される入力コンデンサとして作用する。そのため、複合電子部品１０３の外部に、図４に示したような入力コンデンサＣｉは不要である。その他の構成は第１の実施形態で図４に示した複合電子部品１０１と同じである。 FIG. 9 is a circuit diagram of the composite electronic component 103 of the present embodiment. In the present embodiment, the composite electronic component 103 is a DCDC converter module incorporating an input capacitor. The chip component 32 of the composite electronic component 103 functions as an input capacitor connected between the power input terminal IN and the ground terminal GND. Therefore, the input capacitor Ci as shown in FIG. 4 is not required outside the composite electronic component 103. Other configurations are the same as those of the composite electronic component 101 shown in FIG. 4 in the first embodiment.
　本実施形態では、電源入力端子ＩＮ、出力端子ＯＵＴ、グランド端子ＧＮＤをそれぞれ複数備えているので、比較的大電流の流れる経路の線路抵抗は低く、低損失化される。また、入力コンデンサであるチップ部品３２と半導体チップ２１との経路長が短縮化され、半導体チップが安定動作し、入力電源ラインへのノイズ重畳が効果的に抑制される。 In this embodiment, since a plurality of power input terminals IN, output terminals OUT, and ground terminals GND are provided, the line resistance of the path through which a relatively large current flows is low, and the loss is reduced. Further, the path length between the chip component 32, which is an input capacitor, and the semiconductor chip 21 is shortened, the semiconductor chip operates stably, and noise superposition to the input power supply line is effectively suppressed.
《第４の実施形態》
　図１０は第４の実施形態に係る複合電子部品１０４の主要部の断面図である。図１１は複合電子部品１０４の、モールド樹脂の無い状態での平面図である。図１０は、図１１におけるＡ－Ａラインでの断面図である。 << Fourth Embodiment >>
FIG. 10 is a cross-sectional view of the main part of the composite electronic component 104 according to the fourth embodiment. FIG. 11 is a plan view of the composite electronic component 104 without a mold resin. FIG. 10 is a cross-sectional view taken along line AA in FIG.
　複合電子部品１０４は、支持材の例であるリードフレーム（１１ａ～１１ｍ，１１Ｐ等）、半導体チップ２１およびチップ部品３１，３２を備える。半導体チップ２１およびチップ部品３１，３２は、リードフレームのダイパッド１１Ｐ上に近接して搭載される。チップ部品３２は上面に２つの接続端子を有する。チップ部品３１は上面に接続端子３１Ｐ１を有し、下面に接続端子３１Ｐ２を有する。接続端子３１Ｐ１の中心と接続端子３１Ｐ２の中心は、平面視で重ならない位置にある。 The composite electronic component 104 includes a lead frame (11a to 11m, 11P, etc.) as an example of a support material, a semiconductor chip 21, and chip components 31 and 32. The semiconductor chip 21 and the chip components 31 and 32 are mounted close to each other on the die pad 11P of the lead frame. The chip component 32 has two connection terminals on the upper surface. The chip component 31 has a connection terminal 31P1 on the upper surface and a connection terminal 31P2 on the lower surface. The center of the connection terminal 31P1 and the center of the connection terminal 31P2 are in positions that do not overlap in plan view.
　図１１に表れるように、リードフレームは端子１１ａ，１１ｂ，１１ｃ，１１ｄ，１１ｅ，１１ｆ，１１ｇ，１１ｈ，１１ｉ，１１ｊ，１１ｋ，１１ｍおよびダイパッド１１Ｐを備える。半導体チップ２１は複数の接続端子を備え、半導体チップ２１の所定の端子はリードフレームの端子１１ａ，１１ｂ，１１ｄ，１１ｇ，１１ｈ，１１ｉ，１１ｊ，１１ｋ，１１ｍにそれぞれワイヤーを介して接続される。半導体チップ２１の所定の端子はチップ部品３１の接続端子３１Ｐ１に、支持材を介さずにワイヤーＷ４を介して直接接続される。このワイヤーＷ４は２本であるので、チップ部品３１と半導体チップ２１の端子との間の線路抵抗は低減される。 As shown in FIG. 11, the lead frame includes terminals 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i, 11j, 11k, 11m and a die pad 11P. The semiconductor chip 21 includes a plurality of connection terminals, and the predetermined terminals of the semiconductor chip 21 are connected to the terminals 11a, 11b, 11d, 11g, 11h, 11i, 11j, 11k, and 11m of the lead frame via wires. The predetermined terminal of the semiconductor chip 21 is directly connected to the connection terminal 31P1 of the chip component 31 through the wire W4 without the support material. Since there are two wires W4, the line resistance between the chip component 31 and the terminal of the semiconductor chip 21 is reduced.
　チップ部品３２は半導体チップ２１の１つの端子とリードフレームの端子１１ｃとの間にワイヤーを介して接続される。 The chip component 32 is connected between one terminal of the semiconductor chip 21 and the terminal 11c of the lead frame via a wire.
　図１０に表れるように、チップ部品３１の接続端子３１Ｐ２はリードフレームの端子１１ｅ，１１ｆにダイボンディングされる。 As shown in FIG. 10, the connection terminal 31P2 of the chip component 31 is die-bonded to the terminals 11e and 11f of the lead frame.
　図１２（Ａ）は上記チップ部品３１の斜視図、図１２（Ｂ）はチップ部品３１の断面図、図１２（Ｃ）はチップ部品３１の導体部分の構造を示す斜視図である。チップ部品３１は複数の導体パターンが形成された絶縁体層を含む複数の絶縁体層の積層体である。本実施形態のチップ部品３１はインダクタンス素子である。チップ部品３１の内部にはコイル導体３１Ｌ、およびビア導体３１Ｖ１，３１Ｖ２を備える。コイル導体３１Ｌは、絶縁体層に沿った複数の導体パターンと複数の層間接続導体とで構成される矩形ヘリカル状の導体パターンである。第１の実施形態で図３（Ａ）（Ｂ）（Ｃ）に示した例と異なり、矩形ヘリカル状の導体パターンの上方端はビア導体３１Ｖ１を介して上面の端子３１Ｐ１に接続され、矩形ヘリカル状の導体パターンの下方端はビア導体３１Ｖ２を介して下面の端子３１Ｐ２に接続される。この構造によれば、インダクタンスにあまり寄与しない導体部分が短くなって、ＤＣＲ（Direct Current Resistance）は小さい。また、図１９の従来例と比べて、端子３１Ｐ１側のダイボンド接続を削除できるので、その分ＤＣＲが低減でき、ＤＣＤＣコンバータの効率が向上する。 12A is a perspective view of the chip component 31, FIG. 12B is a cross-sectional view of the chip component 31, and FIG. 12C is a perspective view showing a structure of a conductor portion of the chip component 31. FIG. The chip component 31 is a laminate of a plurality of insulator layers including an insulator layer on which a plurality of conductor patterns are formed. The chip component 31 of this embodiment is an inductance element. The chip component 31 includes a coil conductor 31L and via conductors 31V1 and 31V2. The coil conductor 31L is a rectangular helical conductor pattern including a plurality of conductor patterns along the insulator layer and a plurality of interlayer connection conductors. Unlike the example shown in FIGS. 3A, 3B, and 3C in the first embodiment, the upper end of the rectangular helical conductor pattern is connected to the terminal 31P1 on the upper surface via the via conductor 31V1, and the rectangular helical The lower end of the conductor pattern is connected to the lower terminal 31P2 via the via conductor 31V2. According to this structure, the conductor portion that does not contribute much to the inductance is shortened, and the DCR (Direct Current Current) is small. Further, since the die bond connection on the terminal 31P1 side can be eliminated as compared with the conventional example of FIG. 19, the DCR can be reduced correspondingly, and the efficiency of the DCDC converter is improved.
　図１３は本実施形態の複合電子部品１０４の回路図である。本実施形態では、複合電子部品１０４は、入力コンデンサを内蔵するＤＣＤＣコンバータモジュールである。基本的な回路構成は、第３の実施形態で図９に示した構成と同じである。なお、本実施形態では、インダクタンス素子であるチップ部品３１の電流経路の線路抵抗が低いので、高効率なＤＣＤＣコンバータが構成される。 FIG. 13 is a circuit diagram of the composite electronic component 104 of the present embodiment. In the present embodiment, the composite electronic component 104 is a DCDC converter module that incorporates an input capacitor. The basic circuit configuration is the same as that shown in FIG. 9 in the third embodiment. In the present embodiment, since the line resistance of the current path of the chip component 31 that is an inductance element is low, a highly efficient DCDC converter is configured.
《第５の実施形態》
　図１４は第５の実施形態に係る複合電子部品１０５の主要部の断面図である。図１５は複合電子部品１０５の、モールド樹脂の無い状態での平面図である。図１４は、図１５におけるＡ－Ａラインでの断面図である。第４の実施形態とは、チップ部品３１の構造が異なる。 << Fifth Embodiment >>
FIG. 14 is a cross-sectional view of the main part of the composite electronic component 105 according to the fifth embodiment. FIG. 15 is a plan view of the composite electronic component 105 without a mold resin. 14 is a cross-sectional view taken along line AA in FIG. The structure of the chip component 31 is different from that of the fourth embodiment.
　図１６（Ａ）はチップ部品３１の斜視図、図１６（Ｂ）はチップ部品３１の断面図、図１６（Ｃ）はチップ部品３１の導体部分の構造を示す斜視図である。チップ部品３１は複数の導体パターンが形成された絶縁体層を含む複数の絶縁体層の積層体である。チップ部品３１の内部にはコイル導体３１Ｌ、およびビア導体３１Ｖ１を備える。チップ部品３１の上面に端子３１Ｐ１、一方端部に端子３１Ｐ２を備える。第４の実施形態で図１０，１２に示した例と異なり、端子３１Ｐ２は、積層体の一方の端部の５面に形成される。コイル導体３１Ｌは、絶縁体層に沿った複数の導体パターンと複数の層間接続導体とで構成される矩形ヘリカル状の導体パターンである。矩形ヘリカル状の導体パターンの上方端はビア導体３１Ｖ１を介して上面の端子３１Ｐ１に接続され、矩形ヘリカル状の導体パターンの下方端は端子３１Ｐ２に接続される。この構造によれば、インダクタンスにあまり寄与しない導体部分が短くなって、ＤＣＲは小さい。また、第４の実施形態に比べて、端子３１Ｐ２とリードフレームとの接続断面積が大きくなり、ダイボンディング部の抵抗値を小さくでき、ダイボンディング部のＤＣＲも小さくできる。 16A is a perspective view of the chip component 31, FIG. 16B is a cross-sectional view of the chip component 31, and FIG. 16C is a perspective view showing the structure of the conductor portion of the chip component 31. The chip component 31 is a laminate of a plurality of insulator layers including an insulator layer on which a plurality of conductor patterns are formed. The chip component 31 includes a coil conductor 31L and a via conductor 31V1. The chip component 31 includes a terminal 31P1 on the upper surface and a terminal 31P2 on one end. Unlike the example shown in FIGS. 10 and 12 in the fourth embodiment, the terminal 31P2 is formed on the five surfaces of one end of the laminate. The coil conductor 31L is a rectangular helical conductor pattern including a plurality of conductor patterns along the insulator layer and a plurality of interlayer connection conductors. The upper end of the rectangular helical conductor pattern is connected to the upper terminal 31P1 via the via conductor 31V1, and the lower end of the rectangular helical conductor pattern is connected to the terminal 31P2. According to this structure, the conductor portion that does not contribute much to the inductance is shortened, and the DCR is small. Further, compared to the fourth embodiment, the connection cross-sectional area between the terminal 31P2 and the lead frame is increased, the resistance value of the die bonding portion can be reduced, and the DCR of the die bonding portion can be reduced.
《第６の実施形態》
　第６の実施形態では、デカップリング用のコンデンサ素子を備える回路モジュールの例である複合電子部品の例を示す。図１７は第６の実施形態に係る複合電子部品１０６の、モールド樹脂の無い状態での平面図である。 << Sixth Embodiment >>
In the sixth embodiment, an example of a composite electronic component that is an example of a circuit module including a capacitor element for decoupling is shown. FIG. 17 is a plan view of the composite electronic component 106 according to the sixth embodiment in the absence of mold resin.
　複合電子部品１０６は、支持材の例であるリードフレーム（１１ａ～１１ｆ，１１Ｐ等）、半導体チップ２１およびチップ部品３２を備える。半導体チップ２１およびチップ部品３２は、リードフレームのダイパッド１１Ｐ上に近接して搭載される。チップ部品３２は一方主面に接続端子（パッド）３２Ｐ１，３２Ｐ２を有する。 The composite electronic component 106 includes a lead frame (11a to 11f, 11P, etc.) that is an example of a support material, a semiconductor chip 21, and a chip component 32. The semiconductor chip 21 and the chip component 32 are mounted close to the die pad 11P of the lead frame. The chip component 32 has connection terminals (pads) 32P1 and 32P2 on one main surface.
　半導体チップ２１は、接続端子を上面側にして、リードフレームのダイパッド１１Ｐ上に搭載され、チップ部品３１は、接続端子３２Ｐ１，３２Ｐ２を上面側にして、ダイパッド１１Ｐ上にダイボンディングされる。 The semiconductor chip 21 is mounted on the die pad 11P of the lead frame with the connection terminal on the upper surface side, and the chip component 31 is die-bonded on the die pad 11P with the connection terminals 32P1 and 32P2 on the upper surface side.
　図１７に表れるように、半導体チップ２１の所定の端子はリードフレームの端子１１ａ，１１ｂ，１１ｃ，１１ｅ，１１ｆにそれぞれワイヤーＷ１，Ｗ２，Ｗ３，Ｗ６，Ｗ７を介して接続される。また、半導体チップ２１の所定の端子はチップ部品３２の接続端子３２Ｐ１に、支持材を介さずにワイヤーＷ４を介して直接接続される。チップ部品３２の接続端子３２Ｐ２はリードフレームの端子１１ｄにワイヤーＷ５を介して接続される。 As shown in FIG. 17, predetermined terminals of the semiconductor chip 21 are connected to terminals 11a, 11b, 11c, 11e, and 11f of the lead frame via wires W1, W2, W3, W6, and W7, respectively. In addition, the predetermined terminal of the semiconductor chip 21 is directly connected to the connection terminal 32P1 of the chip component 32 through the wire W4 without the support material. The connection terminal 32P2 of the chip component 32 is connected to the terminal 11d of the lead frame via a wire W5.
　図１８は本実施形態の複合電子部品１０６の回路図である。本実施形態では、複合電子部品１０６はＡＤ変換回路に用いられる回路モジュールである。半導体チップ２１は信号入力端子ＳＩＮの電圧を所定ビット数のデジタル値に変換し、シリアルデータ通信用の信号ラインＳＣＬ，ＳＤＡを介してＡＤ変換値を外部回路へ出力する。 FIG. 18 is a circuit diagram of the composite electronic component 106 of the present embodiment. In the present embodiment, the composite electronic component 106 is a circuit module used for an AD conversion circuit. The semiconductor chip 21 converts the voltage of the signal input terminal SIN into a digital value of a predetermined number of bits, and outputs the AD conversion value to an external circuit via the serial data communication signal lines SCL and SDA.
　チップ部品３２はキャパシタンス素子である。このチップ部品３２の一端は、半導体チップ２１の電源ラインに接続され、他端はグランドに接続されるデカップリング用コンデンサである。 The chip part 32 is a capacitance element. One end of the chip component 32 is connected to the power supply line of the semiconductor chip 21 and the other end is a decoupling capacitor connected to the ground.
　本実施形態によれば、半導体チップからデカップリング用のコンデンサ素子までの電流経路長が短いので、等価直列インダクタンス（ESL）が小さく、ノイズ低減効果が高い。また、その分、コンデンサ単体でのESLがそれほど小さくなくてよい。 According to the present embodiment, since the current path length from the semiconductor chip to the decoupling capacitor element is short, the equivalent series inductance (ESL) is small and the noise reduction effect is high. In addition, the ESL of the capacitor alone need not be so small.
　最後に、上述の実施形態の説明は、すべての点で例示であって、制限的なものではない。当業者にとって変形および変更が適宜可能である。例えば、異なる実施形態で示した構成の部分的な置換または組み合わせが可能である。本発明の範囲は、上述の実施形態ではなく、特許請求の範囲によって示される。さらに、本発明の範囲には、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 Finally, the description of the above embodiment is illustrative in all respects and not restrictive. Modifications and changes can be made as appropriate by those skilled in the art. For example, partial replacements or combinations of the configurations shown in the different embodiments are possible. The scope of the present invention is shown not by the above embodiments but by the claims. Furthermore, the scope of the present invention is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.
　例えば、各実施形態では、支持材上に半導体チップとチップ部品を隣接させて配置したが、ワイヤー接続される半導体チップとチップ部品とが近接していて、且つ、半導体チップとチップ部品との間に他のチップ部品が配置されていてもよい。 For example, in each embodiment, the semiconductor chip and the chip component are disposed adjacent to each other on the support material. However, the semiconductor chip and the chip component to be wire-connected are close to each other and between the semiconductor chip and the chip component. Other chip parts may be arranged on the board.
　また、例えば、図４、図９、図１３では降圧コンバータを例示したが、昇圧コンバータや昇降圧コンバータにも同様に適用できる。 For example, although the step-down converter is illustrated in FIGS. 4, 9, and 13, it can be similarly applied to a step-up converter and a step-up / step-down converter.
Ｃ…接続領域
Ｃｉ…入力コンデンサ
Ｃｏ…出力コンデンサ
Ｅ…電源
ＦＬ…フィレット
ＧＮＤ…グランド端子
ＩＮ…電源入力端子
ＯＵＴ…出力端子
Ｑ１，Ｑ２…スイッチング素子
Ｓ…絶縁領域
ＳＢ…はんだボール
ＳＣＬ，ＳＤＡ…信号ライン
ＳＩＮ…信号入力端子，
Ｗ，Ｗ１～Ｗ１４…ワイヤー
１１…リードフレーム
１１ａ，１１ｂ，１１ｃ，１１ｄ，１１ｅ，１１ｆ，１１ｇ，１１ｈ，１１ｉ，１１ｊ，１１ｋ，１１ｍ…端子
１１Ｐ…ダイパッド
１２…積層基板
１２ａ，１２ｂ…接続端子
１２Ｐ…共通電極
２１…半導体チップ
２１Ｃ…スイッチング制御回路
３０，３１，３２…チップ部品
３１Ｅ１，３２Ｅ２…平面導体
３１Ｌ…コイル導体
３１Ｐ１，３１Ｐ２…接続端子
３１Ｖ１，３１Ｖ２…ビア導体
３２Ｃ１，３２Ｃ２…ビア導体
３２Ｅ１，３２Ｅ２…平面導体
３２Ｐ１，３２Ｐ２…接続端子
４０…モールド樹脂
１０１～１０６…複合電子部品 C ... Connection area Ci ... Input capacitor Co ... Output capacitor E ... Power supply FL ... Fillet GND ... Ground terminal IN ... Power supply input terminal OUT ... Output terminals Q1, Q2 ... Switching element S ... Insulation area SB ... Solder balls SCL, SDA ... Signal Line SIN ... Signal input terminal,
W, W1 to W14 ... Wire 11 ... Lead frames 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i, 11j, 11k, 11m ... Terminal 11P ... Die pad 12 ... Multilayer substrate 12a, 12b ... Connection terminal 12P ... Common electrode 21 ... Semiconductor chip 21C ... Switching control circuits 30, 31, 32 ... Chip components 31E1, 32E2 ... Planar conductor 31L ... Coil conductors 31P1, 31P2 ... Connection terminals 31V1, 31V2 ... Via conductors 32C1, 32C2 ... Via conductors 32E1, 32E2 ... Planar conductors 32P1, 32P2 ... Connection terminals 40 ... Mold resins 101 to 106 ... Composite electronic components

Claims (7)

  1. 　支持材上に搭載され、一方主面に接続端子を有する半導体チップと、
    　前記支持材上の、前記半導体チップに近接する位置に搭載され、一方主面に接続端子を有するチップ部品と、
    を有し、
    　前記半導体チップは、前記接続端子を上面側にして、前記支持材上に搭載され、
    　前記チップ部品は、上面に第１接続端子、下面に第２接続端子をそれぞれ有し、
    　前記チップ部品は、前記第１接続端子を上面側にして、前記支持材上に搭載されて、前記第２接続端子が前記支持材に接続され、
    　前記半導体チップの前記接続端子と前記チップ部品の前記第１接続端子とは、前記支持材を介さずにワイヤーを介して直接接続されている、
    　ことを特徴とする複合電子部品。     A semiconductor chip mounted on a support material and having a connection terminal on one main surface;
    A chip component mounted on the support material at a position close to the semiconductor chip and having a connection terminal on one main surface;
    Have
    The semiconductor chip is mounted on the support material with the connection terminal on the upper surface side,
    The chip component has a first connection terminal on the upper surface and a second connection terminal on the lower surface,
    The chip component is mounted on the support material with the first connection terminal on the upper surface side, and the second connection terminal is connected to the support material,
    The connection terminal of the semiconductor chip and the first connection terminal of the chip component are directly connected via a wire without the support material,
    A composite electronic component characterized by that.
  2. 　支持材上に搭載され、一方主面に接続端子を有する半導体チップと、
    　前記支持材上の、前記半導体チップに近接する位置に搭載され、一方主面に接続端子を有するチップ部品と、
    を有し、
    　前記半導体チップは、前記接続端子を上面側にして、前記支持材上に搭載され、
    　前記チップ部品は、上面に第１接続端子、端部に第２接続端子をそれぞれ有し、
    　前記チップ部品は、前記第１接続端子を上面側にして、前記支持材上に搭載されて、前記第２接続端子が前記支持材に接続され、
    　前記半導体チップの前記接続端子と前記チップ部品の前記第１接続端子とは、前記支持材を介さずにワイヤーを介して直接接続されている、
    　ことを特徴とする複合電子部品。     A semiconductor chip mounted on a support material and having a connection terminal on one main surface;
    A chip component mounted on the support material at a position close to the semiconductor chip and having a connection terminal on one main surface;
    Have
    The semiconductor chip is mounted on the support material with the connection terminal on the upper surface side,
    The chip component has a first connection terminal on the upper surface and a second connection terminal on the end,
    The chip component is mounted on the support material with the first connection terminal on the upper surface side, and the second connection terminal is connected to the support material,
    The connection terminal of the semiconductor chip and the first connection terminal of the chip component are directly connected via a wire without the support material,
    A composite electronic component characterized by that.
  3. 　前記半導体チップおよび前記チップ部品は、共通の電極上に搭載される、請求項１または２に記載の複合電子部品。 The composite electronic component according to claim 1 or 2, wherein the semiconductor chip and the chip component are mounted on a common electrode.
  4. 　前記支持材はリードフレームであり、
    　前記半導体チップおよび前記チップ部品は、前記リードフレームのダイパッドに搭載される、請求項１から３のいずれかに記載の複合電子部品。     The support material is a lead frame;
    The composite electronic component according to claim 1, wherein the semiconductor chip and the chip component are mounted on a die pad of the lead frame.
  5. 　請求項１から４のいずれかに記載の複合電子部品を備え、
    　前記複合電子部品は、電源入力端子、電源出力端子およびグランド端子を有し、
    　前記半導体チップはスイッチング素子およびスイッチング制御回路を含むスイッチング電源用ＩＣであり、
    　前記チップ部品はインダクタンス素子であり、前記チップ部品の第１端は前記スイッチング素子に接続され、第２端は前記電源出力端子に接続される、
    　ＤＣＤＣコンバータモジュール。     A composite electronic component according to any one of claims 1 to 4,
    The composite electronic component has a power input terminal, a power output terminal and a ground terminal,
    The semiconductor chip is a switching power supply IC including a switching element and a switching control circuit,
    The chip component is an inductance element, a first end of the chip component is connected to the switching element, and a second end is connected to the power output terminal.
    DCDC converter module.
  6. 　支持材上に搭載され、一方主面に接続端子を有する半導体チップと、
    　前記支持材上の、前記半導体チップに近接する位置に搭載され、一方主面に接続端子を有するチップ部品と、
    を有し、
    　前記半導体チップは、前記接続端子を上面側にして、前記支持材上に搭載され、
    　前記チップ部品は、少なくとも上面に接続端子が位置するように、前記支持材上に搭載され、
    　前記半導体チップの前記接続端子と前記チップ部品の前記接続端子とは、前記支持材を介さずにワイヤーを介して直接接続されている、
    　ことを特徴とする複合電子部品。     A semiconductor chip mounted on a support material and having a connection terminal on one main surface;
    A chip component mounted on the support material at a position close to the semiconductor chip and having a connection terminal on one main surface;
    Have
    The semiconductor chip is mounted on the support material with the connection terminal on the upper surface side,
    The chip component is mounted on the support material such that the connection terminal is located at least on the upper surface,
    The connection terminal of the semiconductor chip and the connection terminal of the chip component are directly connected via a wire without the support material,
    A composite electronic component characterized by that.
  7. 　請求項６に記載の複合電子部品を備え、
    　電源端子およびグランド端子を有し、
    　前記チップ部品は、前記電源端子と前記グランド端子との間に接続される、デカップリング用のコンデンサ素子である、
    　回路モジュール。     A composite electronic component according to claim 6,
    It has a power supply terminal and a ground terminal,
    The chip component is a decoupling capacitor element connected between the power supply terminal and the ground terminal.
    Circuit module.
PCT/JP2015/080984 2014-11-12 2015-11-04 Composite electronic component, circuit module, and dc-dc converter module WO2016076162A1 (en)

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