WO2016070744A1 - 一种系统间全局时钟确定的方法和结构 - Google Patents

一种系统间全局时钟确定的方法和结构 Download PDF

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WO2016070744A1
WO2016070744A1 PCT/CN2015/093142 CN2015093142W WO2016070744A1 WO 2016070744 A1 WO2016070744 A1 WO 2016070744A1 CN 2015093142 W CN2015093142 W CN 2015093142W WO 2016070744 A1 WO2016070744 A1 WO 2016070744A1
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Prior art keywords
signal
clock
recording unit
time
reference clock
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PCT/CN2015/093142
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English (en)
French (fr)
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张博
房磊
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武汉数字派特科技有限公司
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Priority to EP15856712.3A priority Critical patent/EP3217249B1/en
Priority to BR112017009283-2A priority patent/BR112017009283B1/pt
Priority to JP2017542249A priority patent/JP6463495B2/ja
Priority to US15/523,942 priority patent/US10416704B2/en
Publication of WO2016070744A1 publication Critical patent/WO2016070744A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Definitions

  • the invention belongs to the technical field of time test measurement, and relates to a method for determining a reference time, in particular to a method for determining global time.
  • the global clock can be applied to multiple domains. Only the global clock can be synchronized between independent systems. When the clocks of the independent systems reach a consistent clock reference, the array can work together to ensure consistent measurement conditions between the systems. Therefore, it is necessary to provide a method for determining the global clock between systems.
  • the existing inter-system global clock determination often uses a timestamp communication method between multiple systems to acquire the timing reference of the respective clock and further calibrate, which is widely used in the communication field, although it can implement the system.
  • Time synchronization but this synchronization method is only limited to the use of off-the-shelf communication protocols (which can pack time references into timestamps) to achieve low-precision global clock synchronization, such as ms or sub-ms or us or sub-us.
  • the accuracy of the method ultimately depends on the speed of the clock, ie the flip frequency, and does not achieve a shorter synchronization accuracy than the clock period. In areas such as nuclear detection and in time-of-flight applications, multiple independent systems often require a consistent time base to meet accurate time measurements.
  • the object of the present invention is to provide a method and structure for determining a global clock between systems.
  • each system is connected through a simple network, and then each communication is determined by a communication between the systems and a signal recording unit.
  • the system's clock phase difference is then calibrated for each system using the individual clock phase differences, resulting in a fully consistent clock reference for all clocks in all systems.
  • the solution of the present invention is:
  • a method for determining a global clock between systems, the path connection between the systems comprising the following steps:
  • the reference clock source generates a calibration signal
  • the calibration signal is distributed to each system, recording the issuance time T d (0) of the calibration signal
  • the system records the calibration signal arrival time T a (n) according to respective local clocks, and each of the systems generates a return signal and according to respective local clocks. Recording the time T b (n) of the return signal, receiving the return signal and recording the arrival time T d (n) of the return signal to the reference clock source to determine the system to the Absolute offset Delay(n) between reference time sources;
  • the receiving and recording of the calibration signal issuance time T d (0) and the return signal arrival time T d (n) is performed by a signal recording unit that cooperates with the reference clock source;
  • the calibration signal is distributed to each system by the signal recording unit that cooperates with the reference clock source.
  • the reference clock source and the signal recording unit cooperating with the reference clock source belong to one of the systems;
  • the reference clock source is a clock controller or a clock controller including a clock controller and a clock controller.
  • the calibration signal is formed by an electrical pulse directly sent by the clock controller or the clock generator receives a clock signal sent by the clock controller.
  • the arrival time T a (n) and the emission time T b (n) are determined via a local clock in each system and a local signal recording unit cooperating with the local clock.
  • the return signal is respectively returned by the response signal or the calibration signal respectively sent by the respective systems.
  • the minimum time measurement scale of the signal recording unit cooperating with the reference clock source is less than 1/2 of the clock period of the reference clock source
  • the local signal recording unit minimum time measurement scale is less than 1/2 of the local clock clock period
  • the minimum time measurement scale of the signal recording unit is within 1 ns.
  • the minimum time measurement scale of the signal recording unit is within 100 ps.
  • the present invention also discloses a structure for determining a global clock between systems, including a path connecting system, a reference clock source, and a signal recording unit cooperating with the reference clock source, the signal recording unit and the reference clock source A path connection, each of the systems is in communication with the reference clock source via the signal recording unit to determine a zero offset between various local clocks of the various systems and the reference clock source.
  • the signal recording unit cooperating with the reference clock source is in a two-way communication connection with the system.
  • the signal recording unit cooperated with the reference clock source and the reference clock source, the signal recording unit cooperated with the reference clock source and the system, and the system is wired connection.
  • each of the systems is provided with a local clock and a signal recording unit connected to the local clock path; preferably, a local clock in one of the systems is used as a reference clock source.
  • the systems are sequentially communicatively coupled to form a linear network structure, and at least one linear network structure is disposed, the signal recording unit cooperating with the reference clock source and a system in each of the linear network structures Inter-communication connection.
  • the signal recording unit cooperating with the reference clock source is in communication with a system at the endpoint in each of the linear network structures.
  • the systems are bidirectional communication connections.
  • one of said linear networks is provided.
  • Each of the systems is directly in communication with the signal recording unit that cooperates with the reference clock source to form a star network structure.
  • a minimum time measurement scale of the signal recording unit cooperating with the reference clock source is less than the reference clock source 1/2 of the clock cycle;
  • the local signal recording unit minimum time measurement scale is less than 1/2 of the local clock clock period
  • the signal recording unit comprises a controller and a time converter communicatively coupled to the controller to receive the controller, the time converter having a time precision of less than 1 ns.
  • the time converter is TDC or TAC, and the time precision of the TDC or TAC is within 100 ps.
  • the reference clock source is a clock controller or a clock controller including a clock controller and a clock controller.
  • a method and structure for determining a global clock between systems according to the present invention When operating independently, each system can work according to its own clock. When multiple systems need a global unified time reference, the reference clock source is first issued. The calibration signal, at the same time, the signal recording unit of the reference clock source starts timing T d (0), and each system receives the calibration signal in turn because of the inconsistency of the distance from the reference clock source, and each system receives the calibration signal, and each system The internal signal recording unit records the arrival time T a (n) of the calibration signal, and each system immediately sends a return signal (response reply or direct circuit connection return calibration signal) to the signal recording unit of the reference clock source and records the return signal. The time T b (n) is also issued.
  • the signal recording unit sequentially receives the return signals from each system, and sequentially records the time T d (n).
  • the synchronization accuracy of time is improved by the addition of a high-precision signal recording unit.
  • a high-precision signal recording unit is arranged at the reference clock source, and the local clock in the system is also provided with a signal recording unit matched thereto, and the minimum time measurement scale of the signal recording unit is less than 1/2 of the clock period of the reference clock source.
  • TDC time-to-digital converter
  • TAC time-to-analog converter
  • TDC time-to-digital converter
  • TAC time-to-analog converter
  • the local clock is offset from the reference clock source zero point. The absolute time offset between each system and the reference clock source is accurately determined to form a global clock.
  • 1 is a working flow chart of an embodiment of a method for determining a global clock between systems
  • FIG. 2 is a schematic diagram showing a connection relationship between a clock source and a clock recording unit in the system
  • FIG. 3 is a schematic structural diagram of a first embodiment of determining a structure of a global clock between systems
  • FIG. 4 is a schematic structural diagram of a second embodiment of determining a structure of a global clock between systems
  • FIG. 5 is a schematic structural diagram of a third embodiment of a structure for determining a global clock between systems.
  • the invention discloses a method for determining a global clock between systems.
  • the path connection between the systems as shown in FIG. 1 , specifically includes the following steps:
  • a clock source is determined as a reference clock source that covers all systems through the network. First, a clock source is determined as a reference clock source, and a calibration signal is generated by the above reference clock source.
  • the reference clock source can be arbitrarily selected. Only the reference clock source needs to be able to transmit to all systems through the network (that is, cover all systems).
  • the reference clock source can be selected from the local clock of each system, and a separate clock source is used as a reference.
  • the reference clock source is determined from the local clock of each system, and may be a clock controller separately, or may include a clock controller and a clock generator controlled by the clock controller, and is set according to actual needs. .
  • the reference clock source generates a calibration signal, which is distributed to each system, and records the issuance time Td (0) of the calibration signal.
  • the calibration signal is generated by the reference clock source, so the calibration signal can be formed either by an electrical pulse directly sent by the clock controller or by the clock generator receiving a clock signal from the clock controller. After the calibration signal is generated, it needs to be sent to each system.
  • the signal recording unit cooperates with the reference clock source to mark the target. The signal is distributed to each system, wherein the signal recording unit includes a controller and a time converter that accepts the control.
  • the reference clock source and the signal recording unit cooperating with the reference clock source belong to one of the systems, and the signal recording unit cooperating with the reference clock source receives and records the issuance time T d (0) of the calibration signal.
  • the system After the calibration signal reaches each system through the network, the system records the calibration signal arrival time T a (n) according to the local clock, and each system generates a return signal and records the return signal emitting time T b according to the local clock. n) receiving a return signal and recording the return signal to the reference clock source arrival time T d (n), thereby determining the absolute offset Delay(n) of the respective systems;
  • the calibration signal issuance time T d (0) and the arrival time T d (n) of the return signal can be recorded by the same timing component, thereby ensuring the same time precision as the timing unit, and in the embodiment shown in FIG.
  • the source-compatible signal recording unit receives and records, specifically, the specific values of the drive records T d (0) and T d (n) of the controller that are accepted by the time converter.
  • Step (3) without considering the accuracy problems when the calibration signal to the time of arrival of each system T a (n) and the return signal sending time T b (n) can be directly determined and recorded by the system according to their local clock,
  • the arrival time T a (n) and the issuance time T b (n) may also be determined by a local clock in each system and a local signal recording unit cooperating with the local clock, and the local signal recording unit structure in each system is the same as above.
  • the reference clock source cooperates with the same signal recording unit structure, and is bidirectionally wired and connected with the local clock.
  • the local signal recording unit records the time zero t a0 (n) of each system starting operation according to the local clock.
  • b (n) t b1 (n)-t a0 (n).
  • the return signals respectively generated by the respective systems may be in various forms. The following is a description of the steps of returning signals respectively for the response signals or the calibration signals respectively sent by the respective systems. It should be understood that if the return signals are other forms. At the same time, the formation of a global clock between systems can also be achieved by the method shown in the present invention.
  • each system can return the signal link through a direct circuit connection, return the calibration signal, or receive a calibration signal through a controller (such as an FPGA that supports asynchronous response).
  • a controller such as an FPGA that supports asynchronous response.
  • an acknowledgment signal is sent, and then the arrival time T d (n) of the reference clock source is reached to determine the absolute offset of the respective systems. ).
  • T c (n) After the size of T c (n) is determined, it can be used as a correction parameter to correct the local clock of the respective system:
  • T c (n)>0 indicating that the system zero is earlier than the reference clock source, the value is subtracted from the timing system of the system.
  • the calibration signal is issued by the reference system (ie, the system whose local clock is used as the reference clock source) and Delay(n) is determined, and the remaining systems determine T a (n) and T b (n), since each system has a local Clock and signal recording unit, so it is also possible to issue calibration signals from the remaining systems and calculate Delay(n).
  • the reference system measures T a (n) and T b (n).
  • the reference system and the rest of the systems have signal processing functions. Therefore, either the measured Delay(n) can be sent to the other party, or the measured T a (n) and T b (n) can be sent to the other party.
  • Any party that obtains Delay(n) and T a (n), T b (n) through the network can determine the correction parameter T c (n) and send T c (n) to each system for correction, or The total processing unit uploaded to the entire system is globally calibrated.
  • each system has its own local clock. When working independently, it can rely on its own local clock to work.
  • the system-to-system global clock shown above is used. The determination method can realize the unification of the global clock between systems conveniently and quickly, and can be applied to various fields as needed.
  • the present invention further discloses a method for global clock between systems, which can improve the accuracy of time synchronization for occasions with high time precision requirements.
  • a method for determining a global clock between systems, the path connection between the systems comprising the following steps:
  • a clock source is determined as a reference clock source that covers all systems through the network. First, a clock source is determined as a reference clock source, and a calibration signal is generated by the above reference clock source.
  • the reference clock source can be arbitrarily selected. Only the reference clock source needs to be able to transmit to all systems through the network (that is, cover all systems).
  • the reference clock source can be selected from each system or an external clock source can be used as a reference.
  • the reference clock source may be a clock controller alone, or may include a clock controller and a clock generator controlled by the clock controller, and are set according to actual needs.
  • the reference clock source generates a calibration signal, the calibration signal being distributed to the systems directly or through a signal recording unit cooperating with a reference clock source, the signal recording unit cooperating with the reference clock source recording the calibration Signal issuance time T d (0);
  • the calibration signal is generated by the reference clock source, so the calibration signal can be formed either by an electrical pulse directly sent by the clock controller or by the clock generator receiving a clock signal from the clock controller. After the calibration signal is generated, it needs to be sent to each system.
  • the calibration signal is distributed to each system by a signal recording unit matched with the reference clock source.
  • the minimum time measurement scale of the signal recording unit is smaller than the reference clock source.
  • One-half of the clock period, which includes a controller and a time converter that accepts the control drive, the reference clock source and the signal recording unit that cooperates with the reference clock source can belong to one of the systems to facilitate system wiring.
  • the signal recording unit that cooperates with the reference clock source distributes the calibration signal to each system while the signal recording unit records the issuance time Td (0) of the calibration signal.
  • the system After the calibration signal reaches each system through the network, the system records the calibration signal arrival time T a (n) according to the local clock and the local signal recording unit, and each system generates a return signal according to the local clock and local.
  • the signal recording unit records the emission time T b (n) of the return signal, and cooperates with the reference clock source to receive the return signal and the recording return signal reaches the arrival time T d (n) of the reference clock source, thereby determining The absolute offset Delay(n) of each system.
  • the calibration signal issuance time T d (0) and the arrival time T d (n) of the return signal are both received and recorded by a high-precision signal recording unit cooperating with the reference clock source, specifically receiving the drive record of the controller by the time converter Specific values for d (0) and T d (n). Since the minimum time measurement scale of the signal recording unit matched with the reference clock source is less than 1/2 of the clock period of the reference clock source, the signal recording unit can accurately measure the time less than one clock cycle length: the global clock required for high synchronization
  • the global clock frequency is generally above 50MHz, the clock period is within 20ns, and even the frequency is above 200MHz, and the clock period is within 2ns.
  • the delay of the global clock on the line also needs to be accurately measured.
  • This delay varies with the length of the line and does not maintain the same phase with the global clock of the system.
  • high-precision clock measurement is required.
  • the device can achieve more accurate time measurements such as line delay or phase deviation by measuring the signal measurement element with a minimum measurement scale less than 1/2 of the clock period of the reference clock.
  • the signal recording unit includes a controller and a time converter that receives the control, and the minimum time measurement scale of the time converter is within 1 ns so that the calibration signal is emitted accurately for the time T d (0).
  • the return time T d (n) of the return signal which can be used for the case where the time precision is required at the ps level.
  • the time converter can be a TDC (Time Digitizer) or a TAC (Time Analog Converter), and the time accuracy of the TDC or TAC is within 100 ps.
  • TDC Time Digitizer
  • TAC Time Analog Converter
  • the controller accepts the controller to read the count value of the TDC (recorded time value). Since the TDC is asynchronous timing, that is, the signal of the clock is instantaneously triggered, generally it is triggered by the edge of the electric pulse.
  • the TDC can not fully rely on the main clock frequency, and the timing can be up to 10 ps through the circuit delay chasing circuit, so the time recording accuracy is within 100 ps, and the signal recording unit is used to record the signal emission time and The return time can meet the requirements of the synchronization accuracy of time at the ps level, and is thus applied to fields such as scanning imaging systems where time precision is required.
  • the arrival time T a (n) and the issuance time T b (n) are also determined via a local clock within each system and a high time precision local signal recording unit that cooperates with the local clock.
  • the structure of the local signal recording unit in each system is the same as the structure of the signal recording unit matched with the reference clock source.
  • the minimum time measurement scale of the local signal recording unit is less than 1/2 of the local clock clock period. Both have the same level of minimum time measurement.
  • the return signals respectively generated by the respective systems may be in various forms. The following is a description of the steps of returning signals respectively for the response signals or the calibration signals respectively sent by the respective systems. It should be understood that if the return signals are other forms.
  • the formation of a global clock between systems can also be achieved by the method shown in the present invention.
  • each system can return the signal link through a direct circuit connection, return the calibration signal, or receive a calibration signal through a controller (such as an FPGA that supports asynchronous response).
  • a controller such as an FPGA that supports asynchronous response.
  • an acknowledgment signal is sent, and then the arrival time T d (n) of the reference clock source is reached to determine the absolute offset of the respective systems. ).
  • T c (n) After the size of T c (n) is determined, it can be used as a correction parameter to correct the local clock of the respective system:
  • T c (n)>0 indicating that the system zero is earlier than the reference clock source, the value is subtracted from the timing system of the system.
  • the time determined by the method is determined by the high-precision time-keeping unit, which not only solves the synchronization problem of the global clock between the systems, but further improves the synchronization precision of the time and can be applied to the core. Detection, time-of-flight applications, etc. require high time synchronization accuracy.
  • the present invention also discloses a structure for determining a global clock between systems, comprising at least two systems, a reference clock source, and a signal recording unit matched with the reference clock source, and the paths between the systems are connected.
  • a signal recording unit is coupled to the reference clock source path, each system communicating with the reference clock source via the signal recording unit to determine a zero offset between various local clocks of the various systems and the reference clock source.
  • the reference clock source and the signal recording unit matched with the reference clock source may be subordinate to one of the systems, or may be separately connected to a reference clock source and a signal recording unit, and the reference clock source is
  • the principle of wages for the structure of the present invention is described in relation to the signal recording unit from one of the systems.
  • a local recording clock and a signal recording unit connected to the local clock path are selected in any system, and the local clock of the system is used as a reference clock source, and the signal recording unit is a timing component, and the reference clock source is to the rest of the network.
  • the system issues a calibration signal and records the time T d (0) of the calibration signal through its own signal recording unit. After receiving the calibration signal, the remaining systems record the arrival time T a (n) of the calibration signal and generate a return signal. After the return signal reaches the reference clock source, the signal recording unit that cooperates with the reference clock source records the arrival time T d (n) of the return signal, and the remaining systems are known by measuring T d (n) and T d (0).
  • the reference system transmits the measured time difference Delay(n) to all other systems via the communication network.
  • each of the remaining systems can measure the difference between its own time zero and the clock zero of the reference system by its own measured T a (n) and the received Delay (n), that is, the difference of the clock reference, and each system passes the difference.
  • the value corrects its own clock system, such as setting the corresponding delay for its own clock system, so that the entire system is in a completely consistent clock reference.
  • the calculation of the various differences described above can also be determined by other processors.
  • the return signal may be the original calibration signal or a response signal sent by the system itself.
  • Delay(n) (T d (n)-T d (0)- ⁇ n /2
  • the signal recording unit can be a commonly used timing component to effectively determine the global clock between systems, the arrival time T a (n) and The issuance time T b (n) can be determined independently by the local clock in each system, and ⁇ n is also preset for each system, determined by experiments and calculations and stored in each system.
  • the minimum time measurement scale of the signal recording unit is smaller than 1/2 of the clock period of the reference clock source, and each system needs to be separately set.
  • the signal recording unit, the signal recording unit inside each system and the signal recording unit matched with the reference clock source have the same structure, and the minimum time measurement scale is also the same.
  • the signal recording unit includes a controller and a high-precision time converter that receives the control drive. And each signal recording unit is respectively connected to a local clock path in the system.
  • the signal recording unit can accurately measure the time less than one clock cycle length: in the global clock required for high synchronization, the global clock frequency is generally above 50 MHz, the clock cycle is within 20 ns, and even the frequency reaches 200 MHz or more, and the clock cycle is within 2 ns.
  • the delay of the global clock on the line also needs to be accurately measured. This delay varies with the length of the line and does not maintain the same phase with the global clock of the system. In order to accurately measure this delay, high-precision clock measurement is required. Instead of relying on the global clock, the device can realize the signal measurement device with a minimum measurement scale smaller than 1/2 of the clock period of the reference clock (local clock). More accurate time measurements such as line delay or phase deviation.
  • the minimum time measurement scale of the time converter is within 1 ns.
  • the time converter is TDC (Time Digitizer) or TAC (Time Analog Converter), TDC or TAC time.
  • the accuracy is within 100ps. Taking TDC as an example, it accepts controller control to record and read time values (ie, record and retrieve values of T d (0) and T d (n)), since TDC can be timed asynchronously, that is, for clocks.
  • the signal is an instant trigger, generally triggered by the edge of the electrical pulse, so there is no communication overhead, and the TDC can not rely entirely on the main clock frequency, and the timing is chased by the circuit delay to measure the ratio than the reference clock source (local clock)
  • the arrival time Ta(n) of the calibration signal and the time T b (n) of the return signal are determined by the local clock in each system and the local signal recording unit with high time precision matched with the local clock.
  • the local signal recording unit records the time zero point t a0 (n) at which each system starts to work.
  • the above-mentioned signal recording unit matched with the reference clock source and each system can realize the calibration signal (response signal) interaction through one line, and the two can also be bidirectionally communicated to realize signal interaction. If a line is used to realize the round-trip signal, since all the systems are connected by the channel, the calibration signal will be broadcasted, and the signal recording unit and the rest of the system will receive it, so the rest of the system will not mistake the signal for
  • the signal of the reference clock source needs to be sent by the controller of the remaining system immediately after the signal is received (the signal is preferably different from the calibration signal of the reference clock source). If the two are connected in two directions, the transmission and acceptance of the calibration signal are differentiated. If you open it, you don't need to consider this kind of problem, and it is easier to send and receive signals.
  • the signal measurement is based on the circuit signal (the transition of the electrical pulse) to accurately obtain the time delay and deviation of different systems, when the signal transmission through the fixed medium, the delay and The deviation is more certain.
  • the reference clock source and the signal recording unit, and between the signal recording unit and the system each system is wired.
  • each system only needs to meet the final communication connection with the reference clock source via the signal recording unit, thereby realizing the setting of the global clock between the systems, and
  • the signal recording unit with high time precision is used to determine the zero point of the clock between each system and the reference clock source, especially suitable for occasions with high time precision requirements.
  • a determining structure of an inter-system global clock includes at least two systems, a reference clock source, and a signal recording unit matched with the reference clock source, the signal recording unit and The reference clock source path is connected, and the two systems are sequentially connected in two directions to form a linear network.
  • the line network may be provided with multiple strips, and the signal recording unit matched with the above reference clock source and one system in each linear network are bidirectional.
  • Communication connection In the embodiment shown in FIG. 3, it is preferred to provide a linear network in which the systems in the linear network are bidirectionally connected, and the signal recording unit cooperating with the reference clock source and the system located in the head in the linear network are bidirectional.
  • the communication connection, between the reference clock source and the signal recording unit, between the signal recording unit and the system at the head, is a wired connection between the systems.
  • All systems are connected in series via a linear network, one node of the linear network (the embodiment shown in Figure 3 is one end of the linear network to ensure that the distance from each system to the reference clock source is different).
  • a unique reference clock source is set.
  • a high-precision signal recording unit is set, and the reference clock source first issues a calibration signal.
  • the signal recording unit of the reference clock source starts timing T d (0), and each system is sequentially inconsistent with the distance from the reference clock source.
  • the signal recording unit inside each system records the arrival time T a (n) of the calibration signal, and each system immediately responds to the reply or direct circuit connection returns the calibration signal to the reference clock source.
  • the signal recording unit records the time T b (n) of the return signal, and also because the distance is different, the signal recording unit sequentially receives the response signals from the respective systems, sequentially recording the time T d (n), the system and the reference clock.
  • multiple systems may have the same distance from the reference clock source, so here During the process, if the number of response signals received by the signal recording unit matched with the reference clock source is less than the system n value (indicating that at least two signals overlap), the probability is very low because the signal recording unit can recognize two more than 10 ps. Signals), the system can be measured in batches, one by one.
  • the measurement between the reference clock source and the remaining systems can be performed in any two systems, as shown in FIG. 4 .
  • the local clock in the system A is used as the reference clock source and the system B is calculated.
  • the clock deviation can calculate the deviation between clock system A and clock system C, and so on, thus completing the deviation of all clock systems on the entire network.
  • a structure for determining an inter-system global clock includes at least one reference clock source, at least two systems, and a signal recording unit matched with the reference clock source.
  • the inter-system path is connected, and the signal recording unit is connected to the reference clock source path, and each system is bidirectionally communicated with the signal recording unit to communicate with the reference clock source via the signal recording unit.
  • a star-shaped network connection is still adopted between the reference clock source and each system, but a signal recording unit matched with the reference clock source is added between the reference clock source and each system, and the local clock of each system can be required according to time precision.
  • a local signal recording unit connected to the respective local clock path is added.
  • the local clocks of the respective systems are bidirectionally connected to the respective local signal recording units.
  • the reference clock is preferably used. There is a wired connection between the source and signal recording unit, the signal recording unit and each system, and a local connection between the local clock and the respective local signal recording unit.
  • the reference clock source When acquiring the global clock, first all the systems are powered on, their respective clocks have been working, and then the deviation of the respective clock system is measured.
  • the local clock of one system is selected as the reference clock source, and the reference clock source is calibrated to the rest of the system.
  • the signal (the calibration signal can be a simple electrical pulse or a clock signal).
  • the signal recording unit of the reference clock source starts timing T d (0).
  • Each system is sequentially accepted because of the inconsistent distance from the reference clock source.
  • the signal recording unit inside each system records the arrival time T a (n) of the calibration signal, and each system immediately responds to the reply or direct circuit connection returns the calibration signal to the reference clock source.
  • the signal recording unit records the time T b (n) of the return signal, and also because the distance is different, the signal recording unit sequentially receives the response signals from the respective systems, sequentially recording the time T d (n), the system and the reference clock source.
  • the number of response signals received by the signal recording unit is less than the system value during the process (indicating at least There are two signals that overlap, and this probability is very low, because the signal recording unit can recognize two signals over 10 ps), and the system can be measured in batches and acquired one by one.

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Abstract

一种系统间全局时钟的确定方法和结构，在系统间需要统一时间基准时，基准时钟源发出标定信号，记录发出时间Td(0)，各系统收到标定信号后，记录到达时间Ta(n)，同时各发出返回信号给基准时钟源的信号记录单元并记录发出时间Tb(n)，同样由于距离不同，信号记录单元依次记录返回信号的到达时间Td(n)，则确定系统与基准时钟源的时间延时Delay(n)，当需要所有系统有完全统一的时间基准时，将获取对应的Delay(n)的发送至各系统，每个系统确定各种本地时钟与基准时钟源零点偏差Tc(n)，将Tc(n)作为校正参数对自己的系统时钟进行校正，从而使得所有系统的本地时钟都有完全一致的时钟基准。

Description

一种系统间全局时钟确定的方法和结构 技术领域
本发明属于时间测试测量技术领域，涉及一种基准时间确定方法，尤其是全局时间的确定方法。
背景技术
全局时钟可应用在多个领域中，独立系统之间只有实现全局时钟的同步，让各个独立系统的时钟达到一致的时钟基准时，才能完成阵列的协同工作，保证系统间具有一致的测量条件，故有必要提供一种系统间全局时钟的确定方法。
现有的系统间全局时钟确定往往采用通过多个系统之间的时间戳通信的方法来获取各自时钟的计时基准再进一步进行校准，这种方法在通信领域中被广泛采用，虽然其能够实现系统间的时间同步，但是这种同步方法仅局限在利用现成通信协议(能将时间基准打包成时间戳)达到精度不高的全局时钟同步，如ms或者亚ms或者us或者亚us级别，这种方法的精度最终依赖于时钟的速度即翻转频率，不会达到比时钟周期更短的同步精度。在诸如核探测领域、在飞行时间应用领域，多个独立系统之间往往需要完全一致的时间基准来满足精准的时间测量，完全同步的全局时间要求精度非常高，要求达到ns至ps级别，往往小于系统时钟的时钟周期，全局时钟的布局需要考虑系统间的各自时钟由于上电顺序不同带来的细微差异，所以传统的方法则无法满足要求。
发明内容
本发明的目的在于提供一种系统间全局时钟确定方法和结构，在多个系统需要全局统一时间基准时，通过简单网络将各个系统连接，然后通过系统之间的通信以及信号记录单元来确定各个系统的时钟相位差值，然后利用各个时钟相位差值对各系统进行校准，从而达到所有系统中的所有时钟都有完全一致的时钟基准。
为达到上述目的，本发明的解决方案是：
一种系统间全局时钟的确定方法，所述系统之间通路连接，包括以下步骤：
(1)确定一时钟源作为基准时钟源，所述基准时钟源覆盖所述的全部系统；
(2)所述基准时钟源产生标定信号，所述标定信号被分发至各系统处，记录所述标定信号的发出时间Td(0)；
(3)所述标定信号到达所述各系统后，所述系统依据各自本地时钟记录所述标定信号到达时间Ta(n)，同时所述各系统处分别产生一返回信号并依据各自本地时钟记录所述返回信号的发出时间Tb(n)，接收所述返回信号并所述记录所述返回信号到达所述基准时钟源的到达时间Td(n)，以确定所述各系统至所述基准时间源之间的绝对偏移Delay(n)；
(4)根据所述绝对偏移Delay(n)、所述标定信号到达时间Ta(n)或所述返回信号的发出时间Tb(n)来分别确定各自本地时钟与基准时钟源之间的零点偏差Tc(n)＝，将Tc(n)作为校正参数对各自系统的本地时钟进行校正以形成全局时钟。
其中，Tc(n)＝(Ta(n)-Delay(n)-Td(0))或Tc(n)＝(Delay(n)+Tb(n)-Td(n))，。
优选的，所述标定信号发出时间Td(0)以及所述返回信号到达时间Td(n)的接收与记录由一与基准时钟源相配合的信号记录单元完成；
优选的，所述步骤(2)中，由所述与基准时钟源相配合的信号记录单元将所述标定信号分发至各系统处。
优选的，所述基准时钟源以及与所述基准时钟源相配合的信号记录单元属于其中一系统；
优选的，所述步骤(1)中，所述基准时钟源为一时钟控制器或包括一时钟控制器以及接受时钟控制器控制的时钟发生器。
优选的，所述标定信号为所述时钟控制器直接发出的一个电脉冲形成或者所述时钟发生器接受所述时钟控制器驱动发出的一段时钟信号。
优选的，所述步骤(3)中，所述到达时间Ta(n)以及发出时间Tb(n)经由各系统内本地时钟以及与所述本地时钟相配合的本地信号记录单元确定。
进一步的，所述到达时间Ta(n)的确定包括以下步骤：当确定各系统开始工作时，本地信号记录单元依据各自本地时钟记录各系统开始工作的时间零点ta0(n)，当判断标定信号到达时，本地的信号记录单元依据各自本地时钟记录标定信号的达到时间ta1(n)，则所述到达时间Ta(n)＝ta1(n)-ta0(n)；当判断返回信号发出时，本地的信号记录单元依据各自本地时钟记录返回信号发出时间tb1(n)，则所述的发出时间Tb(n)＝tb1(n)-ta0(n)。
优选的，所述步骤(3)中，所述返回信号为所述各系统分别发出的应答信号或所述标定信号分别返回。
优选的，(I)若为所述应答信号返回，则各系统的绝对偏移Delay(n)＝(Td(n)-Td(0)-Δn)/2，其中Δn为各系统应答反应时间；
(II)若为所述标定信号返回，则各系统的绝对偏移Delay(n)＝(Td(n)-Td(0))/2，返回信号的发出时间Tb(n)＝Ta(n)。
优选的，所述步骤(I)中，所述Δn为系统预设值；或所述Δn由各系统内的信号记录单元确定，则所述Δn＝Ta(n)-Tb(n)。
与所述基准时钟源相配合的信号记录单元的最小时间测量刻度小于所述基准时钟源的时钟周期的1/2；
所述本地的信号记录单元最小时间测量刻度小于本地时钟时钟周期的1/2；
优选的，所述信号记录单元的最小时间测量刻度在1ns以内。
进一步的，所述信号记录单元的最小时间测量刻度在100ps以内。
本发明还公开了一种确定系统间全局时钟的结构，包括通路连接的系统、一基准时钟源以及与所述基准时钟源相配合的信号记录单元，所述信号记录单元与所述基准时钟源通路连接、所述每一个系统均经由所述信号记录单元与所述基准时钟源通信以确定各系统各种本地时钟与所述基准时钟源之间的零点偏差。
所述与基准时钟源相配合的信号记录单元与所述系统之间为双向通信连接。
优选的，所述与基准时钟源相配合的信号记录单元与所述基准时钟源之间、所述与基准时钟源相配合的信号记录单元与所述系统之间、所述系统之间为有线连接。
优选的，所述各系统分别设有本地时钟以及与所述本地时钟通路连接的信号记录单元；优选的，以其中一系统内的本地时钟作为基准时钟源。
所述系统之间依次通信连接以形成线状网络结构，且至少设置一条线状网络结构，所述与基准时钟源相配合的信号记录单元与所述每个线状网络结构中的一系统之间通信连接。
所述与基准时钟源相配合的信号记录单元和所述每一个线状网络结构中位于端点处的一系统之间通信连接。
优选的，所述系统之间为双向通信连接。
优选的，设置一条所述线状网络。
所述各系统分别直接和所述与基准时钟源相配合的信号记录单元之间通信连接以形成星状网络结构。
与所述基准时钟源相配合的信号记录单元的最小时间测量刻度小于所述基准时钟源的时 钟周期的1/2；
所述本地的信号记录单元最小时间测量刻度小于所述本地时钟时钟周期的1/2；
优选的，所述信号记录单元包括一控制器以及与所述控制器通信连接以接受所述控制器驱动的时间转换器，所述时间转换器的时间精度在1ns以内。
优选的，所述时间转换器为TDC或者TAC，所述TDC或者TAC的时间精度在100ps以内。
所述基准时钟源为一时钟控制器或包括一时钟控制器以及接受时钟控制器控制的时钟发生器。
由于采用上述方案，本发明的有益效果是：
1、本发明所公开的一种系统间全局时钟的确定方法和结构，在独立工作时，各系统可依赖自己的时钟进行工作，在多个系统需要全局统一时间基准时，基准时钟源首先发出标定信号，同时，基准时钟源的信号记录单元开始计时Td(0)，各个系统由于其离基准时钟源的距离不一致，会先后依次接受到标定信号，各系统收到标定信号后，各个系统内部的信号记录单元记录该标定信号的到达时间Ta(n)，同时各系统立即发送一返回信号(应答回复或者直接电路连接返回标定信号)给基准时钟源的信号记录单元并记录下返回信号的发出时间Tb(n)，同样由于距离不同，信号记录单元会先后依次接收到来自各个系统的返回信号，依次记录时间Td(n)，系统与基准时钟源的时间延时为：Delay(n)＝(Td(n)-Td(0))/2或Delay(n)＝(Td(n)-Td(0)-Δn)/2，Δn的数值根据应用场合不同采用前述步骤确定；同时可以计算系统与基准时钟源的连线长度为L(n)＝Delay(n)*C，C的速度接近光速。当需要所有系统有完全统一的时间基准时，基准系统将获取对应的Delay(n)的数据发送各系统，每个系统计算自己本地时钟与基准时钟源零点偏差Tc(n)：Tc(n)＝(Ta(n)-Delay(n)-Td(0))或Tc(n)＝(Delay(n)+Tb(n)-Td(n))，并将Tc(n)作为校正参数让自己的系统时钟进行校正。(1)如果Tc(n)＞0，说明本系统时钟零点早于基准时钟源，则在本系统计时系统中减去该值。(2)如果Tc(n)＜0，说明本系统时钟零点晚于基准时钟源，则在本系统计时系统中加上该值。
2、通过高精度信号记录单元的加入，使得时间的同步精度提高。在基准时钟源处设置高精度的信号记录单元，同时系统内本地时钟也分别设有与其配合的信号记录单元，信号记录单元的最小时间测量刻度小于基准时钟源的时钟周期的1/2，可为时间数字转换器(TDC)或者时间模拟转换器(TAC)，由该时间数字转换器(TDC)或者时间模拟转换器(TAC)配合基准时钟源以及各系统内本地时钟来确定每个系统自己本地时钟与基准时钟源零点偏差，可 精确确定各系统与基准时钟源之间的时间绝对偏移以形成全局时钟。
3、通过系统之间的时间测量和通信完成各个系统时间系统的归一化校正，免去了专用可靠时钟线的复杂设计。
4、增加系统的扩展性，当系统之间设置为线状网络结构时，可以任意在系统中增加系统，新增的系统只需要完成一次测量就可以保证自己与系统达到一致的时间基准。
附图说明
图1为一种系统间全局时钟的确定方法一实施例的工作流程图；
图2为系统内时钟源与时钟记录单元的连接关系示意图；
图3为一种确定系统间全局时钟的结构第一实施例的结构示意图；
图4为一种确定系统间全局时钟的结构第二实施例的结构示意图；
图5为一种确定系统间全局时钟的结构第三实施例的结构示意图。
具体实施方式
以下结合附图所示实施例对本发明作进一步的说明。
本发明公开了一种系统间全局时钟的确定方法，所述系统之间通路连接，如图1所示，具体包括以下步骤：
(1)确定一时钟源作为基准时钟源，该基准时钟源通过网络覆盖全部系统。首先，确定一时钟源作为基准的时钟源，由上述基准时钟源产生标定信号。
由于各系统内部均有各自的本地时钟，故首先需要确定唯一时钟源作为基准，基准时钟源可任意选择，只需要该基准时钟源满足能够通过网络传输到所有系统(即覆盖所有系统)。基准时钟源可从各系统的本地时钟中进行选择，也单独外置一时钟源作为基准。作为一优选方案，上述基准时钟源从各系统的本地时钟中确定，结构上可单独为一时钟控制器，也可包括一时钟控制器以及接受时钟控制器控制的时钟发生器，根据实际需要设置。
(2)所述基准时钟源产生标定信号，所述标定信号被分发至各系统处，记录所述标定信号的发出时间Td(0)。
如前所述，标定信号由基准时钟源产生，故标定信号既可以由时钟控制器直接发出的一个电脉冲形成，也能为时钟发生器接受所述时钟控制器驱动发出的一段时钟信号。标定信号产生后其需要发送至各系统处，本实施例中，由与基准时钟源相配合的信号记录单元将该标 定信号分发至各系统处，其中信号记录单元包括一控制器以及接受该控制驱动的时间转换器，
基准时钟源以及与基准时钟源相配合的信号记录单元属于其中一系统，同时与基准时钟源相配合的信号记录单元接收并记录标定信号的发出时间Td(0)。
(3)标定信号通过网络到达各系统后，系统依据各自本地时钟记录标定信号到达时间Ta(n)，同时各系统处分别产生一返回信号并依据各自本地时钟记录返回信号发出时间Tb(n)，接收返回信号并所述记录返回信号到达基准时钟源的到达时间Td(n)，从而确定所述各系统的绝对偏移Delay(n)；
标定信号发出时间Td(0)以及返回信号的到达时间Td(n)可由同一计时元件记录，从而可保证与计时单元相同的时间精度，图1所示实施例中，均通过与基准时钟源相配合的信号记录单元接收并记录，具体的是由时间转换器接受控制器的驱动记录Td(0)和Td(n)的具体数值。
步骤(3)中，若不考虑精度问题时，标定信号至各系统的到达时间Ta(n)以及返回信号的发出时间Tb(n)可直接由系统根据各自的本地时钟确定并记录，到达时间Ta(n)以及发出时间Tb(n)也可经由各系统内本地时钟以及与所述本地时钟相配合的本地信号记录单元确定，各系统内的本地信号记录单元结构与上述与基准时钟源相配合的信号记录单元结构相同，其与本地时钟双向通信有线连接，当确定各系统开始工作时，本地信号记录单元依据各自本地时钟记录各系统开始工作的时间零点ta0(n)，当判断标定信号到达时，本地的信号记录单元依据各自本地时钟记录标定信号(脉冲或时钟信号)的达到时间ta1(n)，则所述到达时间Ta(n)＝ta1(n)-ta0(n)；当判断返回信号发出时，本地的信号记录单元依据各自本地时钟记录返回信号的发出时间tb1(n)，则所述的发出时间Tb(n)＝tb1(n)-ta0(n)。
各系统处分别产生的返回信号可为各种形式，以下以返回信号为所述各系统分别发出的应答信号或所述标定信号分别返回对该步骤进行说明，应理解，若返回信号为其他形式时，采用本发明所示的方法也可实现系统间全局时钟的形成。
当标定信号到达所述各系统后，各系统既可以通过直接电路连接返回信号链路，将标定信号返回，也可以通过控制器(如FPGA这种支持异步响应的控制器)接收到标定信号，则立即(不依赖与控制器的主时钟条件下)发出应答信号，然后在记录下到达所述基准时钟源的到达时间Td(n)，以确定所述各系统的绝对偏移Delay(n)。
(I)若为所述应答信号返回，则Delay(n)＝(Td(n)-Td(0)-Δn)/2，其中Δn为各系统应答反应时间；步骤(I)中，不考虑时间精度问题时，Δn为预设值，预先通过实验和计算确定后存储于各自系统中，此外Δn也可由各系统内的本地时钟以及本地的信号记录单元配合确 定，则Δn＝Tb(n)-Ta(n)；
(II)若为所述标定信号返回，则Delay(n)＝(Td(n)-Td(0))/2；
(4)根据所述绝对偏移Delay(n)以及所述标定信号到达时间Ta(n)或根据所述绝对偏移Delay(n)以及所述返回信号的发出时间Tb(n)调整所述各系统处的时钟以形成全局时钟：分别确定各自本地时钟与基准时钟源之间的零点偏差Tc(n)＝(Ta(n)-Delay(n)-Td(0))或Tc(n)＝(Delay(n)+Tb(n)-Td(n))，并将Tc(n)作为校正参数对各自系统的本地时钟进行校正以形成全局时钟。
从标定信号的发出至到达各系统的过程中，存在Td(0)+Delay(n)＝Ta(n)-Tc(n)，则Tc(n)＝Ta(n)-Td(0)-Delay(n)＝{Ta(n)-((Td(n)+Td(0))/2-Δn/2}，其中若返回信号为标定信号，则Δn＝0；在返回信号发出至其到达基准时钟源的过程中，存在Td(n)-Delay(n)＝Tb(n)-Tc(n)，则Tc(n)＝Tb(n)-Td(n)+Delay(n)＝{Ta(n)-((Td(n)+Td(0))/2-Δn/2}，其中若返回信号为标定信号，则Δn＝0。
Tc(n)大小确定后则可将其作为校正参数对各自系统的本地时钟进行校正：
(1)如果Tc(n)＞0，说明本系统时钟零点早于基准时钟源，则在本系统的计时系统中减去该值。
(2)如果Tc(n)＜0，说明本系统时钟零点晚于基准时钟源，则在本系统计时系统中加上该值，这样保证所有的系统具有完全一致的时间基准。
上述方法中，由基准系统(即本地时钟作为基准时钟源的系统)发出标定信号并确定Delay(n)，其余系统确定Ta(n)和Tb(n)，由于各个系统均设有本地时钟和信号记录单元，所以也可以由其余系统发出标定信号并计算Delay(n)，基准系统测量Ta(n)和Tb(n)，同时，由于基准系统和其余系统都具备信号处理功能，所以，既可以将测量的Delay(n)发送给对方，也可以将测量的Ta(n)和Tb(n)发送给对方。任何一方只要通过网络获取到了Delay(n)和Ta(n)、Tb(n)，都可以确定校正参数Tc(n)，并将Tc(n)发送给各个系统进行校正，或者上传给整个系统的总处理单元进行全局的校正。
采用本发明所示的方法，各系统都有自己的本地时钟，在独立工作时，可依赖自己的本地时钟进行工作，在系统间需要全局统一时间基准时，通过上述所示的系统间全局时钟的确定方法，即能够方便快捷的实现系统间全局时钟的统一，可根据需要应用至各领域中。
在上述实施例所示的基础上，本发明进一步的公开了一种系统间全局时钟的方法，其可提高时间同步的精度以用于对于时间精度要求较高的场合。
一种系统间全局时钟的确定方法，所述系统之间通路连接，包括以下步骤：
(1)确定一时钟源作为基准时钟源，该基准时钟源通过网络覆盖全部系统。首先，确定一时钟源作为基准时钟源，由上述基准时钟源产生标定信号。
由于各系统内部均有各自的本地时钟，故首先需要确定唯一时钟源作为基准，基准时钟源可任意选择，只需要该基准时钟源满足能够通过网络传输到所有系统(即覆盖所有系统)。基准时钟源可从各系统中选择，也可外置的一时钟源作为基准。本实施例中，上述基准时钟源可单独为一时钟控制器，也可包括一时钟控制器以及接受时钟控制器控制的时钟发生器，根据实际需要设置。
(2)所述基准时钟源产生标定信号，所述标定信号直接或通过与基准时钟源相配合的信号记录单元被分发至各系统处，与基准时钟源相配合的信号记录单元记录所述标定信号的发出时间Td(0)；
如前所述，标定信号由基准时钟源产生，故标定信号既可以由时钟控制器直接发出的一个电脉冲形成，也能为时钟发生器接受所述时钟控制器驱动发出的一段时钟信号。标定信号产生后其需要发送至各系统处，本实施例中，由与基准时钟源相配合的信号记录单元将该标定信号分发至各系统处，信号记录单元最小时间测量刻度小于基准时钟源的时钟周期的1/2，其包括一控制器以及接受该控制驱动的时间转换器，基准时钟源以及与基准时钟源相配合的信号记录单元可属于其中一系统以便于系统连线布置。在与基准时钟源相配合的信号记录单元将标定信号分发至各系统的同时信号记录单元记录标定信号的发出时间Td(0)。
(3)标定信号通过网络到达各系统后，系统依据各自本地时钟以及本地的信号记录单元记录标定信号到达时间Ta(n)，同时各系统处分别产生一返回信号并依据各自本地时钟以及本地的信号记录单元记录返回信号的发出时间Tb(n)，与基准时钟源相配合信号记录单元接收返回信号并所述记录返回信号到达基准时钟源的到达时间Td(n)，从而确定所述各系统的绝对偏移Delay(n)。
标定信号发出时间Td(0)以及返回信号的到达时间Td(n)均通过与基准时钟源相配合的高精度信号记录单元接收并记录，具体由时间转换器接受控制器的驱动记录Td(0)和Td(n)的具体数值。由于与基准时钟源相配合的信号记录单元最小时间测量刻度小于基准时钟源的时钟周期的1/2设置，这样信号记录单元可以精确测量小于一个时钟周期长度的时间：在高同步要求的全局时钟中，全局时钟频率一般在50MHz以上，时钟周期在20ns以内，甚至频率达到200MHz以上，时钟周期在2ns以内。但是全局时钟在线路上的延时也需要被精确测量，而这种延时随线路长度不同而不同，不会与系统全局时钟保持相同相位，为了精确测量这种 延时，需要高精度的时钟测量装置，而不是依赖全局时钟，通过最小测量刻度小于基准时钟的时钟周期的1/2的信号测量元件，能实现诸如线路延时或者相位偏差等更高精度的时间测量。
作为一优选的方案，其中信号记录单元包括一控制器以及接受该控制驱动的时间转换器，该时间转换器的最小时间测量刻度在1ns以内从而可精确的记录标定信号发出时间Td(0)以及返回信号的返回时间Td(n)，从而可用于对于时间精度要求在ps级别的场合。
进一步的，该时间转换器可为TDC(时间数字转换器)或者TAC(时间模拟转换器)，TDC或者TAC的时间精度在100ps以内。以TDC为例，其接受控制器控制读取TDC的计数值(记录的时间值)，由于TDC是异步计时，也就是对时钟的信号是即时触发，一般来说是电脉冲的跳变沿触发，故不存在通信开销，且TDC能不完全依赖主时钟频率，通过电路延时追赶电路来计时，计时精度可以达到10ps，故采用时间精度在100ps以内信号记录单元用于记录信号的发出时间与返回时间，可以满足时间的同步精度在ps级别的要求，从而应用于如扫描成像系统等对于时间精度要求较高的领域中。
到达时间Ta(n)以及发出时间Tb(n)也经由各系统内本地时钟以及与所述本地时钟相配合的高时间精度的本地信号记录单元确定。各系统内本地的信号记录单元结构与上述与基准时钟源相配合的信号记录单元结构相同，同理，所述本地的信号记录单元最小时间测量刻度小于所述本地时钟时钟周期的1/2设置，二者具有同一级别的最小时间测量，。当确定各系统开始工作时，本地信号记录单元记录各系统开始工作的时间零点ta0(n)，当判断标定信号到达时，本地的信号记录单元依据本地时钟记录标定信号(脉冲或时钟信号)的达到时间ta1(n)，则所述到达时间Ta(n)＝ta1(n)-ta0(n)，当判断返回信号发出时，本地的信号记录单元依据本地时钟记录返回信号(脉冲或时钟信号或应答信号)发出时间tb1(n)，则所述的发出时间Tb(n)＝tb1(n)-ta0(n)，这样可保证Ta(n)、Tb(n)与前述Td(0)、Td(n)具有同一级别的精度。
各系统处分别产生的返回信号可为各种形式，以下以返回信号为所述各系统分别发出的应答信号或所述标定信号分别返回对该步骤进行说明，应理解，若返回信号为其他形式时，采用本发明所示的方法也可实现系统间全局时钟的形成。当标定信号到达所述各系统后，各系统既可以通过直接电路连接返回信号链路，将标定信号返回，也可以通过控制器(如FPGA这种支持异步响应的控制器)接收到标定信号，则立即(不依赖与控制器的主时钟条件下)发出应答信号，然后在记录下到达所述基准时钟源的到达时间Td(n)，以确定所述各系统的绝对偏移Delay(n)。
(I)若为所述应答信号返回，则Delay(n)＝(Td(n)-Td(0)-Δn)/2，其中Δn为各系统应答反应时间；考虑到时间精度问题，Δn是由各系统内的信号记录单元确定，Δn＝Tb(n)-Ta(n)；
(II)若为所述标定信号返回，则Delay(n)＝(Td(n)-Td(0))/2；
(4)根据所述绝对偏移Delay(n)以及所述返回信号到达时间Ta(n)调整所述各系统处的时钟以形成全局时钟：分别确定各自本地时钟与基准时钟源之间的零点偏差Tc(n)＝(Ta(n)-Delay(n)-Td(0))或Tc(n)＝(Delay(n)+Tb(n)-Td(n))，并将Tc(n)作为校正参数对各自系统的本地时钟进行校正以形成全局时钟。
从标定信号的发出至到达各系统的过程中，存在Td(0)+Delay(n)＝Ta(n)-Tc(n)，则Tc(n)＝Ta(n)-Td(0)-Delay(n)＝{Ta(n)-((Td(n)+Td(0))/2-Δn/2}，其中若返回信号为标定信号，则Δn＝0；在返回信号发出至其到达基准时钟源的过程中，存在Td(n)-Delay(n)＝Tb(n)-Tc(n)，则Tc(n)＝Tb(n)-Td(n)+Delay(n)＝{Ta(n)-((Td(n)+Td(0))/2-Δn/2}，其中若返回信号为标定信号，则Δn＝0。
Tc(n)大小确定后则可将其作为校正参数对各自系统的本地时钟进行校正：
(1)如果Tc(n)＞0，说明本系统时钟零点早于基准时钟源，则在本系统的计时系统中减去该值。
(2)如果Tc(n)＜0，说明本系统时钟零点晚于基准时钟源，则在本系统计时系统中加上该值，这样保证所有的系统具有完全一致的时间基准。
上述实施例中，通过高精度的时间计时单元来确定本方法中所需要确定的时间，不仅可解决系统间全局时钟的同步问题，更进一步的，还能够提高时间的同步精度，可应用于核探测、飞行时间应用等对时间同步精度要求高的领域。
对应上述方法，本发明还公开了一种系统间全局时钟确定的结构，包括至少两个系统、一基准时钟源以及与所述基准时钟源相配合的信号记录单元，上述系统之间通路连接，信号记录单元与基准时钟源通路连接、每一个系统均经由所述信号记录单元与所述基准时钟源通信以确定各系统各种本地时钟与所述基准时钟源之间的零点偏差。
其中如图2所示，基准时钟源以及与所述基准时钟源相配合的信号记录单元可从属于其中一系统中，也可单独外接一基准时钟源以及信号记录单元，以下以基准时钟源以及与信号记录单元从属于其中一系统中对本发明所示结构的工资原理进行说明。
多个系统之间可用现成的(或者新建简单的)通信网络连接起来。当各系统上电启动开始工作，各系统内的本地时钟开始工作，由于上电时间和各个系统本地时钟起振的差异，各个系统上的本地时钟不是在同一时刻开始，本发明所示的系统间全局时钟确定的结构通过信 号记录单元、基准时钟源以及各系统内的本地时钟进行相互计时和比较得到各个系统的时钟的相对差值，然后在利用差值将各自的时钟统一到一致的时间基准，完成全局时钟的部署。具体在的，选择任意一系统内设置本地时钟以及与本地时钟通路连接的信号记录单元，以该系统的本地时钟作为基准时钟源，信号记录单元为一计时元件，该基准时钟源向网络中其余系统发出一个标定信号，并通过自己的信号记录单元记录标定信号的发出时间Td(0)，其余系统接收到标定信号后，记录下标定信号的到达时间Ta(n)并产生一个返回信号，返回信号到达基准时钟源后，与基准时钟源相配合的信号记录单元记录下返回信号的到达时间Td(n)，通过测算Td(n)和Td(0)则可知道其余系统距离基准系统的距离，也即固定的时间差Delay(n)，基准系统将测算的时间差Delay(n)通过通信网络发送给其他所有系统。同时，各个其余系统通过自己测定的Ta(n)与收到的Delay(n)可测算自己的时间零点与基准系统的时钟零点的差值，即时钟基准的差值，各个系统通过该差值校正自己的时钟系统，例如给自己的时钟系统设置对应的延时，从而使整个系统处于完全一致的时钟基准。上述各种差值的计算也可通过其他处理器确定。
本实施例中，上述返回信号可为原标定信号也可为系统自己发出的一个应答信号，当系统采取标定信号返回时，不需要考试时间开销的问题，则Delay(n)＝(Td(n)-Td(0))/2；当系统采取应答方式返回信号时，则有一个应答时间的开销，即则Delay(n)＝(Td(n)-Td(0)-Δn)/2，该结构用于对时间精度要求不严格的领域时，信号记录单元可为一常用的计时元件即能有效的实现用于系统间全局时钟的确定，到达时间Ta(n)和发出时间Tb(n)可经由各系统内本地时钟自己独立确定，Δn也为各系统预设值，通过实验和计算确定并存储于各系统中。
但当本发明所示的结果应用于对时间精度要求较高的场合时，则信号记录单元的最小时间测量刻度小于基准时钟源的时钟周期的1/2设置，各系统内需要分别设置了一信号记录单元，各系统内部的信号记录单元以及与基准时钟源相配合的信号记录单元结构相同，最小时间测量刻度也相同，信号记录单元包括一控制器以及接受该控制驱动的高精度时间转换器，且各信号记录单元分别与系统内的本地时钟通路连接。这样信号记录单元可以精确测量小于一个时钟周期长度的时间：在高同步要求的全局时钟中，全局时钟频率一般在50MHz以上，时钟周期在20ns以内，甚至频率达到200MHz以上，时钟周期在2ns以内。但是全局时钟在线路上的延时也需要被精确测量，而这种延时随线路长度不同而不同，不会与系统全局时钟保持相同相位，为了精确测量这种延时，需要高精度的时钟测量装置，而不是依赖全局时钟，通过最小测量刻度小于基准时钟(本地时钟)的时钟周期的1/2的信号测量装置，能实现诸 如线路延时或者相位偏差等更高精度的时间测量。
作为一优选方案，时间转换器的最小时间测量刻度在1ns以内，更进一步的，本实施例中时间转换器为TDC(时间数字转换器)或者TAC(时间模拟转化器)，TDC或者TAC的时间精度在100ps以内。以TDC为例，其接受控制器控制进行时间值的记录和读取(即记录和调取Td(0)和Td(n)的值)，由于TDC可以异步计时，也就是对时钟的信号是即时触发，一般来说是电脉冲的跳变沿触发，故不存在通信开销，且TDC能不完全依赖主时钟频率，通过电路延时追赶电路来计时，测量比基准时钟源(本地时钟)时钟周期更短的时间长度，计时精度可以达到10ps，故采用此种精度的时间转换单元可精确的实现各系统至基准时钟源时钟零点的测量，使得时间的同步精度在ps级别的要求，从而可应用于对于时间精度要求较高的领域中。
这样设置后，标定信号的到达时间Ta(n)以及返回信号的发出时间Tb(n)经由各系统内本地时钟以及与所述本地时钟相配合的高时间精度的本地信号记录单元确定，当确定各系统开始工作时，本地信号记录单元记录各系统开始工作的时间零点ta0(n)，当判断标定信号到达时，本地的信号记录单元记录标定信号的达到时间ta1(n)，则所述到达时间Ta(n)＝ta1(n)-ta0(n)，当判断返回信号发出时，本地的信号记录单元记录返回信号的发出时间tb1(n)，则所述的发出时间Tb(n)＝tb1(n)-ta0(n)，这样可保证Ta(n)、Tb(n)与前述Td(0)、Td(n)具有同一级别的精度。
若返回信号为应答信号时，则Δn＝Tb(n)-Ta(n)；这样确定的Δn值具有与Td(0)、Td(n)同一数量级的精度，从而最终保证时钟零点的精度。
上述与基准时钟源相配合的信号记录单元和各系统之间既可以通过一条线路实现标定信号(应答信号)交互，二者之间也可双向通信连接以实现信号交互。若采用一条线路实现信号往返时，由于所有的系统都是通路连接的，标定信号会被广播发出，信号记录单元和其余的系统都会收到，所以为让其余的系统不会误认为该信号为基准时钟源的信号，需要其余系统的控制器接收到信号后再立即发出信号(信号最好与基准时钟源的标定信号不一样)，若二者双向通信连接时，标定信号的发送和接受区分开来，则无需考虑此种问题，信号的发送与接受更为容易。
此外，考虑到本发明所示的结构中，其信号测量是基于电路信号(电脉冲的跳变)来精确获取不同系统的时间延时和偏差，当通过固定媒介的信号传输，其延时和偏差更为确定，为达到全局时钟的精度为ps级别的要求，故基准时钟源与信号记录单元之间，信号记录单元与系统之间，各系统之间均为有线连接。
通过上述分析可知，采用本发明所示的一种系统间全局时钟的确定结构，各系统只需满足最终经由信号记录单元与基准时钟源通信连接，即可实现系统间全局时钟的设置，且由于采用时间精度高的信号记录单元实现各系统与基准时钟源之间时钟零点的确定，尤其适合对时间精度要求较高的场合。
以下结合具体实施例对本发明所示的确定系统间全局时钟的结构进行说明。
第一实施例中，如图3所示，一种系统间全局时钟的确定结构，包括至少两系统、一基准时钟源以及一与上述基准时钟源相配合的信号记录单元，该信号记录单元与基准时钟源通路连接、各系统之间依次双向通信连接以形成线状网络，线状网络可设置多条，与上述基准时钟源相配合的信号记录单元和每条线状网络中的一个系统双向通信连接。图3所示实施例中，优选设置一条线性网络，此条线性网络中的系统之间双向通信连接，且与基准时钟源相配合的信号记录单元和该线性网络中位于首部的系统之间双向通信连接，基准时钟源与信号记录单元之间，信号记录单元与位于首部的系统之间，各系统之间均为有线连接。
通过线状网络串联所有系统，在线状网络的一个节点(图3所示实施例为在线状网络的一端以尽量保证各个系统到基准时钟源的距离都不一样。)设置唯一的基准时钟源，同时设置一个高精度的信号记录单元，基准时钟源首先发出标定信号，同时，基准时钟源的信号记录单元开始计时Td(0)，各个系统由于其离基准时钟源的距离不一致，会先后依次接受到标定信号，各系统收到标定信号后，各个系统内部的信号记录单元记录该标定信号的到达时间Ta(n)，同时各系统立即应答回复或者直接电路连接返回标定信号给基准时钟源的信号记录单元并记录返回信号的发出时间Tb(n)，同样由于距离不同，信号记录单元会先后依次接收到来自各个系统的应答信号，依次记录时间Td(n)，系统与基准时钟源的时间延时为：Delay(n)＝(Td(n)-Td(0))/2或Delay(n)＝(Td(n)-Td(0)-Δn)/2，Δn的数值根据应用场合不同采用前述步骤确定；同时可以计算系统与基准时钟源的连线长度为L(n)＝Delay(n)*C，C接近光速，当需要系统间有完全统一的时间基准时，基准系统将获取对应的Delay(n)的数据发送各系统，每个系统计算自己本地时钟与基准时钟源零点偏差Tc(n)：Tc(n)＝(Ta(n)-Delay(n)-Td(0))或Tc(n)＝(Delay(n)+Tb(n)-Td(n))，并将Tc(n)作为校正参数让自己的系统时钟进行校正：
(1)如果Tc(n)＞0，说明本系统时钟零点早于基准系统，则在本系统计时系统中减去该值。
(2)如果Tc(n)＜0，说明本系统时钟零点晚于基准系统，则在本系统计时系统中加上该值。
考虑到若设置多条线状网络，可能出现多个系统到基准时钟源距离相同的情况，故在此 过程中，如果与基准时钟源相配合的信号记录单元收到的应答信号次数少于系统n值(说明至少有两个信号有重叠，这个概率非常低，因为信号记录单元能识别超过10ps的两个信号)，可以对系统分批进行测量，逐一获取。
上述基准时钟源与其余系统之间的测算可以在任意两个系统中进行，具体如图4所示，第二实施例中，系统A中的本地时钟作为基准时钟源与系统B完成测算，得到系统A与系统B二者之间的时钟偏差，再将系统B作为基准与系统C完成测算，得到系统B与系统C的之间的时钟偏差，通过第一步确定系统A、B之间的时钟偏差，可计算出时钟系统A与时钟系统C的偏差，依次类推，从而完成整个网上所有时钟系统的偏差。
第三实施例中，如图5所示，本发明所示的一种确定系统间全局时钟的结构，包括至少一基准时钟源，至少两系统以及一与上述基准时钟源相配合的信号记录单元，系统间通路连接，信号记录单元与基准时钟源通路连接，各系统分别与该信号记录单元双向通信连接以经由信号记录单元与基准时钟源通信。本实施例中，基准时钟源和各系统之间仍然采取星状网络连接，但基准时钟源和各系统之间增设与基准时钟源相配合的信号记录单元，各系统本地时钟可根据时间精度需要增设与各自本地时钟通路连接的本地的信号记录单元，若增设本地的信号记录单元，则各系统的本地时钟分别与各自的本地信号记录单元双向通信连接，本实施例中，优选的，基准时钟源与信号记录单元之间、信号记录单元与各系统之间为有线连接，本地时钟与各自的本地信号记录单元之间也是有线连接。
获取全局时钟时，首先是所有的系统上电，各自的时钟都己经工作，然后开始测算各自时钟系统的偏差，任选一个系统的本地时钟作为基准时钟源，基准时钟源向其余系统发出标定信号(该标定信号可以是简单的电脉冲或者是时钟信号)，同时，基准时钟源的信号记录单元开始计时Td(0)，各个系统由于其离基准时钟源的距离不一致，会先后依次接受到标定信号，各系统收到标定信号后，各个系统内部的信号记录单元记录该标定信号的到达时间Ta(n)，同时各系统立即应答回复或者直接电路连接返回标定信号给基准时钟源的信号记录单元并记录返回信号的发出时间Tb(n)，同样由于距离不同，信号记录单元会先后依次接收到来自各个系统的应答信号，依次记录时间Td(n)，系统与基准时钟源的时间延时为：Delay(n)＝(Td(n)-Td(0))/2或Delay(n)＝(Td(n)-Td(0)-Δn)/2，Δn的数值根据应用场合不同采用前述步骤确定；同时可以计算系统与基准时钟源的连线长度为L(n)＝Delay(n)*C，C的大小接近光速，当需要系统间需要有完全统一的时间基准时，基准系统将获取对应的Delay(n)的数据发送各系统，每个系统计算自己本地时钟与基准时钟源零点偏差：Tc(n)＝(Ta(n)-Delay(n)-Td(0))或Tc(n)＝ (Delay(n)+Tb(n)-Td(n))，并将Tc(n)作为校正参数对自己的系统时钟进行校正。
(1)如果Tc(n)＞0，说明本系统时钟零点早于基准系统，则在本系统计时系统中减去该值。
(2)如果Tc(n)＜0，说明本系统时钟零点晚于基准系统，则在本系统计时系统中加上该值。
同前所述，考虑到采用星状网络时，可能出现多个系统到基准时钟源距离相同的情况，故在此过程中，如果信号记录单元收到的应答信号次数少于系统值(说明至少有两个信号有重叠，这个概率非常低，因为信号记录单元能识别超过10ps的两个信号)，可以对系统分批进行测量，逐一获取。
上述的对实施例的描述是为便于该技术领域的普通技术人员能理解和使用本发明。熟悉本领域技术的人员显然可以容易地对这些实施例做出各种修改，并把在此说明的一般原理应用到其他实施例中而不必经过创造性的劳动。因此，本发明不限于上述实施例，本领域技术人员根据本发明的揭示，不脱离本发明范畴所做出的改进和修改都应该在本发明的保护范围之内。

Claims (10)

  1. 一种系统间全局时钟的确定方法，所述系统之间通路连接，其特征在于：包括以下步骤：
    (1)确定一时钟源作为基准时钟源，所述基准时钟源覆盖所述的全部系统；
    (2)所述基准时钟源产生标定信号，所述标定信号被分发至各系统处，记录所述标定信号的发出时间Td(0)；
    (3)所述标定信号到达所述各系统后，所述系统依据各自本地时钟记录所述标定信号到达时间Ta(n)，同时所述各系统处分别产生一返回信号并依据各自本地时钟记录所述返回信号的发出时间Tb(n)，接收所述返回信号并所述记录所述返回信号到达所述基准时钟源的到达时间Td(n)，以确定所述各系统至所述基准时间源之间的绝对偏移Delay(n)；
    (4)根据所述绝对偏移Delay(n)、所述标定信号到达时间Ta(n)或所述返回信号的发出时间Tb(n)确定各自本地时钟与基准时钟源之间的零点偏差Tc(n)，将Tc(n)作为校正参数对各自系统的本地时钟进行校正以形成全局时钟。
  2. 根据权利要求1所述系统间全局时钟的确定方法，其特征在于：所述标定信号发出时间Td(0)以及所述返回信号到达时间Td(n)的接收与记录由一与基准时钟源相配合的信号记录单元完成；
    优选的，所述步骤(2)中，由所述与基准时钟源相配合的信号记录单元将所述标定信号分发至各系统处；
    优选的，所述基准时钟源以及与所述基准时钟源相配合的信号记录单元属于其中一系统；
    优选的，所述步骤(1)中，所述基准时钟源为一时钟控制器或包括一时钟控制器以及接受时钟控制器控制的时钟发生器；
    优选的，所述标定信号为所述时钟控制器直接发出的一个电脉冲形成或者所述时钟发生器接受所述时钟控制器驱动发出的一段时钟信号；
    优选的，所述步骤(3)中，所述标定信号的到达时间Ta(n)以及所述返回信号的发出时间Tb(n)经由各系统内本地时钟以及与所述本地时钟相配合的本地信号记录单元确定；
    优选的，当确定各系统开始工作时，本地信号记录单元依据各自本地时钟记录各系统开始工作的时间零点ta0(n)，当判断标定信号到达时，本地的信号记录单元依据各自本地时钟记录标定信号的达到时间ta1(n)，则所述到达时间Ta(n)＝ta1(n)-ta0(n)；当判断返回信号发出时，本地的信号记录单元依据各自本地时钟记录返回信号发出时间tb1(n)，则所述的发出时间 Tb(n)＝tb1(n)-ta0(n)；
    优选的，所述步骤(3)中，所述返回信号为所述各系统分别发出的应答信号或所述标定信号分别返回，记录应答信号或所述标定信号到达时间Td(n)，确定所述各系统的绝对偏移Delay(n)：
    (I)若为所述应答信号返回，则Delay(n)＝(Td(n)-Td(0)-Δn)/2，其中Δn为各系统应答反应时间；
    (II)若为所述标定信号返回，则Delay(n)＝(Td(n)-Td(0))/2；
    优选的，所述步骤(I)中，所述Δn为系统预设值；或所述Δn由各系统内的信号记录单元确定，所述Δn＝Tb(n)-Ta(n)；
    优选的，所述步骤(4)中，Tc(n)＝(Ta(n)-Delay(n)-Td(0))或Tc(n)＝(Tb(n)+Delay(n)-Td(n))。
  3. 根据权利要求2所述系统间全局时钟的确定方法，其特征在于：与所述基准时钟源相配合的信号记录单元最小时间测量刻度小于基准时钟源的时钟周期的1/2；所述本地的信号记录单元最小时间测量刻度小于所述本地时钟时钟周期的1/2；
    优选的，所述信号记录单元的最小时间测量刻度在1ns以内；
    优选的，所述信号记录单元的最小时间测量刻度在100ps以内。
  4. 一种用于实现权利要求1至3任一项所述系统间全局时钟确定方法的结构，包括通路连接的系统，其特征在于：还包括一基准时钟源以及与所述基准时钟源相配合的信号记录单元，所述与所述基准时钟源相配合的信号记录单元与所述基准时钟源通路连接、所述每一个系统均经由与所述基准时钟源相配合的信号记录单元与所述基准时钟源通信以确定各系统各自本地时钟与所述基准时钟源之间的零点偏差。
  5. 根据权利要求4所述确定系统间全局时钟的结构，其特征在于：所述各系统内部设有与各自系统的本地时钟通路连接的信号记录单元；
    优选的，以其中一系统内的本地时钟以及信号记录单元作为基准时钟源以及与基准时钟源相配合的信号记录单元；
    优选的，所述与基准时钟源相配合的信号记录单元与所述系统之间为双向通信连接；
    优选的，所述与基准时钟源相配合的信号记录单元与所述基准时钟源之间、所述与基准时钟源相配合的信号记录单元与所述系统之间、所述系统之间为有线连接。
  6. 根据权利要求4或5所述的确定系统间全局时钟的结构，其特征在于：所述系统之间依次通信连接以形成线状网络结构，且至少设置一条线状网络结构，所述与基准时钟源相配 合的信号记录单元与所述每个线状网络结构中的一系统之间通信连接。
  7. 根据权利要求6所述确定系统间全局时钟的结构，其特征在于：所述与基准时钟源相配合的信号记录单元和所述每一个线状网络结构中位于端点处的一系统之间通信连接；
    优选的，所述系统之间为双向通信连接；
    优选的，设置一条所述线状网络。
  8. 根据权利要求4或5所述确定系统间全局时钟的结构，其特征在于：所述各系统分别直接和所述与基准时钟源相配合的信号记录单元之间相连接以形成星状网络结构。
  9. 根据权利要求4或5所述确定系统间全局时钟的结构，其特征在于：与所述基准时钟源相配合的信号记录单元的最小时间测量刻度小于所述基准时钟源的时钟周期的1/2；
    所述本地的信号记录单元最小时间测量刻度小于所述本地时钟时钟周期的1/2；
    优选的，所述信号记录单元包括一控制器以及与所述控制器通信连接以接受所述控制器驱动的时间转换器，所述时间转换器的时间精度在1ns以内；
    优选的，所述时间转换器为TDC或者TAC，所述TDC或者TAC的时间精度在100ps以内。
  10. 根据权利要求4或5所述确定系统间全局时钟的结构，其特征在于：所述基准时钟源为一时钟控制器或包括一时钟控制器以及接受时钟控制器控制的时钟发生器。
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