WO2016070719A1 - 一种提供系统内全局时钟的方法和装置 - Google Patents

一种提供系统内全局时钟的方法和装置 Download PDF

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Publication number
WO2016070719A1
WO2016070719A1 PCT/CN2015/092602 CN2015092602W WO2016070719A1 WO 2016070719 A1 WO2016070719 A1 WO 2016070719A1 CN 2015092602 W CN2015092602 W CN 2015092602W WO 2016070719 A1 WO2016070719 A1 WO 2016070719A1
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Prior art keywords
clock
signal
terminal
recording unit
clock source
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PCT/CN2015/092602
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English (en)
French (fr)
Inventor
房磊
张博
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武汉数字派特科技有限公司
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Application filed by 武汉数字派特科技有限公司 filed Critical 武汉数字派特科技有限公司
Priority to BR112017009285-9A priority Critical patent/BR112017009285B1/pt
Priority to JP2017542247A priority patent/JP6419981B2/ja
Priority to US15/523,944 priority patent/US10187196B2/en
Priority to EP15856695.0A priority patent/EP3217590B1/en
Publication of WO2016070719A1 publication Critical patent/WO2016070719A1/zh
Priority to HK18103279.6A priority patent/HK1243842A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/46—Monitoring; Testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging

Definitions

  • the invention belongs to the technical field of time test measurement, and relates to a method for determining a reference time, in particular to a method for determining global time.
  • the global clock is applied in many fields to ensure that all components in the system have the same time reference.
  • multiple terminal components often require a completely consistent time reference to meet accurate time measurement.
  • a method of obtaining communication delay and correcting by timestamp communication between a plurality of terminals is widely used in the field of communication, but this synchronization method is limited only to global clock synchronization using an off-the-shelf communication protocol to achieve low precision, such as ms. Or sub-ms level, the accuracy of this method ultimately depends on the speed of the clock, that is, the flip frequency, and will not achieve a shorter synchronization accuracy than the clock cycle. So the traditional method can only be as shown in Figure 1.
  • Adding a fanout which necessarily requires changing the hardware that has been determined, and because in a particular field, such as a scanning imaging system, multiple (several to several thousand) detectors (ie, terminals) need to be unified
  • the time base is used to satisfy the global unified clock, and each detector requires a picosecond (ps) level time measuring device to require a higher time resolution for the entire instrument system, and the accuracy of time synchronization is required at the ps level, so
  • the requirements for line lengths are required at the micron (um) level, and the design of existing global clocks cannot meet this requirement.
  • Time base Accurate measurement of the delay from the clock source to the terminal due to the use of a high-precision signal recording unit, and the clock source's flip frequency is not high, so that it can be used in applications where synchronization accuracy is high.
  • the method and device for providing a global clock in a system according to the present invention do not need to control the length of a clock connection line from each terminal to a clock source, and do not need to specially consider clock routing, thereby avoiding a large number of connections to bring system assembly. Difficulties in correction, maintenance, and expansion.
  • the solution of the present invention is:
  • the present invention discloses a method for providing a global clock in a system.
  • the system includes at least two terminals, and the path connection between the terminals includes the following steps:
  • the step (1) further includes the step of determining a clock source as a reference, and generating a calibration signal from the reference clock source.
  • the clock source is a clock controller or includes a clock controller and a clock generator controlled by the clock controller;
  • the calibration signal is formed by an electrical pulse directly sent by the clock controller or the clock generator receives a clock signal sent by the clock controller;
  • the reference clock source is a local clock or an external clock source inside any one of the terminals.
  • the signal recording unit cooperates with the clock source as a reference to record the issuance time T(0) of the calibration signal;
  • the calibration signal is distributed to each terminal in the system by the signal recording unit cooperating with the clock source as a reference.
  • the clock source as a reference and the signal recording unit cooperating with the reference clock source belong to one of the terminals.
  • the minimum time measurement scale of the signal recording unit is less than 1/2 of the clock period of the reference clock source
  • the minimum time measurement scale of the signal recording unit is within 1 ns;
  • the calibration signal reaches the terminals, the respective terminals respectively return signals, record the arrival time T(n) of the return signal, and determine the absolute offset Delay(n) of each terminal;
  • the arrival time T(n) of the return signal is received and recorded by a signal recording unit cooperating with a clock source as a reference.
  • the return signal is respectively returned by the response signal sent by each terminal or the calibration signal
  • the absolute offset of each terminal is determined via a processor or an external processor with the signal recording unit or the terminal, and the time at each terminal is adjusted to form a global clock.
  • the present invention also discloses an apparatus for providing a global clock in a system, comprising at least one clock source, at least two terminals, and a path connection between the terminals, which further includes a signal record matched with the clock source. And a signal recording unit coupled to the clock source path, each of the terminals communicating with the clock source via the signal recording unit to determine an absolute time offset between each terminal and the clock source.
  • the terminals are sequentially connected in communication to form a linear network structure, and a signal recording unit cooperating with the clock source is in communication connection with a terminal in the linear network structure.
  • a signal recording unit that cooperates with the clock source and a terminal that is located at the endpoint in the linear network structure are communicatively coupled.
  • the signal recording unit and the terminal are bidirectional communication connections.
  • a wired connection is between the signal recording unit and the clock source, between the signal recording unit and the terminal, and between the terminals.
  • a signal recording unit is respectively disposed in each terminal to determine a response time of each terminal.
  • each of the terminals is respectively connected with the signal recording unit to form a star network structure.
  • each of the terminals is in a two-way communication connection with the signal recording unit.
  • a wired connection is between the clock source and the signal recording unit, and between the signal recording unit and each terminal.
  • a signal recording unit is respectively disposed in each terminal to determine a response time of each terminal.
  • the minimum time measurement scale of the signal recording unit is less than 1/2 of the clock period of the clock source as the reference.
  • the signal recording unit comprises a controller and a time converter communicatively coupled to the controller to receive the controller, the time converter having a time precision of less than 1 ns.
  • the time converter is TDC or TAC, and the time precision of the TDC or TAC is within 100 ps.
  • a method and apparatus for providing a global clock in a system wherein the terminals in the system are connected by a path, and each terminal and the respective paths respectively communicate with a predetermined clock source through a signal recording unit, and the clock is connected.
  • the source sends a calibration signal to the network, and the signal recording unit records the current issuance time T(0) of the calibration signal, and each terminal hanging on the network receives the calibration signal in sequence due to the different distances of the separated clock sources, and the signal is received.
  • Return can be the active return of the calibration signal or the passive return of the response signal after each terminal responds
  • the return signal returns to the signal recording unit sequentially along the network, and the signal recording unit sequentially records the time T(n) of each return signal.
  • the signal recording unit can measure the delay of each terminal and the clock source signal. In an actual system, this delay can be used as a correction parameter to ensure that all terminals are in a completely consistent time reference.
  • the synchronization accuracy of time is improved by the addition of a high-precision signal recording unit.
  • a high-accuracy signal recording unit at the clock source such as a time-to-digital converter (TDC) or a time-to-analog converter (TAC)
  • TDC time-to-digital converter
  • TAC time-to-analog converter
  • TDC time-to-digital converter
  • TAC time-to-analog converter
  • TDC can not rely on the main clock frequency completely, and it can be timed by the circuit delay chasing circuit, measuring the time length shorter than the clock period, and the timing precision can reach 10ps. This can meet the requirements of time synchronization accuracy at the ps level, and can be applied to occasions with high time precision requirements.
  • the length of the clock connection line is not controlled, any connection, the network between the terminals can be arbitrarily connected, only need to meet each terminal finally through the signal recording unit and the clock source communication connection, the global clock can be deployed and solved.
  • Traditional methods require precise design and implementation difficulties for all wire lengths.
  • FIG. 1 is a schematic structural diagram of a global clock determining apparatus of a conventional star network structure
  • FIG. 2 is a working flow chart of a method for providing a global clock in a system according to the present invention
  • FIG. 3 is a schematic structural diagram of a first embodiment of a global clock device in a system according to the present invention.
  • FIG. 4 is a schematic structural diagram of a second embodiment of a global clock device in a system according to the present invention.
  • a method of providing a global clock in a system includes the following steps:
  • a clock source as a reference is determined, and a calibration signal is generated from the reference clock source.
  • a system can have multiple clock sources or a unique clock source. When there are multiple clock sources, you need to first determine one of the clock sources as the reference.
  • the reference clock source can be arbitrarily selected. Only the clock source can be passed.
  • the network transmits to all terminals (that is, covers all terminals), and an external clock source can also be used as the reference clock of the entire system.
  • the above clock source can be a single clock controller or a clock controller.
  • the clock generator controlled by the clock controller can be arbitrarily set according to actual needs.
  • a calibration signal is generated, which is distributed to each terminal in the system, and the time T(0) at which the calibration signal is issued is recorded.
  • the clock source after the clock source as the reference is determined, the clock source generates a calibration signal, and the specific form of the calibration signal is determined by the clock source.
  • the calibration signal can be directly sent by the clock controller. An electrical pulse is generated, or a clock signal is generated by the control clock. The calibration signal is generated and distributed to each terminal. When the calibration signal is distributed, the calibration signal is emitted for a time T(0).
  • each terminal After the calibration signal reaches the terminals via the network, each terminal generates a return signal, records the arrival time T(n) of the return signal, and determines the absolute offset Delay(n) of each terminal:
  • the form of the return signal may be various.
  • the following describes the working principle of the method for providing a global clock in the system according to the present invention with the return signal as the response signal or the calibration signal. It should be understood that if the return signal is in other forms, the following is adopted.
  • the method shown in the present invention can also realize the formation of a global clock of each terminal in the system.
  • each terminal can return to the signal link through a direct circuit connection, and the calibration will be performed.
  • the signal is returned. It can also receive the calibration signal through a controller (such as an FPGA that supports asynchronous response). Immediately (without relying on the controller's main clock condition), the response signal is sent. When the return signal is sent, then The arrival time T(n) of the return signal is recorded, so that the respective terminals reach the absolute offset Delay(n) as the reference clock source.
  • the calibration signal issuance time T(0) and the arrival time T(n) of the return signal are received and recorded by the same timing component, so that the two have the same order of magnitude precision.
  • both pass and the clock source The matched signal recording unit accepts and determines a specific time, wherein the signal recording unit includes a controller and a time converter that accepts the control drive, and the drive record T(0) and T(n) of the controller are accepted by the time converter
  • the distribution of the calibration signal may be directly distributed to each terminal by the clock source control, or may be distributed to each terminal by the signal recording unit cooperating with the above-mentioned reference clock source.
  • ⁇ n is a preset value, which can be determined in advance by experiments and calculations
  • step (3) Adjusting the time at each terminal according to the absolute offset to form a global clock.
  • the time difference (absolute offset) calculated above can be used as the correction coefficient to ensure that the timing systems of the respective terminals are completely synchronized.
  • instructions may be sent via the signal recording unit or the processor or external processor of each terminal according to the absolute offset of each terminal to adjust the time at each terminal to form a global clock.
  • the present invention further discloses a method for providing a global clock in a system, which can improve the accuracy of time synchronization for use in situations where time accuracy is high.
  • a method of providing a global clock within a system comprising the steps of:
  • a clock source as a reference is determined, and a calibration signal is generated from the reference clock source.
  • the reference clock source can be arbitrarily selected, and only needs to be satisfied that the clock source can be transmitted through the network. All terminals (that is, all terminals are covered), and an external clock source can also be used as the reference clock of the entire system.
  • the above clock source can be a single clock controller, a clock controller, and a clock control.
  • the clock generator controlled by the device can be arbitrarily set according to actual needs.
  • a calibration signal is generated, which is distributed to each terminal in the system, and the time T(0) at which the calibration signal is issued is recorded.
  • the clock source After the clock source as the reference is determined, the clock source generates a calibration signal, and the specific form of the calibration signal is determined by the clock source.
  • the calibration signal can be directly generated by the clock controller to generate an electrical pulse, or controlled by The clock generates a clock signal, and the calibration signal is generated and distributed to each terminal, where the calibration signal can be directly distributed to each terminal by the clock source control, or can be distributed to the signal recording unit matched with the above-mentioned reference clock source. At each terminal.
  • the signal recording unit cooperating with the above-mentioned reference clock source records the calibration signal issuance time T(0), wherein the minimum time measurement scale of the signal recording unit matched with the clock source is smaller than the reference clock source.
  • the delay of the global clock on the line also needs to be accurately measured. This delay varies with the length of the line and does not maintain the same phase with the global clock of the system.
  • the device can achieve more accurate time measurements such as line delay or phase deviation by a signal measuring device with a minimum measurement scale less than 1/2 of the clock period of the reference clock.
  • the signal recording unit includes a controller and a time converter receiving the control, and the minimum time measurement scale of the time converter is within 1 ns so that the calibration signal is emitted T(0) accurately and Returns the return time T(n) of the signal, which can be used where the time accuracy is required at the ps level.
  • the time converter can be a TDC (Time Digitizer) or a TAC (Time Analog Converter), and the time accuracy of the TDC or TAC is within 100 ps.
  • TDC time Digitizer
  • TAC Time Analog Converter
  • the time converter accepts the controller to read the count value of the TDC (the recorded time value). Since the TDC is an asynchronous timing, that is, the signal of the clock is an instant trigger, which is a jump of the electric pulse. Trigger, so there is no communication overhead, and TDC can not rely on the main clock frequency completely, and the timing can be up to 10ps through the circuit delay chasing circuit. Therefore, the signal recording unit with time precision within 100ps is used for recording signals. The time of issue and the return time can meet the requirements of the synchronization accuracy of time at the ps level, and thus can be applied to fields such as scanning imaging systems where time precision is required.
  • the above-mentioned clock source as a reference and the signal recording unit matched with the reference clock source may belong to one of the terminals in the system, and the clock source and the signal recording unit may share a processor. .
  • each terminal After the calibration signal reaches the terminals via the network, each terminal generates a return signal, records the arrival time T(n) of the return signal, and determines the absolute offset Delay(n) of each terminal:
  • the form of the return signal may be various.
  • the following describes the working principle of the method for providing a global clock in the system according to the present invention with the return signal as the response signal or the calibration signal. It should be understood that if the return signal is in other forms, the following is adopted.
  • the method shown in the present invention can also realize the formation of a global clock of each terminal in the system.
  • each terminal can return the signal link through a direct circuit connection, return the calibration signal, or receive a calibration signal through a controller (such as an FPGA that supports asynchronous response).
  • a controller such as an FPGA that supports asynchronous response.
  • an acknowledgement signal is issued, and when the return signal is issued, then the arrival time T(n) of the return signal is accepted and determined by the signal recording unit cooperating with the clock source.
  • a signal recording unit is also built in each terminal, and the signal recording unit is communicably connected to each terminal and a clock source and a signal recording unit matched with the clock source via the network, and ⁇ n is recorded by signals in each terminal.
  • step (3) Adjusting the time at each terminal according to the absolute offset to form a global clock.
  • the time difference (absolute offset) calculated above can be used as the correction coefficient to ensure that the timing systems of the respective terminals are completely synchronized.
  • each terminal can be terminated according to a signal recording unit or each terminal or an external processor.
  • the absolute offset at the end sends an instruction to adjust the time at each terminal to form a global clock.
  • a signal recording unit that measures a scale less than 1/2 of a clock period of the clock source as a reference is used to determine the time T(0) of the calibration signal and the return.
  • the arrival time T(n) of the signal can realize the synchronization accuracy of the global clock in the system without considering the wiring problem.
  • the present invention also discloses an apparatus for providing a global clock in a system, including at least one clock source, at least two terminals, and a signal recording unit matched with a clock source, and the terminal
  • the inter-path connection, the signal recording unit is communicatively coupled to the clock source, and each terminal communicates with the clock source via the signal recording unit to determine an absolute offset of each terminal to the clock source.
  • Each terminal is finally connected to the clock source via the signal recording unit through the network.
  • the clock source sends a calibration signal to the network, and the signal recording unit records the current transmission time T(0) of the calibration signal, and the terminal hangs on the network.
  • the calibration signal is received in turn, and the signal is returned (active or passive return), and the returned signal (ie, the calibration signal or the response signal) is sequentially returned to the signal recording unit along the network.
  • the signal recording unit sequentially records the time T(n) of each return signal, so that the signal recording unit can measure the precise delay (absolute offset) of each terminal and the clock source signal, which can be delayed in an actual system. As a correction parameter, all terminals are guaranteed to be in a completely consistent time base.
  • the signal recording unit can be a common timing component to effectively realize the global clock of each terminal in the system.
  • the minimum time measurement scale of the signal recording unit is Less than 1/2 of the clock period of the clock source as the reference.
  • the signal recording unit includes a controller and a time converter receiving the control, and the minimum time measurement scale of the time converter is within 1 ns so that the calibration signal is emitted T(0) accurately and Returns the return time T(n) of the signal, which can be used where the time accuracy is required at the ps level.
  • the time converter can be a TDC (Time Digitizer) or a TAC (Time Analog Converter), and the time accuracy of the TDC or TAC is within 100 ps.
  • TDC time Digitizer
  • TAC Time Analog Converter
  • the time converter accepts the controller to read the count value of the TDC (the recorded time value). Since the TDC is an asynchronous timing, that is, the signal of the clock is an instant trigger, which is a jump of the electric pulse. Trigger, so there is no communication overhead, and TDC can not rely on the main clock frequency completely, and the timing can be up to 10ps through the circuit delay chasing circuit. Therefore, the signal recording unit with time precision within 100ps is used for recording signals. The time of issue and the return time can meet the requirements of the synchronization accuracy of time at the ps level, and thus can be applied to fields such as scanning imaging systems where time precision is required.
  • the above-mentioned signal recording unit matched with the clock source and each terminal can realize the calibration signal (response signal) interaction through one line, and the two can also be bidirectionally communicated to realize signal interaction. If a line is used to realize the round-trip signal, since all the terminals are connected, the signal will be broadcasted, and the signal recording unit and the remaining terminals will receive it, so that the remaining terminals will not mistake the signal as the clock source.
  • the signal needs to be sent by the controller of the terminal immediately after the signal is received (the signal is preferably different from the calibration signal of the clock source). If the two signals are connected in two directions, the transmission and reception of the calibration signal are separated, Considering this kind of problem, it is easier to send and receive signals.
  • the signal measurement is based on a circuit signal (electric pulse hopping) to accurately acquire time delays and deviations of different terminals when passing through a fixed medium.
  • Signal transmission, the delay and deviation are more certain, in order to achieve the global clock accuracy of the ps level requirements, so between the clock source and the signal recording unit, between the signal recording unit and the terminal, each terminal is wired .
  • each terminal only needs to satisfy the final communication connection with the clock source via the signal recording unit, thereby realizing the setting of the global clock in the system, and each terminal can be configured.
  • the length of the connection line between the terminal and the clock source need not be considered, which solves the problem that the traditional method requires accurate design and implementation of all the connection lengths, and the signal recording unit with time precision within 100 ps is realized.
  • the determination of the absolute offset between the terminal and the clock source is especially suitable for occasions where the time accuracy is high.
  • the apparatus for providing a global clock in the system according to the present invention is used, although it is not necessary to consider how to set or connect between the terminals, it is not necessary to consider the problem of the length of the connection between the terminals and the clock source, but if between the terminals When the connection is too complicated, it is inconvenient in actual use.
  • the apparatus for providing a global clock in the system includes at least one clock source, at least two terminals, and a signal recording unit matched with the clock source, a signal recording unit and a clock source.
  • Pathway connection The terminals are sequentially connected in two directions to form a linear network.
  • a plurality of linear networks may be disposed, and the signal recording unit is bidirectionally connected to one terminal of each linear network.
  • a linear network is preferably provided, and the signal recording unit is bidirectionally connected with the terminal located at the head, between the clock source and the signal recording unit, and between the signal recording unit and the terminal located at the head.
  • the terminals are wired.
  • one node of the online network Connect all terminals in a line network, one node of the online network (the embodiment shown in Figure 3 is one end of the online network to ensure that the distance from each terminal to the clock source is different).
  • a high-precision signal recording unit the clock source first sends a calibration signal, and at the same time, the signal recording unit of the clock source starts timing T(0), and each terminal receives the calibration signal in turn because of the inconsistency of the distance from the clock source. After receiving the calibration signal, the terminal immediately responds to the reply or directly returns the calibration signal to the signal recording unit of the clock source.
  • the signal recording unit sequentially receives the response signals from the respective terminals, and sequentially records the time T ( n)
  • the value of (0)- ⁇ n)/2, ⁇ n is determined according to the application.
  • multiple terminals may have the same distance from the clock source. Therefore, if the number of response signals received by the signal recording unit is less than the terminal value (indicating at least two) The signals overlap, this probability is very low, because the signal recording unit can recognize two signals exceeding 10 ps), and the terminals can be measured in batches and acquired one by one.
  • the time control precision is high, and at the same time, the length of the clock connection line is not controlled, and any connection can reduce a large number of traces of the system, and all terminals can be serially connected through a set of wires.
  • the realization of the global clock in the number of terminals reaches 100 or 1000, can solve a lot of problems that make system assembly and maintenance become extremely difficult.
  • the terminal can be continuously added to the online network, and the clock connection with the upper level can be increased.
  • the hardware of the clock source can be easily and simply completed without changing the hardware of the clock source.
  • the apparatus for providing a global clock in a system includes at least one clock source, at least two terminals, and a signal recording unit matched with the clock source, and signal recording.
  • the unit is coupled to the clock source path, and each terminal is in two-way communication with the signal recording unit to communicate with the clock source via the signal recording unit.
  • a star network connection is still adopted between the clock source and each terminal, but a signal recording unit is added between the clock source and each terminal, and each terminal is bidirectionally connected to the signal recording unit.
  • Clock source and signal There is a wired connection between the recording units, the signal recording unit and each terminal.
  • the clock source first sends a calibration signal.
  • the signal recording unit starts timing the calibration signal is issued as T (0). Because each terminal is inconsistent from the clock source, it will receive the calibration signal in turn, and the terminal receives Immediately after the signal, the signal recovery unit that returns the calibration signal to the clock source is returned immediately. Similarly, due to the different distances, the signal recording unit sequentially receives the response signals from the respective terminals, and sequentially records the time T(n).
  • the speed close to the speed of light, thus, we get the absolute time difference between all terminals in the system and the clock source.
  • the time difference calculated above can be used as the correction coefficient to ensure that the timing systems of the respective terminals are completely synchronized.
  • the time synchronization accuracy is high relative to the prior art, and on the other hand, the length of the connection between each terminal and the signal recording unit can be The actual requirements are arbitrarily set, and the length of the clock connection line is not controlled, and the wiring is convenient and simple.

Abstract

一种提供系统内全局时钟的方法和装置，系统内终端之间通路连接，各终端分别最终通过信号记录单元与时钟源通信连接，时钟源向网络上发出一个标定信号，信号记录单元记录标定信号当前的发出时间T(0)，各终端由于相隔时钟源的距离不同，会依次收到该标定信号，并将信号返回，返回信号沿着网络依次先后返回到信号记录单元，信号记录单元再依次记录各个返回信号的时间T(n)，这样，信号记录单元就能测量各个终端与时钟源信号的延时，将此延时作为校正参数可保证终端处于完全一致的时间基准，且这样设置对各终端到时钟源的时钟连接线的长度不用控制，无需特别考虑时钟走线，避免了大量的连线带来系统组装、校正、维护、扩展的困难。

Description

一种提供系统内全局时钟的方法和装置 技术领域
本发明属于时间测试测量技术领域，涉及一种基准时间确定方法，尤其是全局时间的确定方法。
背景技术
全局时钟应用在多个领域，保证系统中各个部件有完全相同的时间基准，例如在核探测领域、在飞行时间应用领域，多个终端组成系统往往需要完全一致的时间基准来满足精准的时间测量。通过多个终端之间的时间戳通信来获取通信延时并校正的方法在通信领域中被广泛采用，但是这种同步方法仅局限在利用现成通信协议达到精度不高的全局时钟同步，如ms或者亚ms级别，这种方法的精度最终依赖于时钟的速度即翻转频率，不会达到比时钟周期更短的同步精度。所以传统方法只能如图1所示，是在系统中设置唯一的一个时钟源，然后将所有需要时钟的终端与时钟源连接，构建一个星状网络，并精确保证所有的连线(从时钟源到各终端)具有完全相等的长度，从而保证各个终端能获得完全一致的同步的时钟信号。这样在超大规模终端组成的复杂系统中需要特别考虑时钟走线，并且大量的连线带来系统组装、校正、维护、扩展的困难，例如采用传统方法如果需要新增一个终端，需要在时钟源处增加一个扇出，这必然需要改变已经确定的硬件，且由于在特定领域中，例如扫描成像系统，其内的多个(几个到几千个)探测器(即终端)均需要统一的时间基准来满足全局统一的时钟，且各个探测器需要皮秒(ps)级别的时间测量装置以使得整个仪器系统要求较高的时间分辨率，对时间的同步的精度要求在ps级别，所以对线长等长的要求需要在微米(um)级别，现有的全局时钟的设计无法达到该要求。
发明内容
本发明的目的在于公开了一种提供系统内全局时钟的方法和装置，所述方法和装置通过确定从时钟源到终端的延时，并将此延时作为校正参数保证所有终端处于完全一致的时间基 准，且由于采用高精度的信号记录单元的配合可完成从时钟源到终端的延时的精确测量，且对时钟源的翻转频率要求不高，使其可用于对同步精度要求高的场合，同时，本发明所述的一种提供系统内全局时钟的方法和装置对各终端到时钟源的时钟连接线的长度不用控制，无需特别考虑时钟走线，避免了大量的连线带来系统组装、校正、维护、扩展的困难。
为达到上述目的，本发明的解决方案是：
本发明公开了一种提供系统内全局时钟的方法，所述系统内包括至少两个终端，所述各终端之间通路连接，包括以下步骤：
(1)产生标定信号，所述标定信号被分发至系统内各终端处，记录所述标定信号的发出时间T(0)；
所述步骤(1)前还包括确定一作为基准的时钟源的步骤，由所述作为基准的时钟源产生标定信号。
优选的，所述时钟源为一时钟控制器或包括一时钟控制器以及接受时钟控制器控制的时钟发生器；
优选的，所述标定信号为所述时钟控制器直接发出的一个电脉冲形成或者所述时钟发生器接受所述时钟控制器驱动发出的一段时钟信号；
优选的，所述作为基准的时钟源为任意一各终端内部的本地时钟或外置的时钟源。
优选的，所述步骤(1)中，由一与作为基准的时钟源相配合的信号记录单元记录所述标定信号的发出时间T(0)；
进一步的，所述步骤(1)中，由所述与作为基准的时钟源相配合的信号记录单元将所述标定信号分发至系统内各终端处。
优选的，作为基准的时钟源以及与所述作为基准的时钟源相配合的信号记录单元属于其中一终端。
优选的，所述信号记录单元的最小时间测量刻度小于作为基准的时钟源的时钟周期的1/2；
优选的，所述信号记录单元的最小时间测量刻度在1ns以内；
(2)所述标定信号到达所述各终端，所述各终端分别返回信号，记录所述返回信号的到达时间T(n)，确定所述各终端的绝对偏移Delay(n)；
优选的，由一与作为基准的时钟源相配合的信号记录单元接收并记录所述返回信号的到达时间T(n)。
优选的，所述返回信号为所述各终端分别发出的应答信号或所述标定信号分别返回
优选的，(I)若所述应答信号返回，则Delay(n)＝(T(n)-T(0)-Δn)/2，其中Δn为各终端应答反应时间；
(II)若所述标定信号返回，则Delay(n)＝(T(n)-T(0))/2。
优选的，所述步骤(I)中，所述Δn为系统预设值；或所述Δn由各终端内的信号记录单元确定，所述各终端收到标定信号后，所述各终端内信号记录单元记录该时间为tn1，所述各终端分别发出应答信号后，所述各终端内信号记录单元记录该时间为tn2则所述Δn＝tn2-tn1。
(3)根据所述绝对偏移调整各终端处的时间以形成全局时钟。
优选的，所述步骤(3)中，经由与信号记录单元或者所述终端的处理器或者外置处理器确定所述各终端的绝对偏移，同时调整各终端处的时间以形成全局时钟。
同时，本发明还公开了一种提供系统内全局时钟的装置，包括至少一时钟源，至少两终端，所述各终端之间通路连接，其还包括一与所述时钟源相配合的信号记录单元，所述信号记录单元与所述时钟源通路连接、所述每一个终端均经由所述信号记录单元与所述时钟源通信以确定各终端到所述时钟源之间的时间绝对偏移。
优选的，所述终端之间依次通信连接以形成线状网络结构，且与所述时钟源相配合的信号记录单元与所述线状网络结构中的一终端之间通信连接。
进一步的，与所述时钟源相配合的信号记录单元和所述线状网络结构中位于端点处的一终端之间通信连接。
进一步的，所述终端之间、所述信号记录单元与所述终端之间为双向通信连接。
进一步的，所述信号记录单元与时钟源之间、所述信号记录单元与所述终端之间、所述终端之间为有线连接。
进一步的，所述各终端内分别设有信号记录单元以确定各终端的应答反应时间。
进一步的，至少设置一条所述线状网络。
优选的，所述每一个终端分别与所述信号记录单元之间通信连接以形成星状网络结构。
进一步的，所述每一个终端分别与所述信号记录单元之间双向通信连接。
进一步的，时钟源与所述信号记录单元之间、所述信号记录单元与所述各终端之间为有线连接。
进一步的，所述各终端内分别设有信号记录单元以确定各终端的应答反应时间。
所述信号记录单元的最小时间测量刻度小于作为基准的时钟源的时钟周期的1/2。
优选的，所述信号记录单元包括一控制器以及与所述控制器通信连接以接受所述控制器驱动的时间转换器，所述时间转换器的时间精度在1ns以内。
优选的，所述时间转换器为TDC或者TAC，所述TDC或者TAC的时间精度在100ps以内。
由于采用上述方案，本发明的有益效果是：
1、本发明所公开的一种提供系统内全局时钟的方法和装置，系统内终端之间通路连接，各终端与分别通过不同路径后最终通过信号记录单元与预先确定的时钟源通信连接，时钟源向网络上发出一个标定信号，信号记录单元记录标定信号当前的发出时间T(0)，挂在网络上的各终端由于相隔时钟源的距离不同，会依次收到该标定信号，并将信号返回(可为标定信号主动返回或者各终端应答后发送应答信号的被动返回)，返回信号沿着网络依次先后返回到信号记录单元，信号记录单元再依次记录各个返回信号的时间T(n)，这样，信号记录单元就能测量各个终端与时钟源信号的延时，在实际系统中，可以将此延时作为校正参数保证所有终端处于完全一致的时间基准。
2、通过高精度信号记录单元的加入，使得时间的同步精度提高。在时钟源处设置高精度的信号记录单元(信号记录单元的最小时间测量刻度小于作为基准的时钟源的时钟周期的1/2)，如时间数字转换器(TDC)或者时间模拟转换器(TAC)，由该时间数字转换器(TDC)或者时间模拟转换器(TAC)来确定信号的发送和返回时间，可精确确定各终端与时钟源之间的时间绝对偏移以形成全局时钟。以TDC为例，TDC能不完全依赖主时钟频率，通过电路延时追赶电路来计时，测量比时钟周期更短的时间长度，计时精度可以达到10ps。这样可以满足时间的同步精度在ps级别的要求，可应用于时间精度要求较高的场合。
3、对时钟连接线的长度不用控制，任意的连接，各终端之间网络可任意连接，只需要满足每个终端最终通过信号记录单元与时钟源通信连接，就能完成全局时钟的部署，解决传统方法需要精确所有连线长度的设计和实现困难。
4、扩展性增强，当采用线状拓扑结构的全局时钟装置时，可通过在线状网络的一端增加一终端和连线，不用改变时钟源的硬件，不用增加时钟源的扇出，即可方便简单的完成系统的扩展；当采用星状拓扑结构的全局时钟装置时，新增终端时虽然需要增加时钟源的扇出接口，但可以不用考虑并严格控制新增终端的时钟连接线与之前已经接入的终端保持完全一致。
5、可以减少系统大量走线，当采用线状拓扑结构的全局时钟装置时，通过一组连线串行连接所有终端，即可完成全局时钟的实现，在终端数量达到百级或者千级，可解决大量的连 线让系统组装和维护变得异常困难的问题。
附图说明
图1为传统的星状网络结构的全局时钟确定装置的结构示意图；
图2为本发明所示的一种提供系统内全局时钟方法的工作流程图；
图3为本发明所示的一种提供系统内全局时钟装置第一实施例的结构示意图；
图4为本发明所示的一种提供系统内全局时钟装置第二实施例的结构示意图。
具体实施方式
以下结合附图所示实施例对本发明作进一步的说明。
一种提供系统内全局时钟的方法，如图2所示，包括以下步骤：
首先，确定一作为基准的时钟源，由所述作为基准的时钟源产生标定信号。一个系统内可以有多个时钟源或者唯一确定的时钟源，当有多个时钟源时，则需要首先确定其中一时钟源作为基准，基准时钟源可任意选择，只需要满足该时钟源可通过网络传输到所有终端(即覆盖所有终端)，此外也可通过外置的一时钟源作为整个系统的基准时钟，上述的时钟源既可以单独为一时钟控制器，也可包括一时钟控制器以及接受时钟控制器控制的时钟发生器，可根据实际需要任意设置。
(1)产生标定信号，所述标定信号被分发至系统内各终端处，记录所述标定信号的发出时间T(0)。
图2所示实施例中，当作为基准的时钟源确定后，该时钟源产生标定信号，标定信号的具体形式是由时钟源决定的，本实施例中，标定信号可以由时钟控制器直接发出一个电脉冲产生，或者由控制时钟发出一段时钟信号形成，标定信号产生之后被分发至各终端处，当标定信号被分发后，记录下标定信号发出时间T(0)。
(2)上述标定信号经由网络到达所述各终端后，各终端处分别产生一返回信号，记录该回信号的到达时间T(n)，确定所述各终端的绝对偏移Delay(n)：
返回信号的形式可有多种，以下以返回信号为应答信号或者标定信号对本发明所示一种提供系统内全局时钟的方法的工作原理进行说明，应理解，若返回信号为其他形式时，采用本发明所示的方法也可实现系统内各终端全局时钟的形成。
当标定信号到达所述各终端后，各终端既可以通过直接电路连接返回信号链路，将标定 信号返回，也可以通过控制器(如FPGA这种支持异步响应的控制器)接收到标定信号，则立即(不依赖与控制器的主时钟条件下)发出应答信号，当发出返回信号后，然后在记录下返回信号的到达时间T(n)，从而所述各终端到作为基准时钟源的绝对偏移Delay(n)。
上述标定信号发出时间T(0)以及返回信号的到达时间T(n)由同一计时元件接收并记录，从而使得二者具有同一数量级的精度，图2所示实施例中，均通过与时钟源相配合的信号记录单元接受并确定具体时间，其中信号记录单元包括一控制器以及接受该控制驱动的时间转换器，由时间转换器接受该控制器的驱动记录T(0)和T(n)，且步骤(1)中，标定信号的分发既可由时钟源控制直接分发至各终端处，也可由与上述作为基准时钟源相配合的信号记录单元分发至各终端处。
(I)若终端通过应答方式将应答信号返回时，与作为基准时钟源相配合的信号记录单元记录标定信号的到达时间T(n)，由于终端做出应答需要一定的时间，故确定所述各终端的绝对偏移Delay(n)＝(T(n)-T(0)-Δn)/2，其中Δn为各终端应答反应时间，由于应答信号可以是一个电脉冲，若本发明所示的提供系统内全局时钟的方法用于对时间精度要求不高的场合时，Δn为预设值，可预先通过实验和计算确定，同时可以计算终端与时钟源的连线长度为L(n)＝Delay(n)*C，C为信号在线路中的传输速度，接近光速。
(II)若通过标定信号形式返回时，与作为基准时钟源相配合的信号记录单元记录标定信号的到达时间T(n)，则所述各终端的绝对偏移Delay(n)＝(T(n)-T(0))/2，同时可以计算终端与时钟源的连线长度为L(n)＝Delay(n)*C，C为信号在线路中的传输速度，接近光速。
由此，我们获得系统中所有终端与时钟源的绝对偏移。
(3)根据所述绝对偏移调整各终端处的时间以形成全局时钟。当需要系统内所有终端有完全统一的时间基准时，将上述计算的时间差(绝对偏移)作为校正系数即能保证各个终端的计时系统完全同步。步骤(3)中，可经由信号记录单元或者各终端的处理器或外置处理器根据各终端的绝对偏移来发送指令以调整各终端处的时间以形成全局时钟。
通过图2所示实施例的步骤，可方便的实现系统内所有终端处于完全一致的时间基准，无需考虑终端至时钟源走线设置的问题。在图2所示实施例的基础上，本发明进一步的公开了一种提供系统内全局时钟的方法，可提高时间同步的精度以用于对于时间精度要求较高的场合。
一种提供系统内全局时钟的方法，包括以下步骤：
首先，确定一作为基准的时钟源，由所述作为基准的时钟源产生标定信号。一个系统内 可以有多个时钟源或者唯一确定的时钟源，当有多个时钟源时，则需要首先确定其中一时钟源作为基准，基准时钟源可任意选择，只需要满足该时钟源可通过网络传输到所有终端(即覆盖所有终端)，此外也可通过外置的一时钟源作为整个系统的基准时钟，上述的时钟源既可以单独为一时钟控制器，也可包括一时钟控制器以及接受时钟控制器控制的时钟发生器，可根据实际需要任意设置。
(1)产生标定信号，所述标定信号被分发至系统内各终端处，记录所述标定信号的发出时间T(0)。
当作为基准的时钟源确定后，该时钟源产生标定信号，标定信号的具体形式是由时钟源决定的，本实施例中，标定信号可以由时钟控制器直接发出一个电脉冲产生，或者由控制时钟发出一段时钟信号形成，标定信号产生之后被分发至各终端处，此处标定信号既可由时钟源控制直接分发至各终端处，也可由与上述作为基准时钟源相配合的信号记录单元分发至各终端处。
当标定信号被分发后，与上述作为基准时钟源相配合的信号记录单元记录下标定信号发出时间T(0)，其中与时钟源相配合的信号记录单元最小时间测量刻度小于作为基准的时钟源的时钟周期的1/2设置，这样信号记录单元可以精确测量小于一个时钟周期长度的时间：在高同步要求的全局时钟中，全局时钟频率一股在50MHz以上，时钟周期在20ns以内，甚至频率达到200MHz以上，时钟周期在2ns以内。但是全局时钟在线路上的延时也需要被精确测量，而这种延时随线路长度不同而不同，不会与系统全局时钟保持相同相位，为了精确测量这种延时，需要高精度的时钟测量装置，而不是依赖全局时钟，通过最小测量刻度小于基准时钟的时钟周期的1/2的信号测量装置，能实现诸如线路延时或者相位偏差等更高精度的时间测量。
作为一优选的方案，其中信号记录单元包括一控制器以及接受该控制驱动的时间转换器，该时间转换器的最小时间测量刻度在1ns以内从而可精确的记录标定信号发出时间T(0)以及返回信号的返回时间T(n)，从而可用于对于时间精度要求在ps级别的场合。
进一步的，该时间转换器可为TDC(时间数字转换器)或者TAC(时间模拟转换器)，TDC或者TAC的时间精度在100ps以内。以TDC为例，其接受控制器控制读取TDC的计数值(记录的时间值)，由于TDC是异步计时，也就是对时钟的信号是即时触发，一股来说是电脉冲的跳变沿触发，故不存在通信开销，且TDC能不完全依赖主时钟频率，通过电路延时追赶电路来计时，计时精度可以达到10ps，故采用时间精度在100ps以内信号记录单元用于记录信 号的发出时间与返回时间，可以满足时间的同步精度在ps级别的要求，从而应用于如扫描成像系统等对于时间精度要求较高的领域中。
此外，从精简结构的角度出发，上述作为基准的时钟源以及与所述作为基准的时钟源相配合的信号记录单元可属于系统内其中一终端，且时钟源与信号记录单元可共用一处理器。
(2)上述标定信号经由网络到达所述各终端后，各终端处分别产生一返回信号，记录该回信号的到达时间T(n)，确定所述各终端的绝对偏移Delay(n)：
返回信号的形式可有多种，以下以返回信号为应答信号或者标定信号对本发明所示一种提供系统内全局时钟的方法的工作原理进行说明，应理解，若返回信号为其他形式时，采用本发明所示的方法也可实现系统内各终端全局时钟的形成。
当标定信号到达所述各终端后，各终端既可以通过直接电路连接返回信号链路，将标定信号返回，也可以通过控制器(如FPGA这种支持异步响应的控制器)接收到标定信号，则立即(不依赖与控制器的主时钟条件下)发出应答信号，当发出返回信号后，然后在通过与时钟源相配合的信号记录单元接受并确定返回信号的到达时间T(n)。
(I)若终端通过应答方式将应答信号返回时，与作为基准时钟源相配合的信号记录单元记录标定信号的到达时间T(n)，由于终端做出应答需要一定的时间，故确定所述各终端的绝对偏移Delay(n)＝(T(n)-T(0)-Δn)/2，其中Δn为各终端应答反应时间，为了保证Δn值具有与T(0)、T(n)同一数量级的精度，各终端内也分别内置一信号记录单元，该信号记录单元经由网络与各终端以及时钟源、与时钟源相配合的信号记录单元通信连接，Δn由各终端内的信号记录单元确定，当各终端收到标定信号后，各终端内信号记录单元记录该时间为tn1，当各终端分别发出应答信号后，各终端内信号记录单元记录该时间为tn2则所述Δn＝tn2-tn1，同时可以计算终端与时钟源的连线长度为L(n)＝Delay(n)*C，C为信号在线路中的传输速度，接近光速。
(II)若通过标定信号形式返回时，与作为基准时钟源相配合的信号记录单元记录标定信号的到达时间T(n)，则所述各终端的绝对偏移Delay(n)＝(T(n)-T(0))/2，同时可以计算终端与时钟源的连线长度为L(n)＝Delay(n)*C，C为信号在线路中的传输速度，接近光速。
由此，我们获得系统中所有终端与时钟源的绝对偏移。
(3)根据所述绝对偏移调整各终端处的时间以形成全局时钟。当需要系统内所有终端有完全统一的时间基准时，将上述计算的时间差(绝对偏移)作为校正系数即能保证各个终端的计时系统完全同步。步骤(3)中，可经由信号记录单元或者各终端或外置处理器根据各终 端处的绝对偏移来发送指令以调整各终端处的时间以形成全局时钟。
通过上述所示的一种提供系统内全局时钟的方法，采用一最小时间测量刻度小于作为基准的时钟源的时钟周期的1/2的信号记录单元确定标定信号的发出时间T(0)以及返回信号的到达时间T(n)，可实现系统内全局时钟的同步精度，而且无需考虑布线问题。
除了以上明确提出的，应理解，结合图2和图3所示的实施例方法，所示的步骤的顺序在其他示例性实施例中可按不同顺序发生。同样，图2和图3所示实施例中，某些步骤可进行省略或者由其他公知的技术完成，此处不一一列举。
对应上述提供系统内全局时钟的方法，本发明还公开了一种用于提供系统内全局时钟的装置，包括至少一时钟源，至少两终端以及一与时钟源相配合的信号记录单元，终端之间通路连接、信号记录单元与时钟源通信连接、各终端分别经由信号记录单元与时钟源通信以确定各终端到时钟源的绝对偏移。
各终端分别通过网络最终经由信号记录单元与时钟源通信连接，初始化时，时钟源向网络上发出一个标定信号，信号记录单元记录标定信号当前的发送时间T(0)，挂在网络上的终端由于相隔时钟源的距离不同，会依次收到该标定信号，并将信号返回(可主动或者被动返回)，返回的信号(即标定信号或者应答信号)沿着网络依次先后返回到信号记录单元，信号记录单元再依次记录各个返回信号的时间T(n)，这样，信号记录单元就能测量各个终端与时钟源信号的精确延时(绝对偏移)，在实际系统中，可以将此延时作为校正参数保证所有终端处于完全一致的时间基准。
信号记录单元可为一常用的计时元件即可有效的实现系统内各终端全局时钟，当本发明所示的装置应用于对时间精度要求较高的场合时，则信号记录单元的最小时间测量刻度小于作为基准的时钟源的时钟周期的1/2设置。
作为一优选的方案，其中信号记录单元包括一控制器以及接受该控制驱动的时间转换器，该时间转换器的最小时间测量刻度在1ns以内从而可精确的记录标定信号发出时间T(0)以及返回信号的返回时间T(n)，从而可用于对于时间精度要求在ps级别的场合。
进一步的，该时间转换器可为TDC(时间数字转换器)或者TAC(时间模拟转换器)，TDC或者TAC的时间精度在100ps以内。以TDC为例，其接受控制器控制读取TDC的计数值(记录的时间值)，由于TDC是异步计时，也就是对时钟的信号是即时触发，一股来说是电脉冲的跳变沿触发，故不存在通信开销，且TDC能不完全依赖主时钟频率，通过电路延时追赶电路来计时，计时精度可以达到10ps，故采用时间精度在100ps以内信号记录单元用于记录信 号的发出时间与返回时间，可以满足时间的同步精度在ps级别的要求，从而应用于如扫描成像系统等对于时间精度要求较高的领域中。
当终端采取应答方式返回信号时，若用于一股的通讯领域时，各终端内预设Δn作为应答时间，若为了确保时间精度，则各终端内分别设置了一信号记录单元，各终端内部的信号记录单元也分别包括一控制器以及接受该控制驱动的高精度时间转换器，当位于网络上的各终端收到标定信号后，各终端内信号记录单元记录该时间为tn1，当各终端分别发出应答信号后，各终端内信号记录单元记录该时间为tn2则所述Δn＝tn2-tn1，通过此种方法确定的Δn值具有与T(0)、T(n)同一数量级的精度。
上述与时钟源相配合的信号记录单元和各终端之间既可以通过一条线路实现标定信号(应答信号)交互，二者之间也可双向通信连接以实现信号交互。若采用一条线路实现信号往返时，由于所有的终端都是连接的，信号会被广播发出，信号记录单元和其余的终端都会收到，所以为让其余的终端不会误认为该信号为时钟源的信号，需要终端的控制器接收到信号后再立即发出信号(信号最好与时钟源的标定信号不一样)，若二者双向通信连接时，标定信号的发送和接受区分开来，则无需考虑此种问题，信号的发送与接受更为容易。
此外，考虑到本发明所示的用于提供系统内全局时钟的装置，其信号测量是基于电路信号(电脉冲的跳变)来精确获取不同终端的时间延时和偏差，当通过固定媒介的信号传输，其延时和偏差更为确定，为达到全局时钟的精度为ps级别的要求，故时钟源与信号记录单元之间，信号记录单元与终端之间，各终端之间均为有线连接。
通过上述分析可知，采用本发明所示的用于提供系统内全局时钟的装置，各终端只需满足最终经由信号记录单元与时钟源通信连接，即可实现系统内全局时钟的设置，各终端之间如何连接、终端与时钟源之间连接线的长度均无需考虑，解决了传统方法需要精确所有连线长度的设计和实现困难的问题，且由于采用时间精度在100ps以内的信号记录单元实现各终端与时钟源之间绝对偏移的确定，尤其适合对时间精度要求较高的场合。
以下结合具体实施例对本发明所示的用于提供系统内全局时钟的装置进行说明。
由于采用本发明所示的用于提供系统内全局时钟的装置，虽然无需考虑各终端之间如何设置或者连接，也无需考虑各终端到时钟源之间连线长度的问题，但是若终端之间连接过于繁杂时，在实际使用还是有所不便。
故第一实施例中，如图3所示，用于提供系统内全局时钟的装置包括至少一时钟源，至少两终端以及一与上述时钟源相配合的信号记录单元，信号记录单元与时钟源通路连接、各 终端之间依次双向通信连接以形成线状网络，一个系统内，线状网络可设置多条，信号记录单元与每条线状网络中的一个终端双向通信连接。图3所示实施例中，优选设置一条线性网络，且信号记录单元与位于首部的终端之间双向通信连接，时钟源与信号记录单元之间，信号记录单元与位于首部的终端之间，各终端之间均为有线连接。
通过线状网络串联所有终端，在线状网络的一个节点(图3所示实施例为在线状网络的一端以尽量保证各个终端到时钟源的距离都不一样。)设置唯一的时钟源，同时设置一个高精度的信号记录单元，时钟源首先发出标定信号，同时，时钟源的信号记录单元开始计时T(0)，各个终端由于其离时钟源的距离不一致，会先后依次接受到标定信号，各终端收到标定信号后，立即应答回复或者直接电路连接返回标定信号给时钟源的信号记录单元，同样由于距离不同，信号记录单元会先后依次接收到来自各个终端的应答信号，依次记录时间T(n)，当有n个终端时，终端与时钟源的时间延时为：Delay(n)＝(T(n)-T(0))/2或Delay(n)(T(n)-T(0)-Δn)/2，Δn的数值根据应用场合不同采用前述步骤确定；同时可以计算终端与时钟源的连线长度为L(n)＝Delay(n)*C，C为信号在线路中的传输速度，接近光速，由此，我们获得系统中所有终端与时钟源的绝对时间差。当需要系统所有终端有完全统一的时间基准时，将上述计算的时间差作为校正系数即能保证各个终端的计时系统完全同步。
考虑到若系统内设置多条线状网络，可能出现多个终端到时钟源距离相同的情况，故在此过程中，如果信号记录单元收到的应答信号次数少于终端值(说明至少有两个信号有重叠，这个概率非常低，因为信号记录单元能识别超过10ps的两个信号)，可以对终端分批进行测量，逐一获取。
这样设置，由于采用信号记录单元，时间控制精度高，同时，对时钟连接线的长度不用控制，任意的连接，可以减少系统大量走线，通过一组连线串行连接所有终端，即可完成全局时钟的实现，在终端数量达到百级或者千级，可解决大量的连线让系统组装和维护变得异常困难的问题。此外，如果终端的数量增加，可以直接在线状网络上继续增加终端，并增加与上一级的时钟连线即可，不用改变时钟源的硬件，即可方便简单的完成系统的扩展。
第二实施例中，如图4所示，本发明所示的用于提供系统内全局时钟的装置包括至少一时钟源，至少两终端以及一与上述时钟源相配合的信号记录单元，信号记录单元与时钟源通路连接，各终端分别与信号记录单元双向通信连接以经由信号记录单元与时钟源通信。本实施例中，时钟源和各终端之间仍然采取星状网络连接，但时钟源和各终端之间增设信号记录单元，且各终端分别与信号记录单元双向通信连接，本实施例中，优选的，时钟源与信号记 录单元之间、信号记录单元与各终端之间为有线连接。
工作时，时钟源首先发出标定信号，同时，信号记录单元开始计时标定信号的发出时间为T(0)，各个终端由于其离时钟源的距离不一致，会先后依次接受到标定信号，终端收到信号后，立即回复或者直接电路连接返回标定信号给时钟源的信号记录单元，同样由于距离不同，信号记录单元会先后依次接收到来自各个终端的应答信号，依次记录时间T(n)。当有n个终端时，则各终端与时钟源的时间延时为：Delay(n)＝(T(n)-T(0))/2或Delay(n)＝(T(n)-T(0)-Δn)/2，Δn的数值根据应用场合不同采用前述步骤确定；同时计算终端与时钟源的连线长度为L(n)＝Delay(n)*C，C为信号在线路中的速度，接近光速，由此，我们获得系统中所有终端与时钟源的绝对时间差。当需要系统所有终端有完全统一的时间基准时，将上述计算的时间差作为校正系数即能保证各个终端的计时系统完全同步。
同前所述，考虑到采用星状网络时，可能出现多个终端到时钟源距离相同的情况，故在此过程中，如果信号记录单元收到的应答信号次数少于终端值(说明至少有两个信号有重叠，这个概率非常低，因为信号记录单元能识别超过10ps的两个信号)，可以对终端分批进行测量，逐一获取。
通过第二实施例所示的用于提供系统内全局时钟的装置，一方面，相对现有技术而已，时间同步精度高，另一方面，各终端与信号记录单元之间连线的长度可根据实际需求任意设置，对时钟连接线的长度不用控制，布线方便简单。
上述的对实施例的描述是为便于该技术领域的普通技术人员能理解和使用本发明。熟悉本领域技术的人员显然可以容易地对这些实施例做出各种修改，并把在此说明的一股原理应用到其他实施例中而不必经过创造性的劳动。因此，本发明不限于上述实施例，本领域技术人员根据本发明的揭示，不脱离本发明范畴所做出的改进和修改都应该在本发明的保护范围之内。

Claims (10)

  1. 一种提供系统内全局时钟的方法，所述系统内包括至少两个终端，所述各终端之间通路连接，其特征在于：包括以下步骤：
    (1)产生标定信号，所述标定信号被分发至系统内各终端处，记录所述标定信号的发出时间T(0)；
    (2)所述标定信号到达所述各终端，所述各终端处分别产生一返回信号，接收所述返回信号并所述记录所述返回信号的到达时间T(n)，确定所述各终端的绝对偏移Delay(n)；
    (3)根据所述绝对偏移调整各终端处的时间以形成全局时钟。
  2. 根据权利要求1所述的提供系统内全局时钟的方法，其特征在于：所述步骤(1)前还包括确定一作为基准的时钟源的步骤，所述作为基准的时钟源覆盖所述的全部终端；
    优选的，所述时钟源为一时钟控制器或包括一时钟控制器以及接受时钟控制器控制的时钟发生器；
    优选的，所述标定信号为所述时钟控制器直接发出的一个电脉冲形成或者所述时钟发生器接受所述时钟控制器驱动发出的一段时钟信号；
    优选的，所述步骤(2)中，所述返回信号为所述各终端分别发出的应答信号或所述标定信号分别返回；
    优选的，所述步骤(3)中，记录应答信号或所述标定信号到达时间T(n)，确定所述各终端的绝对偏移Delay(n)：
    (I)若为所述应答信号返回，则Delay(n)＝(T(n)-T(0)-Δn)/2，其中Δn为各终端应答反应时间；
    (II)若为所述标定信号返回，则Delay(n)＝(T(n)-T(0))/2。
  3. 根据权利要求1或2所述的提供系统内全局时钟的方法，其特征在于：所述标定信号发出时间T(0)以及所述返回信号到达时间T(n)的接收和记录由一与作为基准的时钟源相配合的信号记录单元完成；
    优选的，所述步骤(1)中，由所述与作为基准的时钟源相配合的信号记录单元将所述标定信号分发至系统内各终端处；
    优选的，作为基准的时钟源以及与所述与作为基准的时钟源相配合的信号记录单元属于系统内其中一终端；
    优选的，所述信号记录单元的最小时间测量刻度小于作为基准的时钟源的时钟周期的 1/2；
    优选的，所述信号记录单元的最小时间测量刻度在1ns以内；
    优选的，所述信号记录单元的最小时间测量刻度在100ps以内；
    优选的，所述步骤(I)中，所述Δn为系统预设值；或所述Δn由各终端内的信号记录单元确定，所述各终端收到标定信号后，所述各终端内信号记录单元记录该时间为tn1，所述各终端分别发出应答信号后，所述各终端内信号记录单元记录该时间为tn2则所述Δn＝tn2-tn1；
    优选的，所述步骤(3)中，经由与信号记录单元或者所述终端的处理器或者外置处理器确定所述各终端的绝对偏移，同时调整各终端处的时间以形成全局时钟。
  4. 一种用于实现权利要求1至3任一项所述提供系统内全局时钟方法的装置，包括一作为基准的时钟源，至少两终端，所述各终端之间通路连接，其特征在于：还包括一与所述时钟源相配合的信号记录单元，所述与时钟源相配合的信号记录单元与所述时钟源通路连接、所述每一个终端均经由所述与时钟源相配合的信号记录单元与所述时钟源通信以确定各终端到所述时钟源之间的时间绝对偏移。
  5. 根据权利要求4所述的提供系统内全局时钟的装置，其特征在于：所述与时钟源相配合的信号记录单元和所述终端之间为双向通信连接；
    优选的，所述与时钟源相配合的信号记录单元与时钟源之间、所述与时钟源相配合的信号记录单元与所述终端之间、所述终端之间为有线连接；
    优选的，所述各终端内分别设有信号记录单元以确定各终端的应答反应时间。
  6. 根据权利要求4或5所述的提供系统内全局时钟的装置，其特征在于：所述终端之间依次通信连接以形成线状网络结构，且至少设置一条线状网络结构，所述与时钟源相配合的信号记录单元与所述每个线状网络结构中的一终端之间通信连接。
  7. 根据权利要求6所述的提供系统内全局时钟的装置，其特征在于：所述与时钟源相配合的信号记录单元和所述每一个线状网络结构中位于端点处的一终端之间通信连接；
    优选的，所述终端之间为双向通信连接；
    优选的，设置一条所述线状网络。
  8. 根据权利要求4或5所述的提供系统内全局时钟的装置，其特征在于：所述每一个终端分别直接和所述与时钟源相配合的信号记录单元之间通信连接以形成星状网络结构。
  9. 根据权利要求4或5所述的提供系统内全局时钟的装置，其特征在于：所述信号记录单元的最小时间测量刻度小于作为基准的时钟源的时钟周期的1/2；
    优选的，所述信号记录单元包括一控制器以及与所述控制器通信连接以接受所述控制器驱动的时间转换器，所述时间转换器的时间精度在1ns以内；
    优选的，所述时间转换器为TDC或者TAC，所述TDC或者TAC的时间精度在100ps以内。
  10. 根据权利要求4或5所述的提供系统内全局时钟的装置，其特征在于：所述时钟源为一时钟控制器或包括一时钟控制器以及接受时钟控制器控制的时钟发生器。
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