WO2016070509A1 - Low-temperature polycrystalline silicon semiconductor thin-film transistor-based goa circuit - Google Patents

Low-temperature polycrystalline silicon semiconductor thin-film transistor-based goa circuit Download PDF

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WO2016070509A1
WO2016070509A1 PCT/CN2015/072354 CN2015072354W WO2016070509A1 WO 2016070509 A1 WO2016070509 A1 WO 2016070509A1 CN 2015072354 W CN2015072354 W CN 2015072354W WO 2016070509 A1 WO2016070509 A1 WO 2016070509A1
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transistor
electrically connected
drain
node
gate
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PCT/CN2015/072354
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French (fr)
Chinese (zh)
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肖军城
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深圳市华星光电技术有限公司
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Priority to US14/422,691 priority Critical patent/US9530367B2/en
Priority to JP2017519240A priority patent/JP6317528B2/en
Priority to GB1703516.3A priority patent/GB2546647B/en
Priority to KR1020177007057A priority patent/KR101937062B1/en
Publication of WO2016070509A1 publication Critical patent/WO2016070509A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor.
  • GOA Gate Drive On Array
  • TFT thin film transistor
  • Array liquid crystal display array
  • the GOA circuit is mainly composed of a pull-up part, a pull-up control part, a transfer part, a pull-down part, and a pull-down sustain circuit part (
  • the pull-down holding part and the boost part responsible for the potential rise are generally composed of a bootstrap capacitor.
  • the pull-up portion is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control part is mainly responsible for controlling the opening of the pull-up part, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down portion is mainly responsible for quickly pulling the scan signal (that is, the potential of the gate of the thin film transistor) to a low level after outputting the scan signal.
  • the pull-down sustain circuit portion is mainly responsible for keeping the scan signal and the signal of the pull-up portion in a closed state (ie, a set negative potential).
  • the rising portion is mainly responsible for the secondary rise of the potential of the pull-up portion to ensure the normal output of the pull-up portion.
  • LTPS-TFT liquid crystal displays have attracted more and more attention.
  • LTPS-TFT liquid crystal displays have high resolution, fast response, high brightness and high opening. Rate and other advantages. Since the low-temperature polysilicon has an order of arrangement of amorphous silicon (a-Si), the low-temperature polysilicon semiconductor itself has an ultra-high electron mobility, which is 100 times higher than that of the amorphous silicon semiconductor, and the gate driver can be fabricated by using GOA technology. On the thin film transistor array substrate, the goal of system integration, space saving and cost of driving the IC are achieved.
  • a-Si amorphous silicon
  • the threshold voltage of a conventional amorphous silicon semiconductor thin film transistor is generally greater than 0 V, and the voltage of the subthreshold region is relatively large with respect to the current, but the threshold voltage of the low temperature polysilicon semiconductor thin film transistor is low (generally about It is about 0V), and the swing of the subthreshold region is small, while the GOA circuit is in the off state, many components operate with threshold voltage.
  • the voltage is close to or even higher than the threshold voltage.
  • the object of the present invention is to provide a GOA circuit based on a low-temperature polysilicon semiconductor thin film transistor, which solves the influence of the low-temperature polysilicon semiconductor thin film transistor's own characteristics on the GOA driving circuit, especially the GOA functionality caused by the leakage problem;
  • the problem that the second node potential cannot be at a higher potential during the non-active period of the pull-down sustain circuit portion.
  • the present invention provides a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor, comprising a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit includes a pull-up control portion and a pull-up a portion, a first pull-down portion, and a pull-down sustain circuit portion;
  • the pull-up control portion includes a first transistor, and a gate and a source thereof are electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the drain is electrically connected to the One node
  • the pull-up portion includes a second transistor having a gate electrically connected to the first node, a source electrically connected to the first clock driving signal, and a drain electrically connected to the output terminal;
  • the pull-down maintaining circuit is electrically connected to the first node, the output end, the constant current constant high potential, and the first, second, and third DC constant voltage low potentials;
  • Potential reverse design including:
  • the gate and the source of the third transistor are electrically connected to a DC constant voltage high potential, and the drain is electrically connected to the source of the fifth transistor;
  • the gate of the fourth transistor is electrically connected to the drain of the third transistor, the source is electrically connected to the DC constant voltage high potential, and the drain is electrically connected to the second node;
  • the gate of the fifth transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the drain of the third transistor The drain is electrically connected to the first DC constant voltage low potential;
  • the gate of the sixth transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the second node and has a drain Electricity Connected to the gate of the eighth transistor;
  • the gate of the seventh transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the second node and has a drain Electrically connected to the source of the eighth transistor;
  • An eighth transistor the gate of the eighth transistor is electrically connected to the drain of the sixteenth transistor, the source is electrically connected to the drain of the seventh transistor, and the drain is electrically connected to the third DC constant voltage low potential ;
  • the gate of the ninth transistor is electrically connected to the drain of the sixteenth transistor, the source is electrically connected to the gate of the tenth transistor, and the drain is electrically connected to the third DC constant voltage low potential ;
  • the gate of the tenth transistor is electrically connected to the source of the ninth transistor, the source is electrically connected to the DC constant voltage high potential, and the drain is electrically connected to the drain of the seventh transistor;
  • An eleventh transistor, the gate and the source of the eleventh transistor are electrically connected to a DC constant voltage high potential, and the drain is electrically connected to the source of the ninth transistor;
  • the gate of the twelfth transistor is electrically connected to the second node, the source is electrically connected to the first node, and the drain is electrically connected to the second DC constant voltage low potential;
  • the gate of the thirteenth transistor is electrically connected to the second node, the source is electrically connected to the output end, and the drain is electrically connected to the first DC constant voltage low potential;
  • the gate of the fifteenth transistor is electrically connected to the output end, the source is electrically connected to the gate of the fourth transistor, and the drain is electrically connected to the first DC constant voltage low potential;
  • the gate of the sixteenth transistor is electrically connected to the output end, the source is electrically connected to the second node, and the drain is electrically connected to the gate of the eighth transistor;
  • the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor provide a positive high potential for controlling opening of the twelfth transistor and the thirteenth transistor;
  • the eighth transistor, the ninth transistor The transistor constitutes a reverse bootstrap of a negative potential during operation for providing a lower potential to the second node during operation; providing a suitable high potential to the second node during the inactive period using the DC constant voltage high potential, such that the first The node and the output maintain a low potential;
  • the first pull-down portion is electrically connected to the first node, the second clock driving signal, and the second DC constant voltage low potential, and the first pull-down portion pulls down the first node according to the second clock driving signal a potential to the second DC constant voltage low potential;
  • the first pull-down portion includes a fourteenth transistor, the gate of the fourteenth transistor is electrically connected to the second clock driving signal, the source is electrically connected to the first node, and the drain is electrically connected to the first Two DC constant voltage low potential;
  • the fourth transistor, the seventh transistor, and the eighth transistor are connected in series.
  • the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor further includes a rising portion electrically connected between the first node and the output terminal for raising the potential of the first node.
  • the rising portion includes a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the output end.
  • the waveform duty ratio of the first clock driving signal and the second clock driving signal is close to 50/50; during the high potential of the second clock driving signal, the fourteenth transistor pulls down the potential of the first node to the first Two DC constant voltage low potential.
  • the gate and the source of the first transistor are electrically connected to the start signal end of the circuit, and the gates of the fifth, sixth, and seventh transistors are electrically connected to the circuit.
  • the start signal end In the first-stage connection relationship of the GOA circuit, the gate and the source of the first transistor are electrically connected to the start signal end of the circuit, and the gates of the fifth, sixth, and seventh transistors are electrically connected to the circuit. The start signal end.
  • the pull-down sustain circuit portion is controlled by the output terminal and the output of the upper N-1th stage GOA unit of the Nth stage GOA unit.
  • the GOA circuit uses the output signal of the output end as a signal for transmitting the upper and lower stages.
  • the invention has the beneficial effects that the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor provided by the invention adopts the high and low potential reverse push design in the pull-down sustaining circuit portion, and sets the first, second and third DC constant voltage low potentials which are sequentially lowered.
  • the constant current and high potential of the constant current can solve the influence of the low-temperature polysilicon semiconductor thin film transistor's own characteristics on the GOA driving circuit, especially the GOA functionality caused by the leakage problem; and solve the current GOA based on the low temperature polysilicon semiconductor thin film transistor.
  • the problem that the second node potential cannot be at a higher potential during the non-active period of the pull-down sustain circuit portion in the circuit effectively maintains the low potential of the first node and the output terminal.
  • FIG. 1 is a circuit diagram of a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor of the present invention
  • FIG. 2 is a circuit diagram showing a first-stage connection relationship of a GOA circuit based on a low-temperature polysilicon semiconductor thin film transistor of the present invention
  • FIG. 3 is a waveform diagram of waveform setting and key node output of a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor of the present invention.
  • the present invention provides a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor.
  • the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor includes: a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit includes a pull-up control portion 100 and a pull-up portion 200. a first pull-down portion 400, and a pull-down sustain circuit portion 500; and a rising portion 300.
  • the pull-up control portion 100 includes a first transistor T1 whose gate and source are electrically connected to the output terminal G(N-1) of the upper N-1th GOA unit of the Nth stage GOA unit.
  • the drain is electrically connected to the first node Q(N).
  • the pull-up portion 200 includes a second transistor T2 whose gate is electrically connected to the first node Q(N), the source is electrically connected to the first clock driving signal CKN, and the drain is electrically connected to the output terminal G ( N).
  • the rising portion 300 includes a capacitor Cb. One end of the capacitor Cb is electrically connected to the first node Q(N), and the other end is electrically connected to the output terminal G(N).
  • the pull-down maintaining circuit portion 500 is electrically connected to the first node Q(N), the output terminal G(N-1) of the upper-stage N-1th GOA unit of the Nth-stage GOA unit, and the output. Terminal G(N), constant current constant voltage high potential H, and first, second, and third DC constant voltage low potentials VSS1, VSS2, VSS3.
  • the pull-down maintaining circuit portion 500 includes: a third transistor T3, the gate and the source of the third transistor T3 are electrically connected to the DC constant voltage high potential H, and the drain is electrically connected to the fifth transistor a fourth transistor T4, the gate of the fourth transistor T4 is electrically connected to the drain of the third transistor T3, the source is electrically connected to the DC constant voltage high potential H, and the drain is electrically connected to the drain a second node P(N); a fifth transistor T5, the gate of the fifth transistor T5 is electrically connected to an output terminal G of the upper N-1th GOA unit of the Nth stage GOA unit -1), the source is electrically connected to the drain of the third transistor T3, the drain is electrically connected to the first DC constant voltage low potential VSS1; the sixth transistor T6, the gate electrical property of the sixth transistor T6 Connected to the output terminal G(N-1) of the upper N-1th GOA unit of the Nth stage GOA unit, the source is electrically connected to the second node P(N), and the drain is
  • the drain of the sixteen transistor T6, the source is electrically connected to the seventh crystal
  • the drain of the transistor T7 is electrically connected to the third DC constant voltage low potential VSS3;
  • the ninth transistor T9, the gate of the ninth transistor T9 is electrically connected to the drain of the sixteenth transistor T6, the source Electrically connected to the gate of the tenth transistor T10, the drain is electrically connected to the third DC constant voltage low potential VSS3;
  • the tenth transistor T10, the gate of the tenth transistor T10 is electrically connected to the ninth transistor T9 a source, a source electrically connected to the DC constant voltage high potential H, a drain electrically connected to the drain of the seventh transistor T7;
  • an eleventh transistor T11, the gate and the source of the eleventh transistor T11 Electrically connected to the DC constant voltage high potential H, the drain is electrically connected to the source of the ninth transistor T9;
  • the twelfth transistor T12, the gate of the twelfth transistor T12 is electrically connected to the second no
  • VSS1 a fifteenth transistor T15, the gate of the fifteenth transistor T15 is electrically connected to the output terminal G(N), the source is electrically connected to the gate of the fourth transistor T4, and the drain is electrically connected to the a DC constant voltage low potential VSS1;
  • the sixteenth transistor T16 the gate of the sixteenth transistor T16 is electrically connected to the output terminal G(N), the source is electrically connected to the second node P(N), and the drain is electrically connected to the eighth transistor.
  • the first pull-down portion 400 includes a fourteenth transistor T14.
  • the gate of the fourteenth transistor T14 is electrically connected to the second clock driving signal XCKN, and the source is electrically connected to the first node Q(N).
  • the drain is electrically connected to the second constant voltage low potential VSS2.
  • the gate and the source of the first transistor T1 are electrically connected to the start signal terminal STV of the circuit, and the fifth, sixth, and seventh transistors T5 are connected.
  • the gates of T6 and T7 are electrically connected to the start signal terminal STV of the circuit.
  • the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor is provided with a DC constant voltage high potential H and three DC constant voltage low potentials VSS1, VSS2, VSS3, and three DC constant voltage low potentials in turn.
  • the third DC constant voltage low potential VSS3 ⁇ the second DC constant voltage low potential VSS2 ⁇ the first DC constant voltage low potential VSS1, the three DC constant voltage low potentials VSS1, VSS2, VSS3 are generally independently controlled, Easy to adjust different potentials.
  • the pull-down sustain circuit portion 500 adopts a high-low potential reverse push design: the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 provide a positive high potential for controlling the first Opening of the twelve transistor T12 and the thirteenth transistor T13; the eighth transistor T8 and the ninth transistor T9 constitute a reverse bootstrap of a negative potential during operation for pulling the second node P(N) during the action
  • the tenth transistor T10 is preferably turned off; during the non-active period, the DC constant voltage high potential H is used
  • the two nodes P(N) provide a suitable high potential such that the first node Q(N) and the output terminal G(N) are maintained at a low potential, eliminating the Ripple voltage of both.
  • the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are connected in series to prevent leakage.
  • the third transistor T3 and the fourth transistor T4 in the pull-down maintaining circuit portion 500 are controlled to be in a conducting state by the DC constant voltage high potential H.
  • the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are controlled to be in a conducting state by the DC constant voltage high potential H.
  • the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are controlled to be in a conducting state by the DC constant voltage high potential H.
  • the fifth transistor T5 the sixth transistor T6, and the seventh transistor T7.
  • the fourth transistor T4 supplies the constant current high potential H to the second node P(N), and the second node P(N) is high, the twelfth transistor T12 and the thirteenth transistor T13 are both turned on.
  • the gates of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are transmitted from the output terminal G(N-1) of the N-1th GOA unit of the upper stage of the Nth stage GOA unit.
  • the fifth potential transistor T5, the sixth transistor T6, and the seventh transistor T7 are both turned on, and the gates of the fifteenth transistor T15 and the sixteenth transistor are high potentials from the output terminal G(N).
  • the fifteen crystal T15 and the fifth transistor T5 pull down the potential of the gate of the fourth transistor T4 to a low first DC constant voltage Bit VSS1
  • the sixteenth transistor T16 and the sixth transistor T6 conduct the DC constant voltage high potential H of the second node P(N), and pass the DC constant voltage high potential H to the eighth transistor T8 and the ninth transistor T9.
  • the seventh transistor T7 and the eighth transistor T8 are both turned on, and the potential of the second node P(N) is pulled down to a lower third DC constant voltage through the seventh transistor T7 and the eighth transistor T8.
  • the output terminal G(N) and the output terminal G(N-1) of the upper N-1th GOA unit of the Nth stage GOA unit are used to control the pull-down sustain circuit portion 500, and the fifth transistor can be attenuated. Leakage of T5, sixth transistor T6, and seventh transistor T7.
  • the pull-down maintaining circuit portion 500 is matched with a DC constant voltage high potential H and three DC constant voltage low potentials VSS1, VSS2, and VSS3, which can solve the low threshold voltage of the low temperature polysilicon semiconductor thin film transistor and the swing of the subthreshold region.
  • the influence of smaller characteristics on the GOA driving circuit, especially the leakage of the GOA function caused by the leakage problem; at the same time, the second node potential in the low-voltage sustaining circuit part of the GOA circuit based on the low-temperature polysilicon semiconductor thin film transistor is not solved.
  • the problem of being at a higher potential effectively maintains the low potential of the first node Q(N) and the output terminal G(N).
  • the rising portion 300 is used to raise the potential of the first node Q(N) during the action.
  • the first pull-down portion 400 is configured to pull down the potential of the first node Q(N) to the second DC constant voltage low potential VSS2 according to the second clock driving signal XCKN during the inactive period.
  • the present invention adopts the output terminal G(N-1) of the upper N-1th GOA unit of the Nth stage GOA unit and the output terminal G(N) of the Nth stage GOA unit to perform upper and lower level transmission, thereby reducing TFT
  • the number of pixels achieves the purpose of effectively saving layout and power consumption.
  • 3 is a waveform diagram of waveform setting and key node output of a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor of the present invention.
  • the first clock driving signal CKN and the second clock driving signal XCKN are clock driving signals of the circuit.
  • the duty ratio of the schematic waveform is close to 50/50, which is preferably occupied in actual design.
  • the space ratio is 50/50, which is used to ensure the output terminal G(N-1) and the output terminal G(N) of the upper N-1th GOA unit of the Nth stage GOA unit to the second node P(N).
  • the abnormal output of the first node Q(N) and the output terminal G(N) is prevented.
  • the waveform of the first node Q(N) will not be very obvious.
  • the potential of the first node Q(N) is pulled down at the first time after the output G(N) is output.
  • the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor of the present invention adopts a high and low potential reverse push design in the pull-down sustaining circuit portion, and sets the first, second, and third DC constant voltage low potentials which are sequentially lowered, and A DC constant voltage high potential can solve the influence of the low-temperature polysilicon semiconductor thin film transistor's own characteristics on the GOA driving circuit, especially the GOA functionality caused by the leakage problem; and solve the current GOA circuit based on the low temperature polysilicon semiconductor thin film transistor.
  • the problem that the second node potential cannot be at a higher potential during the non-active period of the pull-down sustain circuit portion effectively maintains the low potential of the first node and the output terminal.

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Abstract

A low-temperature polycrystalline silicon semiconductor thin-film transistor-based GOA circuit comprising multiple cascade GOA units. A level N GOA unit comprises a pull-up control part (100), a pull-up part (200), a first pull-down part (400), and a pull-down holding circuit part (500). The pull-down holding circuit part (500) employs a high-low potential backstepping design and is provided with consecutively lowered first, second, and third direct current constant voltage potentials (VSS1, VSS2, and VSS3) and a direct current constant voltage high potential (H). This solves an impact on a GOA driver circuit by properties of the low temperature polysilicon semiconductor thin-film transistor itself, particularly a GOA functional shortcoming brought forth by the problem of electric leakage, also solves the problem that the potential of a second node (P(N)) in the pull-down holding circuit part in an existing low-temperature polycrystalline silicon semiconductor thin-film transistor-based GOA circuit cannot remain at an increased potential during inactivity, and effectively maintains a low potential for a first node (Q(N)) and an output end (G(N)).

Description

基于低温多晶硅半导体薄膜晶体管的GOA电路GOA circuit based on low temperature polysilicon semiconductor thin film transistor 技术领域Technical field
本发明涉及显示技术领域，尤其涉及一种基于低温多晶硅半导体薄膜晶体管的GOA电路。The present invention relates to the field of display technologies, and in particular, to a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor.
背景技术Background technique
GOA(Gate Drive On Array)，是利用薄膜晶体管(thin film transistor，TFT)液晶显示器阵列(Array)制程将栅极驱动器制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式。GOA (Gate Drive On Array) is a driving method in which a gate driver is fabricated on a thin film transistor array substrate by a thin film transistor (TFT) liquid crystal display array (Array) process to realize progressive scanning.
通常，GOA电路主要由上拉部分(Pull-up part)、上拉控制部分(Pull-up control part)、下传部分(Transfer part)、下拉部分(Pull-down part)、下拉维持电路部分(Pull-down Holding part)、以及负责电位抬升的上升部分(Boost part)组成，上升部分一般由一自举电容构成。Generally, the GOA circuit is mainly composed of a pull-up part, a pull-up control part, a transfer part, a pull-down part, and a pull-down sustain circuit part ( The pull-down holding part and the boost part responsible for the potential rise are generally composed of a bootstrap capacitor.
上拉部分主要负责将输入的时钟信号(Clock)输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制部分主要负责控制上拉部分的打开，一般是由上级GOA电路传递来的信号作用。下拉部分主要负责在输出扫描信号后，快速地将扫描信号(亦即薄膜晶体管的栅极的电位)拉低为低电平。下拉维持电路部分则主要负责将扫描信号和上拉部分的信号保持在关闭状态(即设定的负电位)。上升部分则主要负责对上拉部分的电位进行二次抬升，确保上拉部分的正常输出。The pull-up portion is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display. The pull-up control part is mainly responsible for controlling the opening of the pull-up part, which is generally a signal transmitted by the upper-level GOA circuit. The pull-down portion is mainly responsible for quickly pulling the scan signal (that is, the potential of the gate of the thin film transistor) to a low level after outputting the scan signal. The pull-down sustain circuit portion is mainly responsible for keeping the scan signal and the signal of the pull-up portion in a closed state (ie, a set negative potential). The rising portion is mainly responsible for the secondary rise of the potential of the pull-up portion to ensure the normal output of the pull-up portion.
随着低温多晶硅(Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管的发展，LTPS-TFT液晶显示器也越来越受关注，LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。由于低温多晶硅较非晶硅(a-Si)的排列有次序，低温多晶硅半导体本身具有超高的电子迁移率，比非晶硅半导体相对高100倍以上，可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上，达到系统整合的目标、节省空间及驱动IC的成本。然而，现有技术中针对低温多晶硅半导体薄膜晶体管的GOA电路的开发较少，尤其需要克服很多由于低温多晶硅半导体薄膜晶体管电性本身带来的问题。例如：传统的非晶硅半导体薄膜晶体管的电学特性中阈值电压一般大于0V，而且亚阈值区域的电压相对于电流的摆幅较大，但是低温多晶硅半导体薄膜晶体管的阈值电压值较低(一般约为0V左右)，而且亚阈值区域的摆幅较小，而GOA电路在关态时很多元件操作与阈值电 压接近，甚至高于阈值电压，这样就会由于电路中TFT的漏电和工作电流的漂移，增加LTPS GOA电路设计的难度，很多适用于非晶硅半导体的扫描驱动电路，不能轻易的应用到低温多晶硅半导体的行扫描驱动电路中，会存在一些功能性问题，这样将会直接导致LTPS GOA电路无法工作，所以在设计电路时必须要考虑到低温多晶硅半导体薄膜晶体管的自身特性对GOA电路的影响。With the development of low temperature poly-silicon (LTPS) semiconductor thin film transistors, LTPS-TFT liquid crystal displays have attracted more and more attention. LTPS-TFT liquid crystal displays have high resolution, fast response, high brightness and high opening. Rate and other advantages. Since the low-temperature polysilicon has an order of arrangement of amorphous silicon (a-Si), the low-temperature polysilicon semiconductor itself has an ultra-high electron mobility, which is 100 times higher than that of the amorphous silicon semiconductor, and the gate driver can be fabricated by using GOA technology. On the thin film transistor array substrate, the goal of system integration, space saving and cost of driving the IC are achieved. However, the development of GOA circuits for low-temperature polysilicon semiconductor thin film transistors in the prior art has been less, and in particular, many problems due to the electrical properties of low-temperature polysilicon semiconductor thin film transistors themselves have to be overcome. For example, the threshold voltage of a conventional amorphous silicon semiconductor thin film transistor is generally greater than 0 V, and the voltage of the subthreshold region is relatively large with respect to the current, but the threshold voltage of the low temperature polysilicon semiconductor thin film transistor is low (generally about It is about 0V), and the swing of the subthreshold region is small, while the GOA circuit is in the off state, many components operate with threshold voltage. The voltage is close to or even higher than the threshold voltage. This will increase the difficulty of the LTPS GOA circuit design due to the leakage of the TFT in the circuit and the drift of the operating current. Many scan drive circuits suitable for amorphous silicon semiconductors cannot be easily applied to low temperatures. In the row scan driving circuit of polycrystalline silicon semiconductor, there are some functional problems, which will directly lead to the inability of the LTPS GOA circuit. Therefore, the influence of the characteristics of the low temperature polysilicon semiconductor thin film transistor on the GOA circuit must be considered when designing the circuit.
发明内容Summary of the invention
本发明的目的在于提供一种基于低温多晶硅半导体薄膜晶体管的GOA电路，解决低温多晶硅半导体薄膜晶体管的自身特性对GOA驱动电路的影响，尤其是漏电问题带来的GOA功能性不良；解决目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题。The object of the present invention is to provide a GOA circuit based on a low-temperature polysilicon semiconductor thin film transistor, which solves the influence of the low-temperature polysilicon semiconductor thin film transistor's own characteristics on the GOA driving circuit, especially the GOA functionality caused by the leakage problem; In the GOA circuit of the polysilicon semiconductor thin film transistor, the problem that the second node potential cannot be at a higher potential during the non-active period of the pull-down sustain circuit portion.
为实现上述目的，本发明提供一种基于低温多晶硅半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分、一上拉部分、一第一下拉部分、和一下拉维持电路部分；To achieve the above object, the present invention provides a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor, comprising a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit includes a pull-up control portion and a pull-up a portion, a first pull-down portion, and a pull-down sustain circuit portion;
所述上拉控制部分包括第一晶体管，其栅极与源极均电性连接于该第N级GOA单元的上一级第N-1级GOA单元的输出端，漏极电性连接于第一节点；The pull-up control portion includes a first transistor, and a gate and a source thereof are electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the drain is electrically connected to the One node
所述上拉部分包括第二晶体管，其栅极电性连接于第一节点，源极电性连接于第一时钟驱动信号，漏极电性连接于输出端；The pull-up portion includes a second transistor having a gate electrically connected to the first node, a source electrically connected to the first clock driving signal, and a drain electrically connected to the output terminal;
所述下拉维持电路部分电性连接于所述第一节点、输出端、一直流恒压高电位、及第一、第二、与第三直流恒压低电位；所述下拉维持电路部分采用高低电位反推设计，包括：The pull-down maintaining circuit is electrically connected to the first node, the output end, the constant current constant high potential, and the first, second, and third DC constant voltage low potentials; Potential reverse design, including:
第三晶体管，所述第三晶体管的栅极和源极均电性连接于直流恒压高电位，漏极电性连接于第五晶体管的源极；a third transistor, the gate and the source of the third transistor are electrically connected to a DC constant voltage high potential, and the drain is electrically connected to the source of the fifth transistor;
第四晶体管，所述第四晶体管的栅极电性连接于第三晶体管的漏极，源极电性连接于直流恒压高电位，漏极电性连接于第二节点；a fourth transistor, the gate of the fourth transistor is electrically connected to the drain of the third transistor, the source is electrically connected to the DC constant voltage high potential, and the drain is electrically connected to the second node;
第五晶体管，所述第五晶体管的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端，源极电性连接于第三晶体管的漏极，漏极电性连接于第一直流恒压低电位；a fifth transistor, the gate of the fifth transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the drain of the third transistor The drain is electrically connected to the first DC constant voltage low potential;
第六晶体管，所述第六晶体管的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端，源极电性连接于第二节点，漏极电 性连接于第八晶体管的栅极；a sixth transistor, the gate of the sixth transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the second node and has a drain Electricity Connected to the gate of the eighth transistor;
第七晶体管，所述第七晶体管的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端，源极电性连接于第二节点，漏极电性连接于第八晶体管的源极；a seventh transistor, the gate of the seventh transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the second node and has a drain Electrically connected to the source of the eighth transistor;
第八晶体管，所述第八晶体管的栅极电性连接于第十六晶体管的漏极，源极电性连接于第七晶体管的漏极，漏极电性连接于第三直流恒压低电位；An eighth transistor, the gate of the eighth transistor is electrically connected to the drain of the sixteenth transistor, the source is electrically connected to the drain of the seventh transistor, and the drain is electrically connected to the third DC constant voltage low potential ;
第九晶体管，所述第九晶体管的栅极电性连接于第十六晶体管的漏极，源极电性连接于第十晶体管的栅极，漏极电性连接于第三直流恒压低电位；a ninth transistor, the gate of the ninth transistor is electrically connected to the drain of the sixteenth transistor, the source is electrically connected to the gate of the tenth transistor, and the drain is electrically connected to the third DC constant voltage low potential ;
第十晶体管，所述第十晶体管的栅极电性连接于第九晶体管的源极，源极电性连接于直流恒压高电位，漏极电性连接于第七晶体管的漏极；a tenth transistor, the gate of the tenth transistor is electrically connected to the source of the ninth transistor, the source is electrically connected to the DC constant voltage high potential, and the drain is electrically connected to the drain of the seventh transistor;
第十一晶体管，所述第十一晶体管的栅极与源极均电性连接于直流恒压高电位，漏极电性连接于第九晶体管的源极；An eleventh transistor, the gate and the source of the eleventh transistor are electrically connected to a DC constant voltage high potential, and the drain is electrically connected to the source of the ninth transistor;
第十二晶体管，所述第十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；a twelfth transistor, the gate of the twelfth transistor is electrically connected to the second node, the source is electrically connected to the first node, and the drain is electrically connected to the second DC constant voltage low potential;
第十三晶体管，所述第十三晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于第一直流恒压低电位；a thirteenth transistor, the gate of the thirteenth transistor is electrically connected to the second node, the source is electrically connected to the output end, and the drain is electrically connected to the first DC constant voltage low potential;
第十五晶体管，所述第十五晶体管的栅极电性连接于输出端，源极电性连接于第四晶体管的栅极，漏极电性连接于第一直流恒压低电位；a fifteenth transistor, the gate of the fifteenth transistor is electrically connected to the output end, the source is electrically connected to the gate of the fourth transistor, and the drain is electrically connected to the first DC constant voltage low potential;
第十六晶体管，所述第十六晶体管的栅极电性连接于输出端，源极电性连接于第二节点，漏极电性连接于第八晶体管的栅极；a sixteenth transistor, the gate of the sixteenth transistor is electrically connected to the output end, the source is electrically connected to the second node, and the drain is electrically connected to the gate of the eighth transistor;
所述第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管提供正向高电位，用于控制第十二晶体管和第十三晶体管的打开；所述第八晶体管、第九晶体管构成作用期间的负电位的反向自举，用于在作用期间向第二节点提供更低电位；利用直流恒压高电位在非作用期间向第二节点提供适当的高电位，使得第一节点与输出端维持低电位；The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor provide a positive high potential for controlling opening of the twelfth transistor and the thirteenth transistor; the eighth transistor, the ninth transistor The transistor constitutes a reverse bootstrap of a negative potential during operation for providing a lower potential to the second node during operation; providing a suitable high potential to the second node during the inactive period using the DC constant voltage high potential, such that the first The node and the output maintain a low potential;
所述第一下拉部分电性连接于所述第一节点、第二时钟驱动信号及第二直流恒压低电位，所述第一下拉部分依据第二时钟驱动信号下拉所述第一节点的电位至所述第二直流恒压低电位；The first pull-down portion is electrically connected to the first node, the second clock driving signal, and the second DC constant voltage low potential, and the first pull-down portion pulls down the first node according to the second clock driving signal a potential to the second DC constant voltage low potential;
所述第一下拉部分包括一第十四晶体管，所述第十四晶体管的栅极电性连接于第二时钟驱动信号，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；The first pull-down portion includes a fourteenth transistor, the gate of the fourteenth transistor is electrically connected to the second clock driving signal, the source is electrically connected to the first node, and the drain is electrically connected to the first Two DC constant voltage low potential;
所述第三直流恒压低电位<第二直流恒压低电位<第一直流恒压低电 位。The third DC constant voltage low potential <the second DC constant voltage low potential <the first DC constant voltage low power Bit.
所述第四晶体管、第七晶体管、与第八晶体管串联。The fourth transistor, the seventh transistor, and the eighth transistor are connected in series.
所述基于低温多晶硅半导体薄膜晶体管的GOA电路，还包括一上升部分，所述上升部分电性连接于所述第一节点与输出端之间，用来抬升所述第一节点的电位。The GOA circuit based on the low temperature polysilicon semiconductor thin film transistor further includes a rising portion electrically connected between the first node and the output terminal for raising the potential of the first node.
所述上升部分包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于输出端。The rising portion includes a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the output end.
第一时钟驱动信号与第二时钟驱动信号的波形占空比接近50/50；在第二时钟驱动信号的高电位期间，所述第十四晶体管下拉所述第一节点的电位至所述第二直流恒压低电位。The waveform duty ratio of the first clock driving signal and the second clock driving signal is close to 50/50; during the high potential of the second clock driving signal, the fourteenth transistor pulls down the potential of the first node to the first Two DC constant voltage low potential.
所述GOA电路的第一级连接关系中，第一晶体管的栅极与源极均电性连接于电路的启动信号端，第五、第六、第七晶体管的栅极均电性连接于电路的启动信号端。In the first-stage connection relationship of the GOA circuit, the gate and the source of the first transistor are electrically connected to the start signal end of the circuit, and the gates of the fifth, sixth, and seventh transistors are electrically connected to the circuit. The start signal end.
用输出端和所述第N级GOA单元的上一级第N-1级GOA单元的输出端来控制下拉维持电路部分。The pull-down sustain circuit portion is controlled by the output terminal and the output of the upper N-1th stage GOA unit of the Nth stage GOA unit.
所述GOA电路采用输出端的输出信号作为上下级传信号。The GOA circuit uses the output signal of the output end as a signal for transmitting the upper and lower stages.
本发明的有益效果：本发明提供的基于低温多晶硅半导体薄膜晶体管的GOA电路，在下拉维持电路部分采用高低电位反推设计，并设置依次降低的第一、第二、第三直流恒压低电位、及一直流恒压高电位，能够解决低温多晶硅半导体薄膜晶体管的自身特性对GOA驱动电路的影响，尤其是漏电问题带来的GOA功能性不良；同时解决了目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题，有效维持第一节点和输出端的低电位。The invention has the beneficial effects that the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor provided by the invention adopts the high and low potential reverse push design in the pull-down sustaining circuit portion, and sets the first, second and third DC constant voltage low potentials which are sequentially lowered. And the constant current and high potential of the constant current can solve the influence of the low-temperature polysilicon semiconductor thin film transistor's own characteristics on the GOA driving circuit, especially the GOA functionality caused by the leakage problem; and solve the current GOA based on the low temperature polysilicon semiconductor thin film transistor. The problem that the second node potential cannot be at a higher potential during the non-active period of the pull-down sustain circuit portion in the circuit effectively maintains the low potential of the first node and the output terminal.
附图说明DRAWINGS
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。The technical solutions and other advantageous effects of the present invention will be apparent from the following detailed description of embodiments of the invention.
附图中，In the drawings,
图1为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的电路图；1 is a circuit diagram of a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor of the present invention;
图2为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的第一级连接关系的电路图；2 is a circuit diagram showing a first-stage connection relationship of a GOA circuit based on a low-temperature polysilicon semiconductor thin film transistor of the present invention;
图3为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的波形设置和关键节点的输出波形图。 3 is a waveform diagram of waveform setting and key node output of a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor of the present invention.
具体实施方式detailed description
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。In order to further clarify the technical means and effects of the present invention, the following detailed description will be made in conjunction with the preferred embodiments of the invention and the accompanying drawings.
请参阅图1-2，本发明提供一种基于低温多晶硅半导体薄膜晶体管的GOA电路。如图1所示，该基于低温多晶硅半导体薄膜晶体管的GOA电路包括：级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分100、一上拉部分200、一第一下拉部分400、和一下拉维持电路部分500；还可包括一上升部分300。Referring to FIG. 1-2, the present invention provides a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor. As shown in FIG. 1, the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor includes: a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit includes a pull-up control portion 100 and a pull-up portion 200. a first pull-down portion 400, and a pull-down sustain circuit portion 500; and a rising portion 300.
所述上拉控制部分100包括第一晶体管T1，其栅极与源极均电性连接于该第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)，漏极电性连接于第一节点Q(N)。The pull-up control portion 100 includes a first transistor T1 whose gate and source are electrically connected to the output terminal G(N-1) of the upper N-1th GOA unit of the Nth stage GOA unit. The drain is electrically connected to the first node Q(N).
所述上拉部分200包括第二晶体管T2，其栅极电性连接于第一节点Q(N)，源极电性连接于第一时钟驱动信号CKN，漏极电性连接于输出端G(N)。The pull-up portion 200 includes a second transistor T2 whose gate is electrically connected to the first node Q(N), the source is electrically connected to the first clock driving signal CKN, and the drain is electrically connected to the output terminal G ( N).
所述上升部分300包括一电容Cb，所述电容Cb的一端电性连接于第一节点Q(N)，另一端电性连接于输出端G(N)。The rising portion 300 includes a capacitor Cb. One end of the capacitor Cb is electrically connected to the first node Q(N), and the other end is electrically connected to the output terminal G(N).
所述下拉维持电路部分500电性连接于所述第一节点Q(N)、所述第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)、输出端G(N)、一直流恒压高电位H、及第一、第二、与第三直流恒压低电位VSS1、VSS2、VSS3。具体的，所述下拉维持电路部分500包括：第三晶体管T3，所述第三晶体管T3的栅极和源极均电性连接于直流恒压高电位H，漏极电性连接于第五晶体管T5的源极；第四晶体管T4，所述第四晶体管T4的栅极电性连接于第三晶体管T3的漏极，源极电性连接于直流恒压高电位H，漏极电性连接于第二节点P(N)；第五晶体管T5，所述第五晶体管T5的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)，源极电性连接于第三晶体管T3的漏极，漏极电性连接于第一直流恒压低电位VSS1；第六晶体管T6，所述第六晶体管T6的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)，源极电性连接于第二节点P(N)，漏极电性连接于第八晶体管T8的栅极；第七晶体管T7，所述第七晶体管T7的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)，源极电性连接于第二节点P(N)，漏极电性连接于第八晶体管T8的源极；第八晶体管T8，所述第八晶体管T8的栅极电性连接于第十六晶体管T6的漏极，源极电性连接于第七晶体 管T7的漏极，漏极电性连接于第三直流恒压低电位VSS3；第九晶体管T9，所述第九晶体管T9的栅极电性连接于第十六晶体管T6的漏极，源极电性连接于第十晶体管T10的栅极，漏极电性连接于第三直流恒压低电位VSS3；第十晶体管T10，所述第十晶体管T10的栅极电性连接于第九晶体管T9的源极，源极电性连接于直流恒压高电位H，漏极电性连接于第七晶体管T7的漏极；第十一晶体管T11，所述第十一晶体管T11的栅极与源极均电性连接于直流恒压高电位H，漏极电性连接于第九晶体管T9的源极；第十二晶体管T12，所述第十二晶体管T12的栅极电性连接于第二节点P(N)，源极电性连接于第一节点Q(N)，漏极电性连接于第二直流恒压低电位VSS2；第十三晶体管T13，所述第十三晶体管T13的栅极电性连接于第二节点P(N)，源极电性连接于输出端G(N)，漏极电性连接于第一直流恒压低电位VSS1；第十五晶体管T15，所述第十五晶体管T15的栅极电性连接于输出端G(N)，源极电性连接于第四晶体管T4的栅极，漏极电性连接于第一直流恒压低电位VSS1；The pull-down maintaining circuit portion 500 is electrically connected to the first node Q(N), the output terminal G(N-1) of the upper-stage N-1th GOA unit of the Nth-stage GOA unit, and the output. Terminal G(N), constant current constant voltage high potential H, and first, second, and third DC constant voltage low potentials VSS1, VSS2, VSS3. Specifically, the pull-down maintaining circuit portion 500 includes: a third transistor T3, the gate and the source of the third transistor T3 are electrically connected to the DC constant voltage high potential H, and the drain is electrically connected to the fifth transistor a fourth transistor T4, the gate of the fourth transistor T4 is electrically connected to the drain of the third transistor T3, the source is electrically connected to the DC constant voltage high potential H, and the drain is electrically connected to the drain a second node P(N); a fifth transistor T5, the gate of the fifth transistor T5 is electrically connected to an output terminal G of the upper N-1th GOA unit of the Nth stage GOA unit -1), the source is electrically connected to the drain of the third transistor T3, the drain is electrically connected to the first DC constant voltage low potential VSS1; the sixth transistor T6, the gate electrical property of the sixth transistor T6 Connected to the output terminal G(N-1) of the upper N-1th GOA unit of the Nth stage GOA unit, the source is electrically connected to the second node P(N), and the drain is electrically connected to a gate of the eighth transistor T8; a seventh transistor T7, the gate of the seventh transistor T7 is electrically connected to an output terminal G of the upper N-1th GOA unit of the Nth stage GOA unit - 1) The source is electrically connected to the second node P(N), the drain is electrically connected to the source of the eighth transistor T8, and the eighth transistor T8 is electrically connected to the gate of the eighth transistor T8. The drain of the sixteen transistor T6, the source is electrically connected to the seventh crystal The drain of the transistor T7 is electrically connected to the third DC constant voltage low potential VSS3; the ninth transistor T9, the gate of the ninth transistor T9 is electrically connected to the drain of the sixteenth transistor T6, the source Electrically connected to the gate of the tenth transistor T10, the drain is electrically connected to the third DC constant voltage low potential VSS3; the tenth transistor T10, the gate of the tenth transistor T10 is electrically connected to the ninth transistor T9 a source, a source electrically connected to the DC constant voltage high potential H, a drain electrically connected to the drain of the seventh transistor T7; an eleventh transistor T11, the gate and the source of the eleventh transistor T11 Electrically connected to the DC constant voltage high potential H, the drain is electrically connected to the source of the ninth transistor T9; the twelfth transistor T12, the gate of the twelfth transistor T12 is electrically connected to the second node P ( N), the source is electrically connected to the first node Q(N), the drain is electrically connected to the second DC constant voltage low potential VSS2, and the thirteenth transistor T13, the gate electrical property of the thirteenth transistor T13 Connected to the second node P(N), the source is electrically connected to the output terminal G(N), and the drain is electrically connected to the first DC constant voltage and low voltage. VSS1; a fifteenth transistor T15, the gate of the fifteenth transistor T15 is electrically connected to the output terminal G(N), the source is electrically connected to the gate of the fourth transistor T4, and the drain is electrically connected to the a DC constant voltage low potential VSS1;
第十六晶体管T16，所述第十六晶体管T16的栅极电性连接于输出端G(N)，源极电性连接于第二节点P(N)，漏极电性连接于第八晶体管T8的栅极；。The sixteenth transistor T16, the gate of the sixteenth transistor T16 is electrically connected to the output terminal G(N), the source is electrically connected to the second node P(N), and the drain is electrically connected to the eighth transistor. The gate of T8;
所述第一下拉部分400包括一第十四晶体管T14，所述第十四晶体管T14的栅极电性连接于第二时钟驱动信号XCKN，源极电性连接于第一节点Q(N)，漏极电性连接于第二恒压低电位VSS2。The first pull-down portion 400 includes a fourteenth transistor T14. The gate of the fourteenth transistor T14 is electrically connected to the second clock driving signal XCKN, and the source is electrically connected to the first node Q(N). The drain is electrically connected to the second constant voltage low potential VSS2.
如图2所示，所述GOA电路的第一级连接关系中，第一晶体管T1的栅极与源极均电性连接于电路的启动信号端STV，第五、第六、第七晶体管T5、T6、T7的栅极均电性连接于电路的启动信号端STV。As shown in FIG. 2, in the first-stage connection relationship of the GOA circuit, the gate and the source of the first transistor T1 are electrically connected to the start signal terminal STV of the circuit, and the fifth, sixth, and seventh transistors T5 are connected. The gates of T6 and T7 are electrically connected to the start signal terminal STV of the circuit.
需要特别说明的是，本发明基于低温多晶硅半导体薄膜晶体管的GOA电路设置了一个直流恒压高电位H、及三个直流恒压低电位VSS1、VSS2、VSS3，且三个直流恒压低电位依次降低，即，第三直流恒压低电位VSS3<第二直流恒压低电位VSS2<第一直流恒压低电位VSS1，该三个直流恒压低电位VSS1、VSS2、VSS3一般分开独立控制，便于进行不同电位的调节。It should be particularly noted that the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor is provided with a DC constant voltage high potential H and three DC constant voltage low potentials VSS1, VSS2, VSS3, and three DC constant voltage low potentials in turn. Decrease, that is, the third DC constant voltage low potential VSS3 < the second DC constant voltage low potential VSS2 < the first DC constant voltage low potential VSS1, the three DC constant voltage low potentials VSS1, VSS2, VSS3 are generally independently controlled, Easy to adjust different potentials.
所述下拉维持电路部分500采用高低电位反推设计：所述第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7提供正向高电位，用于控制第十二晶体管T12和第十三晶体管T13的打开；所述第八晶体管T8、第九晶体管T9构成作用期间的负电位的反向自举，用于在作用期间将第二节点P(N)拉低至至第三直流恒压低电位VSS3电位，使第十晶体管T10关闭的较好；在非作用期间利用直流恒压高电位H向第 二节点P(N)提供适当的高电位，使得第一节点Q(N)与输出端G(N)维持低电位，消除二者的波纹(Ripple)电压。所述第四晶体管T4、第七晶体管T7、与第八晶体管T8串联，能够防止漏电。The pull-down sustain circuit portion 500 adopts a high-low potential reverse push design: the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 provide a positive high potential for controlling the first Opening of the twelve transistor T12 and the thirteenth transistor T13; the eighth transistor T8 and the ninth transistor T9 constitute a reverse bootstrap of a negative potential during operation for pulling the second node P(N) during the action As low as the third DC constant voltage low potential VSS3 potential, the tenth transistor T10 is preferably turned off; during the non-active period, the DC constant voltage high potential H is used The two nodes P(N) provide a suitable high potential such that the first node Q(N) and the output terminal G(N) are maintained at a low potential, eliminating the Ripple voltage of both. The fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are connected in series to prevent leakage.
所述下拉维持电路部分500中第三晶体管T3、第四晶体管T4受直流恒压高电位H的控制处于导通状态，在非作用期间，第五晶体管T5、第六晶体管T6、第七晶体管T7截止，由第四晶体管T4向第二节点P(N)提供一直流恒压高电位H，第二节点P(N)为高电位时，第十二晶体管T12、第十三晶体管T13均导通，通过第十二晶体管下拉第一节点Q(N)的电位到第二直流恒压低电位VSS2，通过第十三晶体管下拉输出端G(N)的电位到第一直流恒压低电位VSS1；在作用期间，第五晶体管T5、第六晶体管T6、第七晶体管T7的栅极为从该第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)传来的高电位，第五晶体管T5、第六晶体管T6、第七晶体管T7均导通，第十五晶体管T15、第十六晶体管的栅极为从输出端G(N)传来的高电位，第十五晶体T15和第五晶体管T5下拉第四晶体管T4栅极的电位至第一直流恒压低电位VSS1，第十六晶体管T16和第六晶体管T6传导第二节点P(N)的直流恒压高电位H，并将此直流恒压高电位H传到第八晶体管T8和第九晶体管T9的栅极，此时，第七晶体管T7和第八晶体管T8均导通，通过第七晶体管T7和第八晶体管T8下拉第二节点P(N)的电位到一更低的第三直流恒压低电位VSS3,同时第九晶体管T9也处于导通状态，通过第九晶体管T9下拉第十晶体管的栅极电位至第三直流恒压低电位VSS3，可以使第十晶体管T10关闭的很好。此处，采用输出端G(N)和该第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)来控制下拉维持电路部分500，可减弱第五晶体管T5、第六晶体管T6、第七晶体管T7的漏电。The third transistor T3 and the fourth transistor T4 in the pull-down maintaining circuit portion 500 are controlled to be in a conducting state by the DC constant voltage high potential H. During the inactive period, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. When the fourth transistor T4 supplies the constant current high potential H to the second node P(N), and the second node P(N) is high, the twelfth transistor T12 and the thirteenth transistor T13 are both turned on. Pulling the potential of the first node Q(N) to the second DC constant voltage low potential VSS2 through the twelfth transistor, and pulling the potential of the output terminal G(N) through the thirteenth transistor to the first DC constant voltage low potential VSS1 During operation, the gates of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are transmitted from the output terminal G(N-1) of the N-1th GOA unit of the upper stage of the Nth stage GOA unit. The fifth potential transistor T5, the sixth transistor T6, and the seventh transistor T7 are both turned on, and the gates of the fifteenth transistor T15 and the sixteenth transistor are high potentials from the output terminal G(N). The fifteen crystal T15 and the fifth transistor T5 pull down the potential of the gate of the fourth transistor T4 to a low first DC constant voltage Bit VSS1, the sixteenth transistor T16 and the sixth transistor T6 conduct the DC constant voltage high potential H of the second node P(N), and pass the DC constant voltage high potential H to the eighth transistor T8 and the ninth transistor T9. Gate, at this time, the seventh transistor T7 and the eighth transistor T8 are both turned on, and the potential of the second node P(N) is pulled down to a lower third DC constant voltage through the seventh transistor T7 and the eighth transistor T8. The potential VSS3, while the ninth transistor T9 is also in an on state, and the tenth transistor T10 can be turned off well by pulling down the gate potential of the tenth transistor to the third DC constant voltage low potential VSS3 through the ninth transistor T9. Here, the output terminal G(N) and the output terminal G(N-1) of the upper N-1th GOA unit of the Nth stage GOA unit are used to control the pull-down sustain circuit portion 500, and the fifth transistor can be attenuated. Leakage of T5, sixth transistor T6, and seventh transistor T7.
所述下拉维持电路部分500搭配直流恒压高电位H、及三个直流恒压低电位VSS1、VSS2、VSS3，能够解决低温多晶硅半导体薄膜晶体管的自身的阈值电压较低、亚阈值区域的摆幅较小等特性对GOA驱动电路的影响，尤其是漏电问题带来的GOA功能性不良；同时解决了目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题，有效维持第一节点Q(N)和输出端G(N)的低电位。The pull-down maintaining circuit portion 500 is matched with a DC constant voltage high potential H and three DC constant voltage low potentials VSS1, VSS2, and VSS3, which can solve the low threshold voltage of the low temperature polysilicon semiconductor thin film transistor and the swing of the subthreshold region. The influence of smaller characteristics on the GOA driving circuit, especially the leakage of the GOA function caused by the leakage problem; at the same time, the second node potential in the low-voltage sustaining circuit part of the GOA circuit based on the low-temperature polysilicon semiconductor thin film transistor is not solved. The problem of being at a higher potential effectively maintains the low potential of the first node Q(N) and the output terminal G(N).
所述上升部分300用来在作用期间抬升所述第一节点Q(N)的电位。The rising portion 300 is used to raise the potential of the first node Q(N) during the action.
所述第一下拉部分400用来在非作用期间依据第二时钟驱动信号XCKN下拉所述第一节点Q(N)的电位至所述第二直流恒压低电位VSS2。 The first pull-down portion 400 is configured to pull down the potential of the first node Q(N) to the second DC constant voltage low potential VSS2 according to the second clock driving signal XCKN during the inactive period.
本发明采用第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)与第N级GOA单元的输出端G(N)进行上、下级传，能够减少TFT的颗数，达到有效节省布局(Layout)和功耗的目的。图3为本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路的波形设置和关键节点的输出波形图。如图3所示，第一时钟驱动信号CKN和第二时钟驱动信号XCKN是电路的时钟驱动信号，从图3中可以看出示意的波形的占空比接近50/50，实际设计时优选占空比为50/50，用来保证该第N级GOA单元的上一级第N-1级GOA单元的输出端G(N-1)和输出端G(N)对第二节点P(N)在作用期间的不间断下拉，防止第一节点Q(N)和输出端G(N)的异常输出，该实施例中第一节点Q(N)的波形将不会为很明显的“凸”字形，在输出端G(N)输出完毕之后第一节点Q(N)的电位会在第一时间被下拉。The present invention adopts the output terminal G(N-1) of the upper N-1th GOA unit of the Nth stage GOA unit and the output terminal G(N) of the Nth stage GOA unit to perform upper and lower level transmission, thereby reducing TFT The number of pixels achieves the purpose of effectively saving layout and power consumption. 3 is a waveform diagram of waveform setting and key node output of a GOA circuit based on a low temperature polysilicon semiconductor thin film transistor of the present invention. As shown in FIG. 3, the first clock driving signal CKN and the second clock driving signal XCKN are clock driving signals of the circuit. As can be seen from FIG. 3, the duty ratio of the schematic waveform is close to 50/50, which is preferably occupied in actual design. The space ratio is 50/50, which is used to ensure the output terminal G(N-1) and the output terminal G(N) of the upper N-1th GOA unit of the Nth stage GOA unit to the second node P(N). During the uninterrupted pull-down during the action, the abnormal output of the first node Q(N) and the output terminal G(N) is prevented. In this embodiment, the waveform of the first node Q(N) will not be very obvious. In the glyph, the potential of the first node Q(N) is pulled down at the first time after the output G(N) is output.
综上所述，本发明的基于低温多晶硅半导体薄膜晶体管的GOA电路，在下拉维持电路部分采用高低电位反推设计，并设置依次降低的第一、第二、第三直流恒压低电位、及一直流恒压高电位，能够解决低温多晶硅半导体薄膜晶体管的自身特性对GOA驱动电路的影响，尤其是漏电问题带来的GOA功能性不良；同时解决了目前基于低温多晶硅半导体薄膜晶体管的GOA电路中下拉维持电路部分在非作用期间第二节点电位不能处于较高的电位的问题，有效维持第一节点和输出端的低电位。In summary, the GOA circuit based on the low temperature polysilicon semiconductor thin film transistor of the present invention adopts a high and low potential reverse push design in the pull-down sustaining circuit portion, and sets the first, second, and third DC constant voltage low potentials which are sequentially lowered, and A DC constant voltage high potential can solve the influence of the low-temperature polysilicon semiconductor thin film transistor's own characteristics on the GOA driving circuit, especially the GOA functionality caused by the leakage problem; and solve the current GOA circuit based on the low temperature polysilicon semiconductor thin film transistor. The problem that the second node potential cannot be at a higher potential during the non-active period of the pull-down sustain circuit portion effectively maintains the low potential of the first node and the output terminal.
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。 In the above, various other changes and modifications can be made in accordance with the technical solutions and technical concept of the present invention, and all such changes and modifications are within the scope of the claims of the present invention. .

Claims (9)

  1. 一种基于低温多晶硅半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分、一上拉部分、一第一下拉部分、和一下拉维持电路部分；A GOA circuit based on a low temperature polysilicon semiconductor thin film transistor, comprising a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit comprises a pull-up control portion, a pull-up portion, and a first pull-down portion And pull the sustain circuit part;
    所述上拉控制部分包括第一晶体管，其栅极与源极均电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端，漏极电性连接于第一节点；The pull-up control portion includes a first transistor, and a gate and a source thereof are electrically connected to an output end of the N-1th stage GOA unit of the upper stage of the Nth stage GOA unit, and the drain is electrically connected to the drain First node;
    所述上拉部分包括第二晶体管，其栅极电性连接于第一节点，源极电性连接于第一时钟驱动信号，漏极电性连接于输出端；The pull-up portion includes a second transistor having a gate electrically connected to the first node, a source electrically connected to the first clock driving signal, and a drain electrically connected to the output terminal;
    所述下拉维持电路部分电性连接于所述第一节点、所述第N级GOA单元的上一级第N-1级GOA单元的输出端、输出端、直流恒压高电位、及第一、第二、与第三直流恒压低电位；The pull-down maintaining circuit is electrically connected to the first node, the output end of the first-stage N-1th GOA unit of the Nth stage GOA unit, the output end, the DC constant voltage high potential, and the first , second, and third DC constant voltage low potential;
    所述下拉维持电路部分采用高低电位反推设计，包括：The pull-down sustain circuit portion adopts a high-low potential reverse push design, including:
    第三晶体管，所述第三晶体管的栅极和源极均电性连接于直流恒压高电位，漏极电性连接于第五晶体管的源极；a third transistor, the gate and the source of the third transistor are electrically connected to a DC constant voltage high potential, and the drain is electrically connected to the source of the fifth transistor;
    第四晶体管，所述第四晶体管的栅极电性连接于第三晶体管的漏极，源极电性连接于直流恒压高电位，漏极电性连接于第二节点；a fourth transistor, the gate of the fourth transistor is electrically connected to the drain of the third transistor, the source is electrically connected to the DC constant voltage high potential, and the drain is electrically connected to the second node;
    第五晶体管，所述第五晶体管的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端，源极电性连接于第三晶体管的漏极，漏极电性连接于第一直流恒压低电位；a fifth transistor, the gate of the fifth transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the drain of the third transistor The drain is electrically connected to the first DC constant voltage low potential;
    第六晶体管，所述第六晶体管的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端，源极电性连接于第二节点，漏极电性连接于第八晶体管的栅极；a sixth transistor, the gate of the sixth transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the second node and has a drain Electrically connected to the gate of the eighth transistor;
    第七晶体管，所述第七晶体管的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端，源极电性连接于第二节点，漏极电性连接于第八晶体管的源极；a seventh transistor, the gate of the seventh transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the second node and has a drain Electrically connected to the source of the eighth transistor;
    第八晶体管，所述第八晶体管的栅极电性连接于第十六晶体管的漏极，源极电性连接于第七晶体管的漏极，漏极电性连接于第三直流恒压低电位；An eighth transistor, the gate of the eighth transistor is electrically connected to the drain of the sixteenth transistor, the source is electrically connected to the drain of the seventh transistor, and the drain is electrically connected to the third DC constant voltage low potential ;
    第九晶体管，所述第九晶体管的栅极电性连接于第十六晶体管的漏极，源极电性连接于第十晶体管的栅极，漏极电性连接于第三直流恒压低电位；a ninth transistor, the gate of the ninth transistor is electrically connected to the drain of the sixteenth transistor, the source is electrically connected to the gate of the tenth transistor, and the drain is electrically connected to the third DC constant voltage low potential ;
    第十晶体管，所述第十晶体管的栅极电性连接于第九晶体管的源极，源极电性连接于直流恒压高电位，漏极电性连接于第七晶体管的漏极； a tenth transistor, the gate of the tenth transistor is electrically connected to the source of the ninth transistor, the source is electrically connected to the DC constant voltage high potential, and the drain is electrically connected to the drain of the seventh transistor;
    第十一晶体管，所述第十一晶体管的栅极与源极均电性连接于直流恒压高电位，漏极电性连接于第九晶体管的源极；An eleventh transistor, the gate and the source of the eleventh transistor are electrically connected to a DC constant voltage high potential, and the drain is electrically connected to the source of the ninth transistor;
    第十二晶体管，所述第十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；a twelfth transistor, the gate of the twelfth transistor is electrically connected to the second node, the source is electrically connected to the first node, and the drain is electrically connected to the second DC constant voltage low potential;
    第十三晶体管，所述第十三晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于第一直流恒压低电位；a thirteenth transistor, the gate of the thirteenth transistor is electrically connected to the second node, the source is electrically connected to the output end, and the drain is electrically connected to the first DC constant voltage low potential;
    第十五晶体管，所述第十五晶体管的栅极电性连接于输出端，源极电性连接于第四晶体管的栅极，漏极电性连接于第一直流恒压低电位；a fifteenth transistor, the gate of the fifteenth transistor is electrically connected to the output end, the source is electrically connected to the gate of the fourth transistor, and the drain is electrically connected to the first DC constant voltage low potential;
    第十六晶体管，所述第十六晶体管的栅极电性连接于输出端，源极电性连接于第二节点，漏极电性连接于第八晶体管的栅极；a sixteenth transistor, the gate of the sixteenth transistor is electrically connected to the output end, the source is electrically connected to the second node, and the drain is electrically connected to the gate of the eighth transistor;
    所述第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管提供正向高电位，用于控制第十二晶体管和第十三晶体管的打开；所述第八晶体管、第九晶体管构成作用期间的负电位的反向自举，用于在作用期间向第二节点提供更低电位；利用直流恒压高电位在非作用期间向第二节点提供适当的高电位，使得第一节点与输出端维持低电位；The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor provide a positive high potential for controlling opening of the twelfth transistor and the thirteenth transistor; the eighth transistor, the ninth transistor The transistor constitutes a reverse bootstrap of a negative potential during operation for providing a lower potential to the second node during operation; providing a suitable high potential to the second node during the inactive period using the DC constant voltage high potential, such that the first The node and the output maintain a low potential;
    所述第一下拉部分电性连接于所述第一节点、第二时钟驱动信号及第二直流恒压低电位，所述第一下拉部分依据第二时钟驱动信号下拉所述第一节点的电位至所述第二直流恒压低电位；The first pull-down portion is electrically connected to the first node, the second clock driving signal, and the second DC constant voltage low potential, and the first pull-down portion pulls down the first node according to the second clock driving signal a potential to the second DC constant voltage low potential;
    所述第一下拉部分包括一第十四晶体管，所述第十四晶体管的栅极电性连接于第二时钟驱动信号，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；The first pull-down portion includes a fourteenth transistor, the gate of the fourteenth transistor is electrically connected to the second clock driving signal, the source is electrically connected to the first node, and the drain is electrically connected to the first Two DC constant voltage low potential;
    所述第三直流恒压低电位<第二直流恒压低电位<第一直流恒压低电位。The third DC constant voltage low potential <the second DC constant voltage low potential < the first DC constant voltage low potential.
  2. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，所述第四晶体管、第七晶体管、与第八晶体管串联。A low temperature polysilicon semiconductor thin film transistor-based GOA circuit according to claim 1, wherein said fourth transistor, said seventh transistor, and said eighth transistor are connected in series.
  3. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，还包括一上升部分，所述上升部分电性连接于所述第一节点与输出端之间，用来抬升所述第一节点的电位。The low temperature polysilicon semiconductor thin film transistor-based GOA circuit of claim 1 further comprising a rising portion electrically connected between said first node and said output terminal for raising said first node Potential.
  4. 如权利要求3所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，所述上升部分包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于输出端。The low temperature polysilicon semiconductor thin film transistor-based GOA circuit of claim 3, wherein the rising portion comprises a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the output end.
  5. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，第一时钟驱动信号与第二时钟驱动信号的波形占空比接近50/50；在第二时钟驱动信号的高电位期间，所述第十四晶体管下拉所述第一节点 的电位至所述第二直流恒压低电位。The low temperature polysilicon semiconductor thin film transistor-based GOA circuit according to claim 1, wherein a waveform duty ratio of the first clock driving signal and the second clock driving signal is close to 50/50; during a high potential period of the second clock driving signal The fourteenth transistor pulls down the first node The potential is low to the second DC constant voltage.
  6. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，所述GOA电路的第一级连接关系中，第一晶体管的栅极与源极均电性连接于电路的启动信号端，第五、第六、第七晶体管的栅极均电性连接于电路的启动信号端。The low-temperature polysilicon semiconductor thin film transistor-based GOA circuit according to claim 1, wherein in the first-stage connection relationship of the GOA circuit, the gate and the source of the first transistor are electrically connected to the start signal end of the circuit. The gates of the fifth, sixth, and seventh transistors are electrically connected to the start signal end of the circuit.
  7. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，用输出端和所述第N级GOA单元的上一级第N-1级GOA单元的输出端来控制下拉维持电路部分。The low temperature polysilicon semiconductor thin film transistor-based GOA circuit according to claim 1, wherein the output terminal and the output terminal of the upper N-1th GOA unit of the Nth stage GOA unit control the pull-down sustain circuit portion .
  8. 如权利要求1所述的基于低温多晶硅半导体薄膜晶体管的GOA电路，其中，所述GOA电路采用输出端的输出信号作为上下级传信号。A low temperature polysilicon semiconductor thin film transistor-based GOA circuit according to claim 1, wherein said GOA circuit uses an output signal of the output terminal as a signal for transmitting the upper and lower stages.
  9. 一种基于低温多晶硅半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元，设N为正整数，第N级GOA单元包括一上拉控制部分、一上拉部分、一第一下拉部分、和一下拉维持电路部分；A GOA circuit based on a low temperature polysilicon semiconductor thin film transistor, comprising a plurality of cascaded GOA units, wherein N is a positive integer, and the Nth stage GOA unit comprises a pull-up control portion, a pull-up portion, and a first pull-down portion And pull the sustain circuit part;
    所述上拉控制部分包括第一晶体管，其栅极与源极均电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端，漏极电性连接于第一节点；The pull-up control portion includes a first transistor, and a gate and a source thereof are electrically connected to an output end of the N-1th stage GOA unit of the upper stage of the Nth stage GOA unit, and the drain is electrically connected to the drain First node;
    所述上拉部分包括第二晶体管，其栅极电性连接于第一节点，源极电性连接于第一时钟驱动信号，漏极电性连接于输出端；The pull-up portion includes a second transistor having a gate electrically connected to the first node, a source electrically connected to the first clock driving signal, and a drain electrically connected to the output terminal;
    所述下拉维持电路部分电性连接于所述第一节点、所述第N级GOA单元的上一级第N-1级GOA单元的输出端、输出端、直流恒压高电位、及第一、第二、与第三直流恒压低电位；The pull-down maintaining circuit is electrically connected to the first node, the output end of the first-stage N-1th GOA unit of the Nth stage GOA unit, the output end, the DC constant voltage high potential, and the first , second, and third DC constant voltage low potential;
    所述下拉维持电路部分采用高低电位反推设计，包括：The pull-down sustain circuit portion adopts a high-low potential reverse push design, including:
    第三晶体管，所述第三晶体管的栅极和源极均电性连接于直流恒压高电位，漏极电性连接于第五晶体管的源极；a third transistor, the gate and the source of the third transistor are electrically connected to a DC constant voltage high potential, and the drain is electrically connected to the source of the fifth transistor;
    第四晶体管，所述第四晶体管的栅极电性连接于第三晶体管的漏极，源极电性连接于直流恒压高电位，漏极电性连接于第二节点；a fourth transistor, the gate of the fourth transistor is electrically connected to the drain of the third transistor, the source is electrically connected to the DC constant voltage high potential, and the drain is electrically connected to the second node;
    第五晶体管，所述第五晶体管的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端，源极电性连接于第三晶体管的漏极，漏极电性连接于第一直流恒压低电位；a fifth transistor, the gate of the fifth transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the drain of the third transistor The drain is electrically connected to the first DC constant voltage low potential;
    第六晶体管，所述第六晶体管的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端，源极电性连接于第二节点，漏极电性连接于第八晶体管的栅极；a sixth transistor, the gate of the sixth transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the second node and has a drain Electrically connected to the gate of the eighth transistor;
    第七晶体管，所述第七晶体管的栅极电性连接于所述第N级GOA单元的上一级第N-1级GOA单元的输出端，源极电性连接于第二节点，漏极电 性连接于第八晶体管的源极；a seventh transistor, the gate of the seventh transistor is electrically connected to an output end of the N-1th GOA unit of the upper stage of the Nth stage GOA unit, and the source is electrically connected to the second node and has a drain Electricity Connected to the source of the eighth transistor;
    第八晶体管，所述第八晶体管的栅极电性连接于第十六晶体管的漏极，源极电性连接于第七晶体管的漏极，漏极电性连接于第三直流恒压低电位；An eighth transistor, the gate of the eighth transistor is electrically connected to the drain of the sixteenth transistor, the source is electrically connected to the drain of the seventh transistor, and the drain is electrically connected to the third DC constant voltage low potential ;
    第九晶体管，所述第九晶体管的栅极电性连接于第十六晶体管的漏极，源极电性连接于第十晶体管的栅极，漏极电性连接于第三直流恒压低电位；a ninth transistor, the gate of the ninth transistor is electrically connected to the drain of the sixteenth transistor, the source is electrically connected to the gate of the tenth transistor, and the drain is electrically connected to the third DC constant voltage low potential ;
    第十晶体管，所述第十晶体管的栅极电性连接于第九晶体管的源极，源极电性连接于直流恒压高电位，漏极电性连接于第七晶体管的漏极；a tenth transistor, the gate of the tenth transistor is electrically connected to the source of the ninth transistor, the source is electrically connected to the DC constant voltage high potential, and the drain is electrically connected to the drain of the seventh transistor;
    第十一晶体管，所述第十一晶体管的栅极与源极均电性连接于直流恒压高电位，漏极电性连接于第九晶体管的源极；An eleventh transistor, the gate and the source of the eleventh transistor are electrically connected to a DC constant voltage high potential, and the drain is electrically connected to the source of the ninth transistor;
    第十二晶体管，所述第十二晶体管的栅极电性连接于第二节点，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；a twelfth transistor, the gate of the twelfth transistor is electrically connected to the second node, the source is electrically connected to the first node, and the drain is electrically connected to the second DC constant voltage low potential;
    第十三晶体管，所述第十三晶体管的栅极电性连接于第二节点，源极电性连接于输出端，漏极电性连接于第一直流恒压低电位；a thirteenth transistor, the gate of the thirteenth transistor is electrically connected to the second node, the source is electrically connected to the output end, and the drain is electrically connected to the first DC constant voltage low potential;
    第十五晶体管，所述第十五晶体管的栅极电性连接于输出端，源极电性连接于第四晶体管的栅极，漏极电性连接于第一直流恒压低电位；a fifteenth transistor, the gate of the fifteenth transistor is electrically connected to the output end, the source is electrically connected to the gate of the fourth transistor, and the drain is electrically connected to the first DC constant voltage low potential;
    第十六晶体管，所述第十六晶体管的栅极电性连接于输出端，源极电性连接于第二节点，漏极电性连接于第八晶体管的栅极；a sixteenth transistor, the gate of the sixteenth transistor is electrically connected to the output end, the source is electrically connected to the second node, and the drain is electrically connected to the gate of the eighth transistor;
    所述第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管提供正向高电位，用于控制第十二晶体管和第十三晶体管的打开；所述第八晶体管、第九晶体管构成作用期间的负电位的反向自举，用于在作用期间向第二节点提供更低电位；利用直流恒压高电位在非作用期间向第二节点提供适当的高电位，使得第一节点与输出端维持低电位；The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor provide a positive high potential for controlling opening of the twelfth transistor and the thirteenth transistor; the eighth transistor, the ninth transistor The transistor constitutes a reverse bootstrap of a negative potential during operation for providing a lower potential to the second node during operation; providing a suitable high potential to the second node during the inactive period using the DC constant voltage high potential, such that the first The node and the output maintain a low potential;
    所述第一下拉部分电性连接于所述第一节点、第二时钟驱动信号及第二直流恒压低电位，所述第一下拉部分依据第二时钟驱动信号下拉所述第一节点的电位至所述第二直流恒压低电位；The first pull-down portion is electrically connected to the first node, the second clock driving signal, and the second DC constant voltage low potential, and the first pull-down portion pulls down the first node according to the second clock driving signal a potential to the second DC constant voltage low potential;
    所述第一下拉部分包括一第十四晶体管，所述第十四晶体管的栅极电性连接于第二时钟驱动信号，源极电性连接于第一节点，漏极电性连接于第二直流恒压低电位；The first pull-down portion includes a fourteenth transistor, the gate of the fourteenth transistor is electrically connected to the second clock driving signal, the source is electrically connected to the first node, and the drain is electrically connected to the first Two DC constant voltage low potential;
    所述第三直流恒压低电位<第二直流恒压低电位)<第一直流恒压低电位；The third DC constant voltage low potential <the second DC constant voltage low potential> <the first DC constant voltage low potential;
    还包括一上升部分，所述上升部分电性连接于所述第一节点与输出端之间，用来抬升所述第一节点的电位；a rising portion electrically connected between the first node and the output terminal for raising the potential of the first node;
    其中，所述上升部分包括一电容，所述电容的一端电性连接于第一节点，另一端电性连接于输出端； The rising portion includes a capacitor, one end of the capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
    其中，第一时钟驱动信号与第二时钟驱动信号的波形占空比接近50/50；在第二时钟驱动信号的高电位期间，所述第十四晶体管下拉所述第一节点的电位至所述第二直流恒压低电位。 The waveform duty ratio of the first clock driving signal and the second clock driving signal is close to 50/50; during the high potential of the second clock driving signal, the fourteenth transistor pulls down the potential of the first node to the The second DC constant voltage is low.
PCT/CN2015/072354 2014-11-03 2015-02-06 Low-temperature polycrystalline silicon semiconductor thin-film transistor-based goa circuit WO2016070509A1 (en)

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JP2017519240A JP6317528B2 (en) 2014-11-03 2015-02-06 GOA circuit based on low temperature polysilicon semiconductor thin film transistor
GB1703516.3A GB2546647B (en) 2014-11-03 2015-02-06 GOA circuit based on LTPS semiconductor TFT
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10510314B2 (en) * 2017-10-11 2019-12-17 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. GOA circuit having negative gate-source voltage difference of TFT of pull down module
CN108806584B (en) * 2018-07-27 2021-02-12 京东方科技集团股份有限公司 Shifting register unit, driving method, grid driving circuit and display device
CN110189680B (en) * 2019-06-24 2021-02-09 京东方科技集团股份有限公司 Shifting register unit, driving method, grid driving circuit and display device
CN113035109B (en) * 2021-02-25 2024-05-17 福建华佳彩有限公司 GIP driving circuit of embedded display screen and control method thereof
CN113327537B (en) * 2021-06-17 2022-08-16 北京京东方显示技术有限公司 Shift register, grid drive circuit and display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007048382A (en) * 2005-08-10 2007-02-22 Mitsubishi Electric Corp Sift register
US20080187089A1 (en) * 2007-02-07 2008-08-07 Mitsubishi Electric Corporation Semiconductor device and shift register circuit
CN101587752A (en) * 2008-12-15 2009-11-25 友达光电股份有限公司 Displacement register
CN101833997A (en) * 2009-09-23 2010-09-15 友达光电股份有限公司 Pull-down control circuit and shift register using the same
CN102629463A (en) * 2012-03-29 2012-08-08 京东方科技集团股份有限公司 Shift register unit, shift register circuit, array substrate and display device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100803163B1 (en) * 2001-09-03 2008-02-14 삼성전자주식회사 Liquid crystal display apparatus
KR100857495B1 (en) * 2002-07-06 2008-09-08 삼성전자주식회사 Method for driving shift resister for driving amorphous-silicon thin film transistor gate
US7310402B2 (en) * 2005-10-18 2007-12-18 Au Optronics Corporation Gate line drivers for active matrix displays
JP2010086637A (en) * 2008-10-02 2010-04-15 Mitsubishi Electric Corp Shift register circuit and image display device with the same
KR101587610B1 (en) * 2009-09-21 2016-01-25 삼성디스플레이 주식회사 Driving circuit
KR101641312B1 (en) * 2009-12-18 2016-07-21 삼성디스플레이 주식회사 Display panel
KR20120038693A (en) * 2010-10-14 2012-04-24 이대천 Glass for display eching installation used un-loading device
KR101186996B1 (en) * 2010-10-28 2012-09-28 엄우식 System of spraying viscosity liquid damping material
CN102708778B (en) * 2011-11-28 2014-04-23 京东方科技集团股份有限公司 Shift register and drive method thereof, gate drive device and display device
KR101963595B1 (en) * 2012-01-12 2019-04-01 삼성디스플레이 주식회사 Gate driver and display apparatus having the same
TWI511459B (en) * 2012-10-11 2015-12-01 Au Optronics Corp Gate driving circuit capable of preventing current leakage
KR102084716B1 (en) * 2013-03-13 2020-03-05 삼성디스플레이 주식회사 Display panel
CN104036725B (en) * 2014-05-29 2017-10-03 京东方科技集团股份有限公司 Image element circuit and its driving method, organic electroluminescence display panel and display device
CN104282265B (en) * 2014-09-26 2017-02-01 京东方科技集团股份有限公司 Pixel circuit, drive method thereof, an organic light-emitting display panel and display device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007048382A (en) * 2005-08-10 2007-02-22 Mitsubishi Electric Corp Sift register
US20080187089A1 (en) * 2007-02-07 2008-08-07 Mitsubishi Electric Corporation Semiconductor device and shift register circuit
CN101587752A (en) * 2008-12-15 2009-11-25 友达光电股份有限公司 Displacement register
CN101833997A (en) * 2009-09-23 2010-09-15 友达光电股份有限公司 Pull-down control circuit and shift register using the same
CN102629463A (en) * 2012-03-29 2012-08-08 京东方科技集团股份有限公司 Shift register unit, shift register circuit, array substrate and display device

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