WO2016061891A1 - 一种斜坡波产生电路及其数模转换电路、指纹识别系统 - Google Patents

一种斜坡波产生电路及其数模转换电路、指纹识别系统 Download PDF

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WO2016061891A1
WO2016061891A1 PCT/CN2014/095016 CN2014095016W WO2016061891A1 WO 2016061891 A1 WO2016061891 A1 WO 2016061891A1 CN 2014095016 W CN2014095016 W CN 2014095016W WO 2016061891 A1 WO2016061891 A1 WO 2016061891A1
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Prior art keywords
circuit
signal
ramp wave
output
wave signal
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PCT/CN2014/095016
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English (en)
French (fr)
Inventor
陈松涛
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to KR1020167022286A priority Critical patent/KR101847515B1/ko
Priority to EP14904513.0A priority patent/EP3211793B1/en
Publication of WO2016061891A1 publication Critical patent/WO2016061891A1/zh
Priority to US15/248,621 priority patent/US9953203B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
    • H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
    • H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
    • H03K4/501—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator
    • H03K4/502—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator the capacitor being charged from a constant-current source
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/20—Image preprocessing
    • G06V10/28—Quantising the image, e.g. histogram thresholding for discrimination between background and foreground patterns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56—Input signal compared with linear ramp

Definitions

  • the present invention relates to the field of fingerprint recognition technologies, and in particular, to a ramp wave generating circuit, a digital-to-analog conversion circuit thereof, and a fingerprint identification system.
  • the capacitive fingerprint sensing system generally adopts a fingerprint sensing pixel circuit as a basic unit, and the Pixel circuit extracts the capacitive coupling signal of each pixel point, and then sends it to other parts of the fingerprint sensing system for amplification, analog-to-digital conversion, image stitching, etc. Extract valid fingerprint information.
  • the prior art processes the pixel array data reading problem in three ways: global analog to digital conversion, local analog to digital conversion, or row/column analog to digital conversion.
  • the digital-to-analog conversion circuit is adopted, and the ramp wave generating circuit and the clock generator in the digital-to-analog conversion circuit are susceptible to PVT (Process/Voltage/Temperature, production process/voltage/temperature). This leads to a deterioration in the performance of the fingerprint recognition system.
  • PVT Process/Voltage/Temperature, production process/voltage/temperature
  • the technical problem to be solved by the present invention is to provide a ramp wave generating circuit, a digital-to-analog conversion circuit thereof, and a fingerprint identification system to solve the problem that the slope wave generating circuit and the clock generator in the prior art are affected by the PVT.
  • a ramp wave generating circuit comprising: an integrating circuit for outputting a ramp wave signal; a signal adjusting circuit comprising a feedback control loop and a transconductance amplifier connected in series, the feedback control loop monitoring a ramp wave signal output by the integrating circuit, and outputting an adjustment control signal to the transconductance amplifier, wherein the transconductance amplifier corrects a ramp wave signal outputted by the integration circuit in a next cycle according to the adjustment signal; Generating circuits for respectively respectively to the integrating circuit and the The signal adjustment circuit outputs a reference voltage signal.
  • the integrating circuit comprising a first bidirectional switch, a second bidirectional switch, a third dual switch, a ramp wave signal generating capacitor, and a first high gain operational amplifier: the first bidirectional switch is connected Between the negative pole and the output end of the first high gain operational amplifier; the ramp wave generating capacitor has one end connected to the negative pole of the first high gain operational amplifier, and the other end is connected to the first through the second bidirectional switch An output of the high gain operational amplifier is connected; one end of the third bidirectional switch is connected to the voltage generating circuit, and the other end is connected between the ramp wave signal generating capacitor and the second bidirectional switch.
  • a circuit as described above wherein the first bidirectional switch, the second bidirectional switch, and the third dual switch are respectively controlled by two inverted signals that do not overlap.
  • the transconductance amplifier comprising an error holding capacitor and an NMOS transistor, wherein a gate of the NMOS transistor is connected to an output of the feedback control loop, and the other two poles are grounded, and the other A negative terminal of the first high gain operational amplifier of the integrating circuit is coupled to provide an error correction current to the integrating circuit.
  • the feedback control loop includes an error amplifier, a positive pole of the error amplifier is connected to a ramp wave signal output end of the integrating circuit, a negative pole is connected to the voltage generating circuit, and an output terminal is The transconductance amplifier is connected.
  • the voltage generating circuit comprises a second high gain operational amplifier, a current mirror circuit and a first matching resistor, a second matching resistor, and a third matching resistor:
  • the current mirror circuit is composed of two a PMOS transistor connected in a current mirror manner, the first connection end of which is connected to the output end of the second high gain operational amplifier, the first connection end of the first matching resistor, and the anode of the first high gain amplifier of the integration circuit
  • the second connection end is connected to the first connection end of the second matching resistor and the voltage input end of the signal adjustment circuit; the first connection end of the third matching resistor and the second connection end of the second matching resistor
  • the connection end is connected to the first connection end of the third bidirectional switch of the integration circuit, the second connection end is connected to the second connection end of the first matching resistor, and is grounded; the negative pole and the output of the second high gain operational amplifier End connection.
  • a fingerprint recognition system comprising a digital to analog conversion circuit comprising a ramp wave generating circuit as described above.
  • a digital to analog conversion circuit comprising a ramp wave generating circuit, a control circuit, a fingerprint signal/hold circuit, a comparator, a clock generator and an N-bit counter as described above: said control a circuit for controlling the ramp wave generating circuit and the N-bit counter to start working simultaneously; the ramp wave generating circuit for outputting a ramp wave signal to the comparator under the control of the control circuit; a signal/hold circuit for outputting the enhanced pixel-sensing signal to the comparator; the comparator for comparing the ramp wave signal and the pixel-sensing signal to the N- a bit counter output signal, and for inverting the output signal when the ramp wave signal is equal to the pixel sense signal; the N-bit counter is used to start working under the control of the control circuit, and The output signal of the comparator is latched when the output signal is inverted, so as to obtain the ADC output codeword signal after the conversion; the clock generator is provided for the digital-to-ana
  • a fingerprint identification system of the present invention is provided with a signal adjustment circuit in a ramp wave generating circuit, which monitors a ramp wave signal generated by the integrating circuit through a feedback control loop in the signal adjusting circuit, and then outputs an adjustment control to the transconductance amplifier
  • the signal corrects the ramp wave signal outputted in the next cycle of the integration circuit, and can automatically adjust the highest point voltage value of the output ramp wave signal, so that the amplitude of the output ramp wave signal is independent of the PVT change, eliminating the PVT Impact.
  • the circuit is simple to implement, there is no requirement for the capacitor material, and the production cost is reduced.
  • the circuit when the circuit is applied to the fingerprint recognition system, it can adapt to the change of the system clock frequency. When the clock frequency changes, the slope of the generated ramp wave signal changes to the single slope ramp ADC gain error, resolution, INL (integration Performance indicators such as nonlinearity and DNL (differential nonlinearity) do not affect.
  • FIG. 1 is a schematic diagram of a connection of a ramp wave generating circuit according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of an automatic tracking-correction mechanism of the ramp wave generating circuit of FIG. 1 during a plurality of ramp wave generating phases;
  • Figure 3 is a schematic diagram of a single slope ramp ADC
  • FIG. 4 is a schematic diagram of circuit connections when the feedback control loop is constructed using an error amplifier in FIG. 1;
  • FIG. 5 is a schematic diagram of another connection of a ramp wave generating circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a digital to analog conversion circuit according to an embodiment of the present invention.
  • the present invention provides a ramp wave generating circuit.
  • the ramp wave signal generated by the ramp wave generating circuit is a single slope ramp wave signal, which includes an integrating circuit 100, a signal adjusting circuit 200, and a voltage generating circuit.
  • the integration circuit 100 is configured to output a ramp wave signal.
  • the integrating circuit 100 includes a first bidirectional switch 110, a second bidirectional switch 121, a third dual switch 130, a ramp wave signal generating capacitor 140, and a first high gain operational amplifier 150.
  • the first bidirectional switch 110 is coupled between the negative terminal and the output terminal of the first high gain operational amplifier 150.
  • One end of the ramp wave generating capacitor 140 is connected to the cathode of the first high gain operational amplifier 150, and the other end is connected to the output of the first high gain operational amplifier through the second bidirectional switch 120.
  • the third bidirectional switch 130 has one end connected to the voltage generating circuit 300 and the other end connected between the ramp wave signal generating capacitor 140 and the second bidirectional switch 120.
  • the first bidirectional switch 110, the second bidirectional switch 120, and the third dual switch 130 are respectively controlled by two inverted signals that do not overlap, that is, the three bidirectional switches are not Will be in the same state at the same time.
  • the signal conditioning circuit 200 is comprised of a series feedback control loop 210 and a transconductance amplifier 220.
  • the feedback control loop 210 monitors the ramp wave signal output by the integrating circuit 100, and outputs an adjustment control signal to the transconductance amplifier 220, and the slope of the next cycle output of the integrating circuit 100 by the transconductance amplifier 220 according to the adjustment signal. The wave signal is corrected.
  • a voltage generating circuit configured to output a reference voltage signal to the integrating circuit and the signal adjusting circuit, respectively.
  • the ramp wave generating circuit works as follows:
  • the ramp wave generating capacitor 140 has no charge.
  • the output signal 301 of the voltage generating circuit 300 is V SET — STOP
  • the output signal 302 is V SET — VCM
  • the output signal 303 is V SET — START .
  • the output ramp signal 101 linearly rises from the voltage V SET — START each time.
  • the feedback control loop 210 monitors the "end value" of the output ramp wave signal 101 of the integrating circuit 100 (ie, the highest point voltage V RAMP_END of the generated ramp wave signal) and the voltage generating circuit 300
  • the output signal 301 is the difference between V SET — STOP
  • the adjustment control signal 201 is output to the transconductance amplifier 220, thereby correcting the charging current of the ramp wave signal generating capacitor 140 that generates the ramp wave signal in the next cycle.
  • This tracking-correction mechanism will be described in detail by taking one of the ramp wave signal 101 generation processes as an example.
  • the bidirectional switch circuit 120 During the output of the ramp wave signal 101, the bidirectional switch circuit 120 is in an on state, and the bidirectional switch circuits 110 and 130 are in an off state; the transconductance amplifier 220 continues to output under the action of the adjustment control signal 201 output from the feedback control loop 210.
  • the steady charging current causes the voltage across the ramp wave signal generating capacitor 140 to rise. It is assumed that the output current change amount of the transconductance amplifier 220 is ⁇ I after the "tracking-correction" process of the previous cycle.
  • g m represents the transconductance of the transconductance amplifier 220
  • ⁇ V error represents the difference between the V RAMP_END and the set value V SET — STOP at the end of the ramp-wave output stage of the previous period.
  • the capacitance value of the ramp wave signal generating capacitor 140 is set to C R , and the ramp wave generating phase duration is T RAMP , then
  • equation (2) above can be established, that is, the ramp wave generating circuit in FIG. 1 will output a stable and accurate ramp wave signal.
  • feedback control loop 210 reduces the output current of transconductance amplifier 220 under the action of a negative feedback mechanism, thereby reducing ⁇ V error at the end of the next cycle. It is foreseeable that after several consecutive cycles, the above formula (2) must be established.
  • feedback control loop 210 increases the output current of transconductance amplifier 220 under the action of a negative feedback mechanism, thereby reducing ⁇ V error at the end of the next cycle. It is foreseeable that after several consecutive cycles, the above formula (2) must be established.
  • feedback control loop 210 increases the output current of transconductance amplifier 220 under the action of a negative feedback mechanism, thereby reducing ⁇ V error at the end of the next cycle. It is foreseeable that after several consecutive cycles, the above formula (2) must be established.
  • the ramp wave generating circuit in Fig. 1 can always output an accurate and stable ramp wave signal, that is, the generated ramp wave signal amplitude ⁇ V RAMP Not related to PVT changes.
  • V SIG is the analog voltage input to the single-slope ramp ADC circuit
  • D SIG is the corresponding quantized output code word
  • the circuit in Figure 1 can always output an accurate and stable ramp wave signal, that is, the generated ramp wave signal amplitude ⁇ V RAMP has nothing to do with the PVT change, and combined with the formula (6), the use map
  • the performance of the single-slope ramp ADC of the 1 ramp-wave generation circuit is also independent of the PVT variation.
  • the feedback control loop 210 of the signal adjustment circuit 200 may be composed only of the error amplifier 211.
  • the positive terminal of the error amplifier 211 is connected to the ramp wave signal output end of the integrating circuit, the negative electrode is connected to the voltage generating circuit, and the output terminal is connected to the transconductance amplifier.
  • the ramp wave generating circuit provided in this embodiment is provided with a signal adjusting circuit for monitoring a ramp wave signal generated by the integrating circuit through a feedback control loop in the signal adjusting circuit, and then outputting an adjustment control signal to the transconductance amplifier, the integrating circuit
  • the ramp signal outputted in the next cycle is corrected, and the highest point voltage value of the output ramp wave signal can be automatically adjusted, so that the amplitude of the output ramp wave signal is independent of the PVT variation, and the influence due to PVT is eliminated.
  • the circuit is simple to implement, and there is no capacitance material. Requirements reduce production costs.
  • the circuit when the circuit is applied to the fingerprint recognition system, it can adapt to the change of the system clock frequency. When the clock frequency changes, the slope of the generated ramp wave signal changes to the single slope ramp ADC gain error, resolution, INL (integration Performance indicators such as nonlinearity and DNL (differential nonlinearity) do not affect.
  • the ramp wave generating circuit includes an integrating circuit 100, a signal adjusting circuit 200, and a voltage generating circuit.
  • the integration circuit 100 is configured to output a ramp wave signal.
  • the integrating circuit 100 includes a first bidirectional switch 110, a second bidirectional switch 121, a third dual switch 130, a ramp wave signal generating capacitor 140, and a first high gain operational amplifier 150.
  • the first bidirectional switch 110 is coupled between the negative terminal and the output terminal of the first high gain operational amplifier 150.
  • One end of the ramp wave signal generating capacitor 140 is connected to the negative terminal of the first high gain operational amplifier 150, and the other end is connected to the output end of the first high gain operational amplifier 150 through the second bidirectional switch 120.
  • the first connection end 131 of the third bidirectional switch 130 is connected to the first connection end 351 of the third matching resistor 350 of the voltage generating circuit 300, and the other end is connected to the ramp wave signal generating capacitor 140 and the second bidirectional switch 120. between. It should be noted that, in the integrating circuit, the first bidirectional switch 110, the second bidirectional switch 120, and the third dual switch 130 are respectively controlled by two inverted signals that do not overlap, that is, the three bidirectional switches are not Will be in the same state at the same time.
  • the signal conditioning circuit consists of a series feedback control loop 210 and a transconductance amplifier 220.
  • the feedback control loop 210 monitors the ramp wave signal output by the integrating circuit 100, and outputs an adjustment control signal to the transconductance amplifier 220, and the slope of the next cycle output of the integrating circuit 100 by the transconductance amplifier 220 according to the adjustment signal. The wave signal is corrected.
  • the transconductance amplifier 220 includes an error holding capacitor 221 and an NMOS transistor 222. The gate of the NMOS transistor 222 is connected to the output of the feedback control loop 210, the other two poles are grounded, and the other is connected to the cathode of the first high gain operational amplifier 150 of the integrating circuit 100, and the error correction is provided to the integrating circuit 100. Current.
  • the error correction current provided by NMOS transistor 222 is determined by feedback control circuit 210
  • the voltage generating circuit 300 is configured to output a reference voltage signal to the integrating circuit and the signal adjusting circuit, respectively.
  • the voltage generating circuit 300 includes a second high gain operational amplifier 310, a current mirror circuit 320 and a first matching resistor 330, a second matching resistor 340, and a third matching resistor 350.
  • the current mirror circuit 320 is composed of two PMOS transistors connected by a current mirror.
  • the first connection end 321 and the output end of the second high gain operational amplifier 310, the first connection end 331 of the first matching resistor 330 and The positive connection of the first high gain amplifier 150 of the integration circuit 100 is connected to the first connection end 341 of the second matching resistor 340 and the voltage input end of the signal adjustment circuit 210; the third matching resistor 350
  • the first connection end 351 is connected to the second connection end 342 of the second matching resistor and the first connection end 131 of the third bidirectional switch 130 of the integration circuit 100.
  • the second connection end 352 of the third matching resistor 350 is The second connection end 332 of the first matching resistor 330 is connected and grounded; the negative terminal of the second high gain operational amplifier 310 is connected to the output end.
  • the ramp wave generating circuit of this embodiment is provided with a signal adjusting circuit for monitoring a ramp wave signal generated by the integrating circuit through a feedback control loop in the signal adjusting circuit, and then outputting an adjustment control signal to the transconductance amplifier, the next cycle of the integrating circuit
  • the output ramp signal is corrected to automatically adjust the highest point voltage of the output ramp signal, so that the amplitude of the output ramp signal is independent of the PVT variation, eliminating the effects of PVT.
  • three matching resistors are set in the voltage generating circuit. When the mutual ratio of the matching resistors is changed, the amplitude of the reference voltage can be flexibly changed within a large range.
  • the present invention further provides a fingerprint identification system, the system comprising a digital-to-analog conversion circuit for performing digital-to-analog conversion on a signal collected by a fingerprint-sensing pixel circuit.
  • the digital to analog conversion circuit includes:
  • the control circuit 601 is configured to control the ramp wave generating circuit 602 and the N-bit counter 603 to start working at the same time;
  • the ramp wave generating circuit 602 may adopt one of the above embodiments;
  • a fingerprint signal/hold circuit 605, configured to output the enhanced pixel processed signal to the comparator 604;
  • the comparator 604 is configured to compare the ramp wave signal and the pixel sensing signal, and output the signal to the N-bit counter 603, and to invert the output signal when the ramp wave signal is equal to the pixel sensing signal;
  • the N-bit counter 603 is configured to start operation under the control of the control circuit 601, and latch the count value when the output signal of the comparator 604 is inverted, so as to obtain the ADC output codeword signal ADC_OUT ⁇ N:1 after the current conversion. >;
  • a clock generator 606 is provided for providing a timing reference for the digital to analog conversion circuit.
  • a signal adjustment circuit is disposed in the ramp wave generation circuit, and the ramp wave signal generated by the integration circuit is monitored by a feedback control loop in the signal adjustment circuit, and then the adjustment control signal is output to the transconductance amplifier.
  • the ramp wave signal outputted in the next cycle of the integration circuit is corrected, so that the stability of the ramp wave signal generated by the integration circuit can be ensured, and the influence due to PVT is eliminated.
  • the invention provides a ramp wave generating circuit, a digital-to-analog conversion circuit thereof and a fingerprint identification system.
  • the signal adjusting circuit is arranged in the ramp wave generating circuit, and the slope generated by the integrating circuit is monitored by a feedback control loop in the signal adjusting circuit.
  • the wave signal is then output to the transconductance amplifier to adjust the control signal, and the ramp signal outputted by the integration circuit in the next cycle is corrected, and the highest point voltage value of the output ramp wave signal can be automatically adjusted, thereby outputting the ramp wave signal.
  • the amplitude is independent of PVT changes, eliminating the effects of PVT. And the circuit is simple to implement, there is no requirement for the capacitor material, and the production cost is reduced.
  • the circuit when the circuit is applied to the fingerprint recognition system, it can adapt to the change of the system clock frequency.
  • the clock frequency changes the slope of the generated ramp wave signal changes to the single slope ramp ADC gain error, resolution, INL (integration Performance indicators such as nonlinearity and DNL (differential nonlinearity) do not affect.

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Abstract

一种斜坡波产生电路及其数模转换电路、指纹识别系统，属于指纹识别技术领域。该电路包括：积分电路（100），用于输出斜坡波信号；信号调整电路（200），包括串联的反馈控制环路（210）和跨导放大器（220），所述反馈控制环路（210）监测所述积分电路（100）输出的斜坡波信号，并向所述跨导放大器（220）输出调整控制信号，由所述跨导放大器（220）根据所述调整控制信号对所述积分电路（100）下一周期输出的斜坡波信号进行修正；电压产生电路（300），用于分别向所述积分电路（100）及所述信号调整电路（200）输出参考电压信号。采用该指纹识别系统，可以解决现有技术中斜坡波产生电路和时钟发生器因受到PVT的影响而导致指纹系统性能恶化的问题。

Description

一种斜坡波产生电路及其数模转换电路、指纹识别系统 技术领域
本发明涉及指纹识别技术领域，尤其涉及一种斜坡波产生电路及其数模转换电路、指纹识别系统。
背景技术
随着安全技术的发展，指纹识别越来越收到人们的重视，其应用的领域也越来越广。电容式指纹感应系统一般采用指纹感应像素(pixel)电路作为基本单元，Pixel电路提取每个像素点的电容耦合信号，再送入指纹感应系统的其他部分进行放大，模数转换，图像拼接等操作，提取出有效的指纹信息。现有技术处理pixel阵列数据读取这个问题通常采用如下三种方式：全局模数转换、本地模数转换或行/列模数转换。在上述三种方式中，均采用了数模转换电路，而数模转换电路中的斜坡波产生电路和时钟发生器容易受到PVT(Process/Voltage/Temperature，生产工艺/电压/温度)的影响，从而导致指纹识别系统的性能的恶化。
发明内容
有鉴于此，本发明要解决的技术问题是提供一种斜坡波产生电路及其数模转换电路、指纹识别系统，以解决现有技术中斜坡波产生电路和时钟发生器因受到PVT的影响而导致指纹系统性能恶化的问题。
本发明解决上述技术问题所采用的技术方案如下：
据本发明的一个方面，提供一种斜坡波产生电路，包括：积分电路，用于输出斜坡波信号；信号调整电路，包括串联的反馈控制环路和跨导放大器，所述反馈控制环路监测所述积分电路输出的斜坡波信号，并向所述跨导放大器输出调整控制信号，由所述跨导放大器根据所述调整信号对所述积分电路下一周期输出的斜坡波信号进行修正；电压产生电路，用于分别向所述积分电路及所 述信号调整电路输出参考电压信号。
提供一种如上所述的电路，所述积分电路包括第一双向开关、第二双向开关、第三双开关、斜坡波信号产生电容及第一高增益运算放大器：所述第一双向开关连接在所述第一高增益运算放大器的负极与输出端之间；所述斜坡波信号产生电容一端与所述第一高增益运算放大器的负极连接，另一端通过所述第二双向开关与所述第一高增益运算放大器的输出端连接；所述第三双向开关一端与所述电压产生电路连接，另一端连接在所述斜坡波信号产生电容与所述第二双向开关之间。
提供一种如上所述的电路，所述第一双向开关、所述第二双向开关及所述第三双开关分别由两路反相且不重叠的周期信号控制动作。
提供一种如上所述的电路，所述跨导放大器包括误差保持电容和NMOS晶体管，其中所述NMOS晶体管的栅极与所述反馈控制环路的输出端连接，另外两极一个接地，另一个与所述积分电路的第一高增益运算放大器的负极连接以向所述积分电路提供误差校正电流。
提供一种如上所述的电路，所述反馈控制环路包括误差放大器，所述误差放大器的正极与所述积分电路的斜坡波信号输出端连接，负极与所述电压产生电路连接，输出端与所述跨导放大器连接。
提供一种如上所述的电路，所述电压产生电路包括第二高增益运算放大器、电流镜电路及第一匹配电阻、第二匹配电阻、第三匹配电阻构成：所电流镜电路由两个以电流镜方式连接的PMOS晶体管构成，其第一连接端与所述第二高增益运算放大器的输出端、所述第一匹配电阻的第一连接端及积分电路的第一高增益放大器的正极连接，第二连接端与所述第二匹配电阻的第一连接端及所述信号调整电路的电压输入端连接；所述第三匹配电阻的第一连接端与所述第二匹配电阻的第二连接端及所述积分电路的第三双向开关的第一连接端连接，第二连接端与第一匹配电阻的第二连接端连接，并接地；所述第二高增益运算放大器的负极与输出端连接。
根据本发明的另一个方面，提供一种指纹识别系统，包括数模转换电路，所述数模转换电路包括如上所述的斜坡波产生电路。
根据本发明的再一个方面，提供一种数模转换电路，包括如上所述的斜坡波产生电路、控制电路、指纹信号/保持电路、比较器、时钟发生器及N-bit计数器：所述控制电路，用于控制所述斜坡波产生电路和所述N-bit计数器同时开始工作；所述斜坡波产生电路，用于在所述控制电路的控制下向比较器输出斜坡波信号；所述指纹信号/保持电路，用于向所述比较器输出经增强处理后的像素感应信号；所述比较器，用于将所述斜坡波信号及所述像素感应信号进行对比，并向所述N-bit计数器输出信号，以及用于在斜坡波信号等于像素感应信号相等时，将所述输出信号进行翻转；所述N-bit计数器，用于在所述控制电路的控制下开始工作，并在所述比较器的输出信号发生翻转时锁存计数值，以便得到本次转换后ADC输出码字信号；时钟发生器，用于为数模转换电路提供计时基准。
本发明的一种指纹识别系统，其在斜坡波产生电路中设置了信号调整电路，通过信号调整电路中的反馈控制环路监测积分电路产生的斜坡波信号，然后向该跨导放大器输出调整控制信号，对该积分电路下一周期输出的斜坡波信号进行修正，能够自动调整输出斜坡波信号的最高点电压值，从而使输出的斜坡波信号的幅度与PVT变化无关，消除了因PVT带来的影响。并且该电路实现简单，对电容材质没有要求，降低了生产成本。另外，将该电路应用到指纹识别系统时，其能够自适应系统时钟频率的变化，当时钟频率变化时，产生的斜坡波信号的斜率变化对单斜率ramp ADC增益误差、分辨率、INL(积分非线性)和DNL(差分非线性)等性能指标不会造成影响。
附图说明
图1为本发明实施例提供的一种斜坡波产生电路连接示意图；
图2为图1中斜坡波产生电路在多个斜坡波产生阶段持续时间里，自动跟踪-校正机制的示意图；
图3为单斜率ramp ADC的原理图；
图4为图1中当反馈控制环路采用误差放大器构成时的电路连接示意图；
图5为本发明实施例提供的另一种斜坡波产生电路连接示意图；
图6本发明实施例提供的一种数模转换电路的示意图。
具体实施方式
为了使本发明所要解决的技术问题、技术方案及有益效果更加清楚、明白，以下结合附图和实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明提供了一种斜坡波产生电路，请参阅图1，该斜坡波产生电路产生的斜坡波信号为单斜率斜坡波信号，其包括积分电路100、信号调整电路200及电压产生电路。
积分电路100，用于输出斜坡波信号。该积分电路100包括第一双向开关110、第二双向开关121、第三双开关130、斜坡波信号产生电容140及第一高增益运算放大器150。该第一双向开关110连接在该第一高增益运算放大器150的负极与输出端之间。该斜坡波信号产生电容140的一端与该第一高增益运算放大器150的负极连接，另一端通过该第二双向开关120与该第一高增益运算放大器的输出端连接。该第三双向开关130一端与该电压产生电路300连接，另一端连接在该斜坡波信号产生电容140与该第二双向开关120之间。需要说明的是，在该积分电路中，第一双向开关110、第二双向开关120及第三双开关130分别由两路反相且不重叠的周期信号控制动作，即这三个双向开关不会同时处于导通状态。
信号调整电路200，由串联的反馈控制环路210和跨导放大器220组成。该反馈控制环路210监测该积分电路100输出的斜坡波信号，并向该跨导放大器220输出调整控制信号，由该跨导放大器220根据该调整信号对该积分电路100下一周期输出的斜坡波信号进行修正。
电压产生电路，用于分别向该积分电路及该信号调整电路输出参考电压信号。
该斜坡波产生电路的工作原理如下：
在该斜坡波产生电路工作的初始阶段，斜坡波信号产生电容140无电荷。记电压产生电路300的输出信号301为VSET_STOP，输出信号302为VSET_VCM，输出 信号303为VSET_START，显然输出的斜坡波信号101每次均从电压VSET_START开始线性上升。
首先，为明确分析重点，当不考虑PVT的影响时的工作情况：
在斜坡波产生电路正常工作阶段，反馈控制环路210监控积分电路100的输出斜坡波信号101的“结束值”(即所产生的斜坡波信号的最高点电压VRAMP_END)和电压产生电路300的输出信号301即VSET_STOP之间的差异，并输出调整控制信号201到跨导放大器220，从而修正下一周期产生斜坡波信号的斜坡波信号产生电容140的充电电流。借由此种自动跟踪-校正机制，在若干个斜坡波信号输出周期后应当满足如下关系：VRAMP_END＝VSET_STOP    (2)
以其中某一次斜坡波信号101产生过程为例对此跟踪-校正机制进行详细说明。
在斜坡波信号101输出过程中，双向开关电路120处于导通状态，而双向开关电路110和130处于断开状态；跨导放大器220在反馈控制环路210输出的调整控制信号201作用下持续输出稳定的充电电流使斜坡波信号产生电容140两端电压上升。假设经过上一周期的“跟踪-校正”过程后跨导放大器220输出电流变化量为ΔI，则有关系
ΔI＝gm*ΔVerror     (3)
上述式(3)中，gm表示跨导放大器220的跨导，ΔVerror表示上一周期斜坡波输出阶段结束时VRAMP_END与设定值VSET_STOP之间的差值。
另外，设定斜坡波信号产生电容140的电容值为CR，斜坡波产生阶段持续时间为TRAMP，则有
Figure PCTCN2014095016-appb-000001
当本周期内斜坡波输出阶段结束时，若VRAMP_END与设定值VSET_STOP之间的差值不为零，即上述式(2)不成立时，上述式(3)中的ΔVerror≠0，即ΔI≠0。所以下一周期斜坡波输出阶段时有
Figure PCTCN2014095016-appb-000002
经过若干连续周期后，如果ΔVerror能足够小，那么上述式(2)就能成立，即图1中的斜坡波产生电路将会输出幅度稳定而精确的斜坡波信号。
在上述分析的基础上，分析PVT变化对斜坡波产生电路性能的影响，为简明起见每次只考虑PVT变化对单一环节造成的影响。
1)PVT变化引起跨导放大器317输出电流I变化
根据公式(4)，当PVT变化引起跨导放大器220输出电流I变大时，由于斜坡波信号产生电容140的电容值CR以及斜坡波产生阶段持续时间TRAMP均未发生变化，那么ΔVerror＝VRAMP_END-VSET_STOP必定也会增大，即此时会出现VRAMP_END>VSET_STOP的现象。
根据公式(3)，在负反馈机制作用下反馈控制环路210会减小跨导放大器220的输出电流，从而使下一周期结束时的ΔVerror减小。可以预见的是，若干连续周期后，必定会有上述式(2)的成立。
2)PVT变化引起电容器310电容值CR变化
根据公式(4)，当PVT变化引起斜坡波信号产生电容140电容值CR变大时，由于跨导放大器220输出电流I以及斜坡波产生阶段持续时间TRAMP均未发生变化，那么ΔVerror＝VRAMP_END-VSET_STOP必定也会减小，即此时会出现VRAMP_END<VSET_STOP的现象。
根据公式(3)，在负反馈机制作用下反馈控制环路210会增大跨导放大器220的输出电流，从而使下一周期结束时的ΔVerror减小。可以预见的是，若干连续周期后，必定会有上述式(2)的成立。
3)PVT变化引起系统时钟频率FCLK变化
根据公式(4)，当PVT变化引起系统时钟频率FCLK变大时，即导致斜坡波产生阶段持续时间TRAMP＝N*TCLK减小；由于斜坡波信号产生电容140的电容值CR以及跨导放大器220输出电流I均未发生变化，那么ΔVerror＝VRAMP_END-VSET_STOP必定也会减小，即此时会出现VRAMP_END<VSET_STOP的现象。
根据公式(3)，在负反馈机制作用下反馈控制环路210会增大跨导放大器220的输出电流，从而使下一周期结束时的ΔVerror减小。可以预见的是，若干连续周期后，必定会有上述式(2)的成立。
通过上述PVT对各环节影响的述分析过程可知，PVT变化引起电路参数波动时，图1中的斜坡波产生电路始终能输出幅度精确、稳定的斜坡波信号，即产生的斜坡波信号幅度ΔVRAMP与PVT变化无关。
请继续参阅图2，为本实施例的斜坡波产生电路应用到指纹识别系统中的单斜率ramp ADC电路(斜坡波数模转换电路)时，在多个斜坡波产生阶段持续时间里，自动跟踪-校正机制的示意图。
图中ΔVerror＝VRAMP_END-VSET_STOP；ΔVRAMP＝VRAMP_END-VSET_START表示输出的斜坡波信号101的电压幅度；TRAMP＝N*TCLK，TCLK为系统时钟发生器的每个周期持续时间。
因此公式(4)可以改写为下述形式：
Figure PCTCN2014095016-appb-000003
请参阅图3，根据单斜率ramp ADC的原理图，可知：
Figure PCTCN2014095016-appb-000004
其中VSIG为单斜率ramp ADC电路输入的模拟电压，DSIG为对应的量化输出码字。
由上述公式(5)可以得出，对于单斜率ramp ADC输入的模拟电压VSIG，其对应的量化输出码字应为：
Figure PCTCN2014095016-appb-000005
由于PVT变化引起电路参数波动时，图1中的电路始终能输出幅度精确、稳定的斜坡波信号，即产生的斜坡波信号幅度ΔVRAMP与PVT变化无关，同时结合公式(6)可知，使用图1中斜坡波产生电路的单斜率ramp ADC的性能也与PVT变化无关。
需要说明的是，在实际应用中，信号调整电路200的反馈控制环路210可仅由误差放大器211构成。请参阅图4，该误差放大器211的正极与该积分电路的斜坡波信号输出端连接，负极与该电压产生电路连接，输出端与该跨导放大器连接。
本实施例提供的斜坡波产生电路，设置了信号调整电路，通过信号调整电路中的反馈控制环路监测积分电路产生的斜坡波信号，然后向该跨导放大器输出调整控制信号，对该积分电路下一周期输出的斜坡波信号进行修正，能够自动调整输出斜坡波信号的最高点电压值，从而使输出的斜坡波信号的幅度与PVT变化无关，消除了因PVT带来的影响。并且该电路实现简单，对电容材质没有 要求，降低了生产成本。另外，将该电路应用到指纹识别系统时，其能够自适应系统时钟频率的变化，当时钟频率变化时，产生的斜坡波信号的斜率变化对单斜率ramp ADC增益误差、分辨率、INL(积分非线性)和DNL(差分非线性)等性能指标不会造成影响。
在上述实施例的基础上，本实施例中提供了另一种斜坡波产生电路。请参阅图5，该斜坡波产生电路包括积分电路100、信号调整电路200及电压产生电路。
积分电路100，用于输出斜坡波信号。该积分电路100包括第一双向开关110、第二双向开关121、第三双开关130、斜坡波信号产生电容140及第一高增益运算放大器150。该第一双向开关110连接在该第一高增益运算放大器150的负极与输出端之间。该斜坡波信号产生电容140的一端与该第一高增益运算放大器150的负极连接，另一端通过该第二双向开关120与该第一高增益运算放大器150的输出端连接。该第三双向开关130第一连接端131与该电压产生电路300的第三匹配电阻350的第一连接端351连接，另一端连接在该斜坡波信号产生电容140与该第二双向开关120之间。需要说明的是，在该积分电路中，第一双向开关110、第二双向开关120及第三双开关130分别由两路反相且不重叠的周期信号控制动作，即这三个双向开关不会同时处于导通状态。
信号调整电路由串联的反馈控制环路210和跨导放大器220组成。该反馈控制环路210监测该积分电路100输出的斜坡波信号，并向该跨导放大器220输出调整控制信号，由该跨导放大器220根据该调整信号对该积分电路100下一周期输出的斜坡波信号进行修正。跨导放大器220包括误差保持电容221和NMOS晶体管222。NMOS晶体管222的栅极与该反馈控制环路210的输出端连接，另外两极一个接地，另一个与该积分电路100的第一高增益运算放大器150的负极连接，向该积分电路100提供误差校正电流。NMOS晶体管222所提供的误差校正电流由反馈控制电路210决定
电压产生电路300，用于分别向该积分电路及该信号调整电路输出参考电压信号。电压产生电路300包括第二高增益运算放大器310、电流镜电路320及第一匹配电阻330、第二匹配电阻340、第三匹配电阻350构成：
所电流镜电路320由两个以电流镜方式连接的PMOS晶体管构成，其第一连接端321与该第二高增益运算放大器310的输出端、该第一匹配电阻330的第一连接端331及积分电路100的第一高增益放大器150的正极连接，第二连接端322与该第二匹配电阻340的第一连接端341及该信号调整电路210的电压输入端连接；该第三匹配电阻350的第一连接端351与该第二匹配电阻的第二连接端342及该积分电路100的第三双向开关130的第一连接端131连接，该第三匹配电阻350的第二连接端352与第一匹配电阻330的第二连接端332连接，并接地；该第二高增益运算放大器310的负极与输出端连接。
本实施例的斜坡波产生电路消除PVT影响的原理与前述是实施例的原理相同，此处不再赘述。
本实施例斜坡波产生电路设置了信号调整电路，通过信号调整电路中的反馈控制环路监测积分电路产生的斜坡波信号，然后向该跨导放大器输出调整控制信号，对该积分电路下一周期输出的斜坡波信号进行修正，能够自动调整输出斜坡波信号的最高点电压值，从而使输出的斜坡波信号的幅度与PVT变化无关，消除了因PVT带来的影响。并且电压产生电路中设置了三个匹配电阻，当改变匹配电阻的相互比例时，可以实现参考电压的幅度在较大范围内灵活变化。
在上述两个实施例的基础上，本发明还提供了一种指纹识别系统，该系统包括一个数模转换电路，用于对指纹感应像素电路采集的信号进行数模转换。请参阅图6，该数模转换电路包括：
控制电路601，用于控制斜坡波产生电路602和N-bit计数器603同时开始工作；
斜坡波产生电路602，用于在控制电路601的控制下向比较器604输出斜坡波信号，该斜坡波产生电路602可采用上述实施例中的一种；
指纹信号/保持电路605，用于向比较器604输出经增强处理后的像素感应信号；
比较器604，用于将斜坡波信号及像素感应信号进行对比，并向N-bit计数器603输出信号，以及用于在斜坡波信号等于像素感应信号相等时，将该输出信号进行翻转；
N-bit计数器603，用于在控制电路601的控制下开始工作，并在比较器604的输出信号发生翻转时锁存计数值，以便得到本次转换后ADC输出码字信号ADC_OUT<N:1>；
时钟发生器606，用于为数模转换电路提供计时基准。
本实施例的指纹识别系统，在斜坡波产生电路中设置了信号调整电路，通过信号调整电路中的反馈控制环路监测积分电路产生的斜坡波信号，然后向该跨导放大器输出调整控制信号，对该积分电路下一周期输出的斜坡波信号进行修正，所以能够保证积分电路产生的斜坡波信号的稳定性，消除了因PVT带来的影响。
以上参照附图说明了本发明的优选实施例，并非因此局限本发明的权利范围。本领域技术人员不脱离本发明的范围和实质内所作的任何修改、等同替换和改进，均应在本发明的权利范围之内。
工业实用性
本发明提供的一种斜坡波产生电路及其数模转换电路、指纹识别系统，其在斜坡波产生电路中设置了信号调整电路，通过信号调整电路中的反馈控制环路监测积分电路产生的斜坡波信号，然后向该跨导放大器输出调整控制信号，对该积分电路下一周期输出的斜坡波信号进行修正，能够自动调整输出斜坡波信号的最高点电压值，从而使输出的斜坡波信号的幅度与PVT变化无关，消除了因PVT带来的影响。并且该电路实现简单，对电容材质没有要求，降低了生产成本。另外，将该电路应用到指纹识别系统时，其能够自适应系统时钟频率的变化，当时钟频率变化时，产生的斜坡波信号的斜率变化对单斜率ramp ADC增益误差、分辨率、INL(积分非线性)和DNL(差分非线性)等性能指标不会造成影响。

Claims (8)

  1. 一种斜坡波产生电路，所述电路包括：
    积分电路，用于输出斜坡波信号；
    信号调整电路，包括串联的反馈控制环路和跨导放大器，所述反馈控制环路监测所述积分电路输出的斜坡波信号，并向所述跨导放大器输出调整控制信号，由所述跨导放大器根据所述调整信号对所述积分电路下一周期输出的斜坡波信号进行修正；
    电压产生电路，用于分别向所述积分电路及所述信号调整电路输出参考电压信号。
  2. 根据权利要求1所述的电路，其中，所述积分电路包括第一双向开关、第二双向开关、第三双开关、斜坡波信号产生电容及第一高增益运算放大器：
    所述第一双向开关连接在所述第一高增益运算放大器的负极与输出端之间；
    所述斜坡波信号产生电容一端与所述第一高增益运算放大器的负极连接，另一端通过所述第二双向开关与所述第一高增益运算放大器的输出端连接；
    所述第三双向开关一端与所述电压产生电路连接，另一端连接在所述斜坡波信号产生电容与所述第二双向开关之间。
  3. 根据权利要求2所述的电路，其中，所述第一双向开关、所述第二双向开关及所述第三双开关分别由两路反相且不重叠的周期信号控制动作。
  4. 根据权利要求2所述的电路，其中，所述跨导放大器包括误差保持电容和NMOS晶体管，其中所述NMOS晶体管的栅极与所述反馈控制环路的输出端连接，另外两极一个接地，另一个与所述积分电路的第一高增益运算放大器的负极连接以向所述积分电路提供误差校正电流。
  5. 根据权利要求1至4任一项所述的电路，其中，所述反馈控制环路包括误差放大器，所述误差放大器的正极与所述积分电路的斜坡波信号输出端连接， 负极与所述电压产生电路连接，输出端与所述跨导放大器连接。
  6. 根据权利要求5所述的电路，其中，所述电压产生电路包括第二高增益运算放大器、电流镜电路及第一匹配电阻、第二匹配电阻、第三匹配电阻构成：
    所电流镜电路由两个以电流镜方式连接的PMOS晶体管构成，其第一连接端与所述第二高增益运算放大器的输出端、所述第一匹配电阻的第一连接端及积分电路的第一高增益放大器的正极连接，第二连接端与所述第二匹配电阻的第一连接端及所述信号调整电路的电压输入端连接；
    所述第三匹配电阻的第一连接端与所述第二匹配电阻的第二连接端及所述积分电路的第三双向开关的第一连接端连接，第二连接端与第一匹配电阻的第二连接端连接，并接地；
    所述第二高增益运算放大器的负极与输出端连接。
  7. 一种指纹识别系统，包括数模转换电路，所述数模转换电路包括如权利要求1至6任一项所述的斜坡波产生电路。
  8. 一种数模转换电路，包括如权利要求1至6任一项所述的斜坡波产生电路、控制电路、指纹信号/保持电路、比较器、时钟发生器及N-bit计数器：
    所述控制电路，设置为控制所述斜坡波产生电路和所述N-bit计数器同时开始工作；
    所述斜坡波产生电路，设置为在所述控制电路的控制下向比较器输出斜坡波信号；
    所述指纹信号/保持电路，设置为向所述比较器输出经增强处理后的像素感应信号；
    所述比较器，设置为将所述斜坡波信号及所述像素感应信号进行对比，并向所述N-bit计数器输出信号，以及用于在斜坡波信号等于像素感应信号相等时，将所述输出信号进行翻转；
    所述N-bit计数器，设置为在所述控制电路的控制下开始工作，并在所述比较器的输出信号发生翻转时锁存计数值，以便得到本次转换后ADC输出码字 信号。
PCT/CN2014/095016 2014-10-24 2014-12-25 一种斜坡波产生电路及其数模转换电路、指纹识别系统 WO2016061891A1 (zh)

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