WO2016061855A1 - Tft阵列基板 - Google Patents

Tft阵列基板 Download PDF

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Publication number
WO2016061855A1
WO2016061855A1 PCT/CN2014/090459 CN2014090459W WO2016061855A1 WO 2016061855 A1 WO2016061855 A1 WO 2016061855A1 CN 2014090459 W CN2014090459 W CN 2014090459W WO 2016061855 A1 WO2016061855 A1 WO 2016061855A1
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Prior art keywords
sub
pixels
row
line
lines
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English (en)
French (fr)
Inventor
陈彩琴
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/423,766 priority Critical patent/US9685465B2/en
Publication of WO2016061855A1 publication Critical patent/WO2016061855A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a TFT array substrate.
  • LCDs liquid crystal displays
  • OLEDs organic light emitting diodes
  • the display panel is an important part of LCD and OLED. Whether it is a display panel of an LCD or a display panel of an OLED, it usually has a thin film transistor (TFT) array substrate.
  • TFT thin film transistor
  • a plurality of R, G, and B sub-pixels arranged in an array, a plurality of scanning lines, and a plurality of data lines are formed on the TFT array substrate.
  • Each sub-pixel receives a scan signal through a corresponding scan line and receives a data signal through a corresponding data line to display an image.
  • FIG. 1 is a schematic view showing the structure of a conventional TFT array substrate.
  • the conventional TFT array substrate includes a plurality of vertical data lines which are parallel to each other and arranged in sequence, such as D1, D2, D3, D4, D5, etc., and a plurality of horizontal scanning lines which are parallel to each other and sequentially arranged, such as G1, G2. , G3, G4, etc., and sub-pixels arranged in an array. Each sub-pixel located in the same row is electrically connected to a scan line located above the sub-pixel of the row through a TFT.
  • each sub-pixel of the first row is electrically connected to the scan line G1 through a TFT
  • each sub-pixel of the second row The pixels are electrically connected to the scan line G2 through a TFT, and so on; each sub-pixel located in the same column is electrically connected to the data line located on the left side of the column sub-pixel through a TFT, for example, each sub-pixel of the first column passes through a The TFT is electrically connected to the data line D1, and each sub-pixel of the second column is electrically connected to the data line D2 through a TFT, and so on.
  • FIG. 2 is a schematic structural view of a conventional TFT array substrate of a Data Line Share (DLS) type.
  • the TFT array substrate of the DLS type has one data line corresponding to every two columns of sub-pixels, and two scanning lines respectively located on the upper and lower sides thereof for each row of sub-pixels.
  • an even-numbered column sub-pixel and an odd-numbered column sub-pixel located on the left and right sides of each data line are electrically connected to the data line by a TFT, that is, the data line is shared.
  • each of the even-numbered sub-pixels is electrically connected to the scan line on the upper side of the row of sub-pixels through a TFT
  • each of the odd-numbered sub-pixels is electrically connected to the row of sub-pixels through a TFT.
  • Side scan line is electrically connected to the scan line on the upper side of the row of sub-pixels through a TFT.
  • each even-numbered column sub-pixel in the first row of sub-pixels is electrically connected to the scan line located on the upper side of the first row of sub-pixels through a TFT G1
  • each odd-numbered column sub-pixel of the first row of sub-pixels is electrically connected to the scan line G2 on the lower side of the first row of sub-pixels through a TFT
  • each of the even-numbered columns of the second row of sub-pixels passes through a TFT electrical
  • Each of the odd-line sub-pixels connected to the scan line G3 and the second row of sub-pixels on the upper side of the second-row sub-pixel is electrically connected to the scan line G4 on the lower side of the second-row sub-pixel by a TFT, and so on.
  • the number of data lines of the DLS type TFT array substrate is halved, which can reduce the cost, but at the same time, the number of scanning lines is doubled, and the charging time of each sub-pixel is reduced because the scanning line is doubled.
  • the signal delay effect of the corresponding data line and scan line tends to have a greater impact.
  • the delay of the data line (scan line) causes the odd column sub-pixel and even column sub-pixel charge rate. The difference results in a display defect of a vertical bright dark line.
  • the driving mode of the data line is two points (2 dot) polarity inversion once, due to the influence of the RC delay.
  • the data signal is not an ideal square wave, and the waveform of the actual data signal should be the arc waveform in Figure 3.
  • Let a sub-pixel be Pxy, x for the xth row, y for the yth column, and P12 subpixels as shown in FIG. 2 for the first row and second column of subpixels.
  • the even-numbered column sub-pixels connected to both sides of each data line are sequentially driven row by row before the odd-numbered column sub-pixels, for example, the sub-pixel P12 connected to the data line D2, P13, P22, P23 are driven in turn.
  • the post-driving sub-pixels are better charged than the first-driven sub-pixels, so P13 is better than P12, P23 is better than P22, and the data signal is very high.
  • the driving order is not changed, and the even-numbered column sub-pixels are driven first, and then the odd-numbered column sub-pixels are driven; that is, for the same row of sub-pixels, the even-numbered column sub-pixels are always driven first, and then the odd-numbered columns of pixels are driven;
  • the even-numbered sub-pixels may have insufficient charging, so that the position corresponding to the even-numbered sub-pixels is insufficient in brightness, and the defects of the vertical bright and dark lines are formed from the overall display effect.
  • the present invention provides a TFT array substrate having a display area and a non-display area, wherein the display area includes a plurality of vertical data lines which are parallel to each other and arranged in sequence, and a plurality of horizontally parallel and sequentially arranged levels. Scan lines, and sub-pixels arranged in an array;
  • an even-numbered column of sub-pixels located on the left and right sides of each data line An odd-numbered column sub-pixel is electrically connected to the data line by a TFT;
  • each even-numbered column of sub-pixels is electrically connected to the scan line located on the upper side of the row of sub-pixels through a TFT.
  • Each odd column sub-pixel is electrically connected to a scan line located on a lower side of the row of sub-pixels through a TFT;
  • the non-display area includes a plurality of fan-out lines, and each of the fan-out lines is connected to a scan line, and each of the fan-out lines includes a linear area parallel to the corresponding scan line, and a diagonal line connecting the straight line area and the corresponding scan line;
  • Each of the two or four scanning lines arranged in sequence is respectively insulated from the oblique line areas of the two fan-out lines connecting the upper and lower adjacent scanning lines, thereby changing the two scannings adjacent to the upper and lower sides. The order in which the lines are driven.
  • Each of the two scanning lines arranged in sequence is insulated from each other by obliquely connecting the two fan-out lines connecting the two scanning lines on the upper and lower sides of the same row of sub-pixels.
  • the oblique line regions respectively connecting the two fan-out lines connecting the two scanning lines on the upper and lower sides of each even-numbered row of sub-pixels are insulated from each other.
  • the oblique line regions respectively connecting the two fan-out lines connecting the two scanning lines on the upper and lower sides of each odd-row sub-pixel are insulated from each other.
  • Each of the four scanning lines arranged in sequence is insulated from each other by obliquely connecting the two fan-out lines connecting the two scanning lines on the upper and lower sides of the same row of sub-pixels.
  • Each of the two scanning lines arranged in sequence is respectively connected between the adjacent upper and lower sub-pixels, and respectively connected to the lower side of the previous row of sub-pixels and the two scanning lines of the upper side of the next row of sub-pixels.
  • the diagonal areas of the fan-out lines are insulated from each other.
  • Each of the four scanning lines arranged in sequence is respectively connected between two adjacent sub-pixels of the upper and lower rows, and two of the two scanning lines located on the lower side of the previous row of sub-pixels and on the upper side of the next row of sub-pixels.
  • the slanted areas of the fanout lines are insulated from each other.
  • the data line is driven in such a way that the polarity of the two points is reversed once.
  • a TFT array substrate is provided with two or four scanning lines arranged in sequence, which respectively correspond to oblique lines of two fan-out lines connecting two upper and lower adjacent scanning lines.
  • the regions are arranged to be insulated from each other, thereby changing the driving order of the two adjacent scanning lines, so that the sub-pixels with uneven spatial and darkness are staggered in the display period of the same frame, and the vertical direction is improved.
  • Straight bright dark lines show defects and increase the aperture ratio.
  • 1 is a schematic structural view of a conventional TFT array substrate
  • FIG. 2 is a schematic structural view of a conventional DLS type TFT array substrate
  • FIG. 3 is a waveform diagram corresponding to the data signal in FIG. 2;
  • FIG. 4 is a schematic diagram showing a data line driving manner of a TFT array substrate of a DLS type with a polarity reversal of two points;
  • FIG. 5 is a schematic structural view of a first embodiment of a TFT array substrate of the present invention.
  • FIG. 6 is a schematic structural view of a second embodiment of a TFT array substrate of the present invention.
  • FIG. 7 is a schematic structural view of a third embodiment of a TFT array substrate of the present invention.
  • FIG. 8 is a schematic structural view of a fourth embodiment of a TFT array substrate of the present invention.
  • Figure 9 is a schematic view showing the structure of a fifth embodiment of the TFT array substrate of the present invention.
  • FIG. 5 is a schematic structural view of a first embodiment of a TFT array substrate according to the present invention.
  • the TFT array substrate has a display area A and a non-display area B.
  • the display area A includes a plurality of vertical data lines which are parallel to each other and arranged in sequence, such as D1, D2, D3, D4, D5, etc., and a plurality of horizontal scanning lines, such as G1, G2, which are arranged in parallel and arranged in sequence. G3, G4, G5, G6, G7, G8, etc., and sub-pixels arranged in an array.
  • an even-numbered column sub-pixel and an odd-numbered column sub-pixel located on the left and right sides of each data line are electrically connected to the data line through a TFT, that is, the data line is shared, for example, Among the first row of sub-pixels, the second column sub-pixel and the third column sub-pixel respectively located on the left and right sides of the data line D2 share the data line D2.
  • each row of sub-pixels two scanning lines respectively disposed on the upper and lower sides thereof are disposed.
  • the scanning line G1 is located on the upper side thereof, and the scanning line G2 is located on the lower side thereof; corresponding to the second row of sub-pixels
  • the scanning line G3 is disposed on the upper side thereof, and the scanning line G4 is located on the lower side thereof.
  • each of the even-numbered sub-pixels is electrically connected to the scan line on the upper side of the row of sub-pixels through a TFT
  • each of the odd-numbered sub-pixels is electrically connected to the lower side of the row of sub-pixels through a TFT.
  • each even-numbered column of sub-pixels is electrically connected to the scan line G1
  • each odd-numbered column of sub-pixels is electrically connected to the scan line G2
  • each even-numbered column The pixels are electrically connected to the scan line G3, and each of the odd-numbered sub-pixels is electrically connected to the scan line G4.
  • the non-display area B includes a plurality of fan-out lines, such as Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, etc., each fan line is connected to a scan line, that is, the fan-out line Z1 corresponds to the connection scan line G1, the fan-out line Z2 corresponds to the scan line G2, and so on, each fan-out line includes a straight line region parallel to the corresponding scan line, and Connect the straight line area to the diagonal line of the corresponding scan line.
  • each fan-out lines such as Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, etc.
  • the main point of the present invention is that the oblique lines of the two fan-out lines connecting the upper and lower adjacent two scanning lines are insulated from each other by two or four scanning lines arranged in sequence, thereby changing the upper and lower sides.
  • the oblique lines of the two fan-out lines connecting the two scanning lines on the upper and lower sides of each of the even-numbered sub-pixels are insulated from each other by two scanning lines arranged in sequence.
  • the interval G1 and G2 scan lines respectively connect the oblique lines of the two fan-out lines Z3 and Z4 of the two scanning lines G3 and G4 located on the upper and lower sides of the second row of sub-pixels to each other to make a fan.
  • the straight line area of the outgoing line Z4 is located above the straight line area of the fan-out line Z3; the G5 and G6 scanning lines are respectively connected to the two fan-out lines Z7 of the two scanning lines G7 and G8 located on the upper and lower sides of the fourth row of sub-pixels.
  • the oblique line regions of Z8 are insulated from each other such that the straight line region of the fan-out line Z8 is located above the straight line region of the fan-out line Z7.
  • the driving order of the two scanning lines on the upper and lower sides of each even-numbered row of sub-pixels is changed by the oblique crossing of the corresponding two fan-out lines.
  • the scan lines G1, G2, G4, G3, G5, G6, G8, G7, etc. are sequentially driven such that the even-numbered column sub-pixels of each odd-row sub-pixel are driven first, and the odd-numbered sub-pixels are driven, and each even-numbered sub-pixel is driven.
  • the odd-numbered sub-pixels are driven first, and the even-numbered sub-pixels are driven, so that the odd-numbered sub-pixels of each odd-row sub-pixel are brighter and the even-numbered sub-pixels are darker, and the odd-numbered sub-pixels of each even-row sub-pixel are darker, and the even-numbered sub-pixels are smaller. bright.
  • the driving method of the data line is that the polarity of the two points is reversed once.
  • the driving sequence is not changed, and finally the bright and dark sub-pixels in each column of sub-pixels are spaced apart, so that the visual feeling is not The difference between light and dark is obtained, and the upper and lower adjacent sides of the TFT between the two rows of sub-pixels are avoided, and the aperture ratio is improved.
  • FIG. 6 shows a second embodiment of a TFT array substrate according to the present invention.
  • two scanning lines arranged in sequence are respectively connected to the upper and lower sides of each odd row of sub-pixels.
  • the diagonal areas of the two fan-out lines of the two scan lines are insulated from each other.
  • the diagonal lines of the two fan-out lines Z1 and Z2 respectively connecting the two scanning lines G1 and G2 on the upper and lower sides of the first row of sub-pixels are insulated from each other, and the straight-line area of the fan-out line Z2 is located at the fan-out line Z1.
  • the gaps G3 and G4 scan lines respectively correspond to the oblique lines of the two fan-out lines Z5 and Z6 connecting the two scanning lines G5 and G6 on the upper and lower sides of the third row of sub-pixels. So that the straight line area of the fan-out line Z6 is above the straight line area of the fan-out line Z5.
  • the driving order of the two scanning lines on the upper and lower sides of each odd-line sub-pixel is insulated from each other by the oblique line areas of the corresponding two fan-out lines.
  • the driving method of the data line is that the polarity of the two points is reversed once.
  • the driving sequence is not changed, and finally the bright and dark sub-pixels in each column of sub-pixels are spaced apart, so that the visual feeling is not The difference between light and dark is obtained, and the upper and lower adjacent sides of the TFT between the two rows of sub-pixels are avoided, and the aperture ratio is improved.
  • FIG. 7 is a third embodiment of a TFT array substrate according to the present invention.
  • four scanning lines arranged in sequence are respectively connected to two scans on the upper and lower sides of the same row of sub-pixels.
  • the diagonal areas of the two fan-out lines of the line are insulated from each other.
  • the diagonal lines of the two fan-out lines Z1 and Z2 respectively connecting the two scanning lines G1 and G2 on the upper and lower sides of the first row of sub-pixels are insulated from each other, and the straight-line area of the fan-out line Z2 is located at the fan-out line Z1.
  • the G3, G4, G5, and G6 scan lines are respectively connected to the oblique lines of the two fan-out lines Z7 and Z8 of the two scanning lines G7 and G8 located on the upper and lower sides of the fourth row of sub-pixels.
  • the regions are insulated from each other such that the straight line region of the fan-out line Z8 is located above the straight line region of the fan-out line Z7, changing the driving order of the scanning lines G7 and G8.
  • the scanning lines G2, G1, G3, G4, G5, G6, G8, G7, etc. are sequentially driven, so that the odd-numbered column sub-pixels of the first-row and fourth-row sub-pixels are driven first, and the even-numbered column sub-pixels are driven.
  • the driving method of the data line is that the polarity of the two points is reversed once, and the driving order is not changed after the polarity of the data signal is reversed.
  • the bright and dark sub-pixels in each column of sub-pixels can be finally spaced apart, so that the difference between light and dark is visually perceived, and the upper and lower adjacent TFTs between the two rows of sub-pixels are avoided, and the opening is raised. rate.
  • FIG. 8 is a fourth embodiment of a TFT array substrate according to the present invention.
  • two scanning lines arranged in sequence are respectively arranged between adjacent upper and lower sub-pixels.
  • the oblique line regions connecting the two fan-out lines on the lower side of the previous row of sub-pixels and the two scanning lines on the upper side of the next-row sub-pixel are insulated from each other.
  • the oblique line area corresponding to the fan-out line Z2 of the scanning line G2 connected to the lower side of the first row of sub-pixels and the oblique line area corresponding to the fan-out line Z3 of the scanning line G3 connected to the upper side of the second-row sub-pixel are insulated from each other, so that the fan The straight line area of the outgoing line Z3 is located at the fanout line Z2 Above the straight line area, the driving order of the scanning lines G2 and G3 is changed; the interval scanning lines Z4 and Z5 correspond to the oblique line area of the fan-out line Z6 of the scanning line G6 connected to the lower side of the third row of sub-pixels and the corresponding connection fourth line
  • the oblique line regions of the fan-out line Z7 of the scanning line G7 on the upper side of the sub-pixel are insulated from each other such that the linear region of the fan-out line Z7 is located above the straight-line region of the fan-out line Z6, changing the driving order of the scanning lines
  • the scan lines G1, G3, G2, G4, G5, G7, G6, G8, etc. are sequentially driven, and correspondingly, the order of driving sequence of each row of sub-pixels is: the even-numbered columns of the first row of sub-pixels a pixel, an even column sub-pixel of the second row of sub-pixels, an odd-column sub-pixel of the first-row sub-pixel, an odd-column sub-pixel of the second-row sub-pixel, an even-column sub-pixel of the third-row sub-pixel, and an even-numbered sub-pixel of the fourth-row sub-pixel a pixel, an odd column sub-pixel of the third row of sub-pixels, and an odd-numbered column of the fourth row of sub-pixels, such that the even-column sub-pixels of the first row and the third row of sub-pixels are darker, and the even-numbered sub-pixels of the second row and the fourth row of sub-pixels
  • the column sub-pixels are brighter
  • the driving method of the data line is that the polarity of the two points is reversed once, and the driving order is not changed after the polarity of the data signal is reversed.
  • the bright and dark sub-pixels in each column of sub-pixels can be finally spaced apart, so that the difference between light and dark is visually perceived, and the upper and lower adjacent TFTs between the two rows of sub-pixels are avoided, and the opening is raised. rate.
  • FIG. 9 shows a fifth embodiment of a TFT array substrate according to the present invention.
  • four scanning lines arranged in sequence are respectively connected between adjacent upper and lower sub-pixels.
  • the oblique line regions of the two fan-out lines located on the lower side of the previous row of sub-pixels and the two scanning lines on the upper side of the next-row sub-pixel are insulated from each other.
  • the oblique line area corresponding to the fan-out line Z2 of the scanning line G2 connected to the lower side of the first row of sub-pixels and the oblique line area corresponding to the fan-out line Z3 of the scanning line G3 connected to the upper side of the second-row sub-pixel are insulated from each other, so that the fan The straight line area of the outgoing line Z3 is located above the straight line area of the fan-out line Z2, and the driving order of the scanning lines G2 and G3 is changed; the interval scanning lines Z4, Z5, Z6, and Z7 are corresponding to the scanning line G8 connected to the lower side of the fourth row of sub-pixels.
  • the hatched area of the fan-out line Z8 and the oblique line area corresponding to the fan-out line Z9 of the scanning line G9 connected to the upper side of the fifth-row sub-pixel are insulated from each other such that the straight line area of the fan-out line Z9 is located above the straight line area of the fan-out line Z8, and the change is made.
  • the scanning lines G1, G3, G2, G4, G5, G6, G7, G9, G8, G10, etc. are sequentially driven, and correspondingly, the driving sequence order of each row of sub-pixels is: first row Even column subpixel of pixel, even column subpixel of second row subpixel, odd column subpixel of first row subpixel, odd column subpixel of second row subpixel, even column subpixel of third row subpixel, third row Odd column subpixel of pixel, even column subimage of fourth row subpixel
  • the even-numbered column sub-pixels of the fifth row of sub-pixels are brighter; the odd-numbered column sub-pixels of the first row and the fourth row of sub-pixels are darker
  • the driving method of the data line is that the polarity of the two points is reversed once, and the driving order is not changed after the polarity of the data signal is reversed.
  • the bright and dark sub-pixels in each column of sub-pixels can be finally spaced apart, so that the difference between light and dark is visually perceived, and the upper and lower adjacent TFTs between the two rows of sub-pixels are avoided, and the opening is raised. rate.
  • the TFT array substrate provided by the present invention is provided with two or four scanning lines arranged in sequence, and the oblique line areas corresponding to the two fan-out lines connecting the upper and lower adjacent scanning lines are respectively set to The mutual insulation crosses, thereby changing the driving order of the two upper and lower adjacent scanning lines, so that sub-pixels with spatially uneven brightness are staggered in the same frame picture display period, and the vertical bright and dark lines are improved. Display defects and increase aperture ratio.

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Abstract

提供了一种TFT阵列基板，其显示区（A）包括多条数据线（D1，D2，D3，D4，D5）、多条扫描线（G1，G2，G3，G4，G5，G6，G7，G8）、及呈阵列式排布的子像素；在同一行子像素中，位于每条数据线（D1，D2，D3，D4，D5）左、右两侧的一偶数列子像素与一奇数列子像素分别通过一TFT共同电性连接于此数据线（D1，D2，D3，D4，D5）；在同一行子像素中，每一偶数列子像素电性连接于位于此行子像素上侧的扫描线，每一奇数列子像素电性连接于位于此行子像素下侧的扫描线；非显示区（B）包括多条扇出线（Z1，Z2，Z3，Z4，Z5，Z6，Z7，Z8），每一扇出线（Z1，Z2，Z3，Z4，Z5，Z6，Z7，Z8）对应连接一条扫描线，每一扇出线（Z1，Z2，Z3，Z4，Z5，Z6，Z7，Z8）包括直线区、及斜线区；每间隔两条或四条依次排列的扫描线，分别对应连接上、下相邻的两条扫描线的两条扇出线的斜线区相互绝缘交叉，改变上、下相邻的两条扫描线的驱动顺序。

Description

TFT阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示器已经逐步取代CRT显示器，广泛的应用于液晶电视、手机、个人数字助理、数字相机、计算机屏幕或笔记本电脑屏幕等。
显示面板是LCD、OLED的重要组成部分。不论是LCD的显示面板，还是OLED的显示面板，通常具有一薄膜晶体管(Thin Film Transistor，TFT)阵列基板。此TFT阵列基板上形成有多个呈阵列式排布的R、G、B子像素、多条扫描线、及多条数据线。每一子像素分别通过对应的扫描线来接收扫描信号、通过对应的数据线来接收数据信号，以显示影像。
图1所示为传统的TFT阵列基板的结构示意图。该传统的TFT阵列基板包括多条相互平行并依次排列的竖直的数据线，如D1、D2、D3、D4、D5等，多条相互平行并依次排列的水平的扫描线，如G1、G2、G3、G4等，及呈阵列式排布的子像素。位于同一行的每个子像素均通过一TFT电性连接于位于该行子像素上方的扫描线，例如第一行的每个子像素通过一TFT电性连接于扫描线G1，第二行的每个子像素通过一TFT电性连接于扫描线G2，依次类推；位于同一列的每个子像素均通过一TFT电性连接于位于该列子像素左侧的数据线，例如第一列的每个子像素通过一TFT电性连接于数据线D1，第二列的每个子像素通过一TFT电性连接于数据线D2，依次类推。
图2所示为现有的共用数据线(Data Line Share，DLS)类型的TFT阵列基板的结构示意图。该DLS类型的TFT阵列基板，对应每两列子像素设置一条数据线，对应每一行子像素设置分别位于其上、下两侧的两条扫描线。在同一行子像素中，位于每条数据线左、右两侧的一偶数列子像素与一奇数列子像素分别通过一TFT共同电性连接于该条数据线，即共用该条数据线。同时，在同一行子像素中，每一偶数列子像素通过一TFT电性连接于位于该行子像素上侧的扫描线，每一奇数列子像素通过一TFT电性连接于位于该行子像素下侧的扫描线。例如，第二列与第三列子像素共用数 据线D2、第四列与第五列子像素共用数据线D3，依次类推；第一行子像素中的每一偶数列子像素通过一TFT电性连接于位于第一行子像素上侧的扫描线G1、第一行子像素中的每一奇数列子像素通过一TFT电性连接于第一行子像素下侧的扫描线G2；第二行子像素中的每一偶数列子像素通过一TFT电性连接于位于第二行子像素上侧的扫描线G3、第二行子像素中的每一奇数列子像素通过一TFT电性连接于第二行子像素下侧的扫描线G4，依次类推。相比于图1中传统的TFT阵列基板，该DLS类型的TFT阵列基板的数据线数目减半，能够减少成本，但同时扫描线数目加倍，每一子像素的充电时间因为扫描线加倍而减少了一半，因此相应数据线和扫描线的信号延迟效应往往会影响更大，例如，在数据线(扫描线)尾端，数据线(扫描线)延迟会造成奇数列子像素与偶数列子像素充电率差异，导致产生竖直亮暗线的显示缺陷。
具体的，请同时参阅图2、图3、图4，如图4所示，数据线的驱动方式为两点(2 dot)极性反转一次，由于阻容延迟(RC Delay)的影响，数据信号并非理想方波，实际数据信号的波形应该为图3中的弧线波形。设一子像素为Pxy，x代表第x行，y代表第y列，如图2中的P12子像素代表第一行第二列子像素。当扫描线G1、G2、G3、G4等依次打开时，连接于每一数据线两侧的偶数列子像素先于奇数列子像素被逐行依次驱动，例如连接于数据线D2上的子像素P12、P13、P22、P23依次被驱动，在数据信号同一极性周期内，后驱动的子像素总比先驱动的子像素充电更好，这样P13比P12充电好，P23比P22充电好，数据信号极性反转后，驱动顺序未改变，依然是先驱动偶数列子像素，后驱动奇数列子像素；也就是对于同一行子像素，总是先驱动偶数列子像素，后驱动奇数列像素；那么先驱动的偶数列子像素可能有充电不足现象，使偶数列子像素对应的位置亮度不足，从整体的显示效果来看便形成了竖直亮暗线的缺陷。
发明内容
本发明的目的在于提供一种TFT阵列基板，使得在同一帧画面显示周期内，将空间上亮暗不均的子像素交错排列，改善了竖直亮暗线的显示缺陷，并提升了开口率。
为实现上述目的，本发明提供一种TFT阵列基板，具有显示区、非显示区，所述显示区包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的子像素；
在同一行子像素中，位于每条数据线左、右两侧的一偶数列子像素与 一奇数列子像素分别通过一TFT共同电性连接于该条数据线；
对应每一行子像素设置分别位于其上、下两侧的两条扫描线；在同一行子像素中，每一偶数列子像素通过一TFT电性连接于位于该行子像素上侧的扫描线，每一奇数列子像素通过一TFT电性连接于位于该行子像素下侧的扫描线；
所述非显示区包括多条扇出线，每一扇出线对应连接一条扫描线，每一扇出线包括平行于相应扫描线的直线区、及连接直线区与相应扫描线的斜线区；
每间隔两条或四条依次排列的扫描线，分别对应连接上、下相邻的两条扫描线的两条扇出线的斜线区相互绝缘交叉，从而改变该上、下相邻的两条扫描线的驱动顺序。
每间隔两条依次排列的扫描线，分别对应连接位于同一行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
分别对应连接位于每一偶数行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
分别对应连接位于每一奇数行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
每间隔四条依次排列的扫描线，分别对应连接位于同一行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
每间隔两条依次排列的扫描线，在相邻的上、下两行子像素之间，分别对应连接位于上一行子像素下侧、及位于下一行子像素上侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
每间隔四条依次排列的扫描线，在相邻的上、下两行子像素之间，分别对应连接位于上一行子像素下侧、及位于下一行子像素上侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
数据线的驱动方式为两点极性反转一次。
本发明的有益效果：本发明提供的一种TFT阵列基板，每间隔两条或四条依次排列的扫描线，将分别对应连接上、下相邻的两条扫描线的两条扇出线的斜线区设置为相互绝缘交叉，从而改变该上、下相邻的两条扫描线的驱动顺序，能够使得在同一帧画面显示周期内，将空间上亮暗不均的子像素交错排列，改善了竖直亮暗线的显示缺陷，并提升了开口率。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图1为传统的TFT阵列基板的结构示意图；
图2为现有的DLS类型的TFT阵列基板的结构示意图；
图3为对应图2中数据信号的波形示意图；
图4为反映DLS类型的TFT阵列基板的数据线驱动方式为两点极性反转一次的示意图；
图5为本发明的TFT阵列基板的第一实施例的结构示意图；
图6为本发明的TFT阵列基板的第二实施例的结构示意图；
图7为本发明的TFT阵列基板的第三实施例的结构示意图；
图8为本发明的TFT阵列基板的第四实施例的结构示意图；
图9为本发明的TFT阵列基板的第五实施例的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图5，为本发明的TFT阵列基板的第一实施例的结构示意图。该TFT阵列基板具有显示区A、非显示区B。所述显示区A包括多条相互平行并依次排列的竖直的数据线、如D1、D2、D3、D4、D5等，多条相互平行并依次排列的水平的扫描线、如G1、G2、G3、G4、G5、G6、G7、G8等，及呈阵列式排布的子像素。
在同一行子像素中，位于每条数据线左、右两侧的一偶数列子像素与一奇数列子像素分别通过一TFT共同电性连接于该条数据线，即共用该条数据线，如在第一行子像素中，分别位于数据线D2左、右两侧的第二列子像素与第三列子像素共用该数据线D2。
对应每一行子像素设置分别位于其上、下两侧的两条扫描线，如对应第一行子像素设置扫描线G1位于其上侧、扫描线G2位于其下侧；对应第二行子像素设置扫描线G3位于其上侧、扫描线G4位于其下侧。在同一行子像素中，每一偶数列子像素通过一TFT电性连接于位于该行子像素上侧的扫描线，每一奇数列子像素通过一TFT电性连接于位于该行子像素下侧的扫描线，如在第一行子像素中，每一偶数列子像素电性连接于扫描线G1，每一奇数列子像素电性连接于扫描线G2；在第二行子像素中，每一偶数列子像素电性连接于扫描线G3，每一奇数列子像素电性连接于扫描线G4。
所述非显示区B包括多条扇出线，如Z1、Z2、Z3、Z4、Z5、Z6、Z7、 Z8等，每一扇出线对应连接一条扫描线，即扇出线Z1对应连接扫描线G1、扇出线Z2对应连接扫描线G2，依次类推，每一扇出线包括平行于相应扫描线的直线区、及连接直线区与相应扫描线的斜线区。
本发明的重点在于，每间隔两条或四条依次排列的扫描线，分别对应连接上、下相邻的两条扫描线的两条扇出线的斜线区相互绝缘交叉，从而改变该上、下相邻的两条扫描线的驱动顺序。
在该第一实施例中，每间隔两条依次排列的扫描线，分别对应连接位于每一偶数行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉，如间隔G1、G2扫描线，分别对应连接位于第二行子像素上、下两侧的G3、G4这两条扫描线的两条扇出线Z3、Z4的斜线区相互绝缘交叉，使得扇出线Z4的直线区位于扇出线Z3的直线区上方；间隔G5、G6扫描线，分别对应连接位于第四行子像素上、下两侧的G7、G8这两条扫描线的两条扇出线Z7、Z8的斜线区相互绝缘交叉，使得扇出线Z8的直线区位于扇出线Z7的直线区上方。
当进行画面显示时，在同一帧画面显示周期内，每一偶数行子像素上、下两侧的两条扫描线的驱动顺序因相应的两条扇出线的斜线区相互绝缘交叉而发生改变，扫描线G1、G2、G4、G3、G5、G6、G8、G7等被依次驱动，使得每一奇数行子像素的偶数列子像素先驱动、奇数列子像素后驱动，每一偶数行子像素的奇数列子像素先驱动、偶数列子像素后驱动，从而每一奇数行子像素的奇数列子像素较亮、偶数列子像素较暗，而每一偶数行子像素的奇数列子像素较暗，偶数列子像素较亮。数据线的驱动方式为两点极性反转一次，数据信号极性反转后，驱动顺序并未改变，最终能够使得每一列子像素中的亮、暗子像素间隔开，使得视觉上感觉不出亮暗差异，同时避免了两行子像素之间的TFT上、下相邻，提升了开口率。
图6所示为本发明TFT阵列基板的第二实施例，在该第二实施例中，每间隔两条依次排列的扫描线，分别对应连接位于每一奇数行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。如分别对应连接位于第一行子像素上、下两侧的G1、G2这两条扫描线的两条扇出线Z1、Z2的斜线区相互绝缘交叉，扇出线Z2的直线区位于扇出线Z1的直线区上方；间隔G3、G4扫描线，分别对应连接位于第三行子像素上、下两侧的G5、G6这两条扫描线的两条扇出线Z5、Z6的斜线区相互绝缘交叉，使得扇出线Z6的直线区位于扇出线Z5的直线区上方。
当进行画面显示时，在同一帧画面显示周期内，每一奇数行子像素上、下两侧的两条扫描线的驱动顺序因相应的两条扇出线的斜线区相互绝缘交 叉而发生改变，扫描线G2、G1、G3、G4、G6、G5、G7、G8等被依次驱动，使得每一奇数行子像素的奇数列子像素先驱动、偶数列子像素后驱动，每一偶数行子像素的偶数列子像素先驱动、奇数列子像素后驱动，从而每一奇数行子像素的奇数列子像素较暗、偶数列子像素较亮，而每一偶数行子像素的奇数列子像素较亮，偶数列子像素较暗。数据线的驱动方式为两点极性反转一次，数据信号极性反转后，驱动顺序并未改变，最终能够使得每一列子像素中的亮、暗子像素间隔开，使得视觉上感觉不出亮暗差异，同时避免了两行子像素之间的TFT上、下相邻，提升了开口率。
其它与第一实施例相同，此处不再赘述。
图7所示为本发明TFT阵列基板的第三实施例，在该第三实施例中，每间隔四条依次排列的扫描线，分别对应连接位于同一行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。如分别对应连接位于第一行子像素上、下两侧的G1、G2这两条扫描线的两条扇出线Z1、Z2的斜线区相互绝缘交叉，扇出线Z2的直线区位于扇出线Z1的直线区上方；间隔G3、G4、G5、G6扫描线，分别对应连接位于第四行子像素上、下两侧的G7、G8这两条扫描线的两条扇出线Z7、Z8的斜线区相互绝缘交叉，使得扇出线Z8的直线区位于扇出线Z7的直线区上方，改变了扫描线G7、G8的驱动顺序。
当进行画面显示时，扫描线G2、G1、G3、G4、G5、G6、G8、G7等被依次驱动，使得第一行与第四行子像素的奇数列子像素先驱动、偶数列子像素后驱动，而第二行、第三行子像素的偶数列子像素先驱动、奇数列子像素后驱动，从而第一行与第四行子像素的奇数列子像素较暗、偶数列子像素较亮，而第二行、第三行子像素的奇数列子像素较亮，偶数列子像素较暗。数据线的驱动方式为两点极性反转一次，数据信号极性反转后，驱动顺序并未改变。依次类推，最终能够使得每一列子像素中的亮、暗子像素间隔开，使得视觉上感觉不出亮暗差异，同时避免了两行子像素之间的TFT上、下相邻，提升了开口率。
其它与第一实施例相同，此处不再赘述。
图8所示为本发明TFT阵列基板的第四实施例，在该第四实施例中，每间隔两条依次排列的扫描线，在相邻的上、下两行子像素之间，分别对应连接位于上一行子像素下侧、及位于下一行子像素上侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。如对应连接第一行子像素下侧的扫描线G2的扇出线Z2的斜线区与对应连接第二行子像素上侧的扫描线G3的扇出线Z3的斜线区相互绝缘交叉，使得扇出线Z3的直线区位于扇出线Z2 的直线区上方，改变了扫描线G2、G3的驱动顺序；间隔扫描线Z4、Z5，对应连接第三行子像素下侧的扫描线G6的扇出线Z6的斜线区与对应连接第四行子像素上侧的扫描线G7的扇出线Z7的斜线区相互绝缘交叉，使得扇出线Z7的直线区位于扇出线Z6的直线区上方，改变了扫描线G6、G7的驱动顺序。
当进行画面显示时，扫描线G1、G3、G2、G4、G5、G7、G6、G8等被依次驱动，相应的，各行子像素的驱动先后顺序数依次为：第一行子像素的偶数列子像素、第二行子像素的偶数列子像素、第一行子像素的奇数列子像素、第二行子像素的奇数列子像素、第三行子像素的偶数列子像素、第四行子像素的偶数列子像素、第三行子像素的奇数列子像素、第四行子像素的奇数列子像素，从而第一行、第三行子像素的偶数列子像素较暗，第二行、第四行子像素的偶数列子像素较亮；第一行、第三行子像素的奇数列子像素较暗，第二行、第四行子像素的奇数列子像素较亮。数据线的驱动方式为两点极性反转一次，数据信号极性反转后，驱动顺序并未改变。依次类推，最终能够使得每一列子像素中的亮、暗子像素间隔开，使得视觉上感觉不出亮暗差异，同时避免了两行子像素之间的TFT上、下相邻，提升了开口率。
其它与第一实施例相同，此处不再赘述。
图9所示为本发明TFT阵列基板的第五实施例，在该第五实施例中，每间隔四条依次排列的扫描线，在相邻的上、下两行子像素之间，分别对应连接位于上一行子像素下侧、及位于下一行子像素上侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。如对应连接第一行子像素下侧的扫描线G2的扇出线Z2的斜线区与对应连接第二行子像素上侧的扫描线G3的扇出线Z3的斜线区相互绝缘交叉，使得扇出线Z3的直线区位于扇出线Z2的直线区上方，改变了扫描线G2、G3的驱动顺序；间隔扫描线Z4、Z5、Z6、Z7，对应连接第四行子像素下侧的扫描线G8的扇出线Z8的斜线区与对应连接第五行子像素上侧的扫描线G9的扇出线Z9的斜线区相互绝缘交叉，使得扇出线Z9的直线区位于扇出线Z8的直线区上方，改变了扫描线G8、G9的驱动顺序。
当进行画面显示时，扫描线G1、G3、G2、G4、G5、G6、G7、G9、G8、G10等被依次驱动，相应的，各行子像素的驱动先后顺序数依次为：第一行子像素的偶数列子像素、第二行子像素的偶数列子像素、第一行子像素的奇数列子像素、第二行子像素的奇数列子像素、第三行子像素的偶数列子像素、第三行子像素的奇数列子像素、第四行子像素的偶数列子像 素、第五行子像素的偶数列子像素、第四行子像素的奇数列子像素、第五行子像素的奇数列子像素，从而第一行、第四行子像素的偶数列子像素较暗，第二行、第五行子像素的偶数列子像素较亮；第一行、第四行子像素的奇数列子像素较暗，第二行、第五行子像素的奇数列子像素较亮。数据线的驱动方式为两点极性反转一次，数据信号极性反转后，驱动顺序并未改变。依次类推，最终能够使得每一列子像素中的亮、暗子像素间隔开，使得视觉上感觉不出亮暗差异，同时避免了两行子像素之间的TFT上、下相邻，提升了开口率。
其它与第一实施例相同，此处不再赘述。
综上所述，本发明提供的TFT阵列基板，每间隔两条或四条依次排列的扫描线，将分别对应连接上、下相邻的两条扫描线的两条扇出线的斜线区设置为相互绝缘交叉，从而改变该上、下相邻的两条扫描线的驱动顺序，能够使得在同一帧画面显示周期内，将空间上亮暗不均的子像素交错排列，改善了垂直亮暗线的显示缺陷，并提升了开口率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (9)

  1. 一种TFT阵列基板，具有显示区、非显示区，所述显示区包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的子像素；
    在同一行子像素中，位于每条数据线左、右两侧的一偶数列子像素与一奇数列子像素分别通过一TFT共同电性连接于该条数据线；
    对应每一行子像素设置分别位于其上、下两侧的两条扫描线；在同一行子像素中，每一偶数列子像素通过一TFT电性连接于位于该行子像素上侧的扫描线，每一奇数列子像素通过一TFT电性连接于位于该行子像素下侧的扫描线；
    所述非显示区包括多条扇出线，每一扇出线对应连接一条扫描线，每一扇出线包括平行于相应扫描线的直线区、及连接直线区与相应扫描线的斜线区；
    每间隔两条或四条依次排列的扫描线，分别对应连接上、下相邻的两条扫描线的两条扇出线的斜线区相互绝缘交叉，从而改变该上、下相邻的两条扫描线的驱动顺序。
  2. 如权利要求1所述的TFT阵列基板，其中，每间隔两条依次排列的扫描线，分别对应连接位于同一行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
  3. 如权利要求2所述的TFT阵列基板，其中，分别对应连接位于每一偶数行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
  4. 如权利要求2所述的TFT阵列基板，其中，分别对应连接位于每一奇数行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
  5. 如权利要求1所述的TFT阵列基板，其中，每间隔四条依次排列的扫描线，分别对应连接位于同一行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
  6. 如权利要求1所述的TFT阵列基板，其中，每间隔两条依次排列的扫描线，在相邻的上、下两行子像素之间，分别对应连接位于上一行子像素下侧、及位于下一行子像素上侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
  7. 如权利要求1所述的TFT阵列基板，其中，每间隔四条依次排列的扫描线，在相邻的上、下两行子像素之间，分别对应连接位于上一行子像素下侧、及位于下一行子像素上侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉。
  8. 如权利要求1所述的TFT阵列基板，其中，所述数据线的驱动方式为两点极性反转一次。
  9. 一种TFT阵列基板，具有显示区、非显示区，所述显示区包括多条相互平行并依次排列的竖直的数据线、多条相互平行并依次排列的水平的扫描线、及呈阵列式排布的子像素；
    在同一行子像素中，位于每条数据线左、右两侧的一偶数列子像素与一奇数列子像素分别通过一TFT共同电性连接于该条数据线；
    对应每一行子像素设置分别位于其上、下两侧的两条扫描线；在同一行子像素中，每一偶数列子像素通过一TFT电性连接于位于该行子像素上侧的扫描线，每一奇数列子像素通过一TFT电性连接于位于该行子像素下侧的扫描线；
    所述非显示区包括多条扇出线，每一扇出线对应连接一条扫描线，每一扇出线包括平行于相应扫描线的直线区、及连接直线区与相应扫描线的斜线区；
    每间隔两条或四条依次排列的扫描线，分别对应连接上、下相邻的两条扫描线的两条扇出线的斜线区相互绝缘交叉，从而改变该上、下相邻的两条扫描线的驱动顺序；
    其中，每间隔两条依次排列的扫描线，分别对应连接位于同一行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉；
    其中，分别对应连接位于每一偶数行子像素上、下两侧的两条扫描线的两条扇出线的斜线区相互绝缘交叉；
    其中，所述数据线的驱动方式为两点极性反转一次。
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