WO2016056872A1 - Tranche épitaxiale en carbure de silicium et dispositif à semi-conducteur comprenant ladite tranche - Google Patents

Tranche épitaxiale en carbure de silicium et dispositif à semi-conducteur comprenant ladite tranche Download PDF

Info

Publication number
WO2016056872A1
WO2016056872A1 PCT/KR2015/010694 KR2015010694W WO2016056872A1 WO 2016056872 A1 WO2016056872 A1 WO 2016056872A1 KR 2015010694 W KR2015010694 W KR 2015010694W WO 2016056872 A1 WO2016056872 A1 WO 2016056872A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon carbide
base substrate
layer
epitaxial layer
pattern
Prior art date
Application number
PCT/KR2015/010694
Other languages
English (en)
Korean (ko)
Inventor
김무성
Original Assignee
엘지이노텍 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지이노텍 주식회사 filed Critical 엘지이노텍 주식회사
Publication of WO2016056872A1 publication Critical patent/WO2016056872A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02447—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Definitions

  • Embodiments relate to a silicon carbide epitaxial wafer and a semiconductor device comprising the same.
  • reducing the crystal defects of the semiconductor layer grown on the substrate and improving the crystallinity of the semiconductor layer are the biggest research tasks for improving the efficiency and characteristics of the semiconductor device.
  • the base substrate including silicon carbide may have defects generated from the base surface of the grating, defects due to the lattice of the grating, and defects generated on the surface of the base substrate.
  • the defects may adversely affect the semiconductor device during the epi layer growth. In addition, it may adversely affect the operation of the switching device later.
  • the base substrate comprising silicon carbide includes Basal Plane Dislocation (BPD). It is important to reduce the base surface potential defect (BPD) because it greatly affects the reliability of the semiconductor device.
  • BPD Basal Plane Dislocation
  • a buffer layer is formed in order to reduce dislocation defects during crystal growth, and a step of forming a pattern on the surface of the substrate using mask formation, etching, or the like is further required for the buffer layer.
  • Embodiments provide a silicon carbide epitaxial wafer and a semiconductor device including the same, which can reduce process costs and improve the quality of a substrate surface.
  • a silicon carbide epitaxial wafer includes an epitaxial layer disposed on the base substrate; And a protrusion pattern disposed on at least one of the base substrate and the epi layer.
  • the semiconductor device according to the embodiment may form a pattern spaced apart from each other by a predetermined distance on the epi layer. Through this pattern, dislocation defects formed thereon can be suppressed.
  • the basal plane dislocation defect (BPD) of the silicon carbide substrate has a great influence on the reliability of the semiconductor device. As a pattern is formed, such dislocation defects can be prevented from defect growth and a high quality epi thin film can be obtained.
  • FIG. 1 is a cross-sectional view of a silicon carbide epitaxial wafer according to a first embodiment.
  • FIG. 2 is a cross-sectional view of a silicon carbide epitaxial wafer according to a second embodiment.
  • FIG 3 is a cross-sectional view of a silicon carbide epitaxial wafer according to a third embodiment.
  • 4 to 8 are views for explaining a manufacturing process of the silicon carbide epitaxial wafer according to the first embodiment.
  • 9 and 10 are cross-sectional views of semiconductor devices including silicon carbide epitaxial wafers according to embodiments.
  • each layer, region, pattern, or structure may be “on” or “under” the substrate, each layer, region, pad, or pattern.
  • Substrate formed in includes all formed directly or through another layer. Criteria for the top / bottom or bottom / bottom of each layer are described with reference to the drawings.
  • each layer (film), region, pattern, or structure may be modified for clarity and convenience of description, and thus do not necessarily reflect the actual size.
  • the silicon carbide epitaxial wafer according to the first embodiment may include a base substrate 100 and an epitaxial layer 200.
  • the base substrate 100 may include silicon carbide (SiC).
  • SiC silicon carbide
  • Such silicon carbide has a large band gap and a high thermal conductivity compared to silicon, while the carrier mobility is as large as that of silicon, and the electron saturation drift rate and breakdown voltage are also large. For this reason, the material is expected to be applied to semiconductor devices requiring high efficiency, high breakdown voltage and high capacity.
  • the epi layer 200 may be disposed on the base substrate 100.
  • the epi layer 200 may include a first epi layer 210 and a second epi layer 220.
  • the first epitaxial layer 210 may be disposed on the base substrate 100
  • the second epitaxial layer 220 may be disposed on the first epitaxial layer 210.
  • At least one epitaxial layer of the first epitaxial layer 210 and the second epitaxial layer 220 may include silicon carbide.
  • the first epitaxial layer 210 and the second epitaxial layer 220 may include silicon carbide.
  • a pattern may be disposed on at least one of the base substrate 100 and the epi layer 200.
  • At least one protrusion pattern 300 may be formed on the first epitaxial layer 210.
  • a plurality of protrusion patterns 300 may be formed on the first epitaxial layer 210.
  • At least one protrusion pattern 300 may be formed on the base substrate 100.
  • a plurality of protrusion patterns 300 may be formed on the base substrate 100.
  • At least one protrusion pattern may be formed on the base substrate 100 and the first epitaxial layer 210.
  • a plurality of protrusion patterns may be formed on the base substrate 100 and the first epitaxial layer 210.
  • first protrusion patterns 310 may be formed on the base substrate 100
  • second protrusion patterns 320 may be formed on the first epitaxial layer 210.
  • the protrusion pattern 300 may include a material similar to or different from that of the base substrate 100 or the first epitaxial layer 210.
  • the base substrate 100 or the first epitaxial layer 210 may include silicon carbide, and the protrusion pattern 300 may include at least one of SiN, p-SiC, and i-SiC. Can be.
  • the protrusion pattern 300 may be integrally formed with the base substrate 100 or the first epitaxial layer 210. That is, the protrusion pattern 300 includes the same or similar material as that of the base substrate 100 or the first epitaxial layer 210, and is integral with the base substrate 100 or the first epitaxial layer 210. It can be formed as.
  • the protrusion patterns 300 may be spaced apart at regular intervals.
  • the protrusion patterns 300 may be spaced apart from each other by nanometers (nm).
  • the protrusion patterns 300 may be spaced apart from each other by about 50 nm or more.
  • the protrusion patterns 300 may be spaced apart from each other at an interval of about 50 nm to about 100 nm or at an interval of about 50 nm to about 200 nm.
  • protrusion patterns 300 When the protrusion patterns 300 are disposed at intervals of less than about 50 nm, adjacent protrusion patterns 300 may be connected to each other so that the protrusion patterns 300 may be formed as a single layer, and the protrusion patterns 300 may be disposed. ) Are arranged at intervals exceeding about 200 nm, the spacing of the projection pattern is too wide, the effect may be lowered.
  • the protrusion pattern 300 may be arranged in a constant size.
  • the size of the projection pattern 300 may mean the diameter or height of the projection pattern.
  • the protrusion pattern 300 may be disposed in a size of about 100 nm to about 500 nm.
  • the protrusion pattern 300 may be disposed in a size of about 200 nm to about 500 nm.
  • the effect of the protrusion pattern may be insignificant, and when disposed in excess of the size of about 500nm, the crystal of the epi layer is changed by the protrusion pattern The effect may be noticeable.
  • the second epitaxial layer 220 may be disposed on the first epitaxial layer 210.
  • the second epitaxial layer 220 may be in contact with the protrusion pattern 300 formed on the first epitaxial layer 210. That is, the second epitaxial layer 220 may be disposed in contact with the first epitaxial layer 210 and the protrusion pattern 300.
  • the protrusion pattern 300 when the protrusion pattern 300 is disposed on the base substrate 100 as shown in FIGS. 2 and 3, the protrusion pattern 300 may include the first epitaxial layer 210 and / or the second epitaxial pattern. And may be placed in contact with layer 220. That is, the first epitaxial layer 210 is disposed in contact with the base substrate 100 and the first protruding pattern 310 or the protruding pattern 300, and the second epitaxial layer 220 is disposed in the first epitaxial layer 220. The epi layer 210 and the second protrusion pattern 320 may be in contact with each other.
  • the protrusion pattern 300 may include a curved surface.
  • the protrusion pattern 300 may include a curved surface in contact with the second epitaxial layer 220.
  • the protrusion pattern 300 may include a semicircle, a hemisphere or an ellipse shape, and the upper surface, that is, the surface contacting the second epitaxial layer 220 may include a curved surface.
  • the protrusion pattern 300 when the protrusion pattern 300 is disposed on the base substrate 100 as shown in FIGS. 2 and 3, the protrusion pattern 300 may include the first epitaxial layer 210 and / or the second epitaxial pattern.
  • the surface in contact with layer 220 may comprise a curved surface.
  • the protrusion pattern 300 may include a semicircle, a hemisphere or an ellipse shape, and the upper surface, that is, the surface in contact with the first epitaxial layer 210 and / or the second epitaxial layer 220. It may include a surface.
  • the base substrate 100 including silicon carbide may have defects generated from the bottom surface of the grating, defects caused by the lattice of the grating, and defects generated on the surface of the base substrate 100.
  • the defects may adversely affect the semiconductor device when the epitaxial layer 200 is grown. In addition, it may adversely affect the operation of the switching device later.
  • the base substrate 100 including silicon carbide may include a Basal Plane Dislocation (BPD). It is important to reduce the base surface potential defect (BPD) because it greatly affects the reliability of the semiconductor device.
  • BPD Basal Plane Dislocation
  • the buffer layer was further formed in the base substrate, and the epi layer was formed on the buffer layer. That is, crystal defects are prevented due to lattice constant mismatch and thermal expansion coefficient difference existing between the base substrate and the epi layer through the buffer layer.
  • an additional patterning process or a regrowth process step such as additional etching was required.
  • defect growth may be suppressed by forming the protrusion pattern 300 on the base substrate 100 or the first epitaxial layer 210. That is, the base surface potential defect BPD included in the base substrate 100 may no longer be grown by the pattern 300.
  • the silicon carbide epitaxial wafer according to the embodiment controls the bottom surface potential defects caused by the base substrate 100, so that a high quality epi thin film can be obtained, and potential bonding, which adversely affects the application of silicon carbide elements, The growth can be prevented and a high performance device can be manufactured.
  • the first epitaxial layer 210 is disposed on the base substrate 100.
  • the base substrate 100 or the first epitaxial layer 210 may include silicon carbide (SiC).
  • droplets may be formed on the first epitaxial layer 210.
  • silicon droplets 330 may be formed on the first epitaxial layer 210.
  • the silicon droplet 330 may be formed by injecting a silicon source onto the first epitaxial layer 210.
  • the silicon droplet 330 may be formed by introducing hydrogen (H 2) gas and monosilane (SiG 4 ) gas onto the first epitaxial layer 210.
  • a protrusion pattern 300 may be formed by injecting a desired gas onto the first epitaxial layer 210 on which the silicon droplets 330 are formed.
  • the projection pattern 300 including silicon nitride (SiN) may be formed by injecting nitrogen gas (N 2) onto the first epitaxial layer 210.
  • N 2 nitrogen gas
  • the embodiment is not limited thereto, and the projection pattern 300 including the p-SiC or i-SiC may be formed by adding carbon gas C or the projection pattern including the gas introduced by adding another gas. 300 can be formed.
  • the protrusion pattern may be formed while the injected gas and the surface of the silicon droplet 330 are replaced.
  • the protrusion pattern 300 formed as described above may have a curved surface.
  • hydrogen chloride (HCl) gas is added to the first epitaxial layer 210 to remove the silicon droplet 330, and spaced apart from the first epitaxial layer 210 by a predetermined distance. Only the protruding pattern 300 may be left.
  • a second epitaxial layer 220 may be formed on the first epitaxial layer 210 on which the protrusion pattern 300 is formed.
  • the second epitaxial layer 220 may include silicon carbide.
  • FIGS. 9 and 10 are cross-sectional views of a semiconductor device.
  • an electrode 416 may be formed on an upper surface of the second epitaxial layer 220.
  • the electrode 416 may include at least one of a metal material such as silver (Ag), copper (Cu), nickel (Ni), aluminum (Al), zinc (Zn), or an alloy thereof, and may be a vacuum deposition method. It can be formed by the method of.
  • a metal material such as silver (Ag), copper (Cu), nickel (Ni), aluminum (Al), zinc (Zn), or an alloy thereof, and may be a vacuum deposition method. It can be formed by the method of.
  • the semiconductor element shown in FIG. 10 is a horizontal semiconductor element.
  • electrodes 410 and 420 are formed on the second epitaxial layer 220.
  • the electrodes 410 and 420 have a horizontal structure arranged almost horizontally on an upper surface of the second epitaxial layer 220.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

La présente invention concerne une tranche épitaxiale en carbure de silicium qui, selon un mode de réalisation, comprend : une couche épitaxiale placée sur un substrat de base ; et un motif saillant placé sur le substrat de base et/ou sur la couche épitaxiale.
PCT/KR2015/010694 2014-10-10 2015-10-08 Tranche épitaxiale en carbure de silicium et dispositif à semi-conducteur comprenant ladite tranche WO2016056872A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2014-0136712 2014-10-10
KR1020140136712A KR102288817B1 (ko) 2014-10-10 2014-10-10 탄화규소 에피 웨이퍼 및 이를 포함하는 반도체 소자

Publications (1)

Publication Number Publication Date
WO2016056872A1 true WO2016056872A1 (fr) 2016-04-14

Family

ID=55653408

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2015/010694 WO2016056872A1 (fr) 2014-10-10 2015-10-08 Tranche épitaxiale en carbure de silicium et dispositif à semi-conducteur comprenant ladite tranche

Country Status (2)

Country Link
KR (1) KR102288817B1 (fr)
WO (1) WO2016056872A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11261169A (ja) * 1998-03-12 1999-09-24 Sony Corp 窒化物系ｉｉｉ−ｖ族化合物半導体の成長方法および半導体装置
JP2001011173A (ja) * 1999-06-30 2001-01-16 Mitsubishi Chemicals Corp ポリテトラメチレンエーテルグリコールの製造方法
JP2003243316A (ja) * 2002-02-20 2003-08-29 Fuji Photo Film Co Ltd 半導体素子用基板およびその製造方法
KR101125327B1 (ko) * 2011-01-25 2012-03-27 엘지이노텍 주식회사 반도체 소자 및 반도체 결정 성장 방법
KR20130053744A (ko) * 2011-11-16 2013-05-24 엘지이노텍 주식회사 반도체 소자 및 반도체 결정 성장 방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001111173A (ja) 1999-10-14 2001-04-20 Fuji Photo Film Co Ltd 半導体素子用基板およびその製造方法およびその半導体素子用基板を用いた半導体素子
KR20130065947A (ko) * 2011-12-12 2013-06-20 엘지이노텍 주식회사 반도체 소자 및 반도체 결정 성장 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11261169A (ja) * 1998-03-12 1999-09-24 Sony Corp 窒化物系ｉｉｉ−ｖ族化合物半導体の成長方法および半導体装置
JP2001011173A (ja) * 1999-06-30 2001-01-16 Mitsubishi Chemicals Corp ポリテトラメチレンエーテルグリコールの製造方法
JP2003243316A (ja) * 2002-02-20 2003-08-29 Fuji Photo Film Co Ltd 半導体素子用基板およびその製造方法
KR101125327B1 (ko) * 2011-01-25 2012-03-27 엘지이노텍 주식회사 반도체 소자 및 반도체 결정 성장 방법
KR20130053744A (ko) * 2011-11-16 2013-05-24 엘지이노텍 주식회사 반도체 소자 및 반도체 결정 성장 방법

Also Published As

Publication number Publication date
KR20160042592A (ko) 2016-04-20
KR102288817B1 (ko) 2021-08-11

Similar Documents

Publication Publication Date Title
WO2012093758A1 (fr) Modèle, procédé de fabrication de celui-ci, et procédé de fabrication d'un dispositif électroluminescent semi-conducteur au nitrure de type vertical
WO2012057512A2 (fr) Dispositif à semi-conducteur composite et son procédé de fabrication
WO2012093757A1 (fr) Modèle, procédé de fabrication de celui-ci, et procédé de fabrication d'un dispositif électroluminescent semi-conducteur au nitrure de type vertical
WO2014133267A1 (fr) Procédé de fabrication de substrat de nitrure
WO2010055987A1 (fr) Procédé de fabrication de substrat d'oxyde de gallium, dispositif électroluminescent et son procédé de fabrication
JP5228583B2 (ja) サセプタおよび気相成長装置
WO2010147357A2 (fr) Substrat hétérogène, dispositif à semi-conducteurs à base de nitrure l'utilisant et son procédé de fabrication
WO2014126300A1 (fr) Ensemble nanostructuré et nanodispositif le comprenant
WO2009093846A2 (fr) Procédé de fabrication d'un dispositif électroluminescent
WO2010098606A2 (fr) Procédé de fabrication de dispositif électroluminescent
KR20120029276A (ko) 질화물 단결정 제조 방법, 이를 이용한 질화물 반도체 발광 소자 및 그 제조 방법
KR20150002066A (ko) 에피택셜 웨이퍼
KR102098297B1 (ko) 에피택셜 웨이퍼
WO2016056872A1 (fr) Tranche épitaxiale en carbure de silicium et dispositif à semi-conducteur comprenant ladite tranche
WO2013062317A1 (fr) Dispositif et procédé pour fabriquer une tranche epi et tranche epi
WO2012102539A2 (fr) Dispositif de semi-conducteur et procédé de croissance d'un cristal de semi-conducteur
WO2016108423A1 (fr) Dispositif électroluminescent
JP6898222B2 (ja) 化合物半導体基板
WO2012074228A2 (fr) Dispositif semi-conducteur à base de nitrure et son procédé de fabrication
WO2012148039A1 (fr) Substrat semi-conducteur, et procédé de fabrication associé
WO2010110608A2 (fr) Dispositif électroluminescent à semi-conducteur à base de nitrure
KR102534857B1 (ko) 탄화규소 에피 웨이퍼 및 이를 포함하는 반도체 소자
WO2009128646A2 (fr) Substrat de semi-conducteur et son procédé de fabrication
KR101125327B1 (ko) 반도체 소자 및 반도체 결정 성장 방법
WO2021145695A1 (fr) Film mince pour dispositif électronique et son procédé de fabrication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15848187

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15848187

Country of ref document: EP

Kind code of ref document: A1