WO2021145695A1 - Film mince pour dispositif électronique et son procédé de fabrication - Google Patents

Film mince pour dispositif électronique et son procédé de fabrication Download PDF

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WO2021145695A1
WO2021145695A1 PCT/KR2021/000534 KR2021000534W WO2021145695A1 WO 2021145695 A1 WO2021145695 A1 WO 2021145695A1 KR 2021000534 W KR2021000534 W KR 2021000534W WO 2021145695 A1 WO2021145695 A1 WO 2021145695A1
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thin film
electronic device
carbon nanotube
metal catalyst
layer
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Korean (ko)
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하준석
차안나
노호균
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전남대학교산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02414—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02444—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02483—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy

Definitions

  • the present invention relates to a thin film for an electronic device and a method for manufacturing the same, and more particularly, ELOG
  • Epitaxy technology is one of the crystal growth methods for growing a thin thin film crystal on a wafer (substrate) made of a single crystal, and a new single crystal layer formed thereby is called an epitaxial layer.
  • the single crystal substrate and the epitaxial layer may be of the same material (homoepitaxy) or different materials (heteroepitaxy), but in both cases, the lattice constant of the material of the single crystal substrate and the material of the epitaxial layer must be the same or similar. If a material having a lattice constant different from the lattice constant of a single crystal substrate is grown as an epitaxial layer to a critical thickness or more, the epitaxial layer has defects such as dislocations or micro-twins. This inevitably happens.
  • Defects in the epitaxial layer deteriorate the optical and electrical properties of the entire electronic device, and thus, research on removing defects in the epitaxial layer or minimizing the density of defects has been conducted.
  • an epitaxial lateral over growth (ELOG) method for suppressing partial transition of defects by using a metal or other material and forming a high-quality epitaxial layer by using the lateral growth of the growth layer is proposed.
  • ELOG epitaxial lateral over growth
  • UWB Ga 2 O 3 (gallium oxide) material has price competitiveness because its manufacturing cost is 1/3 to 1/5 times lower than that of GaN or SiC.
  • Ga 2 O 3 Since the thin film has defects due to the increase in penetration dislocation and strain, there is a need to study a thin film to which a simple process is applied while reducing defects.
  • An object of the present invention is to provide a high-quality thin film for an electronic device formed by the ELOG method and a method for manufacturing the same.
  • an embodiment of the present invention provides a thin film for an electronic device.
  • the thin film for an electronic device comprises: a substrate; a buffer layer positioned on the substrate; a carbon nanotube-metal catalyst composite layer positioned on the buffer layer; and a metal oxide epitaxial layer positioned on the carbon nanotube-metal catalyst composite layer.
  • the substrate may include sapphire, silicon or FTO.
  • the buffer layer material may be the same material as the metal oxide epitaxial layer.
  • the metal catalyst of the carbon nanotube-metal catalyst composite layer may include palladium, titanium, nickel, copper or gold.
  • the particle size of the metal catalyst may be 50 nm or less.
  • the metal oxide epitaxial layer may include Ga 2 O 3 , ITO, MgO or MoO 3 .
  • another embodiment of the present invention provides a method of manufacturing a thin film for an electronic device.
  • a method of manufacturing a thin film for an electronic device includes: preparing a substrate; forming a buffer layer on the substrate; forming a carbon nanotube-metal catalyst composite layer on the buffer layer; and forming a metal oxide epitaxial layer on the carbon nanotube-metal catalyst composite layer.
  • the substrate in the step of preparing the substrate, may include sapphire, silicon or FTO.
  • the buffer layer material in the step of growing the buffer layer on the substrate, may be the same material as the metal oxide epitaxial layer.
  • the step of growing the buffer layer on the substrate may be performed by a vapor phase epitaxy (VPE) method.
  • VPE vapor phase epitaxy
  • the growth temperature of the buffer layer in the step of growing the buffer layer on the substrate, may be 300 °C to 700 °C.
  • the metal catalyst of the carbon nanotube-metal catalyst composite layer includes palladium, titanium, nickel, copper or gold. can do.
  • the coating of the carbon nanotube-metal catalyst composite layer on the buffer layer may be performed by a spray method.
  • the thickness of the formed carbon nanotube-metal catalyst composite layer may be 5 nm to 100 nm.
  • the size of the metal catalyst particles may be 50 nm or less.
  • the metal oxide epitaxial layer in the step of growing the metal oxide epitaxial layer on the carbon nanotube-metal catalyst composite layer, includes Ga 2 O 3 , ITO, MgO or MoO 3 . can do.
  • the step of growing a metal oxide epitaxial layer on the carbon nanotube-metal catalyst composite layer may be performed by a vapor phase epitaxy (VPE) method.
  • VPE vapor phase epitaxy
  • the growth temperature of the metal oxide epitaxial layer in the step of growing the metal oxide epitaxial layer on the carbon nanotube-metal catalyst composite layer, may be 300°C to 700°C.
  • the penetration dislocation and strain that were conventionally internally generated due to the difference in the lattice constant between the substrate and the epitaxial structure are reduced, so that it is hardly affected by the difference in the lattice constant, so that it is free from defects can
  • the ELOG method is performed by a spray method, it can be applied to a large area, and the process is relatively simple, thereby reducing production costs and advantageous for mass production.
  • FIG. 1 is a schematic diagram of a thin film for an electronic device according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a carbon nanotube-palladium composite according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of a method of manufacturing a thin film for an electronic device according to an embodiment of the present invention.
  • FIG. 4 is a Raman signal graph of a thin film for an electronic device according to an embodiment of the present invention.
  • 5 is XRD Omega rocking curves of a thin film for an electronic device according to an embodiment of the present invention.
  • FIG. 6 is a TEM image of a comparative example, according to an embodiment of the present invention.
  • FIG. 7 is a TEM image of a preparation example, according to an embodiment of the present invention.
  • a thin film for an electronic device according to an embodiment of the present invention will be described.
  • FIG. 1 is a schematic diagram of a thin film for an electronic device according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a carbon nanotube-palladium composite according to an embodiment of the present invention.
  • the thin film for an electronic device a substrate 10; a buffer layer 20 positioned on the substrate 10; a carbon nanotube-metal catalyst composite layer 30 positioned on the buffer layer 20; and a metal oxide epitaxial layer 40 positioned on the carbon nanotube-metal catalyst composite layer 30; includes
  • the substrate 10 may include sapphire (Al 2 O 3 ), silicon (Si), or fluorine doped tin oxide (FTO).
  • the substrate 10 may be a sapphire c-plane.
  • the substrate 10 has a different lattice constant from the buffer layer.
  • the buffer layer 20 may be positioned on the substrate 10 .
  • the buffer layer 20 may be the same material as the metal oxide epitaxial layer 40 .
  • both the buffer layer 20 and the metal oxide epitaxial layer 40 may include a Ga 2 O 3 material.
  • the buffer layer 20 may use a material having the same or similar crystal structure as that of the metal oxide epitaxial layer 40 .
  • the buffer layer 20 has a lattice constant different from that of the substrate 10 , which may cause defects due to penetration dislocation or strain on the buffer layer 20 .
  • the buffer layer 20 reduces the interfacial energy of the metal oxide epitaxial layer 40 to enable high-density nucleation, and induces the metal oxide epitaxial layer 40 to grow in a two-dimensional plane. This can help to form a high-quality thin film.
  • the carbon nanotube-metal catalyst composite layer 30 may be positioned on the buffer layer 20 .
  • the carbon nanotube may be, for example, a single-walled carbon nanotube (single-walled CNT, SWCNT).
  • Carbon nanotubes have electrical properties such as high electrical conductivity, mechanical properties such as high mechanical strength, and thermal and chemical stability.
  • the metal catalyst of the carbon nanotube-metal catalyst composite layer 30 may include palladium (Pd), titanium (Ti), nickel (Ni), copper (Cu), or gold (Au).
  • the carbon nanotube-metal catalyst composite layer 30 may be a single-walled carbon nanotube-palladium composite layer.
  • the particle size of the metal catalyst may be 50 nm or less. For example, it may be 20 nm or less.
  • the carbon nanotube-metal catalyst composite layer 30 may be one in which a metal catalyst is deposited and bonded to the surface of the carbon nanotube.
  • a metal catalyst is deposited and bonded to the surface of the carbon nanotube.
  • palladium (Pd) may be bonded to the surface of the carbon nanotube.
  • the carbon nanotube-metal catalyst composite layer 30 may serve as a conventional mask layer, and may prevent defects from diffusing into the metal oxide epitaxial layer 40 .
  • the carbon nanotube-metal catalyst composite layer 30 absorbs or relieves strain generated due to a large difference in lattice constant and thermal expansion coefficient between the substrate 10 and the metal oxide epitaxial layer 40 . can do it
  • a metal oxide epitaxial layer 40 may be positioned on the carbon nanotube-metal catalyst composite layer 30 .
  • the metal oxide epitaxial layer 40 may include Ga 2 O 3 , indium tin oxide (ITO), MgO, or MoO 3 .
  • the metal oxide epitaxial layer 40 is defective due to a difference in lattice constant from the substrate 10 due to the presence of the buffer layer 20 and the carbon nanotube-metal catalyst composite layer 30 between the substrate 10 and the substrate 10 . may not have
  • FIG. 3 is a flowchart of a method of manufacturing a thin film for an electronic device according to an embodiment of the present invention.
  • the manufacturing method of the thin film for an electronic device preparing a substrate (S100); forming a buffer layer on the substrate (S200); forming a carbon nanotube-metal catalyst composite layer on the buffer layer (S300); and forming a metal oxide epitaxial layer on the carbon nanotube-metal catalyst composite layer (S400); includes
  • a substrate is prepared (S100).
  • the substrate may include sapphire (Al 2 O 3 ), silicon (Si), or fluorine doped tin oxide (FTO).
  • the substrate may be a sapphire c-plane.
  • the substrate has a different lattice constant from the buffer layer.
  • a buffer layer is formed on the substrate (S200).
  • the buffer layer material may be the same material as the metal oxide epitaxial layer material.
  • the buffer layer may use a material having the same or similar crystal structure as that of the metal oxide epitaxial layer.
  • the buffer layer may be formed in the same manner as the metal oxide epitaxial layer.
  • Formation of the buffer layer may be performed by a vapor phase epitaxy (VPE) method, preferably by a hydride vapor phase epitaxy (HVPE) method.
  • VPE vapor phase epitaxy
  • HVPE hydride vapor phase epitaxy
  • MOCVD metal organic chemical vapor deposition
  • LPE liquid phase epitaxy
  • MBE molecular beam epitaxy
  • HVPE has a growth rate several times faster than MOCVD, which is mainly used for group III nitride semiconductor growth, has a very low impurity concentration in the grown thin film, and can be economical in operation of equipment.
  • the formation (growth) temperature of the buffer layer may be 300 °C to 700 °C. For example, it may be 450 °C to 520 °C. When the temperature is less than 300° C., growth of the buffer layer does not occur smoothly, and when it exceeds 700° C., a parasitic reaction may occur to interfere with epitaxial growth.
  • the metal catalyst of the carbon nanotube-metal catalyst composite layer may include palladium (Pd), titanium (Ti), nickel (Ni), copper (Cu), or gold (Au).
  • the step of forming the carbon nanotube-metal catalyst composite layer may be performed by a spray method.
  • the spraying method is economical because it does not require complicated processes or equipment to be coated by drying after application by spraying.
  • the thickness of the formed carbon nanotube-metal catalyst composite layer may be 5 nm to 100 nm. Preferably, it may be 10 nm to 30 nm. If the thickness is less than 5 nm, the penetration potential control may not be properly controlled due to the lack of a metal catalyst that is non-uniformly sprayed, and if it exceeds 100 nm, the growth portion of the metal oxide is narrowed and the growth rate of the epitaxial layer may be slow.
  • the particle size of the metal catalyst may be 50 nm or less. For example, it may be 20 nm or less.
  • the carbon nanotube-metal catalyst composite layer absorbs or alleviates strain generated due to a large difference in lattice constant and thermal expansion coefficient between the substrate and the metal oxide epitaxial layer, thereby reducing defects in the thin film.
  • the metal oxide epitaxial layer may include Ga 2 O 3 , indium tin oxide (ITO), MgO, or MoO 3 .
  • Formation of the metal oxide epitaxial layer may be performed by a vapor phase epitaxy (VPE) method, preferably by a hydride vapor phase epitaxy (HVPE) method.
  • VPE vapor phase epitaxy
  • HVPE hydride vapor phase epitaxy
  • MOCVD metal organic chemical vapor deposition
  • LPE liquid phase epitaxy
  • MBE molecular beam epitaxy
  • the formation (growth) temperature of the metal oxide epitaxial layer may be 300°C to 700°C. For example, it may be 450 °C to 520 °C. When the temperature is less than 300° C., the growth of the metal oxide epitaxial layer does not occur smoothly, and when it exceeds 700° C., a parasitic reaction may occur to interfere with the epitaxial growth.
  • a lateral growth ELOG Epitaxial Lateral Overgrowth
  • the epitaxial thin film is selectively grown vertically or horizontally according to the mask and pattern of the substrate, and the penetration dislocation is bent or blocked by the mask in the horizontal growth region, thereby suppressing penetration into the surface.
  • the growth rate of the epitaxial layer was increased by blocking the penetration dislocation with the carbon nanotube-metal catalyst composite layer instead of the conventional mask layer, and the quality of the epitaxial layer was improved.
  • the growth (formation) temperature is performed at 450°C to 520°C.
  • the pressure is 1000 sccm for N 2 as a carrier gas, 100 to 200 sccm for O 2 as a reaction gas, and 20 to 30 sccm for HCl.
  • Ga 2 O 3 Buffer layer is grown on the substrate using HVPE for 30 minutes. make it
  • SWCNT single-walled carbon nanotube
  • PdCl 2 /HCl solution 0.5wt% of single-walled carbon nanotube (SWCNT) dispersion solution (relative to the total weight of distilled water in which carbon nanotubes are dispersed) and PdCl 2 /HCl solution are mixed in a 3:1 volume ratio (carbon nanotube: palladium ion) for about 5 minutes During stirring at room temperature at a speed of 200 rpm, a carbon nanotube-palladium composite is prepared.
  • SWCNT single-walled carbon nanotube
  • the single-walled carbon nanotube-palladium composite is applied on the Ga 2 O 3 buffer layer by a spray process, and then dried in an oven at about 80° C. for about 1 hour. Next, the dried single-walled carbon nanotube-palladium thin film is washed in DI water to remove impurities.
  • the growth temperature is carried out at 450 °C to 520 °C.
  • the pressure is 1000 sccm for N 2 as a carrier gas, 100 to 200 sccm for O2 as a reaction gas, and 20 to 30 sccm for HCl, using HVPE for 30 minutes on the single-walled carbon nanotube-palladium composite layer.
  • Ga 2 O 3 epitaxial layer is grown.
  • the growth temperature is carried out at 450 °C to 520 °C.
  • the pressure is 1000 sccm for N 2 as a carrier gas, 100 to 200 sccm for O2 as a reaction gas, and 20 to 30 sccm for HCl.
  • FIG. 4 is a Raman signal graph of a thin film for an electronic device according to an embodiment of the present invention.
  • the single-walled carbon nanotube-palladium composite in the preparation example was coated on the Ga 2 O 3 buffer layer by a spray process and then observed using Raman mapping. It can be seen that a single-walled carbon nanotube-palladium thin film layer is formed on the Ga 2 O 3 buffer layer.
  • the full width half maximum (FWHM) value of the rocking curve of the (0006) plane is related to the screw or mixed dislocation in the thin film, and the rocking of the (10(-)14) plane
  • the FWHM value of the curve is related to the penetration dislocation and strain in the thin film.
  • FIG. 6 is a TEM image of a comparative example, according to an embodiment of the present invention.
  • defects occur due to a difference in lattice constants between the conventional substrate (Al 2 O 3 ) and Ga 2 O 3 .
  • FIG. 7 is a TEM image of a preparation example, according to an embodiment of the present invention.
  • a defect occurs due to the difference in lattice constant between the conventional substrate (Al 2 O 3 ) and Ga 2 O 3 , but the defect is extinguished by the single-walled carbon nanotube-palladium, so that the compressive strain in the thin film is effectively reduced It can be seen that the quality of the thin film is improved by relaxation.
  • the penetration dislocation and strain that were conventionally internally generated due to the difference in the lattice constant between the substrate and the metal oxide epitaxial structure are reduced, and thus, the thin film for an electronic device is hardly affected by the lattice constant difference. can be free in
  • the ELOG method is performed by a spray method, it can be applied to a large area, and the process is relatively simple, thereby reducing production costs and advantageous for mass production.

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Abstract

Un mode de réalisation de la présente invention concerne un film mince pour un dispositif électronique. Le film mince comprend : un substrat ; une couche tampon positionnée sur le substrat ; une couche composite de nanotubes de carbone et catalyseur métallique positionnée sur la couche tampon ; et une couche épitaxiale d'oxyde métallique positionnée sur la couche composite de nanotubes de carbone et catalyseur métallique. Dans le film mince pour un dispositif électronique selon un mode de réalisation de la présente invention, la dislocation d'enfilage et la contrainte, qui se produisaient généralement à l'intérieur en raison de la différence de constante de réseau entre un substrat et une structure épitaxiale d'oxyde métallique, sont réduites et, par conséquent, le film mince est peu affecté par la différence de constante de réseau et peut donc être exempt de défauts.
PCT/KR2021/000534 2020-01-17 2021-01-14 Film mince pour dispositif électronique et son procédé de fabrication WO2021145695A1 (fr)

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KR10-2020-0006534 2020-01-17
KR1020200006534A KR102274144B1 (ko) 2020-01-17 2020-01-17 전자 소자용 박막 및 그의 제조방법

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060092771A (ko) * 2005-02-19 2006-08-23 삼성에스디아이 주식회사 탄소나노튜브 구조체 및 그 제조방법과, 탄소나노튜브 구조체를 이용한 전계방출소자 및 그 제조방법
KR100774359B1 (ko) * 2006-10-23 2007-11-08 부산대학교 산학협력단 갈륨나이트라이드 박막 위에 에피탁셜 성장된 갈륨옥사이드투명 전계효과 트랜지스터 제조방법 및 그 트랜지스터
KR20100117075A (ko) * 2008-02-25 2010-11-02 스몰텍 에이비 나노구조 프로세싱을 위한 도전성 보조층의 증착과 선택적 제거
KR101210426B1 (ko) * 2012-02-28 2012-12-11 한빔 주식회사 반도체 발광소자용 서브마운트 기판 및 이를 이용한 반도체 발광소자의 제조방법
JP2015187072A (ja) * 2014-03-26 2015-10-29 ツィンファ ユニバーシティ エピタキシャル構造体

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8734929B2 (en) * 2008-08-25 2014-05-27 Snu R&Db Foundation Hydrophobic composites and methods of making the same
KR101636915B1 (ko) * 2010-09-03 2016-07-07 삼성전자주식회사 그래핀 또는 탄소나노튜브를 이용한 반도체 화합물 구조체 및 그 제조방법과, 반도체 화합물 구조체를 포함하는 반도체 소자
KR101125327B1 (ko) 2011-01-25 2012-03-27 엘지이노텍 주식회사 반도체 소자 및 반도체 결정 성장 방법
KR102099877B1 (ko) * 2013-11-05 2020-04-10 삼성전자 주식회사 질화물 반도체 디바이스의 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060092771A (ko) * 2005-02-19 2006-08-23 삼성에스디아이 주식회사 탄소나노튜브 구조체 및 그 제조방법과, 탄소나노튜브 구조체를 이용한 전계방출소자 및 그 제조방법
KR100774359B1 (ko) * 2006-10-23 2007-11-08 부산대학교 산학협력단 갈륨나이트라이드 박막 위에 에피탁셜 성장된 갈륨옥사이드투명 전계효과 트랜지스터 제조방법 및 그 트랜지스터
KR20100117075A (ko) * 2008-02-25 2010-11-02 스몰텍 에이비 나노구조 프로세싱을 위한 도전성 보조층의 증착과 선택적 제거
KR101210426B1 (ko) * 2012-02-28 2012-12-11 한빔 주식회사 반도체 발광소자용 서브마운트 기판 및 이를 이용한 반도체 발광소자의 제조방법
JP2015187072A (ja) * 2014-03-26 2015-10-29 ツィンファ ユニバーシティ エピタキシャル構造体

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