WO2016046741A1 - Wafer-träger-anordnung, verfahren zu deren herstellung und verwendung der anordnung bei der bearbeitung des wafers - Google Patents
Wafer-träger-anordnung, verfahren zu deren herstellung und verwendung der anordnung bei der bearbeitung des wafers Download PDFInfo
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- WO2016046741A1 WO2016046741A1 PCT/IB2015/057291 IB2015057291W WO2016046741A1 WO 2016046741 A1 WO2016046741 A1 WO 2016046741A1 IB 2015057291 W IB2015057291 W IB 2015057291W WO 2016046741 A1 WO2016046741 A1 WO 2016046741A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
- C23C16/4582—Rigid and flat substrates, e.g. plates or discs
- C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
- C23C16/4586—Elements in the interior of the support, e.g. electrodes, heating or cooling devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
- B01J—CHEMICAL OR PHYSICAL PROCESSES, e.g. CATALYSIS OR COLLOID CHEMISTRY; THEIR RELEVANT APPARATUS
- B01J19/00—Chemical, physical or physico-chemical processes in general; Their relevant apparatus
- B01J19/0046—Sequential or parallel reactions, e.g. for the synthesis of polypeptides or polynucleotides; Apparatus and devices for combinatorial chemistry or for making molecular arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68728—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of separate clamping members, e.g. clamping fingers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
Definitions
- WAFER-CARRIER ARRANGEMENT METHOD FOR THE PRODUCTION AND USE OF THE ARRANGEMENT FOR MACHINING THE WAFERS
- the present invention relates to a wafer carrier arrangement comprising a wafer, a carrier system comprising a carrier and an elastomer layer and a connecting layer, wherein the connecting layer is a sol-gel layer.
- the invention further relates to a coated wafer for a wafer carrier arrangement according to the invention, to the use of a sol-gel layer as connection layer for a corresponding wafer carrier arrangement and to a method for processing the back side of a wafer.
- wafers In the manufacture of such electronic components and circuits (diodes, transistors, ICs, sensors, etc.), structures and layers for generating the desired electronic functions are applied to wafers (optionally doped silicon wafers, gallium arsenide, etc.) by means of various technologies.
- wafers optionally doped silicon wafers, gallium arsenide, etc.
- these wafers are provided with a protective film or other protective layer on completion of the necessary manufacturing steps on the front side (that is, the active side or the side on which the applied structures are located).
- This film or layer has the task of the wafer front side and in particular the applied thereon electrical and mechanical structures during the subsequent subsequent thinning and / or other processing of the backside of the wafer. Thinning is accomplished by techniques such as grinding, lapping, grinding, etching, or the like of the backside of the wafer.
- the aim of this procedure is to reduce the original thickness of the wafer.
- the extent of the reduction is decisively determined by the expected mechanical and thermal loads during the thinning and / or the subsequent subsequent process steps: Since the wafer, when it is thinned, has already undergone a large number of process steps, it already has a high economic Value. Therefore, the risk of breaking the wafer must be kept as low as possible. Accordingly, thinning to the extent that it would actually be desired, often not possible because otherwise occur too large losses due to breakage of the wafer.
- the wafer is then placed backside down (active side up) on a sawing foil, an expansion foil or a frame. Subsequently, the separation of the wafer, d. H.
- the wafer is separated into individual components (microplates, dies). This separation is often done by means of rotary cutting discs or other mechanical sawing devices. However, laser separation methods are also used. Alternatively, the wafers are also broken during separation, with some supportive methods such as scratches used.
- methods are also used today in which the wafer on the front side is already structured prior to the thinning process by means of grinding scribing, scribing, chemical etching, plasma etching of trenches and / or structures such that these structures during the subsequent Thinning process by mechanical and / or chemical processes can be achieved from the back so that the wafer is separated.
- the carrier layer proposed there is not optimally adapted: in particular in the case of three-dimensionally structured wafer surfaces (such as, for example, bumped wafers or wafers with an undercut on their surface), the proposed carrier plain (eg, polyimide or polyamide) too hard: Since the plasma polymer release layer substantially coats the surface structures of the wafer with a consistently thick layer, gaps such as undercuts or gaps between the bumps should be filled by the material for the backing layer. If this is the case, however, it is due to the hardness of the carrier layer that the carrier layer is not destructively removable from the wafer again.
- the carrier plain eg, polyimide or polyamide
- the carrier layer does not fill out the surface structures, cavities remain which adversely affect the adhesion between carrier layer and separating layer and can lead to undesired inclusions.
- additional mechanical stress is generated for the wafer.
- WO 2007/09946 A1 discloses a separation method in which thinned wafers can be mechanically separated after thinning. This is made possible by the use of a plasma polymer separating layer in combination with an elastomer layer.
- a wafer carrier arrangement comprising a wafer
- a carrier system comprising a carrier and an elastomeric layer, wherein the elastomeric layer is oriented towards the wafer and
- tie layer wherein the tie layer is a sol-gel layer, preparable from the monomers
- each R 1 is independently of the other H or a - C 8 alkyl radical
- R 2, R 3, R 4, R 5, R 6 and R 7 are each independently of one another a - C 20 alkyl radical, a fluorinated - C 20 alkyl Radical, a - C 20 -aminoalkyl radical, a C 2 - C 20 - Alkenyl radical, an aryl radical, a fluorinated aryl radical, a mono-, di- or tri-C 4 -alkylated aryl radical, where the alkylations are independent of one another in terms of their C atom number and / or wherein the radical may also be fluorinated, or a C 3 -C 20 -epoxy radical.
- a wafer preferably comprises electronic components on its front side, this front side being protected by the connection layer to be used according to the invention.
- a wafer-carrier arrangement wherein in the connecting layer each represents independently of the other H or a - C 5 -alkyl radical and / or R 2, R 3, R 4, R 5, R 6 and R 7 in each case independently of one another - C 8- alkyl radical, a fluorinated-C 8 -alkyl radical, a - C 8 -aminoalkyl radical, a C 2 - C 8 -alkenyl radical, an aryl radical, a fluorinated aryl radical, a simple a double or triple C 4 -alkylated aryl radical, the alkylations being independent of one another in terms of their C atom number and / or the radical also being fluorinated, or a C 3 -C 8 -epoxy radical.
- Preferred solvents in the preparation of the compound layer are selected from the group consisting of alcohols, in particular methanol, ethanol, propanol, butanol, pentanol, water, aprotic solvents, in particular PGMEA (1-methoxy-2-propyl acetate), acetone or ethyl acetate.
- Particularly preferred solvents are selected from the group of the alcohols, in particular 2-propanol and 2-methyl-1-propanol.
- Preferred activators for the sol-gel reaction in the preparation of the compound layer are selected from the group consisting of acids and bases, in particular TMAH (tetramethylammonium hydroxide), formic acid, hydrochloric acid and sulfuric acid.
- Further preferred activators are Lewis acids or bases, organometallic compounds such as e.g. Tributyltin or fluoride-containing compounds, such. TBAF (tetrabutylammonium fluoride) or cesium fluoride.
- Particularly preferred activators are TMAH, TBAF and sulfuric acid.
- each R1 is independently of the other H or a - C 3 alkyl and / or R2, R3, R4, R5, R6 and R7 are each independently a - C 3 alkyl radical or a fluorinated Represent C 3 alkyl.
- the wafer carrier arrangement according to the invention can be separated very easily and, above all, without much mechanical stress for the wafer. In this case, it is possible to chemically remove the sol-gel layer after separation, for example.
- the sol-gel layer to be used according to the invention has the advantage that sol-gel layers can generally be adapted to the requirements in terms of their properties. Preference is given to sol-gel layers which are temperature resistant up to 450 ° C ⁇ without chemical change.
- the sol-gel layer used according to the invention is silicon-based and thus readily compatible with elastomers, in particular with silicon-based elastomers.
- the compound layer to be used according to the invention is inexpensive and non-toxic. After the polymerization, the sol-gel layer is chemically constant over a long period of time. Due to the monomers used, it is easy to introduce into typical wafer production processes, since it can be produced, for example, from a liquid.
- molar ratio of the monomers (1) to the sum of the molar amounts of the monomers (2), (3) and (4) is 0.032 (1: 31, 25) to 1, 6 (1, 6: 1) is preferably 0.05 to 1 (1: 20 to 1: 1) and more preferably 0.064 to 0.5 (1: 15.63 to 0.5: 1).
- the layer thickness of the connecting layer is 10 to 200 nm, preferably 20 to 150 nm and particularly preferably 30 to 100 nm.
- the preferred layer thicknesses allow a particularly stress-free separation of the carrier system from the wafer.
- elastomer layer is an organosilicon layer.
- the elastomer layer (that is to say a layer consisting of elastomer) is preferably a layer consisting of a material selected from the group consisting of Methyl, phenyl, epoxyalkyl, epoxyarylalkylsilicone or mixed functional silicone, eg methylphenylsilicone; (Catalytically) via silicone-crosslinked silicone elastomer having at least one of the aforementioned functionalities and their mixtures with silicone resins, all with or without fillers.
- the elastomer layer has a Shore A hardness of 40 to 100, preferably 45 to 90, more preferably 50 to 80 and particularly preferably 55 to 75. The Shore hardness is determined according to DIN 53505-A-87.
- the adhesive force (adhesion) between the respective layers can be determined by the person skilled in the art according to DIN EN ISO 4618: 2007-03, and is defined as "the total of the binding forces between a coating and its substrate.”
- the adhesive force between the layers which is preferred the surface of the lowest adhesive force (as an interface) determined according to measurement example 1 determined.
- this particularly preferred wafer carrier arrangement is that, owing to the properties of the elastomer material (flexibility, extensibility), it is possible to produce an ideal connection between the elastomer layer and the bonding layer on the wafer.
- the adhesive strength between the bonding layer and the elastomer layer can be produced such that when the wafer carrier arrangement according to the invention is separated, the elastomer material is completely detached from the bonding layer. In this case, this separation is preferably mechanical.
- the wafer comprises electronic components on the side facing the connection layer (front side).
- a wafer carrier arrangement according to the invention is preferred, wherein the carrier is a glass plate or a second wafer.
- Part of the invention is also a coated wafer of a wafer carrier arrangement according to the invention, wherein the coating is a bonding layer, as defined above.
- This coated wafer can be used as a precursor to the wafer carrier assembly of the present invention by applying a carrier system as defined above to the tie layer.
- the connecting layer has a static water edge angle of> 80 °, preferably> 83 °, and / or a surface energy of 15-25 mJ / m 2 on the side facing away from the wafer
- Part of the invention is also the use of a bonding layer as defined above for producing a wafer carrier arrangement according to the invention or a coated wafer according to the invention.
- a further aspect of the invention is a method for processing the back side of a wafer, comprising the steps: a) providing a wafer carrier arrangement according to the invention, b) processing the back side of the wafer, and c) mechanically separating the wafer carrier arrangement along the interface between the elastomeric layer and the tie layer.
- Processing of the backside of the wafer may be in particular: metallization, thinning TSV: through silicon via-contacting, lithography techniques.
- the mechanical separation for the process according to the invention is preferably carried out as follows:
- the wafer-carrier assembly is fixed by vacuum or mechanically on both sides, the flexible fixation on the support side is raised starting from one side, whereby the carrier detaches from the wafer.
- This process is carried out as described in WO 002010072826 A2, in particular as described in FIG. 3 and the accompanying text.
- step c) the bonding layer is chemically removed from the wafer.
- This chemical removal can in principle be effected by any suitable means. It is important to ensure that the bonding layer is reliably removed, while the wafer and in particular the electronic components possibly present on the wafer are not affected.
- Suitable means for the chemical removal of the tie layer are strong acids and alkalis, as well as compounds which provide fluoride ions, e.g. TBAF, CsF, HF or KHF2 Particularly preferred for the chemical removal of the compound layer is tetrabutylammonium fluoride (TBAF).
- TBAF tetrabutylammonium fluoride
- TBAF is known for a variety of applications, but so far not for the specific one proposed here.
- TBAF is known, for example, as a means for the removal of silyl-containing protective groups, in the preparation of sol-gel systems as activator / catalyst, as a remover for silicones and as a phase transfer catalyst. Applicability to sol-gel layers has not previously been known in particular in connection with the present invention.
- TEOS tetraethyoxysilane
- modifier alkyl-modified silane
- Silanes with large alkyl radicals such as Hexadecyltrimethoxysilane or fluorinated alkyl radicals
- both the times until activation of the mixture, as well as the storage stability can be influenced.
- the lower the activator content the longer the mixture takes to activate, but also the storage stability is significantly increased.
- the resulting surface energies can also be influenced: If less activator is added, the surface energies are reduced.
- the choice of activator also influences the resulting adhesive forces, which increase by up to 35% for acid-based activators, such as sulfuric acid, compared to TMAH-based activators. The adhesive forces with equimolar replacement of TMAH by TBAF hardly change.
- FIG. 2 schematically illustrates the separation of a wafer carrier arrangement according to the invention.
- the reference numerals have the same meaning as in FIG. 1.
- the reference numerals have the same meaning as in FIG. 1.
- the reference numerals have the same meaning as in FIG. 1.
- the reference numerals have the same meaning as in FIG. 1.
- the reference numerals have the same meaning as in FIG. 1.
- the wafer 1 is first coated on its front with liquid monomers 2 for the bonding layer 3 (sol-gel layer).
- the material 4 for the elastomer layer 5 is initially still liquid.
- FIG. 1 c) represents the wafer carrier arrangement 1, 3, 5 according to the invention in a finished form, in which material for the elastomer layer 4 was first applied starting from FIG. 1 b). Subsequently, the carrier 7 was placed on the not yet (fully) cured elastomer layer and subsequently cured in the material for the elastomer layer 4 to the elastomer layer 5.
- FIG. 2 a) the already thinned wafer 1 is applied to a second carrier 9.
- the carrier 7 and the elastomer layer are mechanically separated from the connecting layer according to FIG. 2b).
- Fig. 2c) is shown schematically that the bonding layer 3 is chemically removed from the wafer (cleaning). At the same time, the carrier 7 can also be freed chemically from the residues of the elastomer layer 5. Examples
- the upper holding plate has a flexible design and consists of polycarbonate, trade name Makroion®, Bayer AG with an E-modulus of 2.2-2.4 GPa.
- the plate is 5 mm thick, has a width of 340 mm and is 400 mm long.
- the holding plate is mounted so that the force is applied to the longer side, which projects beyond the wafer (diameter 300 mm). Before the force measurement, the wafer stack is separated by lifting this free end of the upper support plate in the direction of the arrow to the wafer half, so that the separation front, which now extends across the wafer, has its maximum length.
- the effective free lever arm length is lengthened, and thus also the force measured at the measuring point along the direction of the arrow.
- the maximum measured tensile force is used as the measured value, which experience has shown to result in an effectively effective lever arm length of about 245 mm.
- the force application point on the lever arm is 95 mm away from the edge of the wafer.
- the adhesion force determination is converted to a 300 mm diameter wafer, with the skilled person taking into account both the changed lever length and the changed length of the separation front.
- the static water edge angle is determined according to DIN 55660-2: 201 1 -12.
- the surface energy (free surface energy) is determined according to DIN 55660-2: 201 1 -12.
- Measuring example 4 Determination of the water roll-off angle
- the wafer is fixed on a tilt plate.
- a drop of water deionized and particle-filtered (0.22 ⁇ m), Waters-Millipore, Milli-Q), either 50 ⁇ _, 25 ⁇ _ or 10 ⁇ _ applied to the wafer.
- the angle at which the water droplet begins to move slowly is determined.
- three measurement runs are performed per drop size. Preferred values range from 10-13 ° for 50 ⁇ _ drops of water, and / or 18-25 ° for 25 ⁇ _ drops and / or 28-55 ° for 10 ⁇ _ drops on the cured tie layers.
- the water roll-off angle is determined, as described in this measurement example, in particular for 25 ⁇ _.
- IPA IPA, 99.8% Carl Roth
- TMAH tetramethyl ammonium hydroxide
- the activity is checked before use by a dip-coat.
- an elongated (about 1x5 cm) part of a new untreated silicon wafer is immersed briefly in the solution. If a layer forms during drying of the precursor, the solution is suitable for spin coating.
- the time to activation is a few minutes to several days, depending on concentration and activator content.
- the wafer to be treated is completely covered with precursor (about 10 mL for a 200mm wafer, about 20 mL for a 300mm wafer) and spun after about 30 seconds of life for 20 seconds at 1000 rpm.
- the still moist layer is annealed at 165 ° C for 10 minutes, whereby the layer thickness of initial 60-80 nm drops to 40-60 nm, and the layer is solid.
- the water discharge angle (50 ⁇ drops) is now 10-13 °, the water contact angle (10 ⁇ tropical, static) 95-105 °.
- a second silicon wafer is coated with addition-crosslinking silicone adhesive, and in the bond chamber at reduced pressure (about 0.3 mbar) by force-free bonding (as described in WO 2010/061004 A1), both wafers are bonded.
- the wafer stack After 10 minutes of curing of the silicone adhesive, the wafer stack can be subjected to further processes.
- the wafer stack is initiated at one location, i. a small part of the wafer is detached from the other. Subsequently, the lower wafer fixed on a vacuum plate is separated with a second vacuum plate. The sol-gel layer remains on the device wafer, the separation between sol-gel release layer and silicone adhesives.
- the wafer is placed under agitated dipping for 10-20 minutes in a solution of 2.5% by weight tetrabutylammonium fluoride (TBAF, 97%, Sigma-Aldrich) in methyl isobuthyl ketone (MIBK) followed by isopropanol washed.
- TBAF tetrabutylammonium fluoride
- MIBK methyl isobuthyl ketone
- a sol-gel coated wafer is cut into 4 by 4 centimeter pieces, and the pieces are placed in the etch solution (static dipping).
- the static dipping values are lower than the values for agitated dipping and can not be directly compared.
- the layer is resistant to organic solvents such as acetone, isopropanol, MIBK, gasoline; but also against water, aromatic hydrocarbons and chlorinated hydrocarbons. Only the combination of organic solvent and etchant dissolved in it (TBAF) leads to a removal.
- organic solvents such as acetone, isopropanol, MIBK, gasoline
- TBAF etchant dissolved in it
- hydrochloric acid HCl aq , 0.95% by weight diluted from 1 M standard solution, Carl Roth
- HDTMS 1 volume% hexadecanetrimethoxysilane
- Example 5 agitated dipping:
- the 300 mm (diameter) wafer provided with a sol-gel layer is fixed on a vibratory plate and incubated with 300 ml of cleaning solution.
- the cleaning solutions used are shown in FIG. 4 to remove.
- the layer thickness of the sol-gel layer is determined with an interferometer, from the reaction time and the layer thickness decrease, the etching rate is after
- Etching rate coating thickness decrease / time determined. It has been found that TBAF-containing solutions are generally to be preferred as cleaning agents.
- a four-by-four-inch piece of sol-gel coated wafer is placed in 50 mL of etching solution. It is dispensed with movement of the solution.
- the etch rate is determined by the equation given in Example 5. Due to the lack of permission of the solution, lower etch rates result than with agitated dipping (Example 5).
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Abstract
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Priority Applications (5)
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US15/513,369 US11193208B2 (en) | 2014-09-22 | 2015-09-22 | Wafer/support arrangement, method for producing the arrangement, and use of the arrangement in the processing of the wafer |
KR1020217042528A KR102431990B1 (ko) | 2014-09-22 | 2015-09-22 | 웨이퍼/지지부 구조체, 상기 구조체의 제조 방법, 및 웨이퍼 제조 공정에서의 상기 구조체의 사용 방법 |
KR1020177004539A KR102408677B1 (ko) | 2014-09-22 | 2015-09-22 | 웨이퍼/지지부 구조체, 상기 구조체의 제조 방법, 및 웨이퍼 제조 공정에서의 상기 구조체의 사용 방법 |
JP2017514852A JP6587075B2 (ja) | 2014-09-22 | 2015-09-22 | ウエハー支持構造体、その製造方法、および、ウエハーの加工におけるその構造体の使用 |
CN201580050238.8A CN106688089B (zh) | 2014-09-22 | 2015-09-22 | 晶片载体结构及其制备方法和该结构在晶片加工中的用途 |
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DE102014219095.9A DE102014219095A1 (de) | 2014-09-22 | 2014-09-22 | Wafer-Träger-Anordnung |
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US (1) | US11193208B2 (de) |
JP (1) | JP6587075B2 (de) |
KR (2) | KR102431990B1 (de) |
CN (1) | CN106688089B (de) |
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JP7100825B2 (ja) * | 2018-10-12 | 2022-07-14 | 東洋紡株式会社 | 離型フィルム |
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WO2004051708A2 (de) | 2002-11-29 | 2004-06-17 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren und vorrichtung zum bearbeiten eines wafers sowie wafer mit trennschicht und trägerschicht |
DE10353530A1 (de) | 2003-11-14 | 2005-06-23 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Wafer mit Deckschicht und Trennschicht, Verfahren zur Herstellung eines solchen Wafers sowie Verfahren zum Dünnen bzw. Rückseitenmetallisieren eines Wafers |
WO2007009946A2 (en) | 2005-07-15 | 2007-01-25 | Solvay (Société Anonyme) | Process for the manufacture of eptifibatide |
US20100043608A1 (en) * | 2006-03-01 | 2010-02-25 | Jakob + Richter Ip-Verwertungs- Gesellschaft Mbh | Method for processing, in particular, thin rear sides of a wafer, wafer-carrier arrangement and method for producing said type of wafer-carrier arrangement |
WO2010061004A1 (de) | 2008-11-28 | 2010-06-03 | Thin Materials Ag | Bonding-verfahren |
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JP2001019933A (ja) * | 1999-07-09 | 2001-01-23 | Dow Corning Toray Silicone Co Ltd | シリコーン系接着性シート、およびその製造方法 |
JP2004043814A (ja) * | 2002-07-15 | 2004-02-12 | Dow Corning Toray Silicone Co Ltd | シリコーン系接着性シート、半導体チップと該チップ取付部の接着方法、および半導体装置 |
US7153759B2 (en) * | 2004-04-20 | 2006-12-26 | Agency For Science Technology And Research | Method of fabricating microelectromechanical system structures |
DE102006009394A1 (de) * | 2006-03-01 | 2007-09-06 | Andreas Jakob | Mehrlagenschichtsystem mit einer Schicht als Trennschicht zum Trägern von dünnen Wafern bei der Halbleiterherstellung |
HUP0600668A2 (en) * | 2006-08-22 | 2008-02-28 | Avicor Kft | Active carrier, process for producing thereof and the use of thereof |
DE102008055155A1 (de) | 2008-12-23 | 2010-07-01 | Thin Materials Ag | Trennverfahren für ein Schichtsystem umfassend einen Wafer |
JP5671265B2 (ja) * | 2010-06-10 | 2015-02-18 | 東京応化工業株式会社 | 基板の加工方法 |
JP5783714B2 (ja) * | 2010-12-17 | 2015-09-24 | キヤノン株式会社 | 光学素子の製造方法 |
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- 2015-09-22 US US15/513,369 patent/US11193208B2/en active Active
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- 2015-09-22 JP JP2017514852A patent/JP6587075B2/ja active Active
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Publication number | Publication date |
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DE102014219095A1 (de) | 2016-03-24 |
KR20220001517A (ko) | 2022-01-05 |
TWI677556B (zh) | 2019-11-21 |
JP2017536690A (ja) | 2017-12-07 |
CN106688089B (zh) | 2019-09-17 |
TW201623506A (zh) | 2016-07-01 |
KR102431990B1 (ko) | 2022-08-12 |
US20170298506A1 (en) | 2017-10-19 |
KR20170061127A (ko) | 2017-06-02 |
US11193208B2 (en) | 2021-12-07 |
JP6587075B2 (ja) | 2019-10-09 |
KR102408677B1 (ko) | 2022-06-14 |
CN106688089A (zh) | 2017-05-17 |
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