WO2016038685A1 - Multiplex communication apparatus - Google Patents

Multiplex communication apparatus Download PDF

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Publication number
WO2016038685A1
WO2016038685A1 PCT/JP2014/073798 JP2014073798W WO2016038685A1 WO 2016038685 A1 WO2016038685 A1 WO 2016038685A1 JP 2014073798 W JP2014073798 W JP 2014073798W WO 2016038685 A1 WO2016038685 A1 WO 2016038685A1
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WO
WIPO (PCT)
Prior art keywords
multiplex communication
data
output unit
communication
input
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PCT/JP2014/073798
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French (fr)
Japanese (ja)
Inventor
伸夫 長坂
重元 廣田
英和 金井
Original Assignee
富士機械製造株式会社
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Application filed by 富士機械製造株式会社 filed Critical 富士機械製造株式会社
Priority to PCT/JP2014/073798 priority Critical patent/WO2016038685A1/en
Priority to JP2016547292A priority patent/JP6511457B2/en
Publication of WO2016038685A1 publication Critical patent/WO2016038685A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems

Definitions

  • the present invention relates to a multiplex communication apparatus that performs multiplex communication with peripheral devices at a distance and constructs a sensor feedback control function with high accuracy.
  • FIG. 5 is a system configuration diagram of a conventional multiple communication system.
  • the multiplex communication system 1001 includes a controller 11 and is divided into an A area (fixed part) 101 and a B area (movable part) 301.
  • the controller 11 controls the entire apparatus by a position / speed / torque command.
  • a area (fixed part) 101 is a multi-axis control amplifier, and controls an AC servo motor, which will be described later, by PID control in response to a command from the controller 11.
  • Area B (movable part) 301 is a head unit, which is a unit attached to the tip of the mounter, and inspects the mounting of the surface-mounted product or the component mounting state on the board.
  • the multi-axis control amplifier which is the A area (fixed portion) 101 has a multi-axis control board 111.
  • the multi-axis control board 111 is a board on which a microcomputer for controlling a 4-axis AC servo motor is mounted.
  • the multi-axis control board 111 includes a PHY-IC 112, a slave ASIC 113, a PHY-IC 114, a 4-axis motor control microcomputer 115, DI 116, D0117, a communication ASIC 118, and four DRV-ICs 119, 120, 121, and 122.
  • the PHY-IC 112 is connected to the controller 11 with a cable 12.
  • the cable 12 is a 100 base-tx based industrial Ethernet (registered trademark) LAN cable.
  • the PHY-IC 112 is connected to the slave ASIC 113.
  • the slave ASIC 113 is connected to the PHY-IC 114 and the 4-axis motor control microcomputer 115.
  • the 4-axis motor control microcomputer 115 is connected to DIs 116 and D0117.
  • the 4-axis motor control microcomputer 115 is connected to the four DRV-ICs 119, 120, 121, and 122 via the communication ASIC 118.
  • the head unit which is the B area (movable part) 301 includes a head substrate 1201, a sensor substrate 311, a limit switch 314, a relay 315, and four AC servomotor / serial encoders 316, 317, 318, and 319.
  • the head substrate 1201 is a substrate that acquires sensor information of the head unit which is the B area (movable part) 301 by I2C communication or SPI communication, and transmits it as slave information of industrial Ethernet (registered trademark). (Moving part) DI / DO control in the head unit which is 301 is performed.
  • the head substrate 1201 includes a PHY-IC 1202, a slave ASIC 1203, and a microcomputer 1204.
  • the microcomputer 1204 has an I2C 1205 and an SPI 1206.
  • the slave ASIC 1203 is connected to the PHY-IC 1202 and the microcomputer 1204.
  • the sensor substrate 311 is a substrate on which the pressure sensor 312 and the acceleration sensor 313 are mounted.
  • the pressure-sensitive sensor 312 is a sensor for controlling the indentation pressure of the mounted component.
  • the pressure sensitive sensor 312 is connected to the I2C 1205 in the microcomputer 1204. Therefore, the sensor value of the pressure sensor 312 is acquired from the microcomputer 1204 via I2C communication.
  • the acceleration sensor 313 is a sensor that detects acceleration in order to suppress vibration of the head unit that is the B area (movable part) 301.
  • the acceleration sensor 313 is connected to the SPI 1206 in the microcomputer 1204. Therefore, the sensor value of the acceleration sensor 313 is acquired from the microcomputer 1204 via SPI communication.
  • the PHY-IC 1202 in the head substrate 1201 is connected to the PHY-IC 114 in the multi-axis control substrate 111 in the A area (fixed portion) 101 by a cable 1301.
  • the cable 1301 is a 100 base-tx-based industrial Ethernet (registered trademark) LAN cable.
  • the limit switch 314, the relay 315, and the four AC servo motor / serial encoders 316, 317, 318, and 319 in the head unit which is the B area (movable part) 301 are the multi-axis control board of the A area (fixed part) 101.
  • 111 are connected to DI 116, D 0117, and four DRV-ICs 119, 120, 121, 122 by cables 1302, 1303, 1304, 1305, 1306, 1307.
  • the present invention has been made in view of the above points, and a small peripheral device that has been conventionally usable only for a short distance can communicate with a unit / apparatus outside the casing at a distance. It is an object to provide a multiplex communication apparatus.
  • the invention according to claim 1 made to solve this problem is a multiplex communication apparatus, wherein serial bus standard data transmission between a microcomputer and a peripheral device is multiplexed within a board or between boards.
  • the “peripheral device” includes, for example, an EEPROM, an A / D converter, a D / A converter, an acceleration sensor, a pressure sensor, or a load cell.
  • serial bus standard data transmission includes, for example, SPI (Serial Peripheral Interface) communication, I2C (Inter-Integrated Circuit) communication, or Microwire (registered trademark) communication.
  • SPI Serial Peripheral Interface
  • I2C Inter-Integrated Circuit
  • Microwire registered trademark
  • a small peripheral device that has been conventionally usable only for a short distance can communicate with a unit / apparatus outside the casing at a distance.
  • FIG. 1 is a system configuration diagram of a multiplex communication system using a multiplex communication board according to an embodiment of the present invention. It is an internal block diagram of the same multiplex communication board. It is the figure by which the multiplex communication protocol by the standard (GbE) of Ethernet (trademark) at the time of the same multiplex communication board transmitting / receiving by a half duplex communication system was represented. It is the figure by which the multiplex communication protocol by the standard (GbE) of Ethernet (trademark) at the time of the same multiplex communication board transmitting / receiving by a half duplex communication system was represented. It is a system block diagram of the multiplex communication system of a prior art.
  • GbE standard
  • Ethernet trademark
  • FIG. 1 is a system configuration diagram of a multiplex communication system in which a multiplex communication board according to an embodiment of the present invention is used.
  • the multiplex communication system 1 includes a controller 11 and is divided into an A area (fixed part) 101 and a B area (movable part) 301.
  • the controller 11 controls the entire apparatus by a position / speed / torque command.
  • a area (fixed part) 101 is a multi-axis control amplifier, and controls an AC servo motor, which will be described later, by PID control in response to a command from the controller 11.
  • Area B (movable part) 301 is a head unit, which is a unit attached to the tip of the mounter, and inspects the mounting of the surface-mounted product or the component mounting state on the board.
  • the multi-axis control amplifier which is the A area (fixed portion) 101 includes a multi-axis control board 111 and the multiplex communication board 201 according to the present embodiment.
  • the multi-axis control board 111 is a board on which a microcomputer for controlling a 4-axis AC servo motor is mounted.
  • the multi-axis control board 111 includes a PHY-IC 112, a slave ASIC 113, a PHY-IC 114, a 4-axis motor control microcomputer 115, DI 116, D0117, a communication ASIC 118, and four DRV-ICs 119, 120, 121, and 122.
  • the 4-axis motor control microcomputer 115 has an I2C 131 and an SPI 132.
  • the PHY-IC 112 is connected to the controller 11 with a cable 12.
  • the cable 12 is a 100 base-tx based industrial Ethernet (registered trademark) LAN cable.
  • the PHY-IC 112 is connected to the slave ASIC 113.
  • the slave ASIC 113 is connected to the PHY-IC 114 and the 4-axis motor control microcomputer 115.
  • the 4-axis motor control microcomputer 115 is connected to DIs 116 and D0117.
  • the 4-axis motor control microcomputer 115 is connected to the four DRV-ICs 119, 120, 121, and 122 via the communication ASIC 118.
  • the multiplex communication board 201 includes an ETHERPHY-IC 202, a multiplex communication FPGA 203, a DO 206, a DI 207, and four DRV-ICs 208, 209, 210, and 211.
  • the multiplex communication FPGA 203 has an I2C 204 and an SPI 205.
  • the ETHERPHY-IC 202 is connected to the multiplex communication FPGA 203.
  • the multiplex communication FPGA 203 is connected to the DO 206, the DI 207, and the four DRV-ICs 208, 209, 210, and 211.
  • the I2C 204 and the SPI 205 in the multiplex communication FPGA 203 are connected to the I2C 131 and the SPI 132 in the 4-axis motor control microcomputer 115.
  • the multiplex communication board 201 is connected to the I2C 131 and the SPI 132 in the multi-axis control board 111 through communication lines in the multi-axis control amplifier of the A area (fixed portion) 101 that is the same housing. .
  • the DO 206, DI 207, and the four DRV-ICs 208, 209, 210, 211 in the multiplex communication board 201 are the DI 116, D 0117, and the four DRV-ICs 119, 120 in the multi-axis control board 111. , 121, 122.
  • the head unit which is the B area (movable part) 301 includes a sensor substrate 311, a multiplex communication substrate 401 according to the present embodiment, a limit switch 314, a relay 315, and four AC servomotor / serial encoders 316, 317, 318, and 319.
  • the sensor substrate 311 is a substrate on which the pressure sensor 312 and the acceleration sensor 313 are mounted.
  • the pressure-sensitive sensor 312 is a sensor for controlling the indentation pressure of the mounted component.
  • the acceleration sensor 313 is a sensor that detects acceleration in order to suppress vibration of the head unit that is the B area (movable part) 301.
  • the multiplex communication board 401 includes an ETHERPHY-IC 402, a multiplex communication FPGA 403, a DI 406, a D 0407, and four DRV-ICs 408, 409, 410, and 411.
  • the multiplex communication FPGA 403 includes an I2C 404 and an SPI 405.
  • the I2C 404 in the multiplex communication FPGA 403 is connected to the pressure-sensitive sensor 312.
  • the SPI 405 in the multiplex communication FPGA 403 is connected to the acceleration sensor 313.
  • the multiplex communication FPGA 403 is connected to the DI 406, D 0407, and the four DRV-ICs 408, 409, 410, and 411.
  • the DI 406, D0407, and four DRV-ICs 408, 409, 410, 411 in the multiplex communication board 401 are a limit switch 314, a relay 315, and four AC servo motor / serial encoders 316, 317, 318. , 319.
  • the ETHERPHY-IC 402 in the multiplex communication board 401 according to the present embodiment is connected by a cable 501 to the ETHERPHY-IC 202 in the multiplex communication board 201 according to the present embodiment in the A area (fixed portion) 101.
  • the cable 501 is an Ethernet (registered trademark) cable for multiplex communication, and a 1000 base-t category 5e anti-bending LAN line is used.
  • FIG. 2 is an internal configuration diagram of the multiplex communication boards 201 and 401 according to the present embodiment. That is, FIG. 2 shows an internal configuration of a board that performs multiplex communication using a serial encoder signal, an I2C signal, and an SPI signal using GbE.
  • the multiplex communication boards 201 and 401 according to the present embodiment are roughly divided into a multiplexing target signal input unit, a multiplexing processing unit, and a multiplexing communication unit using GbE.
  • the multiple communication boards 201 and 401 according to the present embodiment are connected by the cable 501 as described above.
  • the multiplex communication board 201 includes a 1000base-t PHY-IC 212, a DIP-SW 213, a multiplex communication protocol processing unit 220, a serial encoder input / output unit 230, an I2C input / output unit 240, an SPI input / output unit 250, It includes a processing unit 260, a DRIVER-IC 270 for RS485, and two I / O input / output units 280 and 290.
  • the 1000base-t PHY-IC 212 is a 1000base-t communication PHY-IC for performing multiplex communication.
  • the DIP-SW 213 is a DIP switch that sets the timing in advance because the mode for determining data at which timing of the clock in SPI communication is determined by the IC of the sensor or the like (however, the default value is a 4-axis motor) UART and IO setting from the control microcomputer 115 side may also be used).
  • the multiplex communication protocol processing unit 220 is a processing unit that performs mixing / separation processing of local data for a multiplex communication protocol.
  • the multiplex communication protocol processing unit 220 includes a GMII-IF data input unit 221, a demultiplexing unit 222, a multiplex mixing unit 223, and a GMII-IF data output unit 224.
  • the serial encoder input / output unit 230 inputs or outputs ABS serial encoder communication data such as AC servo motors 316 to 319.
  • the serial encoder input / output unit 230 transmits data to the multiplex communication protocol processing unit 220 or outputs data received from the multiplex communication protocol processing unit 220.
  • the serial encoder input / output unit 230 includes an HDLC-I / F data input unit 231, a reception buffer 232, an HDLC-I / F data output unit 233, and a transmission buffer 234, and these signals each signal to be multiplexed.
  • the I2C input / output unit 240 samples the data using the I2C communication clock and the high-speed clock in the multiplex communication FPGA 203 and transmits the H and L (1, 0) signals to the multiplex communication protocol processing unit 220.
  • the I2C input / output unit 240 outputs the H, L (1, 0) signal from the multiplex communication protocol processing unit 220 to the I / O input / output unit 280.
  • the I2C input / output unit 240 includes an I2C-I / F data input unit 241, a reception buffer 242, an I2C-I / F data output unit 243, and a transmission buffer 244, which multiplex each signal to be multiplexed.
  • the SPI input / output unit 250 samples data using the SPI communication clock and the high-speed clock in the multiplex communication FPGA 203, and transmits the H and L (1, 0) signals to the multiplex communication protocol processing unit 220.
  • the SPI input / output unit 250 outputs the H, L (1, 0) signal from the multiplex communication protocol processing unit 220 to the I / O input / output unit 290.
  • the mode for determining data at which timing of the clock is determined in advance by the DIP-SW 213 since it is determined by the IC such as a sensor.
  • the SPI input / output unit 250 includes an SPI-I / F data input unit 251, a reception buffer 252, an SPI-I / F data output unit 253, and a transmission buffer 254, which multiplex each signal to be multiplexed.
  • the multiplex processing unit 260 is a multiplex processing unit for realizing the function of the multiplex communication board 201 according to the present embodiment, and is a multiplex communication FPGA 203.
  • the multiplex processing unit 260 includes a multiplex communication protocol processing unit 220, a serial encoder input / output unit 230, an I2C input / output unit 240, and an SPI input / output unit 250.
  • the RS485 DRIVER-IC 270 is a DRIVER-IC of the physical layer RS485 of the serial encoder.
  • the I / O input / output unit 280 is an input / output unit suitable for the I2C signal level.
  • the I / O input / output unit 290 is an input / output unit suitable for the SPI signal level.
  • the multiplex communication board 401 includes a 1000-base-t PHY-IC 412, an LED 413, a multiplex communication protocol processing unit 420, a serial encoder input / output unit 430, an I2C input / output unit 440, and an SPI input / output unit 450.
  • the 1000base-t PHY-IC 412 is a 1000base-t communication PHY-IC for performing multiplex communication.
  • the LED 413 is a visual confirmation LED for checking whether the specification matches the 4-axis motor control microcomputer 115 side by SPI communication.
  • the multiplex communication protocol processing unit 420 is a processing unit that performs mixing / separation processing of local data for a multiplex communication protocol.
  • the multiplex communication protocol processing unit 420 includes a GMII-IF data input unit 421, a demultiplexing unit 422, a multiplex mixing unit 423, and a GMII-IF data output unit 424.
  • the serial encoder input / output unit 430 inputs or outputs ABS serial encoder communication data of the AC servo motors 316 to 319 and the like.
  • the serial encoder input / output unit 430 transmits data to the multiplex communication protocol processing unit 420 or outputs data received from the multiplex communication protocol processing unit 420.
  • the serial encoder input / output unit 430 includes an HDLC-I / F data input unit 431, a reception buffer 432, an HDLC-I / F data output unit 433, and a transmission buffer 434.
  • the I2C input / output unit 440 samples data using the I2C communication clock and the high-speed clock in the multiplex communication FPGA 403 and transmits the H, L (1, 0) signal to the multiplex communication protocol processing unit 420.
  • the I2C input / output unit 440 outputs the H, L (1, 0) signal from the multiplex communication protocol processing unit 420 to the I / O input / output unit 480.
  • the I2C input / output unit 440 includes an I2C-I / F data input unit 441, a reception buffer 442, an I2C-I / F data output unit 443, and a transmission buffer 444, which multiplex each signal to be multiplexed.
  • the SPI input / output unit 450 samples data using the SPI communication clock and the high-speed clock in the multiplex communication FPGA 403 and transmits the H, L (1, 0) signal to the multiplex communication protocol processing unit 420.
  • the SPI input / output unit 450 outputs the H, L (1, 0) signal from the multiplex communication protocol processing unit 420 to the I / O input / output unit 490.
  • the mode for determining data at which timing of the clock is determined in advance by the DIP-SW 213 since it is determined by the IC such as a sensor.
  • the SPI input / output unit 450 includes an SPI-I / F data input unit 451, a reception buffer 452, an SPI-I / F data output unit 453, and a transmission buffer 454, which multiplex each signal to be multiplexed.
  • the multiplex processing unit 460 is a multiplex processing unit for realizing the function of the multiplex communication board 401 according to the present embodiment, and is a multiplex communication FPGA 403.
  • the multiplex processing unit 460 includes a multiplex communication protocol processing unit 420, a serial encoder input / output unit 430, an I2C input / output unit 440, and an SPI input / output unit 450.
  • the RS485 DRIVER-IC 470 is a DRIVER-IC of the physical layer RS485 of the serial encoder.
  • the I / O input / output unit 480 is an input / output unit suitable for the I2C signal level.
  • the I / O input / output unit 490 is an input / output unit that conforms to the SPI signal level.
  • the multiplex communication boards 201 and 401 according to the present embodiment use GbE (1000 base-t, half-duplex communication) and perform transmission / reception by switching at a fixed number of times.
  • 3 and 4 show a multiplex communication protocol based on the Ethernet (registered trademark) standard GbE when the multiplex communication boards 201 and 401 (see FIG. 2) according to the present embodiment perform transmission and reception by the half-duplex communication method.
  • FIG. 1 1000 base-t, half-duplex communication
  • FIG. 3 is a diagram showing a multiplex communication protocol of a half-duplex communication method for transmitting data from A area 2 to B area 3, but half-duplex for transmitting data from B area 3 to A area 2.
  • the multiplex communication protocol of the communication method is not described.
  • FIG. 4 shows a half-duplex communication protocol for transmitting data from B area 3 to A area 2, but transmits data from A area 2 to B area 3.
  • the multiplex communication protocol of the half duplex communication system is not described.
  • the multiplex communication protocol is a communication protocol as shown in FIG. 3 and FIG. 4 for each 125 MHz clock, and transmits / receives 8 bits, and performs communication synthesis / separation on the local side.
  • the 8 bits are represented by “B0”, “B1”, “B2”, “B3”, “B4”, “B5”, “B6”, “B7” arranged in the vertical axis in FIGS.
  • the numerical values “0” to “14” arranged on the horizontal axis are the counter numbers of the clock (125 MHz, which is the same as that for the standard GbE) for performing multiplexed communication.
  • the numerical values “15” to “29” arranged on the horizontal axis are the counter numbers of the clock (125 MHz, which is the same as that for the standard GbE) for performing multiplexed communication.
  • SPI-D represents data of SPI communication. “With / without SPI” is a flag indicating the presence / absence of data. “With SPI” indicates that there is SPI data. “No SPI” indicates that there is no SPI data. “I2C-D” represents I2C communication data. “I2C present / not present” is a flag indicating the presence / absence of data. “I2C present” indicates that there is I2C data. “No I2C” indicates that there is no I2C data.
  • “DO0”, “DO1”, “DO2”, and “DO3” are digital output signals (Hi: 1, Low: 0).
  • “DI1”, “DI2”, and “DI3” are digital input signals (Hi: 1, Low: 0).
  • “encoder 1 data”, “encoder 2 data”, “encoder 3 data”, and “encoder 4 data” are data for multiplexing encoder signals.
  • the “FEC (15, 11) shortening system” is a shortening system of the Hamming code (15, 11) (3 BIT is fixed to 0) and is 4 BIT data added for error correction.
  • a total of 11 BITs of 8 BIT + (3 BIT is fixed to 0) in a horizontal row with the counter number “2” to “9” are targeted.
  • a total of 11 BITs of 8 BIT + (3 BIT is fixed to 0) in a horizontal row with the counter number “17” to “24” are targeted.
  • “SS1”, “SS2”, “SS3”, and “SS4” are selection signals for devices to be communicated by SPI communication.
  • “MODE0”, “MODE1”, “MODE2”, and “MODE3” represent clock timing modes (Clock Phase) for determining data by SPI communication.
  • “CLK_I2C_NO” and “CLK_SPI_NO” provide four types of representative clock frequencies for I2C and SPI communication (for example, 1, 2, 5, and 10 MHz) for use in peripheral devices on the movable part side. The clock to be specified is specified.
  • the pressure-sensitive sensor 312 and the acceleration sensor 313, which are small peripheral devices that have conventionally been used only for a short distance, can communicate with each other between units and devices outside the casing.
  • the analog output of the sensor is directly connected to the A / D of the microcomputer, so there is no resolution due to noise, and the wiring-saving standards such as industrial Ethernet (registered trademark) or CC-Link (registered trademark) Since it is necessary to select a unit on which A / D or the like is mounted as a slave device, it has not been possible to reduce the size.
  • the pressure-sensitive sensor 312 and the acceleration sensor 313, which are peripheral devices can be directly connected to the multiplex communication board 401 according to this embodiment with high speed and low delay. Good complex control is possible.
  • the 4-axis motor control microcomputer 115 can directly collect data from the sensors (the pressure-sensitive sensor 312 and the acceleration sensor 313), so that there is little delay and high-performance feedback control can be realized.
  • the communication line includes a multi-axis control amplifier that is A area (fixed part) 101 and a head unit that is B area (movable part) 301. It is only necessary to connect one LAN line of the Ethernet (registered trademark) cable 501 for multiplex communication between the two.
  • the multi-axis control amplifier that is the A area (fixed part) 101 and the B area (movable) No change in wiring with the head unit 301 is required. This can be dealt with only by changing the CPU of the multi-axis control board 111. Therefore, even if the device has already been delivered, the effect of the new function can be obtained by using a new head unit that is the B area (movable part) 301 without wiring work.
  • notch FILTER notch FILTER, etc.
  • the processing load is high because the load on the CPU during this processing is large and the heat generation is high. It is necessary to use an expensive CPU.
  • a control CPU is used by utilizing a predetermined function (for example, LPF, HPF (High Pass Filer), or notch) or a frequency digital filter function in the multiplex communication FPGAs 203 and 403.
  • a predetermined function for example, LPF, HPF (High Pass Filer), or notch
  • a frequency digital filter function in the multiplex communication FPGAs 203 and 403.
  • this invention is not limited to the said embodiment, A various change is possible in the range which does not deviate from the meaning.
  • the pressure-sensitive sensor 312 and the acceleration sensor 313 are used as “peripheral devices”.
  • an EEPROM, an A / D converter, a D / A converter, a load cell, or the like may be used as the “peripheral device”.
  • SPI communication and I2C communication are performed as “serial bus standard data transmission”.
  • Serial bus standard data transmission Microwire (registered trademark) communication or the like may be performed.
  • Multiplex Communication System 115 4-axis Motor Control Microcomputer 201 Multiplex Communication Board 202 ETHERPHY-IC 203 FPGA for multiplex communication 233 HDLC-I / F output unit 234 Transmission buffer 243 I2C-I / F data output unit 244 Transmission buffer 253 SPI-I / F data output unit 254 Transmission buffer 311 Sensor substrate 312 Pressure sensor 313 Acceleration sensor 401 Multiplex communication substrate 402 ETHERPHY-IC 403 FPGA for multiplex communication 433 HDLC-I / F output unit 434 Transmission buffer 443 I2C-I / F data output unit 444 Transmission buffer 453 SPI-I / F data output unit 454 Transmission buffer 501 Ethernet (registered trademark) cable for multiplex communication

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)

Abstract

Provided is a multiplex communication apparatus for enabling the communication of small-sized peripheral devices, which were conventionally able to be used only at short distances, between remote outside-casing units/apparatuses. An ETHERPHY-IC 402 in a multiplex communication board 401 is connected to an ETHERPHY-IC 202 in a multiplex communication board 201 of an A-area (fixed part) 101 by use of a cable 501. The cable 501 is a cable of a multiplex communication-use Ethernet (Registered Trademark), which comprises a 1000base-t-use category-5e flexible LAN line.

Description

多重通信装置Multiplex communication equipment
　本発明は、距離の離れた周辺デバイスと多重化通信し、センサフィードバック制御機能を高精度に構築する多重通信装置に関するものである。 The present invention relates to a multiplex communication apparatus that performs multiplex communication with peripheral devices at a distance and constructs a sensor feedback control function with high accuracy.
　従来より、距離の離れた周辺デバイスと通信する多重通信装置としては、以下の多重通信システムがある。 Conventionally, as a multiplex communication apparatus that communicates with a peripheral device at a distance, there are the following multiplex communication systems.
  図５は、従来技術の多重通信システムのシステム構成図である。図５に表したように、多重通信システム１００１は、コントローラ１１を有し、Ａエリア（固定部）１０１とＢエリア（可動部）３０１に分かれる。コントローラ１１は、位置・速度・トルク指令などで装置全体をコントロールする。 FIG. 5 is a system configuration diagram of a conventional multiple communication system. As illustrated in FIG. 5, the multiplex communication system 1001 includes a controller 11 and is divided into an A area (fixed part) 101 and a B area (movable part) 301. The controller 11 controls the entire apparatus by a position / speed / torque command.
　Ａエリア（固定部）１０１は、多軸制御アンプであって、コントローラ１１からの指令で後述するＡＣサーボモータをＰＩＤ制御で制御する。Ｂエリア（可動部）３０１は、ヘッドユニットであって、マウンタの先端部につくユニットで、表面実装品の実装又は基板上の部品実装状態を検査する。 A area (fixed part) 101 is a multi-axis control amplifier, and controls an AC servo motor, which will be described later, by PID control in response to a command from the controller 11. Area B (movable part) 301 is a head unit, which is a unit attached to the tip of the mounter, and inspects the mounting of the surface-mounted product or the component mounting state on the board.
　Ａエリア（固定部）１０１である多軸制御アンプは、多軸制御基板１１１を有する。 The multi-axis control amplifier which is the A area (fixed portion) 101 has a multi-axis control board 111.
　多軸制御基板１１１は、４軸ＡＣサーボモータを制御するマイコンを載せた基板である。多軸制御基板１１１は、ＰＨＹ－ＩＣ１１２、スレーブＡＳＩＣ１１３、ＰＨＹ－ＩＣ１１４、４軸モータ制御用マイコン１１５、ＤＩ１１６、Ｄ０１１７、通信ＡＳＩＣ１１８、及び４つのＤＲＶ－ＩＣ１１９，１２０，１２１，１２２を有する。 The multi-axis control board 111 is a board on which a microcomputer for controlling a 4-axis AC servo motor is mounted. The multi-axis control board 111 includes a PHY-IC 112, a slave ASIC 113, a PHY-IC 114, a 4-axis motor control microcomputer 115, DI 116, D0117, a communication ASIC 118, and four DRV- ICs 119, 120, 121, and 122.
　ＰＨＹ－ＩＣ１１２は、コントローラ１１にケーブル１２で接続される。ケーブル１２は、１００ｂａｓｅ－ｔxベースの産業用のイーサネット（登録商標）規格のＬＡＮケーブルである。ＰＨＹ－ＩＣ１１２は、スレーブＡＳＩＣ１１３に接続される。 The PHY-IC 112 is connected to the controller 11 with a cable 12. The cable 12 is a 100 base-tx based industrial Ethernet (registered trademark) LAN cable. The PHY-IC 112 is connected to the slave ASIC 113.
　スレーブＡＳＩＣ１１３は、ＰＨＹ－ＩＣ１１４と４軸モータ制御用マイコン１１５に接続される。 The slave ASIC 113 is connected to the PHY-IC 114 and the 4-axis motor control microcomputer 115.
　４軸モータ制御用マイコン１１５は、ＤＩ１１６及びＤ０１１７に接続される。４軸モータ制御用マイコン１１５は、通信ＡＳＩＣ１１８を介して、４つのＤＲＶ－ＩＣ１１９，１２０，１２１，１２２に接続される。 The 4-axis motor control microcomputer 115 is connected to DIs 116 and D0117. The 4-axis motor control microcomputer 115 is connected to the four DRV- ICs 119, 120, 121, and 122 via the communication ASIC 118.
　Ｂエリア（可動部）３０１であるヘッドユニットは、ヘッド基板１２０１、センサ基板３１１、リミットスイッチ３１４、リレー３１５、及び４つのＡＣサーボモータ／シリアルエンコーダ３１６，３１７，３１８，３１９を有する。 The head unit which is the B area (movable part) 301 includes a head substrate 1201, a sensor substrate 311, a limit switch 314, a relay 315, and four AC servomotor / serial encoders 316, 317, 318, and 319.
　ヘッド基板１２０１は、Ｂエリア（可動部）３０１であるヘッドユニットのセンサ情報をＩ２Ｃ通信又はＳＰＩ通信で取得し、産業用のイーサネット（登録商標）のスレーブ情報として送信する基板であり、その他Ｂエリア（可動部）３０１であるヘッドユニット内のＤＩ／ＤＯ制御等を行う。ヘッド基板１２０１は、ＰＨＹ－ＩＣ１２０２、スレーブＡＳＩＣ１２０３、及びマイコン１２０４を有する。マイコン１２０４は、Ｉ２Ｃ１２０５とＳＰＩ１２０６を有する。 The head substrate 1201 is a substrate that acquires sensor information of the head unit which is the B area (movable part) 301 by I2C communication or SPI communication, and transmits it as slave information of industrial Ethernet (registered trademark). (Moving part) DI / DO control in the head unit which is 301 is performed. The head substrate 1201 includes a PHY-IC 1202, a slave ASIC 1203, and a microcomputer 1204. The microcomputer 1204 has an I2C 1205 and an SPI 1206.
　スレーブＡＳＩＣ１２０３は、ＰＨＹ－ＩＣ１２０２とマイコン１２０４に接続される。 The slave ASIC 1203 is connected to the PHY-IC 1202 and the microcomputer 1204.
　センサ基板３１１は、感圧センサ３１２と加速度センサ３１３を実装する基板である。感圧センサ３１２は、実装部品の押し込み圧を制御するためのセンサである。感圧センサ３１２は、マイコン１２０４内のＩ２Ｃ１２０５に接続される。従って、感圧センサ３１２のセンサ値は、Ｉ２Ｃ通信経由で、マイコン１２０４から取得される。加速度センサ３１３は、Ｂエリア（可動部）３０１であるヘッドユニットの振動を抑制するために加速度を検出するセンサである。加速度センサ３１３は、マイコン１２０４内のＳＰＩ１２０６に接続される。従って、加速度センサ３１３のセンサ値は、ＳＰＩ通信経由で、マイコン１２０４から取得される。 The sensor substrate 311 is a substrate on which the pressure sensor 312 and the acceleration sensor 313 are mounted. The pressure-sensitive sensor 312 is a sensor for controlling the indentation pressure of the mounted component. The pressure sensitive sensor 312 is connected to the I2C 1205 in the microcomputer 1204. Therefore, the sensor value of the pressure sensor 312 is acquired from the microcomputer 1204 via I2C communication. The acceleration sensor 313 is a sensor that detects acceleration in order to suppress vibration of the head unit that is the B area (movable part) 301. The acceleration sensor 313 is connected to the SPI 1206 in the microcomputer 1204. Therefore, the sensor value of the acceleration sensor 313 is acquired from the microcomputer 1204 via SPI communication.
　ヘッド基板１２０１内のＰＨＹ－ＩＣ１２０２は、Ａエリア（固定部）１０１の多軸制御基板１１１内のＰＨＹ－ＩＣ１１４にケーブル１３０１で接続される。ケーブル１３０１は、１００ｂａｓｅ－ｔxベースの産業用のイーサネット（登録商標）規格のＬＡＮケーブルである。 The PHY-IC 1202 in the head substrate 1201 is connected to the PHY-IC 114 in the multi-axis control substrate 111 in the A area (fixed portion) 101 by a cable 1301. The cable 1301 is a 100 base-tx-based industrial Ethernet (registered trademark) LAN cable.
　Ｂエリア（可動部）３０１であるヘッドユニット内のリミットスイッチ３１４、リレー３１５、及び４つのＡＣサーボモータ／シリアルエンコーダ３１６，３１７，３１８，３１９は、Ａエリア（固定部）１０１の多軸制御基板１１１内のＤＩ１１６、Ｄ０１１７、及び４つのＤＲＶ－ＩＣ１１９，１２０，１２１，１２２に、ケーブル１３０２，１３０３，１３０４，１３０５，１３０６，１３０７で接続される。 The limit switch 314, the relay 315, and the four AC servo motor / serial encoders 316, 317, 318, and 319 in the head unit which is the B area (movable part) 301 are the multi-axis control board of the A area (fixed part) 101. 111 are connected to DI 116, D 0117, and four DRV- ICs 119, 120, 121, 122 by cables 1302, 1303, 1304, 1305, 1306, 1307.
　尚、距離の離れた周辺デバイスと通信する多重通信装置に関連する発明としては、以下の各特許文献に記載された発明がある。 In addition, as inventions related to a multiplex communication apparatus that communicates with peripheral devices at a distance, there are inventions described in the following patent documents.
特表２００９－５２４２８１号公報Special table 2009-524281 特表２００８－５１９４７１号公報JP 2008-519471 A
　しかしながら、図５に表された従来技術のシステムでは、新機能追加用センサを追加する場合、産業用イーサネット上のデータ量が増加し追加前の通信周期で許容されたバイト数を超えると通信の周期と制御周期が大きくなり、従来の制御性能より劣化する。 However, in the prior art system shown in FIG. 5, when adding a sensor for adding a new function, if the amount of data on the industrial Ethernet increases and exceeds the number of bytes allowed in the communication cycle before the addition, The cycle and the control cycle become large, and the conventional control performance is deteriorated.
　また、産業用のイーサネット（登録商標）の使用時や省配線時は、一般的に、スレーブ同士での通信は不可である。従って、産業用のイーサネット（登録商標）規格のＬＡＮケーブルをケーブル１３０に使用すると、１度マスタであるコントローラ１１でデータを取得した後にＡエリア（固定部）１０１である多軸制御アンプに反映されるため、遅延時間が大きくなり、高精度な制御ができず、また、コントローラ１１の負荷が大きい。 Also, when using industrial Ethernet (registered trademark) or when wiring is reduced, communication between slaves is generally not possible. Therefore, when an industrial Ethernet (registered trademark) standard LAN cable is used for the cable 130, it is reflected in the multi-axis control amplifier which is the A area (fixed portion) 101 after data is acquired once by the controller 11 which is the master. For this reason, the delay time becomes large, high-precision control cannot be performed, and the load on the controller 11 is large.
　特に、感圧センサ３１２や加速度センサ３１３のようなシリアルバス規格のセンサを利用する場合には、一般的に、同じ筐体内の基板間・基板内の近距離での利用を前提とするため、筐体外や距離の離れた間ではノイズに弱く、誤動作・データ化けする可能性が高い。 In particular, when a serial bus standard sensor such as the pressure sensor 312 or the acceleration sensor 313 is used, it is generally assumed that the sensor is used at a short distance between the boards in the same housing or in the board. It is vulnerable to noise outside the case and at a distance, and there is a high possibility of malfunction and data corruption.
　そこで、本発明は、上述した点を鑑みてなされたものであり、従来、短い距離間でしか使用できなかった小型の周辺デバイスが距離のはなれた筐体外のユニット・装置間で通信可能となる多重通信装置を提供することを課題とする。 Therefore, the present invention has been made in view of the above points, and a small peripheral device that has been conventionally usable only for a short distance can communicate with a unit / apparatus outside the casing at a distance. It is an object to provide a multiplex communication apparatus.
　この課題を解決するためになされた請求項１に係る発明は、多重通信装置であって、基板内又は基板間で、マイコンと周辺デバイス間のシリアルバス規格のデータ伝送を多重化したこと、を特徴とする。 The invention according to claim 1 made to solve this problem is a multiplex communication apparatus, wherein serial bus standard data transmission between a microcomputer and a peripheral device is multiplexed within a board or between boards. Features.
　尚、「周辺デバイス」には、例えば、ＥＥＰＲＯＭ、Ａ／Ｄ変換器、Ｄ／Ａ変換器、加速度センサ、感圧センサ、又はロードセル等がある。 The “peripheral device” includes, for example, an EEPROM, an A / D converter, a D / A converter, an acceleration sensor, a pressure sensor, or a load cell.
　また、「シリアルバス規格のデータ伝送」には、例えば、ＳＰＩ（Serial Peripheral Interface）通信、Ｉ２Ｃ（Inter-Integrated Circuit）通信、又はＭｉｃｒｏｗｉｒｅ（登録商標）通信等がある。 In addition, “serial bus standard data transmission” includes, for example, SPI (Serial Peripheral Interface) communication, I2C (Inter-Integrated Circuit) communication, or Microwire (registered trademark) communication.
　本発明では、従来、短い距離間でしか使用できなかった小型の周辺デバイスが距離のはなれた筐体外のユニット・装置間で通信可能となる。 In the present invention, a small peripheral device that has been conventionally usable only for a short distance can communicate with a unit / apparatus outside the casing at a distance.
本発明の一実施形態に係る多重通信基板が使用された多重通信システムのシステム構成図である。1 is a system configuration diagram of a multiplex communication system using a multiplex communication board according to an embodiment of the present invention. 同多重通信基板の内部構成図である。It is an internal block diagram of the same multiplex communication board. 同多重通信基板が半２重通信方式で送受信を行う際のイーサネット（登録商標）の規格ＧｂＥによる多重通信プロトコルが表された図である。It is the figure by which the multiplex communication protocol by the standard (GbE) of Ethernet (trademark) at the time of the same multiplex communication board transmitting / receiving by a half duplex communication system was represented. 同多重通信基板が半２重通信方式で送受信を行う際のイーサネット（登録商標）の規格ＧｂＥによる多重通信プロトコルが表された図である。It is the figure by which the multiplex communication protocol by the standard (GbE) of Ethernet (trademark) at the time of the same multiplex communication board transmitting / receiving by a half duplex communication system was represented. 従来技術の多重通信システムのシステム構成図である。It is a system block diagram of the multiplex communication system of a prior art.
［１．多重通信システムのシステム構成］
  以下、本発明を具体化した多重通信基板について図面を参照しつつ説明する。図１は、本発明の一実施形態に係る多重通信基板が使用された多重通信システムのシステム構成図である。 [1. System configuration of multiplex communication system]
Hereinafter, a multiplex communication board embodying the present invention will be described with reference to the drawings. FIG. 1 is a system configuration diagram of a multiplex communication system in which a multiplex communication board according to an embodiment of the present invention is used.
　図１に表したように、多重通信システム１は、コントローラ１１を有し、Ａエリア（固定部）１０１とＢエリア（可動部）３０１に分かれる。コントローラ１１は、位置・速度・トルク指令などで装置全体をコントロールする。 As shown in FIG. 1, the multiplex communication system 1 includes a controller 11 and is divided into an A area (fixed part) 101 and a B area (movable part) 301. The controller 11 controls the entire apparatus by a position / speed / torque command.
　Ａエリア（固定部）１０１は、多軸制御アンプであって、コントローラ１１からの指令で後述するＡＣサーボモータをＰＩＤ制御で制御する。Ｂエリア（可動部）３０１は、ヘッドユニットであって、マウンタの先端部につくユニットで、表面実装品の実装又は基板上の部品実装状態を検査する。 A area (fixed part) 101 is a multi-axis control amplifier, and controls an AC servo motor, which will be described later, by PID control in response to a command from the controller 11. Area B (movable part) 301 is a head unit, which is a unit attached to the tip of the mounter, and inspects the mounting of the surface-mounted product or the component mounting state on the board.
　Ａエリア（固定部）１０１である多軸制御アンプは、多軸制御基板１１１、及び本実施形態に係る多重通信基板２０１を有する。 The multi-axis control amplifier which is the A area (fixed portion) 101 includes a multi-axis control board 111 and the multiplex communication board 201 according to the present embodiment.
　多軸制御基板１１１は、４軸ＡＣサーボモータを制御するマイコンを載せた基板である。多軸制御基板１１１は、ＰＨＹ－ＩＣ１１２、スレーブＡＳＩＣ１１３、ＰＨＹ－ＩＣ１１４、４軸モータ制御用マイコン１１５、ＤＩ１１６、Ｄ０１１７、通信ＡＳＩＣ１１８、及び４つのＤＲＶ－ＩＣ１１９，１２０，１２１，１２２を有する。４軸モータ制御用マイコン１１５は、Ｉ２Ｃ１３１とＳＰＩ１３２を有する。 The multi-axis control board 111 is a board on which a microcomputer for controlling a 4-axis AC servo motor is mounted. The multi-axis control board 111 includes a PHY-IC 112, a slave ASIC 113, a PHY-IC 114, a 4-axis motor control microcomputer 115, DI 116, D0117, a communication ASIC 118, and four DRV- ICs 119, 120, 121, and 122. The 4-axis motor control microcomputer 115 has an I2C 131 and an SPI 132.
　ＰＨＹ－ＩＣ１１２は、コントローラ１１にケーブル１２で接続される。ケーブル１２は、１００ｂａｓｅ－ｔxベースの産業用のイーサネット（登録商標）規格のＬＡＮケーブルである。ＰＨＹ－ＩＣ１１２は、スレーブＡＳＩＣ１１３に接続される。 The PHY-IC 112 is connected to the controller 11 with a cable 12. The cable 12 is a 100 base-tx based industrial Ethernet (registered trademark) LAN cable. The PHY-IC 112 is connected to the slave ASIC 113.
　スレーブＡＳＩＣ１１３は、ＰＨＹ－ＩＣ１１４と４軸モータ制御用マイコン１１５に接続される。 The slave ASIC 113 is connected to the PHY-IC 114 and the 4-axis motor control microcomputer 115.
　４軸モータ制御用マイコン１１５は、ＤＩ１１６及びＤ０１１７に接続される。４軸モータ制御用マイコン１１５は、通信ＡＳＩＣ１１８を介して、４つのＤＲＶ－ＩＣ１１９，１２０，１２１，１２２に接続される。 The 4-axis motor control microcomputer 115 is connected to DIs 116 and D0117. The 4-axis motor control microcomputer 115 is connected to the four DRV- ICs 119, 120, 121, and 122 via the communication ASIC 118.
　本実施形態に係る多重通信基板２０１は、ＥＴＨＥＲＰＨＹ－ＩＣ２０２、多重通信用ＦＰＧＡ２０３、ＤＯ２０６、ＤＩ２０７、及び４つのＤＲＶ－ＩＣ２０８，２０９，２１０，２１１を有する。多重通信用ＦＰＧＡ２０３は、Ｉ２Ｃ２０４とＳＰＩ２０５を有する。 The multiplex communication board 201 according to this embodiment includes an ETHERPHY-IC 202, a multiplex communication FPGA 203, a DO 206, a DI 207, and four DRV- ICs 208, 209, 210, and 211. The multiplex communication FPGA 203 has an I2C 204 and an SPI 205.
　ＥＴＨＥＲＰＨＹ－ＩＣ２０２は、多重通信用ＦＰＧＡ２０３に接続される。 The ETHERPHY-IC 202 is connected to the multiplex communication FPGA 203.
　多重通信用ＦＰＧＡ２０３は、ＤＯ２０６、ＤＩ２０７、及び４つのＤＲＶ－ＩＣ２０８，２０９，２１０，２１１に接続される。多重通信用ＦＰＧＡ２０３内のＩ２Ｃ２０４とＳＰＩ２０５は、４軸モータ制御用マイコン１１５内のＩ２Ｃ１３１とＳＰＩ１３２に接続される。 The multiplex communication FPGA 203 is connected to the DO 206, the DI 207, and the four DRV- ICs 208, 209, 210, and 211. The I2C 204 and the SPI 205 in the multiplex communication FPGA 203 are connected to the I2C 131 and the SPI 132 in the 4-axis motor control microcomputer 115.
　つまり、本実施形態に係る多重通信基板２０１は、同じ筐体であるＡエリア（固定部）１０１の多軸制御アンプ内で、多軸制御基板１１１内のＩ２Ｃ１３１、ＳＰＩ１３２と通信線で接続される。 That is, the multiplex communication board 201 according to the present embodiment is connected to the I2C 131 and the SPI 132 in the multi-axis control board 111 through communication lines in the multi-axis control amplifier of the A area (fixed portion) 101 that is the same housing. .
　また、本実施形態に係る多重通信基板２０１内のＤＯ２０６、ＤＩ２０７、及び４つのＤＲＶ－ＩＣ２０８，２０９，２１０，２１１は、多軸制御基板１１１内のＤＩ１１６、Ｄ０１１７、及び４つのＤＲＶ－ＩＣ１１９，１２０，１２１，１２２に接続される。 Also, the DO 206, DI 207, and the four DRV- ICs 208, 209, 210, 211 in the multiplex communication board 201 according to the present embodiment are the DI 116, D 0117, and the four DRV- ICs 119, 120 in the multi-axis control board 111. , 121, 122.
　Ｂエリア（可動部）３０１であるヘッドユニットは、センサ基板３１１、本実施形態に係る多重通信基板４０１、リミットスイッチ３１４、リレー３１５、及び４つのＡＣサーボモータ／シリアルエンコーダ３１６，３１７，３１８，３１９を有する。 The head unit which is the B area (movable part) 301 includes a sensor substrate 311, a multiplex communication substrate 401 according to the present embodiment, a limit switch 314, a relay 315, and four AC servomotor / serial encoders 316, 317, 318, and 319. Have
　センサ基板３１１は、感圧センサ３１２と加速度センサ３１３を実装する基板である。感圧センサ３１２は、実装部品の押し込み圧を制御するためのセンサである。加速度センサ３１３は、Ｂエリア（可動部）３０１であるヘッドユニットの振動を抑制するために加速度を検出するセンサである。 The sensor substrate 311 is a substrate on which the pressure sensor 312 and the acceleration sensor 313 are mounted. The pressure-sensitive sensor 312 is a sensor for controlling the indentation pressure of the mounted component. The acceleration sensor 313 is a sensor that detects acceleration in order to suppress vibration of the head unit that is the B area (movable part) 301.
　本実施形態に係る多重通信基板４０１は、ＥＴＨＥＲＰＨＹ－ＩＣ４０２、多重通信用ＦＰＧＡ４０３、ＤＩ４０６、Ｄ０４０７、及び４つのＤＲＶ－ＩＣ４０８，４０９，４１０，４１１を有する。多重通信用ＦＰＧＡ４０３は、Ｉ２Ｃ４０４とＳＰＩ４０５を有する。 The multiplex communication board 401 according to the present embodiment includes an ETHERPHY-IC 402, a multiplex communication FPGA 403, a DI 406, a D 0407, and four DRV- ICs 408, 409, 410, and 411. The multiplex communication FPGA 403 includes an I2C 404 and an SPI 405.
　多重通信用ＦＰＧＡ４０３内のＩ２Ｃ４０４は、感圧センサ３１２に接続される。多重通信用ＦＰＧＡ４０３内のＳＰＩ４０５は、加速度センサ３１３に接続される。 The I2C 404 in the multiplex communication FPGA 403 is connected to the pressure-sensitive sensor 312. The SPI 405 in the multiplex communication FPGA 403 is connected to the acceleration sensor 313.
　多重通信用ＦＰＧＡ４０３は、ＤＩ４０６、Ｄ０４０７、及び４つのＤＲＶ－ＩＣ４０８，４０９，４１０，４１１に接続される。 The multiplex communication FPGA 403 is connected to the DI 406, D 0407, and the four DRV- ICs 408, 409, 410, and 411.
　本実施形態に係る多重通信基板４０１内のＤＩ４０６、Ｄ０４０７、及び４つのＤＲＶ－ＩＣ４０８，４０９，４１０，４１１は、リミットスイッチ３１４、リレー３１５、及び４つのＡＣサーボモータ／シリアルエンコーダ３１６，３１７，３１８，３１９に接続される。 The DI 406, D0407, and four DRV- ICs 408, 409, 410, 411 in the multiplex communication board 401 according to the present embodiment are a limit switch 314, a relay 315, and four AC servo motor / serial encoders 316, 317, 318. , 319.
　本実施形態に係る多重通信基板４０１内のＥＴＨＥＲＰＨＹ－ＩＣ４０２は、Ａエリア（固定部）１０１の本実施形態に係る多重通信基板２０１内のＥＴＨＥＲＰＨＹ－ＩＣ２０２にケーブル５０１で接続される。ケーブル５０１は、多重通信用のイーサネット（登録商標）のケーブルであり、１０００ｂａｓｅ－ｔ用のカテゴリー５ｅの対屈曲性のあるＬＡＮ線が使用される。 The ETHERPHY-IC 402 in the multiplex communication board 401 according to the present embodiment is connected by a cable 501 to the ETHERPHY-IC 202 in the multiplex communication board 201 according to the present embodiment in the A area (fixed portion) 101. The cable 501 is an Ethernet (registered trademark) cable for multiplex communication, and a 1000 base-t category 5e anti-bending LAN line is used.
［２．多重通信基板の内部構成］
　図２は、本実施形態に係る多重通信基板２０１，４０１の内部構成図である。つまり、図２は、シリアルエンコーダ信号、Ｉ２Ｃ信号、及びＳＰＩ信号をＧｂＥを利用した多重通信を行う基板の内部構成が表される。本実施形態に係る多重通信基板２０１，４０１は、多重化対象信号の入力部、多重化処理部、及びＧｂＥを利用した多重化通信部に、大きく分けられる。 [2. Internal configuration of multiplex communication board]
FIG. 2 is an internal configuration diagram of the multiplex communication boards 201 and 401 according to the present embodiment. That is, FIG. 2 shows an internal configuration of a board that performs multiplex communication using a serial encoder signal, an I2C signal, and an SPI signal using GbE. The multiplex communication boards 201 and 401 according to the present embodiment are roughly divided into a multiplexing target signal input unit, a multiplexing processing unit, and a multiplexing communication unit using GbE.
　図２に表されたように、本実施形態に係る多重通信基板２０１，４０１は、上述したように、ケーブル５０１で接続される。 As shown in FIG. 2, the multiple communication boards 201 and 401 according to the present embodiment are connected by the cable 501 as described above.
　本実施形態に係る多重通信基板２０１は、１０００ｂａｓｅ－ｔ用ＰＨＹ－ＩＣ２１２、ＤＩＰ－ＳＷ２１３、多重通信プロトコル処理部２２０、シリアルエンコーダ入出力部２３０、Ｉ２Ｃ入出力部２４０、ＳＰＩ入出力部２５０、多重処理部２６０、ＲＳ４８５用ＤＲＩＶＥＲ－ＩＣ２７０、及び２つのＩ／Ｏ入出力部２８０，２９０を有する。 The multiplex communication board 201 according to this embodiment includes a 1000base-t PHY-IC 212, a DIP-SW 213, a multiplex communication protocol processing unit 220, a serial encoder input / output unit 230, an I2C input / output unit 240, an SPI input / output unit 250, It includes a processing unit 260, a DRIVER-IC 270 for RS485, and two I / O input / output units 280 and 290.
　１０００ｂａｓｅ－ｔ用ＰＨＹ－ＩＣ２１２は、多重通信を行うための１０００ｂａｓｅ－ｔの通信用ＰＨＹ－ＩＣである。 The 1000base-t PHY-IC 212 is a 1000base-t communication PHY-IC for performing multiplex communication.
　ＤＩＰ－ＳＷ２１３は、ＳＰＩ通信ではクロックのどのタイミングでデータを確定するかのモードはセンサ等のＩＣで決まるため、予めそのタイミングを設定するＤＩＰスイッチである（但し、あくまでもｄｅｆａｕｌｔ値で、４軸モータ制御用マイコン１１５側からのＵＡＲＴ，ＩＯ設定でもよい）。 The DIP-SW 213 is a DIP switch that sets the timing in advance because the mode for determining data at which timing of the clock in SPI communication is determined by the IC of the sensor or the like (however, the default value is a 4-axis motor) UART and IO setting from the control microcomputer 115 side may also be used).
　多重通信プロトコル処理部２２０は、ローカル側のデータを多重通信用プロトコル用に混合・分離処理を行う処理部である。多重通信プロトコル処理部２２０は、ＧＭＩＩ－ＩＦデータ入力部２２１、多重分離部２２２、多重混合部２２３、及びＧＭＩＩ－ＩＦデータ出力部２２４を有する。 The multiplex communication protocol processing unit 220 is a processing unit that performs mixing / separation processing of local data for a multiplex communication protocol. The multiplex communication protocol processing unit 220 includes a GMII-IF data input unit 221, a demultiplexing unit 222, a multiplex mixing unit 223, and a GMII-IF data output unit 224.
　シリアルエンコーダ入出力部２３０は、ＡＣサーボモータ３１６～３１９等のＡＢＳシリアルエンコーダ通信データを入力又は出力する。シリアルエンコーダ入出力部２３０は、 多重通信プロトコル処理部２２０へデータを送信又は多重通信プロトコル処理部２２０から受信したデータを出力する。シリアルエンコーダ入出力部２３０は、ＨＤＬＣ－Ｉ／Ｆデータ入力部２３１、受信バッファ２３２、ＨＤＬＣ－Ｉ／Ｆデータ出力部２３３、及び送信バッファ２３４を有し、それらは、多重化対象の各信号を多重化するための入出力部とそのバッファである。 The serial encoder input / output unit 230 inputs or outputs ABS serial encoder communication data such as AC servo motors 316 to 319. The serial encoder input / output unit 230 transmits data to the multiplex communication protocol processing unit 220 or outputs data received from the multiplex communication protocol processing unit 220. The serial encoder input / output unit 230 includes an HDLC-I / F data input unit 231, a reception buffer 232, an HDLC-I / F data output unit 233, and a transmission buffer 234, and these signals each signal to be multiplexed. An input / output unit for multiplexing and its buffer.
　Ｉ２Ｃ入出力部２４０は、Ｉ２Ｃ通信のクロック、多重通信用ＦＰＧＡ２０３内の高速なクロックでデータをサンプルし、Ｈ，Ｌ（１，０）信号を多重通信プロトコル処理部２２０へ送信する。Ｉ２Ｃ入出力部２４０は、多重通信プロトコル処理部２２０からのＨ，Ｌ（１，０）信号をＩ／Ｏ入出力部２８０へ出力する。Ｉ２Ｃ入出力部２４０は、Ｉ２Ｃ－Ｉ／Ｆデータ入力部２４１、受信バッファ２４２、Ｉ２Ｃ－Ｉ／Ｆデータ出力部２４３、及び送信バッファ２４４を有し、それらは、多重化対象の各信号を多重化するための入出力部とそのバッファである。 The I2C input / output unit 240 samples the data using the I2C communication clock and the high-speed clock in the multiplex communication FPGA 203 and transmits the H and L (1, 0) signals to the multiplex communication protocol processing unit 220. The I2C input / output unit 240 outputs the H, L (1, 0) signal from the multiplex communication protocol processing unit 220 to the I / O input / output unit 280. The I2C input / output unit 240 includes an I2C-I / F data input unit 241, a reception buffer 242, an I2C-I / F data output unit 243, and a transmission buffer 244, which multiplex each signal to be multiplexed. The input / output unit and its buffer
　ＳＰＩ入出力部２５０は、ＳＰＩ通信のクロック、多重通信用ＦＰＧＡ２０３内の高速なクロックでデータをサンプルし、Ｈ，Ｌ（１，０）信号を多重通信プロトコル処理部２２０へ送信する。ＳＰＩ入出力部２５０は、多重通信プロトコル処理部２２０からのＨ，Ｌ（１，０）信号をＩ／Ｏ入出力部２９０へ出力する。クロックのどのタイミングでデータを確定するかのモードは、センサ等のＩＣで決まるため、ＤＩＰ－ＳＷ２１３で予め設定する。ＳＰＩ入出力部２５０は、ＳＰＩ－Ｉ／Ｆデータ入力部２５１、受信バッファ２５２、ＳＰＩ－Ｉ／Ｆデータ出力部２５３、及び送信バッファ２５４を有し、それらは、多重化対象の各信号を多重化するための入出力部とそのバッファである。 The SPI input / output unit 250 samples data using the SPI communication clock and the high-speed clock in the multiplex communication FPGA 203, and transmits the H and L (1, 0) signals to the multiplex communication protocol processing unit 220. The SPI input / output unit 250 outputs the H, L (1, 0) signal from the multiplex communication protocol processing unit 220 to the I / O input / output unit 290. The mode for determining data at which timing of the clock is determined in advance by the DIP-SW 213 since it is determined by the IC such as a sensor. The SPI input / output unit 250 includes an SPI-I / F data input unit 251, a reception buffer 252, an SPI-I / F data output unit 253, and a transmission buffer 254, which multiplex each signal to be multiplexed. The input / output unit and its buffer
　多重処理部２６０は、本実施形態に係る多重通信基板２０１の機能を実現するための多重処理部であり、多重通信用ＦＰＧＡ２０３である。多重処理部２６０は、多重通信プロトコル処理部２２０、シリアルエンコーダ入出力部２３０、Ｉ２Ｃ入出力部２４０、及びＳＰＩ入出力部２５０を有する。 The multiplex processing unit 260 is a multiplex processing unit for realizing the function of the multiplex communication board 201 according to the present embodiment, and is a multiplex communication FPGA 203. The multiplex processing unit 260 includes a multiplex communication protocol processing unit 220, a serial encoder input / output unit 230, an I2C input / output unit 240, and an SPI input / output unit 250.
　ＲＳ４８５用ＤＲＩＶＥＲ－ＩＣ２７０は、シリアルエンコーダの物理層ＲＳ４８５のＤＲＩＶＥＲ－ＩＣである。 The RS485 DRIVER-IC 270 is a DRIVER-IC of the physical layer RS485 of the serial encoder.
　Ｉ／Ｏ入出力部２８０は、Ｉ２Ｃの信号レベルにあった入出力部である。 The I / O input / output unit 280 is an input / output unit suitable for the I2C signal level.
　Ｉ／Ｏ入出力部２９０は、ＳＰＩの信号レベルにあった入出力部である。 The I / O input / output unit 290 is an input / output unit suitable for the SPI signal level.
　同様にして、本実施形態に係る多重通信基板４０１は、１０００ｂａｓｅ－ｔ用ＰＨＹ－ＩＣ４１２、ＬＥＤ４１３、多重通信プロトコル処理部４２０、シリアルエンコーダ入出力部４３０、Ｉ２Ｃ入出力部４４０、ＳＰＩ入出力部４５０、多重処理部４６０、ＲＳ４８５用ＤＲＩＶＥＲ－ＩＣ４７０、及び２つのＩ／Ｏ入出力部４８０，４９０を有する。 Similarly, the multiplex communication board 401 according to the present embodiment includes a 1000-base-t PHY-IC 412, an LED 413, a multiplex communication protocol processing unit 420, a serial encoder input / output unit 430, an I2C input / output unit 440, and an SPI input / output unit 450. A multi-processing unit 460, an RS485 DRIVER-IC 470, and two I / O input / output units 480 and 490.
　１０００ｂａｓｅ－ｔ用ＰＨＹ－ＩＣ４１２は、多重通信を行うための１０００ｂａｓｅ－ｔの通信用ＰＨＹ－ＩＣである。 The 1000base-t PHY-IC 412 is a 1000base-t communication PHY-IC for performing multiplex communication.
　ＬＥＤ４１３は、ＳＰＩ通信で４軸モータ制御用マイコン１１５側と仕様があっているかの目視確認用ＬＥＤである。 The LED 413 is a visual confirmation LED for checking whether the specification matches the 4-axis motor control microcomputer 115 side by SPI communication.
　多重通信プロトコル処理部４２０は、ローカル側のデータを多重通信用プロトコル用に混合・分離処理を行う処理部である。多重通信プロトコル処理部４２０は、ＧＭＩＩ－ＩＦデータ入力部４２１、多重分離部４２２、多重混合部４２３、及びＧＭＩＩ－ＩＦデータ出力部４２４を有する。 The multiplex communication protocol processing unit 420 is a processing unit that performs mixing / separation processing of local data for a multiplex communication protocol. The multiplex communication protocol processing unit 420 includes a GMII-IF data input unit 421, a demultiplexing unit 422, a multiplex mixing unit 423, and a GMII-IF data output unit 424.
　シリアルエンコーダ入出力部４３０は、ＡＣサーボモータ３１６～３１９等のＡＢＳシリアルエンコーダ通信データを入力又は出力する。シリアルエンコーダ入出力部４３０は、 多重通信プロトコル処理部４２０へデータを送信又は多重通信プロトコル処理部４２０から受信したデータを出力する。シリアルエンコーダ入出力部４３０は、ＨＤＬＣ－Ｉ／Ｆデータ入力部４３１、受信バッファ４３２、ＨＤＬＣ－Ｉ／Ｆデータ出力部４３３、及び送信バッファ４３４を有し、それらは、多重化対象の各信号を多重化するための入出力部とそのバッファである。 The serial encoder input / output unit 430 inputs or outputs ABS serial encoder communication data of the AC servo motors 316 to 319 and the like. The serial encoder input / output unit 430 transmits data to the multiplex communication protocol processing unit 420 or outputs data received from the multiplex communication protocol processing unit 420. The serial encoder input / output unit 430 includes an HDLC-I / F data input unit 431, a reception buffer 432, an HDLC-I / F data output unit 433, and a transmission buffer 434. An input / output unit for multiplexing and its buffer.
　Ｉ２Ｃ入出力部４４０は、Ｉ２Ｃ通信のクロック、多重通信用ＦＰＧＡ４０３内の高速なクロックでデータをサンプルし、Ｈ，Ｌ（１，０）信号を多重通信プロトコル処理部４２０へ送信する。Ｉ２Ｃ入出力部４４０は、多重通信プロトコル処理部４２０からのＨ，Ｌ（１，０）信号をＩ／Ｏ入出力部４８０へ出力する。Ｉ２Ｃ入出力部４４０は、Ｉ２Ｃ－Ｉ／Ｆデータ入力部４４１、受信バッファ４４２、Ｉ２Ｃ－Ｉ／Ｆデータ出力部４４３、及び送信バッファ４４４を有し、それらは、多重化対象の各信号を多重化するための入出力部とそのバッファである。 The I2C input / output unit 440 samples data using the I2C communication clock and the high-speed clock in the multiplex communication FPGA 403 and transmits the H, L (1, 0) signal to the multiplex communication protocol processing unit 420. The I2C input / output unit 440 outputs the H, L (1, 0) signal from the multiplex communication protocol processing unit 420 to the I / O input / output unit 480. The I2C input / output unit 440 includes an I2C-I / F data input unit 441, a reception buffer 442, an I2C-I / F data output unit 443, and a transmission buffer 444, which multiplex each signal to be multiplexed. The input / output unit and its buffer
　ＳＰＩ入出力部４５０は、ＳＰＩ通信のクロック、多重通信用ＦＰＧＡ４０３内の高速なクロックでデータをサンプルし、Ｈ，Ｌ（１，０）信号を多重通信プロトコル処理部４２０へ送信する。ＳＰＩ入出力部４５０は、多重通信プロトコル処理部４２０からのＨ，Ｌ（１，０）信号をＩ／Ｏ入出力部４９０へ出力する。クロックのどのタイミングでデータを確定するかのモードは、センサ等のＩＣで決まるため、ＤＩＰ－ＳＷ２１３で予め設定する。ＳＰＩ入出力部４５０は、ＳＰＩ－Ｉ／Ｆデータ入力部４５１、受信バッファ４５２、ＳＰＩ－Ｉ／Ｆデータ出力部４５３、及び送信バッファ４５４を有し、それらは、多重化対象の各信号を多重化するための入出力部とそのバッファである。 The SPI input / output unit 450 samples data using the SPI communication clock and the high-speed clock in the multiplex communication FPGA 403 and transmits the H, L (1, 0) signal to the multiplex communication protocol processing unit 420. The SPI input / output unit 450 outputs the H, L (1, 0) signal from the multiplex communication protocol processing unit 420 to the I / O input / output unit 490. The mode for determining data at which timing of the clock is determined in advance by the DIP-SW 213 since it is determined by the IC such as a sensor. The SPI input / output unit 450 includes an SPI-I / F data input unit 451, a reception buffer 452, an SPI-I / F data output unit 453, and a transmission buffer 454, which multiplex each signal to be multiplexed. The input / output unit and its buffer
　多重処理部４６０は、本実施形態に係る多重通信基板４０１の機能を実現するための多重処理部であり、多重通信用ＦＰＧＡ４０３である。多重処理部４６０は、多重通信プロトコル処理部４２０、シリアルエンコーダ入出力部４３０、Ｉ２Ｃ入出力部４４０、及びＳＰＩ入出力部４５０を有する。 The multiplex processing unit 460 is a multiplex processing unit for realizing the function of the multiplex communication board 401 according to the present embodiment, and is a multiplex communication FPGA 403. The multiplex processing unit 460 includes a multiplex communication protocol processing unit 420, a serial encoder input / output unit 430, an I2C input / output unit 440, and an SPI input / output unit 450.
　ＲＳ４８５用ＤＲＩＶＥＲ－ＩＣ４７０は、シリアルエンコーダの物理層ＲＳ４８５のＤＲＩＶＥＲ－ＩＣである。 The RS485 DRIVER-IC 470 is a DRIVER-IC of the physical layer RS485 of the serial encoder.
　Ｉ／Ｏ入出力部４８０は、Ｉ２Ｃの信号レベルにあった入出力部である。 The I / O input / output unit 480 is an input / output unit suitable for the I2C signal level.
　Ｉ／Ｏ入出力部４９０は、ＳＰＩの信号レベルにあった入出力部である。 The I / O input / output unit 490 is an input / output unit that conforms to the SPI signal level.
［３．多重通信プロトコル］
　本実施形態に係る多重通信基板２０１，４０１は、ＧｂＥ（１０００ｂａｓｅ－ｔ、半２重通信）を使用し、一定回数毎に送受信を切り替えて行う。図３，図４は、本実施形態に係る多重通信基板２０１，４０１（図２参照）が半２重通信方式で送受信を行う際のイーサネット（登録商標）の規格ＧｂＥによる多重通信プロトコルが表わされた図である。 [3. Multiplex communication protocol]
The multiplex communication boards 201 and 401 according to the present embodiment use GbE (1000 base-t, half-duplex communication) and perform transmission / reception by switching at a fixed number of times. 3 and 4 show a multiplex communication protocol based on the Ethernet (registered trademark) standard GbE when the multiplex communication boards 201 and 401 (see FIG. 2) according to the present embodiment perform transmission and reception by the half-duplex communication method. FIG.
　図３，図４では、縦軸に通信方向が表される。図３は、Ａエリア２からＢエリア３にデータを送信する半２重通信方式の多重通信プロトコルが表わされた図であるが、Ｂエリア３からＡエリア２にデータを送信する半２重通信方式の多重通信プロトコルは記載されていない。これに対して、図４は、Ｂエリア３からＡエリア２にデータを送信する半２重通信方式の多重通信プロトコルが表された図であるが、Ａエリア２からＢエリア３にデータを送信する半２重通信方式の多重通信プロトコルは記載されていない。 3 and 4, the vertical axis represents the communication direction. FIG. 3 is a diagram showing a multiplex communication protocol of a half-duplex communication method for transmitting data from A area 2 to B area 3, but half-duplex for transmitting data from B area 3 to A area 2. The multiplex communication protocol of the communication method is not described. On the other hand, FIG. 4 shows a half-duplex communication protocol for transmitting data from B area 3 to A area 2, but transmits data from A area 2 to B area 3. The multiplex communication protocol of the half duplex communication system is not described.
　多重通信プロトコルは、１２５ＭＨｚのクロック毎に図３，図４に表されるような通信プロトコルであり、８ＢＩＴの送受信を行い、ローカル側の通信合成・分離を行う。その８ＢＩＴは、図３，図４では、縦軸に並んだ「Ｂ０」，「Ｂ１」，「Ｂ２」，「Ｂ３」，「Ｂ４」，「Ｂ５」，「Ｂ６」，「Ｂ７」で表される。 The multiplex communication protocol is a communication protocol as shown in FIG. 3 and FIG. 4 for each 125 MHz clock, and transmits / receives 8 bits, and performs communication synthesis / separation on the local side. The 8 bits are represented by “B0”, “B1”, “B2”, “B3”, “B4”, “B5”, “B6”, “B7” arranged in the vertical axis in FIGS. The
　図３では、横軸に並んだ「０」～「１４」の数値は、多重化通信を行うクロック（規格ＧｂＥ用と同じ１２５ＭＨｚ）のカウンタ数である。同様にして、図４では、横軸に並んだ「１５」～「２９」の数値は、多重化通信を行うクロック（規格ＧｂＥ用と同じ１２５ＭＨｚ）のカウンタ数である。 In FIG. 3, the numerical values “0” to “14” arranged on the horizontal axis are the counter numbers of the clock (125 MHz, which is the same as that for the standard GbE) for performing multiplexed communication. Similarly, in FIG. 4, the numerical values “15” to “29” arranged on the horizontal axis are the counter numbers of the clock (125 MHz, which is the same as that for the standard GbE) for performing multiplexed communication.
　図３，図４において、「ＳＰＩ－Ｄ」は、ＳＰＩ通信のデータを表す。「ＳＰＩ有／無」は、データ有無のフラグである。「ＳＰＩ有」は、ＳＰＩデータが有ることを表す。「ＳＰＩ無」は、ＳＰＩのデータが無いことを表す。「Ｉ２Ｃ－Ｄ」は、Ｉ２Ｃ通信のデータを表す。「Ｉ２Ｃ有／無」は、データ有無のフラグである。「Ｉ２Ｃ有」は、Ｉ２Ｃデータが有ることを表す。「Ｉ２Ｃ無」は、Ｉ２Ｃのデータが無いことを表す。 3 and 4, “SPI-D” represents data of SPI communication. “With / without SPI” is a flag indicating the presence / absence of data. “With SPI” indicates that there is SPI data. “No SPI” indicates that there is no SPI data. “I2C-D” represents I2C communication data. “I2C present / not present” is a flag indicating the presence / absence of data. “I2C present” indicates that there is I2C data. “No I2C” indicates that there is no I2C data.
　図３，図４において、「ＤＯ０」，「ＤＯ１」，「ＤＯ２」，「ＤＯ３」は、デジタル出力信号（Ｈｉ：１，Ｌｏｗ：０）である。「ＤＩ１」，「ＤＩ２」，「ＤＩ３」は、デジタル入力信号（Ｈｉ：１，Ｌｏｗ：０）である。 3 and 4, “DO0”, “DO1”, “DO2”, and “DO3” are digital output signals (Hi: 1, Low: 0). “DI1”, “DI2”, and “DI3” are digital input signals (Hi: 1, Low: 0).
　図３，図４において、「エンコーダ１　データ」，「エンコーダ２　データ」，「エンコーダ３　データ」，「エンコーダ４　データ」は、エンコーダ信号を多重化するデータである。「ＦＥＣ（１５，１１）短縮系」は、ハミング符号（１５，１１）の短縮系（３ＢＩＴが０固定）で、誤り訂正用に付加される４ＢＩＴデータである。図３では、カウンタ数が「２」～「９」の横一列の８ＢＩＴ＋（３ＢＩＴが０固定）の計１１ＢＩＴを対象とする。図４では、カウンタ数が「１７」～「２４」の横一列の８ＢＩＴ＋（３ＢＩＴが０固定）の計１１ＢＩＴを対象とする。 3 and 4, “encoder 1 data”, “encoder 2 data”, “encoder 3 data”, and “encoder 4 data” are data for multiplexing encoder signals. The “FEC (15, 11) shortening system” is a shortening system of the Hamming code (15, 11) (3 BIT is fixed to 0) and is 4 BIT data added for error correction. In FIG. 3, a total of 11 BITs of 8 BIT + (3 BIT is fixed to 0) in a horizontal row with the counter number “2” to “9” are targeted. In FIG. 4, a total of 11 BITs of 8 BIT + (3 BIT is fixed to 0) in a horizontal row with the counter number “17” to “24” are targeted.
　図３，図４において、「ＳＳ１」，「ＳＳ２」，「ＳＳ３」，「ＳＳ４」は、ＳＰＩ通信で通信対象とするデバイスの選択信号である。「ＭＯＤＥ０」，「ＭＯＤＥ１」，「ＭＯＤＥ２」，「ＭＯＤＥ３」は、ＳＰＩ通信でデータを確定するクロックのタイミングのモード（Clock Phase）を表す。また、「ＣＬＫ＿Ｉ２Ｃ＿ＮＯ」、「ＣＬＫ＿ＳＰＩ＿ＮＯ」は、Ｉ２Ｃ，ＳＰＩ通信の代表的なｃｌｏｃｋ周波数を０－３の４種類（例えば、１，２，５，１０ＭＨｚ）用意し、可動部側の周辺デバイスで使用するｃｌｏｃｋを指定する。 3 and 4, “SS1”, “SS2”, “SS3”, and “SS4” are selection signals for devices to be communicated by SPI communication. “MODE0”, “MODE1”, “MODE2”, and “MODE3” represent clock timing modes (Clock Phase) for determining data by SPI communication. In addition, “CLK_I2C_NO” and “CLK_SPI_NO” provide four types of representative clock frequencies for I2C and SPI communication (for example, 1, 2, 5, and 10 MHz) for use in peripheral devices on the movable part side. The clock to be specified is specified.
　尚、「空き」は、データそのものが存在しないことを表す。 Note that “free” means that the data itself does not exist.
　図３に表されたように、カウンタ数が「０」，「１」の通信開始時はプリアンブル２個が送受信される。カウンタ数が「１４」では、送受信を切り替えるため、お互いに送信ＯＦＦの状態とする。 As shown in FIG. 3, two preambles are transmitted and received at the start of communication with the counter numbers “0” and “1”. When the number of counters is “14”, transmission and reception are switched, so that transmission is mutually turned off.
　図４に表されたように、カウンタ数が「１５」～「２９」の後半１５回分は、送受信の方向を切り替えて通信を行う。 As shown in FIG. 4, for the last 15 times of the counter number “15” to “29”, communication is performed by switching the transmission / reception direction.
［４．まとめ］
　すなわち、本実施形態では、従来、短い距離間でしか使用できなかった小型の周辺デバイスである感圧センサ３１２や加速度センサ３１３が距離のはなれた筐体外のユニット・装置間で通信可能となる。 [4. Summary]
That is, in the present embodiment, the pressure-sensitive sensor 312 and the acceleration sensor 313, which are small peripheral devices that have conventionally been used only for a short distance, can communicate with each other between units and devices outside the casing.
　従来は、センサのアナログ出力をマイコンのＡ／Ｄに直接接続するので、ノイズで分解能が出なかったり、また、産業用のイーサネット（登録商標）又はＣＣ－Ｌｉｎｋ（登録商標）等の省配線規格品のスレーブ機器でＡ／Ｄ等が搭載されたユニットを選択する必要があるため、小型化することができなかった。しかしながら、本実施の形態では、高速・低遅延で直接に本実施形態に係る多重通信基板４０１に周辺デバイスである感圧センサ３１２や加速度センサ３１３が接続できるため、ハードウエア的に小型で精度の良い複雑な制御が可能となる。 Conventionally, the analog output of the sensor is directly connected to the A / D of the microcomputer, so there is no resolution due to noise, and the wiring-saving standards such as industrial Ethernet (registered trademark) or CC-Link (registered trademark) Since it is necessary to select a unit on which A / D or the like is mounted as a slave device, it has not been possible to reduce the size. However, in this embodiment, the pressure-sensitive sensor 312 and the acceleration sensor 313, which are peripheral devices, can be directly connected to the multiplex communication board 401 according to this embodiment with high speed and low delay. Good complex control is possible.
　つまり、センサ類（感圧センサ３１２や加速度センサ３１３）と４軸モータ制御用マイコン１１５が直接通信を行うので、コントローラ１１の負荷が増えない。４軸モータ制御用マイコン１１５は、センサ類（感圧センサ３１２や加速度センサ３１３）からのデータを直接収集できるため、遅延が少なく、高性能なフィードバック制御が実現可能である。 That is, since the sensors (the pressure sensor 312 and the acceleration sensor 313) and the 4-axis motor control microcomputer 115 communicate directly, the load on the controller 11 does not increase. The 4-axis motor control microcomputer 115 can directly collect data from the sensors (the pressure-sensitive sensor 312 and the acceleration sensor 313), so that there is little delay and high-performance feedback control can be realized.
　本実施形態では、他の通信データと多重化するために、ユニット間の追加配線がなく、省配線化できる。よって、本実施形態では、例えば、センサ出力用のアナログ出力ケーブル、ＲＳ４８５ケーブル、又はイーサネット（登録商標）用ケーブルの追加が不要である。 In the present embodiment, since multiplexing with other communication data is performed, there is no additional wiring between units, and wiring can be saved. Therefore, in this embodiment, for example, it is not necessary to add an analog output cable for sensor output, an RS485 cable, or an Ethernet (registered trademark) cable.
　つまり、他の信号線（エンコーダ・ＤＩＯ）を含めて多重化しているため、通信線としては、Ａエリア（固定部）１０１である多軸制御アンプとＢエリア（可動部）３０１であるヘッドユニットとの間を、多重通信用のイーサネット（登録商標）のケーブル５０１のＬＡＮ線を１本接続するだけでよく、省配線を実現可能にする。 That is, since other signal lines (encoders / DIOs) are multiplexed, the communication line includes a multi-axis control amplifier that is A area (fixed part) 101 and a head unit that is B area (movable part) 301. It is only necessary to connect one LAN line of the Ethernet (registered trademark) cable 501 for multiplex communication between the two.
　本実施形態では、既に出荷済み装置のワイヤーハーネスの配線を変更せず、新型ユニット内の基板の追加・変更や、マイコンを搭載するユニット側のソフトウエアの変更のみで、装置の機能拡張が可能である。 In this embodiment, it is possible to expand the function of the device by changing the software on the unit side where the microcomputer is installed without changing the wiring of the wire harness of the already shipped device It is.
　つまり、Ｂエリア（可動部）３０１であるヘッドユニットでセンサ類（感圧センサ３１２や加速度センサ３１３）を変更しても、Ａエリア（固定部）１０１である多軸制御アンプとＢエリア（可動部）３０１であるヘッドユニットとの間での配線変更が不要である。多軸制御基板１１１のＣＰＵを変更するのみで対応可能である。従って、既に納入された装置でも、配線工事なしで、Ｂエリア（可動部）３０１であるヘッドユニットの新型を使用することで、新機能の効果を得られる。 That is, even if the sensors (pressure-sensitive sensor 312 and acceleration sensor 313) are changed in the head unit that is the B area (movable part) 301, the multi-axis control amplifier that is the A area (fixed part) 101 and the B area (movable) No change in wiring with the head unit 301 is required. This can be dealt with only by changing the CPU of the multi-axis control board 111. Therefore, even if the device has already been delivered, the effect of the new function can be obtained by using a new head unit that is the B area (movable part) 301 without wiring work.
　従来は、機械系の振動制御等では、デジタルフィルタ（ノッチＦＩＬＴＥＲ等）を使用するのが一般的であるが、この処理時のＣＰＵにかかる負荷が大きく、発熱が高くなるため、処理能力が高い高価なＣＰＵを使用する必要がある。しかしながら、本実施形態では、多重通信用ＦＰＧＡ２０３，４０３に予め決められた機能（例えば、ＬＰＦ、ＨＰＦ（High Pass Filer）、又はノッチ等）又は周波数のデジタルフィルタ機能を利用することで、制御用ＣＰＵに対し、負荷を減らし、発熱を低く抑えられるので、処理能力が低い安価な制御用ＣＰＵを選択することが可能である。 Conventionally, it is common to use a digital filter (notch FILTER, etc.) for mechanical vibration control, etc., but the processing load is high because the load on the CPU during this processing is large and the heat generation is high. It is necessary to use an expensive CPU. However, in the present embodiment, a control CPU is used by utilizing a predetermined function (for example, LPF, HPF (High Pass Filer), or notch) or a frequency digital filter function in the multiplex communication FPGAs 203 and 403. On the other hand, since the load is reduced and the heat generation can be kept low, it is possible to select an inexpensive control CPU having a low processing capability.
［５．その他］
　尚、本発明は上記実施形態に限定されるものでなく、その趣旨を逸脱しない範囲で様々な変更が可能である。
　例えば、本実施の形態では、「周辺デバイス」として、感圧センサ３１２や加速度センサ３１３を使用する。その他に、「周辺デバイス」として、ＥＥＰＲＯＭ、Ａ／Ｄ変換器、Ｄ／Ａ変換器、又はロードセル等を使用してもよい。 [5. Others]
In addition, this invention is not limited to the said embodiment, A various change is possible in the range which does not deviate from the meaning.
For example, in this embodiment, the pressure-sensitive sensor 312 and the acceleration sensor 313 are used as “peripheral devices”. In addition, an EEPROM, an A / D converter, a D / A converter, a load cell, or the like may be used as the “peripheral device”.
　また、本実施の形態では、「シリアルバス規格のデータ伝送」として、ＳＰＩ通信やＩ２Ｃ通信を行う。その他に、「シリアルバス規格のデータ伝送」として、Ｍｉｃｒｏｗｉｒｅ（登録商標）通信等を行ってもよい。 Further, in the present embodiment, SPI communication and I2C communication are performed as “serial bus standard data transmission”. In addition, as the “serial bus standard data transmission”, Microwire (registered trademark) communication or the like may be performed.
　　１　多重通信システム
１１５　４軸モータ制御用マイコン
２０１　多重通信基板
２０２　ＥＴＨＥＲＰＨＹ－ＩＣ
２０３　多重通信用ＦＰＧＡ
２３３　ＨＤＬＣ－Ｉ／Ｆ出力部
２３４　送信バッファ
２４３　Ｉ２Ｃ－Ｉ／Ｆデータ出力部
２４４　送信バッファ
２５３　ＳＰＩ－Ｉ／Ｆデータ出力部
２５４　送信バッファ
３１１　センサ基板
３１２　感圧センサ
３１３　加速度センサ
４０１　多重通信基板
４０２　ＥＴＨＥＲＰＨＹ－ＩＣ
４０３　多重通信用ＦＰＧＡ
４３３　ＨＤＬＣ－Ｉ／Ｆ出力部
４３４　送信バッファ
４４３　Ｉ２Ｃ－Ｉ／Ｆデータ出力部
４４４　送信バッファ
４５３　ＳＰＩ－Ｉ／Ｆデータ出力部
４５４　送信バッファ
５０１　多重通信用のイーサネット（登録商標）のケーブル 1 Multiplex Communication System 115 4-axis Motor Control Microcomputer 201 Multiplex Communication Board 202 ETHERPHY-IC
203 FPGA for multiplex communication
233 HDLC-I / F output unit 234 Transmission buffer 243 I2C-I / F data output unit 244 Transmission buffer 253 SPI-I / F data output unit 254 Transmission buffer 311 Sensor substrate 312 Pressure sensor 313 Acceleration sensor 401 Multiplex communication substrate 402 ETHERPHY-IC
403 FPGA for multiplex communication
433 HDLC-I / F output unit 434 Transmission buffer 443 I2C-I / F data output unit 444 Transmission buffer 453 SPI-I / F data output unit 454 Transmission buffer 501 Ethernet (registered trademark) cable for multiplex communication

Claims (4)

  1. 　基板内又は基板間で、マイコンと周辺デバイス間のシリアルバス規格のデータ伝送を多重化したこと、を特徴とする多重通信装置。 A multiplex communication device characterized by multiplexing serial bus standard data transmission between a microcomputer and peripheral devices within a substrate or between substrates.
  2. 　データの論理層と物理層の内部インターフェイスの前記物理層として用いられるイーサネット（登録商標）用の物理層回路と、
    　多重通信用ワイヤーハーネスとして用いられるＬＡＮ線と、を備えたこと、を特徴とする請求項１に記載の多重通信装置。     A physical layer circuit for Ethernet (registered trademark) used as the physical layer of the logical interface of the data and the internal interface of the physical layer;
    The multiplex communication apparatus according to claim 1, further comprising a LAN line used as a multiplex communication wire harness.
  3. 　ローカル出力部と、
    　バッファと、を備え、
    　前記ローカル出力部は、連続的に出力するためのデータ数分を前記バッファにためた後に、前記バッファにためたデータの出力を開始すること、を特徴とする請求項１に記載の多重通信装置。     A local output section;
    A buffer, and
    The multiplex communication apparatus according to claim 1, wherein the local output unit starts outputting data for the buffer after storing the number of data for continuous output in the buffer. .
  4. 　予め決められた機能又は周波数のデジタルフィルタ機能を備え、
    　前記周辺デバイスの値に対して前記機能で処理した結果を出力すること、を特徴とする請求項１に記載の多重通信装置。     It has a digital filter function of a predetermined function or frequency,
    The multiplex communication apparatus according to claim 1, wherein the result of processing by the function is output for the value of the peripheral device.
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JP7391116B2 (en) 2019-06-28 2023-12-04 アナログ・ディヴァイシス・インターナショナル・アンリミテッド・カンパニー 1 port of low complexity Ethernet node (LEN)
US11940943B2 (en) 2019-06-28 2024-03-26 Analog Devices International Unlimited Company Low complexity ethernet node (LEN) one port

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