WO2016033825A1 - 像素结构 - Google Patents

像素结构 Download PDF

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Publication number
WO2016033825A1
WO2016033825A1 PCT/CN2014/086594 CN2014086594W WO2016033825A1 WO 2016033825 A1 WO2016033825 A1 WO 2016033825A1 CN 2014086594 W CN2014086594 W CN 2014086594W WO 2016033825 A1 WO2016033825 A1 WO 2016033825A1
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WIPO (PCT)
Prior art keywords
layer
pixel
common electrode
pixel electrode
electrode patterns
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PCT/CN2014/086594
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English (en)
French (fr)
Chinese (zh)
Inventor
黄俊儒
廖培钧
张哲嘉
叶于菱
Original Assignee
友达光电股份有限公司
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Publication of WO2016033825A1 publication Critical patent/WO2016033825A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • the present invention relates to a pixel structure, and more particularly to a pixel structure for a liquid crystal driving mode in which a horizontal electric field and a fringe electric field are mixed.
  • TN twisted nematic liquid crystal
  • IPS in-plane switching
  • FFS margin field switching
  • MAA multi-domain vertical alignment
  • the storage capacitance (Cst) of the FFS liquid crystal display panel is related to the overlapping area of the two electrodes.
  • Cst storage capacitance
  • the FFS liquid crystal display panel may cause some problems due to excessive Cst, such as an excessively large RC loading of the data line, resulting in insufficient charging rate.
  • the IPS does not have the above problem, the liquid crystal efficiency of the IPS liquid crystal display panel is lower than that of the FFS liquid crystal display panel, and the operating voltage of the IPS liquid crystal display panel is higher than that of the FFS liquid crystal display panel.
  • the present invention provides a pixel structure that can solve the problems of the FFS liquid crystal display panel and the IPS liquid crystal display panel when applied to a display panel.
  • the pixel structure of the present invention includes scan lines and data lines, active elements, pixel electrodes, and a common electrode.
  • the active component is electrically connected to the scan line and the data line.
  • the pixel electrode is electrically connected to the active device, wherein the pixel electrode includes a plurality of first layer pixel electrode patterns and a plurality of second layer pixel electrode patterns.
  • the common electrode is electrically insulated from the pixel electrode, and the common electrode includes a plurality of first layer common electrode patterns and a plurality of second layer common electrode patterns.
  • Each of the first layer of pixel electrode patterns and the corresponding second layer of common electrode patterns have a fringe field, and each of the first layer shares an electrode pattern and a corresponding second There is a fringe electric field between the layer pixel electrode patterns.
  • the pixel structure wherein the edge electric field is formed between each of the first layer pixel electrode patterns and the at least two corresponding second layer common electrode patterns, and each of the first layer shares an electrode pattern and the at least two The fringe electric field is formed between the corresponding second layer of pixel electrode patterns.
  • each of the first layer of pixel electrode patterns and the at least two corresponding second layer of common electrode patterns constitute a first set of edge electric field electrode groups, and each of the first layer shares an electrode pattern and the at least The two corresponding second layer pixel electrode patterns form a second set of fringe electric field electrode groups, and the horizontal electric field is formed between the first set of fringe electric field electrode groups and the second set of fringe electric field electrode groups.
  • the line width of each of the first layer pixel electrode patterns and the first layer common electrode pattern is greater than 0 and less than or equal to 30 ⁇ m, respectively, and each of the second layer pixel electrode patterns and each of The line widths of the second layer common electrode patterns are respectively greater than 0 and less than or equal to 10 ⁇ m, and the distance between each of the second layer pixel electrode patterns and the adjacent second layer common electrode patterns is greater than 0 and less than or equal to 30 ⁇ m.
  • a distance between each of the second layer of pixel electrode patterns and the adjacent second layer of pixel electrode patterns is greater than 0 and less than or equal to 20 ⁇ m, and each of the second layer common electrode patterns and the adjacent second layer share the electrode pattern The distance between them is greater than 0 and less than or equal to 20 ⁇ m.
  • the pixel electrode further includes a pixel electrode connection structure, the second layer pixel electrode patterns and the first layer pixel electrode patterns are electrically connected to the pixel electrode connection structure, and the active device and the The pixel electrode connection structure is electrically connected.
  • the pixel electrode connection structure includes: a first layer connection portion connecting the first layer pixel electrode patterns; a second layer connection portion connecting the second layer pixel electrode patterns; a contact window electrically connecting the active component to the first layer connection portion; and a second contact window electrically connecting the second layer connection portion to the first layer connection portion.
  • the common electrode further includes a common electrode connection structure, the second layer common electrode patterns and the first layer common electrode patterns are electrically connected to the common electrode connection structure, and the common electrode connection structure Electrically connected to a common electrode line.
  • the common electrode connection structure includes: a first layer connection portion connecting the first layer common electrode patterns, and the first layer connection portion is in electrical contact with the common electrode line; a second layer a connecting portion connecting the second layer common electrode patterns; and a contact window electrically connecting the second layer connecting portion and the first layer connecting portion.
  • the above pixel structure wherein the first layer of pixel electrode patterns and the second layer of pixel electrodes The pattern is parallel to the data line, and the first layer common electrode patterns and the second layer common electrode patterns are parallel to the data lines.
  • Another pixel structure of the present invention includes scan lines and data lines, active elements, pixel electrodes, and a common electrode.
  • the active component is electrically connected to the scan line and the data line.
  • the pixel electrode is electrically connected to the active device, wherein the pixel electrode includes a plurality of first layer pixel electrode patterns and a plurality of second layer pixel electrode patterns.
  • the common electrode is electrically insulated from the pixel electrode, and the common electrode includes a plurality of common electrode patterns. There is a fringe electric field between each of the first layer of pixel electrode patterns and the corresponding common electrode pattern. There is a horizontal electric field between each second layer of pixel electrode patterns and an adjacent common electrode pattern.
  • the fringe electric field is formed between each of the first layer of pixel electrode patterns and the at least two corresponding common electrode patterns.
  • the first layer of pixel electrode patterns and the at least two corresponding common electrode patterns form a set of fringe electric field electrode groups, and the set of edge electric field electrode groups and the adjacent second layer of pixel electrode patterns This horizontal electric field is formed between.
  • the line width of each of the first layer of pixel electrode patterns is greater than 0 and less than or equal to 30 ⁇ m
  • the line width of each of the second layer of pixel electrode patterns and each of the common electrode patterns is greater than 0 and less than or equal to 10 ⁇ m
  • the distance between each second layer pixel electrode pattern and the adjacent common electrode pattern is greater than 0 and less than or equal to 30 ⁇ m
  • the distance between each common electrode pattern and the adjacent common electrode pattern is greater than 0 and less than or equal to 20 ⁇ m.
  • the pixel electrode further includes a pixel electrode connection structure, the second layer of pixel electrodes and the first layer of pixel electrodes are electrically connected to the pixel electrode connection structure, and the active device and the pixel electrode The connection structure is electrically connected.
  • the pixel electrode connection structure includes: a second layer connection portion connecting the second layer pixel electrode patterns; a first layer connection portion connecting the first layer pixel electrode patterns; a contact window electrically connecting the active component to the first layer connection portion; and a second contact window electrically connecting the second layer connection portion to the first layer connection portion.
  • the common electrode further includes a common electrode connection structure, the common electrode patterns are electrically connected to the common electrode connection structure, and the common electrode connection structure is electrically connected to a common electrode line.
  • the first layer of pixel electrode patterns and the second layer of pixel electrode patterns are parallel to the data line, and the common electrode patterns are parallel to the data line.
  • each pixel electrode pattern and the corresponding common film pattern of different film layers may be There are fringe electric fields.
  • each pixel electrode pattern may have a horizontal electric field between the common electrode patterns of adjacent identical film layers. Therefore, according to an embodiment of the present invention, a liquid crystal driving mode having a horizontal electric field and a fringe electric field in the same pixel structure can be simultaneously provided, so that the FFS technology can be improved in a large size storage capacitor without increasing the process cost. Excessive problems, and can improve the liquid crystal efficiency of IPS technology is lower than FFS and the operating voltage is higher than FFS.
  • FIG. 1 is a cross-sectional view of a display panel in accordance with an embodiment of the present invention.
  • FIG. 2 is a top plan view of a pixel structure in accordance with a first embodiment of the present invention
  • Figure 3A is a cross-sectional view of the pixel structure of Figure 2 taken along line A-A';
  • 3B is a schematic cross-sectional view showing an electric field formed by the pixel structure of FIG. 3A;
  • Figure 4 is a cross-sectional view of the pixel structure of Figure 2 taken along line B-B';
  • Figure 5 is a cross-sectional view of the pixel structure of Figure 2 taken along line D-D';
  • Figure 6 is a plan view of a pixel structure in accordance with a second embodiment of the present invention.
  • Figure 7A is a cross-sectional view of the pixel structure of Figure 6 taken along line E-E';
  • FIG. 7B is a schematic cross-sectional view showing an electric field formed by the pixel structure of FIG. 7A;
  • Figure 8 is a cross-sectional view of the pixel structure of Figure 6 taken along line F-F';
  • Figure 9 is a cross-sectional view of the pixel structure of Figure 6 taken along line G-G';
  • Figure 10 is a plan view of a pixel structure in accordance with a third embodiment of the present invention.
  • Figure 11A is a cross-sectional view of the pixel structure of Figure 10 taken along line H-H';
  • FIG. 11B is a schematic cross-sectional view showing an electric field formed by the pixel structure of FIG. 11A;
  • Figure 12 is a cross-sectional view of the pixel structure of Figure 10 taken along line I-I';
  • Figure 13 is a cross-sectional view of the pixel structure of Figure 10 taken along line J-J';
  • Figure 14 is a plan view of a pixel structure in accordance with a fourth embodiment of the present invention.
  • Figure 15A is a cross-sectional view of the pixel structure of Figure 14 taken along line K-K';
  • 15B is a schematic cross-sectional view showing an electric field formed by the pixel structure of FIG. 15A;
  • Figure 16 is a cross-sectional view of the pixel structure of Figure 14 taken along line L-L';
  • Figure 17 is a cross-sectional view of the pixel structure of Figure 14 taken along line M-M';
  • Figure 18 is a top plan view of a pixel structure in accordance with a fifth embodiment of the present invention.
  • HE, HE1, HE2 horizontal electric field
  • a display panel 1000 of the present invention has a first substrate 100, a second substrate 200, a display medium 150, and a pixel array layer PX.
  • the display panel 1000 is a liquid crystal display panel.
  • the material of the first substrate 100 may be glass, quartz, organic polymer, metal or the like.
  • the first substrate 100 includes a pixel array layer PX, and the pixel array layer PX is composed of a plurality of pixel structures 10.
  • the second substrate 200 is located opposite to the first substrate 100.
  • the material of the second substrate 200 may be glass, quartz, an organic polymer or the like, but the invention is not limited thereto.
  • the display medium 150 is located between the pixel array layer PX on the first substrate 100 and the second substrate 200.
  • Display medium 150 includes a plurality of liquid crystal molecules (not shown).
  • the liquid crystal molecules may be positive liquid crystal molecules or negative liquid crystal molecules.
  • the pixel array layer PX is located on the first substrate 100, and the display medium 150 is covered over the pixel array layer PX.
  • the pixel array layer PX is composed of a plurality of pixel structures 10.
  • a pixel structure of some embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order to clearly illustrate an embodiment of the present invention, the following drawings depict only one of the pixel structures of the pixel array layer PX.
  • the pixel structure 10 shown in FIG. 2 includes a scan line SL, a data line DL, a common electrode line CL, an active device T, a pixel electrode P, and a common electrode C.
  • the scanning line SL and the extending direction of the data line DL are different, and it is preferable that the extending direction of the scanning line SL is perpendicular to the extending direction of the data line DL.
  • the scan line SL and the data line DL are different film layers, and the scan line SL and the common electrode line CL are located in the same film layer.
  • An insulating layer (not shown) is interposed between the scan line SL and the data line DL.
  • the scan line SL and the data line DL are mainly used to supply a driving voltage to the pixel electrode P and to transmit a driving signal for driving the pixel structure 10.
  • the common electrode line CL is mainly used to supply a common voltage to the common electrode C.
  • Scan line SL, common electrode line CL, and data line DL are generally It is made of metal materials.
  • the present invention is not limited thereto.
  • other conductive materials may be used for the scan line SL, the common electrode line CL, and the data line DL, including alloys, oxides of metal materials, nitrides of metal materials, and metal materials.
  • the oxynitride is a stack of a metal material and other conductive materials, but the invention is not limited thereto.
  • the material of the pixel electrode P and the common electrode C is, for example, a transparent conductive layer including a metal oxide such as indium-tin-oxide (ITO), indium zinc oxide (IZO), aluminum.
  • a metal oxide such as indium-tin-oxide (ITO), indium zinc oxide (IZO), aluminum.
  • ITO indium-tin-oxide
  • IZO indium zinc oxide
  • ATO aluminum tin oxide
  • ATO aluminum zinc oxide
  • IGZO indium gallium zinc oxide
  • the stack is stacked, but the invention is not limited thereto.
  • the active device T is electrically connected to the scan line SL and the data line DL.
  • the active device T is, for example, a thin film transistor including a gate, a channel layer, a drain, and a source.
  • An insulating layer (not shown) is further covered on the gate of the active device T, which is also referred to as a gate insulating layer (GI), and the insulating layer electrically insulates the scan line SL and the data line DL.
  • the material of the insulating layer is, for example, an inorganic material, an organic material, or a combination thereof.
  • the inorganic material is, for example, a stacked layer including silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON) or at least two kinds of materials described above, but the invention is not limited thereto.
  • Figure 3A is a cross-sectional view of the pixel structure of Figure 2 taken along line A-A'.
  • the common electrode C of the pixel structure 10 is electrically insulated from the pixel electrode P.
  • the pixel electrode P includes a plurality of pixel electrode patterns P1, P2, P3.
  • the pixel electrode pattern P1 is directly disposed on the first substrate 100.
  • the film layer in which the pixel electrode pattern P1 is located is defined as the first layer
  • the film layer in which the pixel electrode patterns P2, P3 are located is defined as the second layer.
  • the common electrode C of the pixel structure 10 includes a plurality of common electrode patterns C1, C2, C3. As shown in FIG. 3A, the common electrode patterns C1 and C2 are located in the second layer similarly to the pixel electrode patterns P2 and P3, and the common electrode pattern C3 is located in the first layer in the same manner as the pixel electrode pattern P1. In the present embodiment, the first layer pixel electrode pattern P1 and the two second layer common electrode patterns C1, C2 constitute a first group of fringe electric field electrode groups ES1.
  • the first layer common electrode pattern C3 and the two second layer pixel electrode patterns P2, P3 constitute a second group of fringe electric field electrode groups ES2.
  • the present invention is not limited thereto.
  • the first set of edge electric field electrode groups ES1 may also be composed of the pixel electrode pattern P1 and the plurality of second layer common electrode patterns C1 and C2.
  • the second group The edge electric field electrode group ES2 can also be electrically connected by the common electrode pattern C3 and more second layer pixels.
  • the pole patterns P2 and P3 are formed.
  • the line width of the pixel electrode pattern P1 located in the first layer is LP1, and the line width of the common electrode pattern C3 located in the first layer is LC3.
  • the line width LP1 and the line width LC3 are, for example, greater than 0 and less than or equal to 30 ⁇ m, respectively.
  • the line widths of the pixel electrode patterns P2 and P3 located in the second layer are LP2 and LP3, and the line widths of the common electrode patterns C1 and C2 located in the second layer are LC1 and LC2.
  • the line widths LP2, LP3 and the line widths LC1, LC2 are, for example, greater than 0 and less than or equal to 10 [mu]m, respectively.
  • the pixel electrode pattern P2 has a distance SP between the adjacent pixel electrode patterns P3, and the common electrode pattern C1 has a distance SC between the adjacent common electrode patterns C2.
  • the distance SP and the distance SC are, for example, greater than 0 and less than or equal to 20 ⁇ m, respectively.
  • the distance between the pixel electrode pattern P2 also located in the second layer and the adjacent common electrode pattern C2 is SH.
  • the distance SH is, for example, greater than 0 and less than or equal to 30 ⁇ m.
  • Figure 3B is a schematic illustration of the electric field formed by the pixel structure of Figure 3A.
  • the fringe electric field FE1 can be formed between the first layer pixel electrode pattern P1 and the corresponding second layer common electrode pattern C1, C2.
  • a fringe electric field FE2 is formed between the first layer common electrode pattern C3 and the corresponding second layer pixel electrode patterns P2, P3.
  • a horizontal electric field HE can also be formed between the second layer pixel electrode pattern P2 and the adjacent second layer common electrode pattern C2.
  • the horizontal electric field HE may be formed between the first group of edge electric field electrode groups ES1 and the second group of edge electric field electrode groups ES2.
  • a plurality of horizontal electric fields HE may be formed in the same pixel structure 10 (for convenience of explanation, FIG. 3B only draws Show a horizontal electric field HE).
  • the first layer electrode pattern and the second layer electrode pattern are designed in a ratio of 1:2, and a fringe electric field with a ratio of 1:1 can be formed in the same pixel structure 10.
  • FE1 (or FE2) and the horizontal electric field HE, and the horizontal electric field HE may be formed in the vicinity of the second electrode layer close to the liquid crystal molecules, but the invention is not limited thereto.
  • the number ratio of the first layer electrode pattern to the second layer electrode pattern may be changed to adjust the number ratio and formation position of the fringe electric field FE1 (or FE2) to the horizontal electric field HE.
  • the first layer electrode pattern and the second layer electrode pattern can be designed in a ratio of 2:1, so that a fringe electric field FE1 (or FE2) and a horizontal electric field HE of a ratio of 1:1 can be formed, and
  • the horizontal electric field HE may be formed in the vicinity of the first electrode layer remote from the liquid crystal molecules.
  • Figure 4 is a cross-sectional view of the pixel structure of Figure 2 taken along line B-B'.
  • the pixel electrode P further includes the pixel electrode connection structure 110, but the invention is not limited thereto.
  • the pixel electrode connection structure 110 includes a first layer connection portion 112, a second layer connection portion 114, a first contact window 116, and a second contact window 118.
  • the first layer connection portion 112 is connected to the first layer pixel electrode pattern P1
  • the second layer connection portion 114 is connected to the second layer pixel electrode patterns P2, P3.
  • the pixel electrode P is electrically connected to the active device T.
  • the second layer of pixel electrode patterns P2 and P3 and the first layer of pixel electrode patterns P1 are electrically connected to the pixel electrode connection structure 110, and the active device T is electrically connected to the pixel electrode connection structure 110.
  • the first contact window 116 electrically connects the conductive layer 180 (the conductive layer 180, that is, the drain of the active device T) to the second layer connecting portion 114, and the second contact window 118 electrically connects the first layer connection portion 112 and the second layer connection portion 114 together.
  • FIG. 5 is a cross-sectional view of the pixel structure of Figure 2 taken along line D-D'.
  • the common electrode C further includes the common electrode connection structure 130, but the invention is not limited thereto.
  • the common electrode connection structure 130 includes a first layer connection portion 132, a second layer connection portion 134, and a contact window 136.
  • the second layer common electrode patterns C1 and C2 and the first layer common electrode pattern C3 are electrically connected to the common electrode connection structure 130, and the common electrode connection structure 130 is electrically connected to the common electrode line CL.
  • the first layer connection portion 132 is connected to the first layer common electrode pattern C3, and the second layer connection portion 134 is connected to the second layer common electrode patterns C1, C2.
  • the first layer connecting portion 132 is in direct contact with the common electrode line CL, but the present invention is not limited thereto.
  • an insulating layer may be disposed between the first layer connecting portion 132 and the common electrode line CL, and the first layer connecting portion 132 and the common electrode line CL are electrically connected to each other through the opening.
  • insulating layers 142 and 144 are disposed between the second layer connecting portion 134 and the first layer connecting portion 132. The second layer connecting portion 134 and the first layer connecting portion 132 are electrically connected to each other through the contact window 136.
  • the material of the insulating layers 142, 144 is, for example, an inorganic material, an organic material, or a combination thereof.
  • the inorganic material is, for example, a stacked layer including silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON) or at least two kinds of materials described above, but the invention is not limited thereto.
  • the pixel electrode patterns P1, P2, P3 and the common electrode patterns C1, C2, and C3 are linear electrode patterns. However, the present invention is not limited thereto. In other embodiments, the pixel electrode patterns P1, P2, and P3 and the common electrode patterns C1, C2, and C3 may have other shapes or patterns. Further, in the present embodiment, the pixel electrode patterns P1, P2, P3 and the common electrode patterns C1, C2, C3 are respectively parallel to the data line DL, but the present invention is not limited thereto.
  • Figure 6 is a top plan view of a pixel structure in accordance with a second embodiment of the present invention.
  • the pixel structure 20 shown in FIG. 6 includes a scan line SL, a data line DL, a common electrode line CL, an active device T, a pixel electrode P, and a common electrode C.
  • the same or similar elements of the pixel structure 20 of FIG. 6 and the pixel structure 10 of FIG. 2 are denoted by the same or similar symbols, and the description thereof will not be repeated.
  • Figure 7A is a cross-sectional view of the pixel structure of Figure 6 taken along line E-E'.
  • the difference between the pixel structure 20 and the pixel structure 10 of FIG. 2 is the number and arrangement of the pattern of the pixel electrode P and the common electrode C.
  • the pixel electrode P of the pixel structure 20 includes a plurality of pixel electrode patterns P1, P2, P3, and P4.
  • the pixel electrode pattern P1 is directly disposed on the first substrate 100.
  • the film layer in which the pixel electrode pattern P1 is located is defined as the first layer
  • the film layer in which the pixel electrode patterns P2, P3, P4 is located is defined as the second layer.
  • the common electrode C of the pixel structure 10 includes a plurality of common electrode patterns C1, C2, C3, and C4. As shown in FIG. 7A, the common electrode patterns C1, C2, and C3 are located in the second layer similarly to the pixel electrode patterns P2, P3, and P4, and the common electrode pattern C4 is located in the first layer as the pixel electrode pattern P1.
  • the first layer pixel electrode pattern P1 and the three second layer common electrode patterns C1, C2, and C3 constitute a first group of fringe electric field electrode groups ES1.
  • the common electrode pattern C4 and the three pixel electrode patterns P2, P3, and P4 constitute a second group of fringe electric field electrode groups ES2.
  • the line width of the pixel electrode pattern P1 located in the first layer is LP1, and the line width of the common electrode pattern C4 located in the first layer is LC4.
  • the line width LP1 and the line width LC4 are, for example, greater than 0 and less than or equal to 50 ⁇ m, respectively.
  • the line widths of the pixel electrode patterns P2, P3, and P4 located in the second layer are LP2, LP3, and LP4, and the line widths of the common electrode patterns C1, C2, and C3 located in the second layer are LC1, LC2, and LC3.
  • the line widths LP2, LP3, LP4 and the line widths LC1, LC2, LC3 are, for example, greater than 0 and less than or equal to 10 ⁇ m, respectively.
  • the pixel electrode pattern P3 has a distance SP1, SP2 between the adjacent pixel electrode patterns P2, P4, respectively, and the common electrode pattern C2 has a distance SC1, SC2 between the adjacent common electrode patterns C1, C3, respectively.
  • the above-described distances SP1, SP2 and the distances SC1, SC2 are, for example, greater than 0 and less than or equal to 20 ⁇ m, respectively.
  • the distance between the pixel electrode pattern P2 also located in the second layer and the adjacent common electrode pattern C2 is SH.
  • the distance SH is, for example, greater than 0 and less than or equal to 30 ⁇ m.
  • FIG. 7B is a schematic cross-sectional view of an electric field formed by the pixel structure of FIG. 7A.
  • the electrode can be shared between the first layer pixel electrode pattern P1 and the corresponding second layer.
  • Two fringe electric fields FE1 are formed between the patterns C1, C2, and C3.
  • two fringe electric fields FE2 may be formed between the first layer common electrode pattern C4 and the corresponding second layer pixel electrode patterns P2, P3, and P4. It is worth mentioning that between the second layer pixel electrode pattern P2 and the adjacent second layer common electrode pattern C3 (ie, between the first group of edge electric field electrode groups ES1 and the second group of edge electric field electrode groups ES2) A horizontal electric field HE is formed.
  • the first layer electrode pattern of the pixel electrode 20 and the second layer electrode pattern are designed in a ratio of 1:3, so that the same pixel structure 20 can be used.
  • a fringe electric field FE1 (or FE2) having a ratio of 2:1 and a horizontal electric field HE are formed, and a horizontal electric field HE may be formed in the vicinity of the second electrode layer close to the liquid crystal molecules, but the present invention is not limited thereto.
  • the number ratio of the first layer electrode pattern to the second layer electrode pattern may be changed to adjust the number ratio and formation position of the fringe electric field FE1 (or FE2) to the horizontal electric field HE.
  • the first layer electrode pattern and the second layer electrode pattern can be designed in a ratio of 3:1, so that a fringe electric field FE1 (or FE2) and a horizontal electric field HE in a ratio of 2:1 can be formed.
  • the horizontal electric field HE may be formed in the vicinity of the first electrode layer remote from the liquid crystal molecules.
  • Figure 8 is a cross-sectional view of the pixel structure of Figure 6 taken along line F-F'. 8 is similar to FIG. 4, and the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated.
  • the pixel electrode P of the pixel structure 20 further includes a pixel electrode connection structure 110.
  • the pixel electrode connection structure 110 includes a first layer connection portion 112, a second layer connection portion 114, a first contact window 116, and a second contact window 118.
  • the first layer connection portion 112 is connected to the first layer pixel electrode pattern P1
  • the second layer connection portion 114 is connected to the second layer pixel electrode patterns P2, P3, P4.
  • the pixel electrode P is electrically connected to the active device T.
  • the second layer of pixel electrode patterns P2, P3, and P4 and the first layer of pixel electrode patterns P1 are electrically connected to the pixel electrode connection structure 110, and the active device T is electrically connected to the pixel electrode connection structure 110.
  • Figure 9 is a cross-sectional view of the pixel structure of Figure 6 taken along line G-G'. 9 is similar to FIG. 5, and the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated.
  • the common electrode C further includes a common electrode connection structure 130.
  • the common electrode connection structure 130 includes a first layer connection portion 132, a second layer connection portion 134, and a contact window 136.
  • the second layer common electrode patterns C1, C2, C3 and the first layer common electrode pattern C4 are electrically connected to the common electrode connection structure 130.
  • the common electrode connection structure 130 is electrically connected to the common electrode line CL.
  • the first layer connection portion 132 is connected to the first layer common electrode pattern C3, and the second layer connection portion 134 is connected to the second layer common electrode patterns C1, C2, C3.
  • Figure 10 is a top plan view of a pixel structure in accordance with a third embodiment of the present invention.
  • the pixel structure 30 shown in FIG. 10 includes a scan line SL, a data line DL, a common electrode line CL, an active device T, a pixel electrode P, and a common electrode C.
  • the same or similar elements of the pixel structure 30 of FIG. 10 and the pixel structure 10 of FIG. 2 are denoted by the same or similar symbols, and the description thereof will not be repeated.
  • Figure 11A is a cross-sectional view of the pixel structure of Figure 10 taken along line H-H'.
  • the difference between the pixel structure 30 and the pixel structure 10 of FIG. 2 is the number and arrangement of the pattern of the pixel electrode P and the common electrode C.
  • the pixel electrode P of the pixel structure 30 includes a plurality of first layer pixel electrode patterns P1 and second layer pixel electrode patterns P2. As shown in FIG. 11A, the first layer pixel electrode pattern P1 is directly disposed on the first substrate 100. Similarly, insulating layers 142 and 144 are sequentially disposed between the second layer pixel electrode pattern P2 and the pixel electrode pattern P1.
  • the common electrode C of the pixel structure 30 includes a plurality of common electrode patterns C1, C2 located in the same film layer. As shown in FIG. 11A, the common electrode patterns C1, C2 and the second layer pixel electrode pattern P2 are located on the same film layer. Similarly, in the present embodiment, the first layer pixel electrode pattern P1 and the two common electrode patterns C1, C2 located in the second layer constitute a set of fringe electric field electrode groups ES.
  • the line width of the first layer pixel electrode pattern P1 is LP1.
  • the line width LP1 is, for example, greater than 0 and less than or equal to 30 ⁇ m.
  • the line width of the second layer pixel electrode pattern P2 is LP2, and the line widths of the common electrode patterns C1, C2 located in the second layer are LC1, LC2.
  • the line width LP2 and the line widths LC1, LC2 are, for example, greater than 0 and less than or equal to 10 ⁇ m, respectively.
  • the second layer pixel electrode pattern P2 has a distance SH1, SH2 between the adjacent second layer common electrode patterns C1, C2, respectively.
  • the distances SH1, SH2 are, for example, greater than 0 and less than or equal to 30 ⁇ m.
  • the common electrode pattern C1 has a distance SC from the adjacent common electrode pattern C2.
  • the distance SC is, for example, greater than 0 and less than or equal to 20 ⁇ m.
  • Figure 11B is a schematic cross-sectional view of the electric field formed by the pixel structure of Figure 11A.
  • the fringe electric field FE can be formed between the first layer pixel electrode pattern P1 and the corresponding second layer common electrode pattern C1, C2.
  • the edge electric field electrode group ES and the second layer pixel electrode pattern P2 on both sides thereof that is, between the second layer pixel electrode pattern P2 and the common electrode patterns C1 and C2, respectively
  • two Horizontal electric fields HE1, HE2 two Horizontal electric fields
  • the common electrode patterns C1 and C2 are designed only in the second layer, and the fringe electric field FE and the level of the ratio of 1:2 can be formed in the same pixel structure 30.
  • the electric fields HE1, HE2, and the horizontal electric fields HE1, HE2 are formed in the vicinity of the second electrode layer close to the liquid crystal molecules, but the present invention is not limited thereto.
  • the common electrode patterns C1, C2 may be designed only on the first layer of electrode layers, such that the horizontal electric fields HE1, HE2 may be formed in the vicinity of the first layer of electrode layers remote from the liquid crystal molecules.
  • the display panel 1000 composed of the pixel structure 30 of the present embodiment can have a low driving voltage and good liquid crystal efficiency and aperture ratio without increasing the process cost.
  • Figure 12 is a cross-sectional view of the pixel structure of Figure 10 taken along line I-I'. 12 is similar to FIG. 4, and the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated.
  • the pixel electrode P of the pixel structure 30 further includes a pixel electrode connection structure 110.
  • the pixel electrode connection structure 110 includes a first layer connection portion 112, a second layer connection portion 114, a first contact window 116, and a second contact window 118.
  • the first layer connection portion 112 is connected to the first layer pixel electrode pattern P1
  • the second layer connection portion 114 is connected to the second layer pixel electrode pattern P2.
  • the pixel electrode P is electrically connected to the active device T.
  • the second layer of the pixel electrode pattern P2 and the first layer of the pixel electrode pattern P1 are electrically connected to the pixel electrode connection structure 110, and the active device T is electrically connected to the pixel electrode connection structure 110.
  • Figure 13 is a cross-sectional view of the pixel structure of Figure 10 taken along line J-J'. 13 is similar to FIG. 5, and the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated.
  • the common electrode C further includes a common electrode connection structure 130.
  • the common electrode connection structure 130 includes a first layer connection portion 132, a second layer connection portion 134, and a contact window 136.
  • the common electrode patterns C1 and C2 are electrically connected to the common electrode connection structure 130.
  • the second layer connection portion 134 is electrically connected to the common electrode line CL through the contact window 136.
  • Figure 14 is a top plan view of a pixel structure in accordance with a fourth embodiment of the present invention.
  • the pixel structure 40 shown in FIG. 14 includes a scan line SL, a data line DL, a common electrode line CL, an active device T, a pixel electrode PE, and a common electrode CE.
  • the same or similar elements of the pixel structure 40 of FIG. 14 and the pixel structure 10 of FIG. 2 are denoted by the same or similar symbols, and the description thereof will not be repeated.
  • the main difference between the pixel structure 40 and the pixel structure 10 of FIG. 2 is the electrode pattern configuration of the pixel electrode PE and the common electrode CE.
  • the electrode patterns of the pixel electrode PE and the common electrode CE of the pixel structure 40 are arranged in a zigzag shape, and the pixel electrode patterns PE1, PE2, PE3 and the common electrode patterns CE1, CE2, and CE3 are not connected to the data line DL. parallel.
  • the present invention is not limited thereto, and in other embodiments, the pixel The structure can also have other electrode pattern configurations.
  • Figure 15A is a cross-sectional view of the pixel structure of Figure 14 taken along line K-K'.
  • the pixel electrode PE of the pixel structure 40 includes a plurality of first layer pixel electrode patterns PE1 and second layer pixel electrode patterns PE2, PE3.
  • the first layer pixel electrode pattern PE1 is directly disposed on the first substrate 100.
  • insulating layers 142 and 144 are sequentially disposed between the second layer pixel electrode patterns PE2 and PE3 and the pixel electrode pattern P1.
  • the common electrode CE of the pixel structure 40 includes a plurality of common electrode patterns CE1, CE2, CE3. As shown in FIG.
  • the common electrode patterns CE1 and CE2 are located in the second layer similarly to the pixel electrode patterns PE2 and PE3, and the common electrode pattern CE3 is located in the first layer as the pixel electrode pattern PE1.
  • the first layer pixel electrode pattern PE1 and the two second layer common electrode patterns CE1, CE2 constitute a first group of fringe electric field electrode groups ES11.
  • the first layer common electrode pattern CE3 and the two second layer pixel electrode patterns PE2, PE3 constitute a second group of fringe electric field electrode groups ES22.
  • the present invention is not limited thereto.
  • the first set of edge electric field electrode groups ES11 may also be composed of the pixel electrode pattern PE1 and the plurality of second layer common electrode patterns CE1, CE2, and likewise, the second set of edges
  • the electric field electrode group ES22 may be composed of the common electrode pattern CE3 and a plurality of second layer pixel electrode patterns PE2, PE3.
  • the line width of the first layer pixel electrode pattern PE1 is LPE1
  • the line width of the first layer common electrode pattern CE3 is LCE3.
  • the line width LPE1 and the line width LCE3 are, for example, greater than 0 and less than or equal to 30 ⁇ m, respectively.
  • the line widths of the second layer pixel electrode patterns PE2, PE3 are LPE2, LPE3, and the line widths of the second layer common electrode patterns CE1, CE2 are LCE1, LCE2.
  • the line widths LPE2, LPE3 and the line widths LCE1, LCE2 are, for example, greater than 0 and less than or equal to 10 [mu]m, respectively.
  • the second layer pixel electrode pattern PE2 has a distance SPE between the adjacent second layer pixel electrode patterns P3, and the distance SCE between the second layer common electrode pattern CE1 and the adjacent second layer common electrode pattern CE2.
  • the distance SPE and the distance SCE are, for example, greater than 0 and less than or equal to 20 ⁇ m, respectively.
  • the distance between the second layer pixel electrode pattern PE2 and the adjacent second layer common electrode pattern CE2 is SHE.
  • the distance SHE is, for example, greater than 0 and less than or equal to 30 ⁇ m.
  • Figure 15B is a schematic cross-sectional view of the electric field formed by the pixel structure of Figure 15A.
  • a fringe electric field FE1 can be formed between the first layer pixel electrode pattern PE1 and the corresponding second layer common electrode patterns CE1, CE2.
  • a fringe electric field FE2 may be formed between the first layer common electrode pattern CE3 and the corresponding second layer pixel electrode patterns PE2, PE3. It is worth mentioning that between the second layer pixel electrode pattern PE2 and the adjacent second layer common electrode pattern CE2 A horizontal electric field HE can also be formed.
  • the horizontal electric field HE may be formed between the first set of edge electric field electrode groups ES11 and the second set of fringe electric field electrode groups ES22. That is, in the pixel structure 40 of the present embodiment, in addition to forming a plurality of fringe electric fields FE1, FE2, a plurality of horizontal electric fields HE may be formed in the same pixel structure 40 (for convenience of explanation, FIG. 15B only draws Show a horizontal electric field HE).
  • the first layer electrode pattern and the second layer electrode pattern are designed in a ratio of 1:2, and a fringe electric field with a ratio of 1:1 can be formed in the same pixel structure 40.
  • FE1 (or FE2) and the horizontal electric field HE, and the horizontal electric field HE may be formed in the vicinity of the second electrode layer close to the liquid crystal molecules, but the invention is not limited thereto.
  • the number ratio of the first layer electrode pattern to the second layer electrode pattern may be changed to adjust the number ratio and formation position of the fringe electric field FE1 (or FE2) to the horizontal electric field HE.
  • the first layer electrode pattern and the second layer electrode pattern can be designed in a ratio of 2:1, so that a fringe electric field FE1 (or FE2) and a horizontal electric field HE of a ratio of 1:1 can be formed, and
  • the horizontal electric field HE may be formed in the vicinity of the first electrode layer remote from the liquid crystal molecules.
  • Figure 16 is a cross-sectional view of the pixel structure of Figure 14 taken along line L-L'.
  • the pixel electrode PE further includes a pixel electrode connection structure 210.
  • the pixel electrode connection structure 210 includes a first layer connection portion 212, a second layer connection portion 214, a first contact window 216, and a second contact window 218.
  • the pixel electrode connection structure 210 is similar to the pixel electrode connection structure 110 of the pixel structure of the above-described embodiment, and therefore the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated. Referring to FIG.
  • the first contact window 216 electrically connects the active device T (not shown) of the conductive layer 180 with the first layer connecting portion 212
  • the second contact window 218 connects the second layer connecting portion 214 . It is electrically connected to the first layer connection portion 212.
  • Figure 17 is a cross-sectional view of the pixel structure of Figure 14 taken along line M-M'.
  • the common electrode CE further includes a common electrode connection structure 230.
  • the common electrode connection structure 230 includes a first layer connection portion 232, a second layer connection portion 234, and a contact window 236.
  • the common electrode connection structure 230 is similar to the common electrode connection structure 130 of the pixel structure of the above-described embodiment, and therefore the same or similar elements are denoted by the same or similar symbols, and the description thereof will not be repeated.
  • the insulating layers 142 and 144 are disposed between the second layer connecting portion 234 and the first layer connecting portion 232.
  • the second layer connecting portion 234 and the first layer connecting portion 232 are electrically connected to each other through the contact window 236.
  • FIG. 18 is a top plan view of a pixel structure in accordance with a fifth embodiment of the present invention.
  • the illustrated pixel structure 50 includes a scan line SL, a data line DL, a common electrode line CL, an active device T, a pixel electrode P, and a common electrode C.
  • the same or similar elements of the pixel structure 50 of FIG. 18 and the pixel structure 10 of FIG. 2 are denoted by the same or similar symbols, and the description thereof will not be repeated.
  • the main difference between the pixel structure 50 and the pixel structure 10 of FIG. 2 lies in the shape of the electrode pattern.
  • the pixel electrode patterns P1, P2, and P3 and the common electrode patterns C1, C2, and C3 are linear electrode patterns compared to the pixel structure 10.
  • the pixel electrode patterns P1, P2, and P3 of the pixel structure 50 are shared.
  • the electrode patterns C1, C2, and C3 are U-shaped electrode patterns.
  • the pixel electrode of the pixel structure of the present invention includes a plurality of first layer pixel electrode patterns and a plurality of second layer pixel electrode patterns.
  • the common electrode of the pixel structure of the present invention also includes a plurality of common electrode patterns, which may be located in the same film layer or different film layers. There may be a fringe electric field between each pixel electrode pattern and a common electrode pattern of a corresponding different film layer.
  • each pixel electrode pattern may have a horizontal electric field between the common electrode patterns of adjacent identical film layers.
  • a liquid crystal driving mode having a horizontal electric field and a fringe electric field in the same pixel structure can be simultaneously provided, so that the FFS technology can be improved in a large size storage capacitor without increasing the process cost. Too large a problem, and can improve the liquid crystal efficiency of IPS technology is lower than FFS, the operating voltage is higher than FFS and requires extra space to design storage capacitors.

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