WO2016031381A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2016031381A1
WO2016031381A1 PCT/JP2015/068737 JP2015068737W WO2016031381A1 WO 2016031381 A1 WO2016031381 A1 WO 2016031381A1 JP 2015068737 W JP2015068737 W JP 2015068737W WO 2016031381 A1 WO2016031381 A1 WO 2016031381A1
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WO
WIPO (PCT)
Prior art keywords
bonding material
semiconductor chip
metal plate
intermediate member
semiconductor device
Prior art date
Application number
PCT/JP2015/068737
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French (fr)
Japanese (ja)
Inventor
卓矢 門口
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トヨタ自動車株式会社
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Publication date
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Publication of WO2016031381A1 publication Critical patent/WO2016031381A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the technology disclosed in this specification relates to a semiconductor device.
  • Patent Document 1 Japanese Unexamined Patent Publication No. 2010-258015 discloses a semiconductor device.
  • the semiconductor device of Patent Document 1 includes a metal electrode plate, a metal part formed on the surface of the metal electrode plate, and a semiconductor chip fixed to the metal part via solder.
  • an object of the present specification is to provide a technique capable of suppressing deformation of a semiconductor chip.
  • the semiconductor device disclosed in this specification includes a semiconductor chip, an intermediate member bonded to the semiconductor chip via a first bonding material, a metal plate bonded to the intermediate member via a second bonding material, It has.
  • a linear expansion coefficient of the intermediate member is larger than a linear expansion coefficient of the semiconductor chip and smaller than a linear expansion coefficient of the metal plate.
  • the rigidity of the first bonding material is greater than or equal to the rigidity of the second bonding material.
  • the semiconductor chip and the intermediate member are bonded by the first bonding material, and the intermediate member and the first metal plate are bonded by the second bonding material, the expansion amount of the semiconductor chip and the first metal plate The influence of the difference between the first bonding material and the second bonding material is dispersed through an intermediate member having an expansion amount intermediate between the two expansion amounts, and the strain is dispersed.
  • the rigidity of the 1st joining material which joins a semiconductor chip is more than the rigidity of a 2nd joining material, the restraining force by a 1st joining material becomes stronger than the restraining force by a 2nd joining material. Thereby, deformation of the semiconductor chip can be suppressed by the first bonding material.
  • the semiconductor device 1 includes a semiconductor chip 10, an intermediate member 30 bonded to the semiconductor chip 10 via a first bonding material 41, and a second bonding material 42 to the intermediate member 30.
  • the 1st metal plate 21 joined via this is provided.
  • the semiconductor device 1 includes a spacer 23 bonded to the semiconductor chip 10 via the third bonding material 43 and a second metal plate 22 bonded to the spacer 23 via the third bonding material 43.
  • the semiconductor device 1 includes a sealing resin 60 that seals the whole.
  • the semiconductor chip 10 is disposed between the first metal plate 21 and the second metal plate 22.
  • the back surface 102 of the semiconductor chip 10 is fixed to the first metal plate 21 via the first bonding material 41, the intermediate member 30, and the second bonding material 42.
  • the surface 101 of the semiconductor chip 10 is fixed to the second metal plate 22 via the third bonding material 43 and the spacer 23.
  • the semiconductor chip 10 has a configuration in which a semiconductor element is formed inside a semiconductor substrate.
  • a semiconductor element for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Semiconductor Field Field Effect Transistor) can be used.
  • IGBT Insulated Gate Bipolar Transistor
  • MOSFET Metal Oxide Semiconductor Semiconductor Field Field Effect Transistor
  • the semiconductor chip 10 is, for example, an IGBT, a gate region, an emitter region, a collector region, and the like are formed inside the semiconductor substrate (not shown).
  • silicon (Si) or silicon carbide (SiC) can be used as the material of the semiconductor substrate.
  • silicon carbide (SiC) is used as the material of the semiconductor substrate.
  • the Young's modulus of silicon (Si) is about 169 GPa.
  • the Young's modulus of silicon carbide (SiC) is about 450 GPa.
  • Silicon (Si) has a linear expansion coefficient of about 3 ppm / ° C.
  • Silicon carbide (SiC) has a linear expansion coefficient of about 5 ppm / ° C.
  • the linear expansion coefficient of the semiconductor chip 10 is smaller than the linear expansion coefficients of the intermediate member 30, the first metal plate 21, and the second metal plate 22.
  • the semiconductor chip 10 expands / contracts due to temperature changes.
  • the semiconductor chip 10 expands when the temperature increases and contracts when the temperature decreases.
  • the semiconductor chip 10 generates heat during operation.
  • the intermediate member 30 is formed in a plate shape.
  • the intermediate member 30 is disposed between the semiconductor chip 10 and the first metal plate 21.
  • a surface 301 of the intermediate member 30 is fixed to the semiconductor chip 10 via the first bonding material 41.
  • the back surface 302 of the intermediate member 30 is fixed to the first metal plate 21 via the second bonding material 42.
  • the plane area of the intermediate member 30 is larger than the plane area of the semiconductor chip 10 and smaller than the plane area of the first metal plate 21.
  • the end 303 of the intermediate member 30 is located outside the position of the end 103 of the semiconductor chip 10.
  • the end part 303 of the intermediate member 30 is located inside the position of the end part 213 of the first metal plate 21.
  • the intermediate member 30 is made of metal.
  • the material of the intermediate member 30 is different from the material of the first metal plate 21 and the second metal plate 22.
  • a material of the intermediate member 30 for example, CuMo and 42 Alloy can be used.
  • CuMo is used as the material of the intermediate member 30.
  • the Young's modulus of CuMo is about 280 GPa for 85Mo15Cu and about 170 GPa for 40Mo60Cu.
  • the Young's modulus of 42 Alloy is about 150 GPa.
  • the coefficient of linear expansion of CuMo is about 9 ppm / ° C.
  • the linear expansion coefficient of 42 Alloy is about 6 ppm / ° C.
  • the linear expansion coefficient of the intermediate member 30 is larger than the linear expansion coefficient of the semiconductor chip 10.
  • the linear expansion coefficient of the intermediate member 30 is smaller than the linear expansion coefficients of the first metal plate 21 and the second metal plate 22.
  • the linear expansion coefficient of the intermediate member 30 is a value between the linear expansion coefficient of the semiconductor chip 10 and the linear expansion coefficient of the first metal plate 21.
  • the intermediate member 30 expands / contracts due to temperature changes. The intermediate member 30 expands when the temperature increases and contracts when the temperature decreases.
  • the first metal plate 21 is disposed below the intermediate member 30.
  • the surface 211 of the first metal plate 21 is fixed to the intermediate member 30 via the second bonding material 42.
  • the back surface 212 (the surface opposite to the second bonding material 42 side) of the first metal plate 21 is exposed from the sealing resin 60.
  • the first cooler 71 is in contact with the back surface 212 of the first metal plate 21.
  • the planar area of the first metal plate 21 is larger than the planar area of the semiconductor chip 10 and the planar area of the intermediate member 30.
  • the end 213 of the first metal plate 21 is located outside the positions of the end 103 of the semiconductor chip 10 and the end 303 of the intermediate member 30.
  • the second metal plate 22 is disposed above the spacer 23.
  • a back surface 222 of the second metal plate 22 is fixed to the spacer 23 via a third bonding material 43.
  • the surface 221 of the second metal plate 22 (the surface opposite to the third bonding material 43 side) is exposed from the sealing resin 60.
  • a second cooler 72 is in contact with the surface 221 of the second metal plate 22.
  • the plane area of the second metal plate 22 is larger than the plane area of the semiconductor chip 10 and the plane area of the intermediate member 30.
  • the end 223 of the second metal plate 22 is located outside the end 103 of the semiconductor chip 10 and the end 303 of the intermediate member 30.
  • copper (Cu) can be aluminum (Al).
  • copper (Cu) is used as the material of the first metal plate 21 and the second metal plate 22.
  • the Young's modulus of copper (Cu) is about 124 GPa.
  • the Young's modulus of aluminum (Al) is about 70 GPa.
  • the linear expansion coefficient of copper (Cu) is about 17 ppm / ° C.
  • the linear expansion coefficient of aluminum (Al) is about 23 ppm / ° C.
  • the linear expansion coefficients of the first metal plate 21 and the second metal plate 22 are larger than the linear expansion coefficients of the semiconductor chip 10 and the intermediate member 30.
  • the first metal plate 21 and the second metal plate 22 expand / contract due to temperature changes.
  • the first metal plate 21 and the second metal plate 22 expand when the temperature increases, and contract when the temperature decreases.
  • the first metal plate 21 and the second metal plate 22 have thermal conductivity and conductivity.
  • the first metal plate 21 and the second metal plate 22 have a function of radiating heat generated in the semiconductor chip 10.
  • the 1st metal plate 21 and the 2nd metal plate 22 have a function as an electrode.
  • the spacer 23 is disposed between the semiconductor chip 10 and the second metal plate 22.
  • the back surface 232 of the spacer 23 is fixed to the semiconductor chip 10 via the third bonding material 43.
  • the surface 231 of the spacer 23 is fixed to the second metal plate 22 via the third bonding material 43.
  • the spacer 23 is formed in a plate shape.
  • the spacer 23 is made of metal.
  • copper (Cu) can be aluminum (Al).
  • the first bonding material 41 is filled between the semiconductor chip 10 and the intermediate member 30.
  • the first bonding material 41 joins the semiconductor chip 10 and the intermediate member 30.
  • the first bonding material 41 is in close contact with the semiconductor chip 10 and the intermediate member 30.
  • the plane area on the intermediate member 30 side of the first bonding material 41 is larger than the plane area on the semiconductor chip 10 side.
  • the second bonding material 42 is filled between the intermediate member 30 and the first metal plate 21.
  • the second bonding material 42 joins the intermediate member 30 and the first metal plate 21.
  • the second bonding material 42 is in close contact with the intermediate member 30 and the first metal plate 21.
  • the plane area on the first metal plate 21 side of the second bonding material 42 is larger than the plane area on the intermediate member 30 side.
  • the third bonding material 43 is filled between the semiconductor chip 10 and the spacer 23 and between the spacer 23 and the second metal plate 22.
  • the third bonding material 43 bonds the semiconductor chip 10 and the spacer 23, and the spacer 23 and the second metal plate 22.
  • the third bonding material 43 is in close contact with the semiconductor chip 10, the spacer 23 and the second metal plate 22.
  • the material of the first bonding material 41 for example, a CuSn compound, a NiSn compound, an Ag sintered body, a Zn-based solder, or the like can be used.
  • Cu3Sn, Cu6Sn5, etc. can be used as the CuSn compound.
  • Ni3Sn4 or the like can be used as the NiSn compound.
  • Ni 3 Sn 4 is used as the material of the first bonding material 41.
  • the Young's modulus of Cu3Sn is about 108 GPa.
  • the Young's modulus of Cu6Sn5 is about 86 GPa.
  • the Young's modulus of Ni3Sn4 is about 133 GPa.
  • the Young's modulus of the Ag sintered body is about 9 to 80 GPa.
  • the material of the second bonding material 42 and the third bonding material 43 for example, Sn solder, SnCu solder, Zn solder, or the like can be used.
  • the Young's modulus of Sn-based solder is about 42 GPa.
  • the Young's modulus of SnCu solder is about 50 GPa.
  • the rigidity of the first bonding material 41 is larger than the rigidity of the second bonding material 42.
  • the Young's modulus of the first bonding material 41 is larger than the Young's modulus of the second bonding material 42.
  • the displacement of the first bonding material 41 is smaller than the displacement of the second bonding material 42. That is, when the same force is applied to the first bonding material 41 and the second bonding material 42, the strain of the first bonding material 41 is smaller than the strain of the second bonding material 42.
  • the Young's modulus of the first bonding material 41 and the second bonding material 42 is smaller than the Young's modulus of the semiconductor chip 10.
  • the sealing resin 60 is filled between the first metal plate 21 and the second metal plate 22.
  • the sealing resin 60 is a member between the first metal plate 21 and the second metal plate 22 (semiconductor chip 10, intermediate member 30, spacer 23, first bonding material 41, second bonding material 42, and third bonding material. 43) is sealed.
  • the sealing resin 60 is in close contact with a member between the first metal plate 21 and the second metal plate 22.
  • an epoxy resin can be used as a main component.
  • the sealing resin 60 may include a curing agent, a stress relaxation agent, a curing accelerator, a filler, and the like.
  • the first cooler 71 is disposed below the first metal plate 21.
  • the first cooler 71 cools the semiconductor chip 10 via the first metal plate 21.
  • the second cooler 72 is disposed above the second metal plate 22.
  • the second cooler 72 cools the semiconductor chip 10 via the second metal plate 22.
  • a water-cooled configuration can be used as the first cooler 71 and the second cooler 72.
  • the back surface 102 of the semiconductor chip 10 is metallized using nickel (Ni). Thereby, a Ni film is formed on the back surface 102 of the semiconductor chip 10. Further, the surface 301 of the intermediate member 30 is plated using nickel (Ni). Thereby, a Ni film is formed on the surface 301 of the intermediate member 30.
  • an Sn-based solder paste 91 is disposed on the surface 301 of the intermediate member 30 on which the Ni film is formed, and the semiconductor chip 10 on which the Ni film is formed is disposed on the solder paste 91.
  • the whole is heat-treated.
  • the Ni film formed on the intermediate member 30 and the semiconductor chip 10 reacts with the Sn-based solder paste 91 to form the first bonding material 41 of the NiSn compound (Ni3Sn4). Further, the semiconductor chip 10 and the intermediate member 30 are bonded by the first bonding material 41.
  • an Sn-based solder paste 91 is disposed on the first metal plate 21, and the intermediate member 30 to which the semiconductor chip 10 is bonded is disposed on the solder paste 91.
  • An Sn-based solder paste 91 is disposed on the semiconductor chip 10, and the spacer 23 is disposed on the solder paste 91. Further, an Sn-based solder paste 91 is disposed on the spacer 23, and the second metal plate 22 is disposed on the solder paste 91.
  • the whole is heat-treated. Thereby, the solder paste 91 is heated and the second bonding material 42 and the third bonding material 43 are formed. Further, the intermediate member 30 and the first metal plate 21 are joined by the second joining material 42. Further, the semiconductor chip 10 and the spacer 23, and the spacer 23 and the second metal plate 22 are bonded by the third bonding material 43.
  • preform solder may be used.
  • the material joined in the above process is placed inside the mold 100 and resin is injected into the mold 100.
  • resin is injected into the mold 100.
  • a sealing resin 60 is formed.
  • the semiconductor device 1 is manufactured as described above.
  • the semiconductor chip 10 when the semiconductor chip 10 is energized, the semiconductor chip 10 generates heat and the temperature of the semiconductor device 1 rises. If it does so, the temperature of the semiconductor chip 10, the intermediate member 30, and the 1st metal plate 21 will rise, and each will expand
  • the semiconductor chip 10, the intermediate member 30, and the first metal plate 21 have different linear expansion coefficients and therefore have different expansion amounts. Due to the difference in expansion amount, the first bonding material between the semiconductor chip 10 and the intermediate member 30. 41 and the second bonding material 42 between the intermediate member 30 and the first metal plate 21 are distorted.
  • the intermediate member 30 is disposed between the semiconductor chip 10 and the first metal plate 21, and the intermediate member 30 is bonded to the semiconductor chip 10 via the first bonding material 41, and via the second bonding material 42. Since the first metal plate 21 is bonded to the intermediate member 30, the strain can be distributed to the first bonding material 41 and the second bonding material 42. That is, if the intermediate member 30 is not disposed between the semiconductor chip 10 and the first metal plate 21 and the semiconductor chip 10 and the first metal plate 21 are bonded by one type of bonding material, the semiconductor chip 10 The difference in expansion amount between the first metal plate 21 and the first metal plate 21 all affect one type of bonding material, and the strain cannot be dispersed.
  • the semiconductor chip 10 and the intermediate member 30 are bonded by the first bonding material 41, and the intermediate member 30 and the first metal plate 21 are bonded by the second bonding material 42.
  • the influence of the difference in expansion amount of the first metal plate 21 are dispersed in the first bonding material 41 and the second bonding material 42 via the intermediate member 30, and the strain is dispersed.
  • the rigidity of the first bonding material 41 for bonding the semiconductor chip 10 is larger than the rigidity of the second bonding material 42, the restraining force by the first bonding material 41 is stronger than the restraining force by the second bonding material 42.
  • transformation of the semiconductor chip 10 can be suppressed by the 1st joining material 41, and the lifetime of the semiconductor device 1 can be improved.
  • the second bonding material 42 since the restraining force by the second bonding material 42 is weaker than the restraining force by the first bonding material 41, the second bonding material 42 can follow the expansion of the first metal plate 21. Thereby, the crack of the 2nd joining material 42 can be suppressed and the lifetime of the semiconductor device 1 can be improved.
  • the Young's modulus of the first bonding material 41 is smaller than the Young's modulus of the semiconductor chip 10, the first bonding material 41 is more easily deformed than the semiconductor chip 10, and the semiconductor chip 10 is excessively restrained by the first bonding material 41. There is nothing to do. Thereby, the semiconductor chip 10 can be held moderately and damage to the semiconductor chip 10 can be suppressed. Further, since the plane area of the intermediate member 30 is larger than the plane area of the semiconductor chip 10, the bonding area of the first bonding material 41 can be increased. Thereby, the semiconductor chip 10 can be reliably joined to the intermediate member 30, and the lifetime of the semiconductor device 1 can be increased.
  • a plurality of through holes 36 may be formed in the intermediate member 30.
  • the through hole 36 extends along the direction from the first metal plate 21 toward the semiconductor chip 10.
  • the through hole 36 is located below the semiconductor chip 10.
  • the plurality of through holes 36 are formed at positions inside the position of the end portion 103 of the semiconductor chip 10.
  • the plurality of through holes 36 may be formed at both an inner position and an outer position than the position of the end portion 103 of the semiconductor chip 10.
  • the through hole 36 is filled with the second bonding material 42.
  • the second bonding material 42 filled in the through hole 36 is in close contact with the first bonding material 41. According to such a configuration, since the through hole 36 is formed in the intermediate member 30, the intermediate member 30 is easily deformed, and the strain of the second bonding material 42 can be reduced.
  • the number of through holes 36 formed in the intermediate member 30 is not particularly limited, and at least one through hole 36 may be formed in the intermediate member 30.
  • the plane area of the intermediate member 30 in plan view is larger than the plane area of the semiconductor chip 10, but the present invention is not limited to this configuration. In another embodiment, the plane area of the intermediate member 30 in plan view may be the same size as the plane area of the semiconductor chip 10.
  • the rigidity of the 1st joining material 41 was a structure larger than the rigidity of the 2nd joining material 42, it is not limited to this structure. In other embodiments, the rigidity of the first bonding material 41 may be the same as the rigidity of the second bonding material 42.
  • the Young's modulus of the 1st joining material 41 was a structure larger than the Young's modulus of the 2nd joining material 42, in another embodiment, the Young's modulus of the 1st joining material 41 is 1st. 2 It may be the same as the Young's modulus of the bonding material 42. In this case, the material of the 1st joining material 41 and the material of the 2nd joining material 42 can use the same material.
  • the rigidity of the first bonding material may be greater than or equal to the rigidity of the second bonding material.
  • the Young's modulus of the first bonding material may be greater than or equal to the Young's modulus of the second bonding material.
  • At least one through hole extending along a direction from the metal plate toward the semiconductor chip is formed in the intermediate member at a position inside the position of the end portion of the semiconductor chip. May be.
  • the Young's modulus of the first bonding material may be smaller than the Young's modulus of the semiconductor chip.
  • the plane area of the intermediate member may be larger than the plane area of the semiconductor chip.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

This semiconductor device 1 contains a semiconductor chip 10, an intermediate member 30 that is joined to said semiconductor chip 10 with a first joining material 41 interposed therebetween, and a first metal plate 21 that is joined to the intermediate member 30 with a second joining material 42 interposed therebetween. The coefficient of linear expansion of the intermediate member 30 is larger than that of the semiconductor chip 10 and smaller than that of the first metal plate 21. The stiffness of the first joining material 41 is greater than or equal to that of the second joining material 42.

Description

半導体装置Semiconductor device
　本明細書に開示の技術は、半導体装置に関する。 The technology disclosed in this specification relates to a semiconductor device.
　特許文献１（日本国特開２０１０－２５８０１５号公報）には半導体装置が開示されている。特許文献１の半導体装置は、金属電極板と、金属電極板の表面に形成された金属部と、金属部にはんだを介して固定された半導体チップとを備えている。 Patent Document 1 (Japanese Unexamined Patent Publication No. 2010-258015) discloses a semiconductor device. The semiconductor device of Patent Document 1 includes a metal electrode plate, a metal part formed on the surface of the metal electrode plate, and a semiconductor chip fixed to the metal part via solder.
　特許文献１の半導体装置では、温度の変化により金属電極板や金属部が膨張／収縮する。これにより、半導体チップが変形することがある。そこで本明細書は、半導体チップの変形を抑制できる技術を提供することを目的とする。 In the semiconductor device of Patent Document 1, the metal electrode plate and the metal part expand / contract due to a change in temperature. As a result, the semiconductor chip may be deformed. Therefore, an object of the present specification is to provide a technique capable of suppressing deformation of a semiconductor chip.
　本明細書に開示する半導体装置は、半導体チップと、前記半導体チップに第１接合材を介して接合された中間部材と、前記中間部材に第２接合材を介して接合された金属板と、を備えている。前記中間部材の線膨張係数が、前記半導体チップの線膨張係数より大きく、かつ、前記金属板の線膨張係数より小さい。前記第１接合材の剛性が、前記第２接合材の剛性以上である。 The semiconductor device disclosed in this specification includes a semiconductor chip, an intermediate member bonded to the semiconductor chip via a first bonding material, a metal plate bonded to the intermediate member via a second bonding material, It has. A linear expansion coefficient of the intermediate member is larger than a linear expansion coefficient of the semiconductor chip and smaller than a linear expansion coefficient of the metal plate. The rigidity of the first bonding material is greater than or equal to the rigidity of the second bonding material.
　このような構成によれば、半導体チップと中間部材が第１接合材により接合され、中間部材と第１金属板が第２接合材により接合されるので、半導体チップと第１金属板の膨張量の相違の影響が両者の膨張量の中間の膨張量の中間部材を介して第１接合材と第２接合材に分散され、ひずみが分散される。また、半導体チップを接合する第１接合材の剛性が第２接合材の剛性以上であるので、第１接合材による拘束力が第２接合材による拘束力よりも強くなる。これにより、第１接合材によって半導体チップの変形を抑制できる。 According to such a configuration, since the semiconductor chip and the intermediate member are bonded by the first bonding material, and the intermediate member and the first metal plate are bonded by the second bonding material, the expansion amount of the semiconductor chip and the first metal plate The influence of the difference between the first bonding material and the second bonding material is dispersed through an intermediate member having an expansion amount intermediate between the two expansion amounts, and the strain is dispersed. Moreover, since the rigidity of the 1st joining material which joins a semiconductor chip is more than the rigidity of a 2nd joining material, the restraining force by a 1st joining material becomes stronger than the restraining force by a 2nd joining material. Thereby, deformation of the semiconductor chip can be suppressed by the first bonding material.
半導体装置の断面図である。It is sectional drawing of a semiconductor device. 半導体装置の製造方法を説明する図である（１）。It is a figure explaining the manufacturing method of a semiconductor device (1). 半導体装置の製造方法を説明する図である（２）。It is a figure explaining the manufacturing method of a semiconductor device (2). 半導体装置の製造方法を説明する図である（３）。It is a figure explaining the manufacturing method of a semiconductor device (3). 他の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on other embodiment.
　以下、実施形態について添付図面を参照して説明する。実施形態に係る半導体装置１は、図１に示すように、半導体チップ１０と、半導体チップ１０に第１接合材４１を介して接合された中間部材３０と、中間部材３０に第２接合材４２を介して接合された第１金属板２１とを備えている。また、半導体装置１は、半導体チップ１０に第３接合材４３を介して接合されたスペーサ２３と、スペーサ２３に第３接合材４３を介して接合された第２金属板２２とを備えている。また、半導体装置１は、全体を封止する封止樹脂６０を備えている。 Hereinafter, embodiments will be described with reference to the accompanying drawings. As shown in FIG. 1, the semiconductor device 1 according to the embodiment includes a semiconductor chip 10, an intermediate member 30 bonded to the semiconductor chip 10 via a first bonding material 41, and a second bonding material 42 to the intermediate member 30. The 1st metal plate 21 joined via this is provided. In addition, the semiconductor device 1 includes a spacer 23 bonded to the semiconductor chip 10 via the third bonding material 43 and a second metal plate 22 bonded to the spacer 23 via the third bonding material 43. . In addition, the semiconductor device 1 includes a sealing resin 60 that seals the whole.
　半導体チップ１０は、第１金属板２１と第２金属板２２の間に配置されている。半導体チップ１０の裏面１０２が、第１接合材４１、中間部材３０、および第２接合材４２を介して第１金属板２１に固定されている。半導体チップ１０の表面１０１が、第３接合材４３およびスペーサ２３を介して第２金属板２２に固定されている。 The semiconductor chip 10 is disposed between the first metal plate 21 and the second metal plate 22. The back surface 102 of the semiconductor chip 10 is fixed to the first metal plate 21 via the first bonding material 41, the intermediate member 30, and the second bonding material 42. The surface 101 of the semiconductor chip 10 is fixed to the second metal plate 22 via the third bonding material 43 and the spacer 23.
　半導体チップ１０は、半導体基板の内部に半導体素子が形成された構成である。半導体チップ１０としては、例えばＩＧＢＴ（Insulated Gate Bipolar Transistor）やＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）を用いることができる。半導体チップ１０が例えばＩＧＢＴである場合、半導体基板の内部にはゲート領域、エミッタ領域、コレクタ領域などが形成されている（図示省略）。 The semiconductor chip 10 has a configuration in which a semiconductor element is formed inside a semiconductor substrate. As the semiconductor chip 10, for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Semiconductor Field Field Effect Transistor) can be used. When the semiconductor chip 10 is, for example, an IGBT, a gate region, an emitter region, a collector region, and the like are formed inside the semiconductor substrate (not shown).
　半導体チップ１０に用いる半導体基板の材質としては、例えばシリコン（Ｓｉ）や炭化ケイ素（ＳｉＣ）を用いることができる。本実施形態では、半導体基板の材質として炭化ケイ素（ＳｉＣ）を用いている。シリコン（Ｓｉ）のヤング率は、約１６９ＧＰａである。また、炭化ケイ素（ＳｉＣ）のヤング率は、約４５０ＧＰａである。また、シリコン（Ｓｉ）の線膨張係数は約３ｐｐｍ／℃である。炭化ケイ素（ＳｉＣ）の線膨張係数は約５ｐｐｍ／℃である。半導体チップ１０の線膨張係数は、中間部材３０、第１金属板２１、および第２金属板２２の線膨張係数より小さい。半導体チップ１０は、温度変化により膨張／収縮する。半導体チップ１０は、温度が上がると膨張し、温度が下がると収縮する。半導体チップ１０は、作動時に発熱する。 As the material of the semiconductor substrate used for the semiconductor chip 10, for example, silicon (Si) or silicon carbide (SiC) can be used. In the present embodiment, silicon carbide (SiC) is used as the material of the semiconductor substrate. The Young's modulus of silicon (Si) is about 169 GPa. Moreover, the Young's modulus of silicon carbide (SiC) is about 450 GPa. Silicon (Si) has a linear expansion coefficient of about 3 ppm / ° C. Silicon carbide (SiC) has a linear expansion coefficient of about 5 ppm / ° C. The linear expansion coefficient of the semiconductor chip 10 is smaller than the linear expansion coefficients of the intermediate member 30, the first metal plate 21, and the second metal plate 22. The semiconductor chip 10 expands / contracts due to temperature changes. The semiconductor chip 10 expands when the temperature increases and contracts when the temperature decreases. The semiconductor chip 10 generates heat during operation.
　中間部材３０は、板状に形成されている。中間部材３０は、半導体チップ１０と第１金属板２１の間に配置されている。中間部材３０の表面３０１が、第１接合材４１を介して半導体チップ１０に固定されている。中間部材３０の裏面３０２が、第２接合材４２を介して第１金属板２１に固定されている。各部材の積層方向に沿って平面視したときに、中間部材３０の平面積は、半導体チップ１０の平面積より大きく、第１金属板２１の平面積より小さい。中間部材３０の端部３０３は、半導体チップ１０の端部１０３の位置より外側に位置している。中間部材３０の端部３０３は、第１金属板２１の端部２１３の位置より内側に位置している。 The intermediate member 30 is formed in a plate shape. The intermediate member 30 is disposed between the semiconductor chip 10 and the first metal plate 21. A surface 301 of the intermediate member 30 is fixed to the semiconductor chip 10 via the first bonding material 41. The back surface 302 of the intermediate member 30 is fixed to the first metal plate 21 via the second bonding material 42. When viewed in plan along the stacking direction of each member, the plane area of the intermediate member 30 is larger than the plane area of the semiconductor chip 10 and smaller than the plane area of the first metal plate 21. The end 303 of the intermediate member 30 is located outside the position of the end 103 of the semiconductor chip 10. The end part 303 of the intermediate member 30 is located inside the position of the end part 213 of the first metal plate 21.
　中間部材３０は、金属により形成されている。中間部材３０の材質は、第１金属板２１および第２金属板２２の材質と異なる。中間部材３０の材質としては、例えばＣｕＭｏ、４２Ａｌｌｏｙを用いることができる。本実施形態では、中間部材３０の材質としてＣｕＭｏを用いている。ＣｕＭｏのヤング率は、８５Ｍｏ１５Ｃｕでは約２８０ＧＰａであり、４０Ｍｏ６０Ｃｕでは約１７０ＧＰａである。４２Ａｌｌｏｙのヤング率は、約１５０ＧＰａである。ＣｕＭｏの線膨張係数は、約９ｐｐｍ／℃である。また、４２Ａｌｌｏｙの線膨張係数は、約６ｐｐｍ／℃である。中間部材３０の線膨張係数は、半導体チップ１０の線膨張係数より大きい。中間部材３０の線膨張係数は、第１金属板２１、および第２金属板２２の線膨張係数より小さい。中間部材３０の線膨張係数は、半導体チップ１０の線膨張係数と第１金属板２１の線膨張係数との間の値である。中間部材３０は、温度変化により膨張／収縮する。中間部材３０は、温度が上がると膨張し、温度が下がると収縮する。 The intermediate member 30 is made of metal. The material of the intermediate member 30 is different from the material of the first metal plate 21 and the second metal plate 22. As a material of the intermediate member 30, for example, CuMo and 42 Alloy can be used. In this embodiment, CuMo is used as the material of the intermediate member 30. The Young's modulus of CuMo is about 280 GPa for 85Mo15Cu and about 170 GPa for 40Mo60Cu. The Young's modulus of 42 Alloy is about 150 GPa. The coefficient of linear expansion of CuMo is about 9 ppm / ° C. Moreover, the linear expansion coefficient of 42 Alloy is about 6 ppm / ° C. The linear expansion coefficient of the intermediate member 30 is larger than the linear expansion coefficient of the semiconductor chip 10. The linear expansion coefficient of the intermediate member 30 is smaller than the linear expansion coefficients of the first metal plate 21 and the second metal plate 22. The linear expansion coefficient of the intermediate member 30 is a value between the linear expansion coefficient of the semiconductor chip 10 and the linear expansion coefficient of the first metal plate 21. The intermediate member 30 expands / contracts due to temperature changes. The intermediate member 30 expands when the temperature increases and contracts when the temperature decreases.
　第１金属板２１は、中間部材３０の下方に配置されている。第１金属板２１の表面２１１が、第２接合材４２を介して中間部材３０に固定されている。第１金属板２１の裏面２１２（第２接合材４２側と反対側の面）は、封止樹脂６０から露出している。第１金属板２１の裏面２１２には、第１冷却器７１が接している。各部材の積層方向に沿って平面視したときに、第１金属板２１の平面積は、半導体チップ１０の平面積および中間部材３０の平面積より大きい。第１金属板２１の端部２１３は、半導体チップ１０の端部１０３および中間部材３０の端部３０３の位置より外側に位置している。 The first metal plate 21 is disposed below the intermediate member 30. The surface 211 of the first metal plate 21 is fixed to the intermediate member 30 via the second bonding material 42. The back surface 212 (the surface opposite to the second bonding material 42 side) of the first metal plate 21 is exposed from the sealing resin 60. The first cooler 71 is in contact with the back surface 212 of the first metal plate 21. When viewed in plan along the stacking direction of each member, the planar area of the first metal plate 21 is larger than the planar area of the semiconductor chip 10 and the planar area of the intermediate member 30. The end 213 of the first metal plate 21 is located outside the positions of the end 103 of the semiconductor chip 10 and the end 303 of the intermediate member 30.
　第２金属板２２は、スペーサ２３の上方に配置されている。第２金属板２２の裏面２２２が、第３接合材４３を介してスペーサ２３に固定されている。第２金属板２２の表面２２１（第３接合材４３側と反対側の面）は、封止樹脂６０から露出している。第２金属板２２の表面２２１には、第２冷却器７２が接している。平面視したときに、第２金属板２２の平面積は、半導体チップ１０の平面積および中間部材３０の平面積より大きい。第２金属板２２の端部２２３は、半導体チップ１０の端部１０３および中間部材３０の端部３０３より外側に位置している。 The second metal plate 22 is disposed above the spacer 23. A back surface 222 of the second metal plate 22 is fixed to the spacer 23 via a third bonding material 43. The surface 221 of the second metal plate 22 (the surface opposite to the third bonding material 43 side) is exposed from the sealing resin 60. A second cooler 72 is in contact with the surface 221 of the second metal plate 22. When viewed in plan, the plane area of the second metal plate 22 is larger than the plane area of the semiconductor chip 10 and the plane area of the intermediate member 30. The end 223 of the second metal plate 22 is located outside the end 103 of the semiconductor chip 10 and the end 303 of the intermediate member 30.
　第１金属板２１および第２金属板２２の材質としては、例えば銅（Ｃｕ）はアルミニウム（Ａｌ）を用いることができる。本実施形態では、第１金属板２１および第２金属板２２の材質として銅（Ｃｕ）を用いている。銅（Ｃｕ）のヤング率は、約１２４ＧＰａである。アルミニウム（Ａｌ）のヤング率は、約７０ＧＰａである。また、銅（Ｃｕ）の線膨張係数は、約１７ｐｐｍ／℃である。アルミニウム（Ａｌ）の線膨張係数は、約２３ｐｐｍ／℃である。第１金属板２１および第２金属板２２の線膨張係数は、半導体チップ１０および中間部材３０の線膨張係数より大きい。第１金属板２１および第２金属板２２は、温度変化により膨張／収縮する。第１金属板２１および第２金属板２２は、温度が上がると膨張し、温度が下がると収縮する。 As the material of the first metal plate 21 and the second metal plate 22, for example, copper (Cu) can be aluminum (Al). In the present embodiment, copper (Cu) is used as the material of the first metal plate 21 and the second metal plate 22. The Young's modulus of copper (Cu) is about 124 GPa. The Young's modulus of aluminum (Al) is about 70 GPa. Moreover, the linear expansion coefficient of copper (Cu) is about 17 ppm / ° C. The linear expansion coefficient of aluminum (Al) is about 23 ppm / ° C. The linear expansion coefficients of the first metal plate 21 and the second metal plate 22 are larger than the linear expansion coefficients of the semiconductor chip 10 and the intermediate member 30. The first metal plate 21 and the second metal plate 22 expand / contract due to temperature changes. The first metal plate 21 and the second metal plate 22 expand when the temperature increases, and contract when the temperature decreases.
　第１金属板２１および第２金属板２２は、熱伝導性および導電性を有している。第１金属板２１および第２金属板２２は、半導体チップ１０において生じた熱を放散する機能を有している。また、第１金属板２１および第２金属板２２は、電極としての機能を有している。 The first metal plate 21 and the second metal plate 22 have thermal conductivity and conductivity. The first metal plate 21 and the second metal plate 22 have a function of radiating heat generated in the semiconductor chip 10. Moreover, the 1st metal plate 21 and the 2nd metal plate 22 have a function as an electrode.
　スペーサ２３は、半導体チップ１０と第２金属板２２の間に配置されている。スペーサ２３の裏面２３２が、第３接合材４３を介して半導体チップ１０に固定されている。スペーサ２３の表面２３１が、第３接合材４３を介して第２金属板２２に固定されている。スペーサ２３は、板状に形成されている。スペーサ２３は、金属により形成されている。スペーサ２３の材質としては、例えば銅（Ｃｕ）はアルミニウム（Ａｌ）を用いることができる。 The spacer 23 is disposed between the semiconductor chip 10 and the second metal plate 22. The back surface 232 of the spacer 23 is fixed to the semiconductor chip 10 via the third bonding material 43. The surface 231 of the spacer 23 is fixed to the second metal plate 22 via the third bonding material 43. The spacer 23 is formed in a plate shape. The spacer 23 is made of metal. As a material of the spacer 23, for example, copper (Cu) can be aluminum (Al).
　第１接合材４１は、半導体チップ１０と中間部材３０の間に充填されている。第１接合材４１は、半導体チップ１０と中間部材３０を接合している。第１接合材４１は、半導体チップ１０と中間部材３０に密着している。第１接合材４１の中間部材３０側の平面積は、半導体チップ１０側の平面積より大きい。 The first bonding material 41 is filled between the semiconductor chip 10 and the intermediate member 30. The first bonding material 41 joins the semiconductor chip 10 and the intermediate member 30. The first bonding material 41 is in close contact with the semiconductor chip 10 and the intermediate member 30. The plane area on the intermediate member 30 side of the first bonding material 41 is larger than the plane area on the semiconductor chip 10 side.
　第２接合材４２は、中間部材３０と第１金属板２１の間に充填されている。第２接合材４２は、中間部材３０と第１金属板２１を接合している。第２接合材４２は、中間部材３０と第１金属板２１に密着している。第２接合材４２の第１金属板２１側の平面積は、中間部材３０側の平面積より大きい。 The second bonding material 42 is filled between the intermediate member 30 and the first metal plate 21. The second bonding material 42 joins the intermediate member 30 and the first metal plate 21. The second bonding material 42 is in close contact with the intermediate member 30 and the first metal plate 21. The plane area on the first metal plate 21 side of the second bonding material 42 is larger than the plane area on the intermediate member 30 side.
　第３接合材４３は、半導体チップ１０とスペーサ２３の間およびスペーサ２３と第２金属板２２の間に充填されている。第３接合材４３は、半導体チップ１０とスペーサ２３、および、スペーサ２３と第２金属板２２を接合している。第３接合材４３は、半導体チップ１０、スペーサ２３および第２金属板２２に密着している。 The third bonding material 43 is filled between the semiconductor chip 10 and the spacer 23 and between the spacer 23 and the second metal plate 22. The third bonding material 43 bonds the semiconductor chip 10 and the spacer 23, and the spacer 23 and the second metal plate 22. The third bonding material 43 is in close contact with the semiconductor chip 10, the spacer 23 and the second metal plate 22.
　第１接合材４１の材質としては、例えばＣｕＳｎ化合物、ＮｉＳｎ化合物、Ａｇ焼結体、Ｚｎ系はんだ等を用いることができる。ＣｕＳｎ化合物としては、Ｃｕ３Ｓｎ、Ｃｕ６Ｓｎ５等を用いることができる。ＮｉＳｎ化合物としては、Ｎｉ３Ｓｎ４等を用いることができる。本実施形態では、第１接合材４１の材質としてＮｉ３Ｓｎ４を用いている。Ｃｕ３Ｓｎのヤング率は、約１０８ＧＰａである。Ｃｕ６Ｓｎ５のヤング率は、約８６ＧＰａである。Ｎｉ３Ｓｎ４のヤング率は、約１３３ＧＰａである。Ａｇ焼結体のヤング率は、約９～８０ＧＰａである。 As the material of the first bonding material 41, for example, a CuSn compound, a NiSn compound, an Ag sintered body, a Zn-based solder, or the like can be used. Cu3Sn, Cu6Sn5, etc. can be used as the CuSn compound. Ni3Sn4 or the like can be used as the NiSn compound. In the present embodiment, Ni 3 Sn 4 is used as the material of the first bonding material 41. The Young's modulus of Cu3Sn is about 108 GPa. The Young's modulus of Cu6Sn5 is about 86 GPa. The Young's modulus of Ni3Sn4 is about 133 GPa. The Young's modulus of the Ag sintered body is about 9 to 80 GPa.
　第２接合材４２および第３接合材４３の材質としては、例えばＳｎ系はんだ、ＳｎＣｕ系はんだ、Ｚｎ系はんだ等を用いることができる。Ｓｎ系はんだのヤング率は、約４２ＧＰａである。ＳｎＣｕ系はんだのヤング率は、約５０ＧＰａである。 As the material of the second bonding material 42 and the third bonding material 43, for example, Sn solder, SnCu solder, Zn solder, or the like can be used. The Young's modulus of Sn-based solder is about 42 GPa. The Young's modulus of SnCu solder is about 50 GPa.
　第１接合材４１の剛性は、第２接合材４２の剛性より大きい。第１接合材４１のヤング率は、第２接合材４２のヤング率より大きい。第１接合材４１と第２接合材４２に同じ力が作用したときに、第１接合材４１の変位は、第２接合材４２の変位より小さい。すなわち、第１接合材４１と第２接合材４２に同じ力が作用したときに、第１接合材４１のひずみは、第２接合材４２のひずみより小さい。また、第１接合材４１および第２接合材４２のヤング率は、半導体チップ１０のヤング率より小さい。 The rigidity of the first bonding material 41 is larger than the rigidity of the second bonding material 42. The Young's modulus of the first bonding material 41 is larger than the Young's modulus of the second bonding material 42. When the same force is applied to the first bonding material 41 and the second bonding material 42, the displacement of the first bonding material 41 is smaller than the displacement of the second bonding material 42. That is, when the same force is applied to the first bonding material 41 and the second bonding material 42, the strain of the first bonding material 41 is smaller than the strain of the second bonding material 42. The Young's modulus of the first bonding material 41 and the second bonding material 42 is smaller than the Young's modulus of the semiconductor chip 10.
　封止樹脂６０は、第１金属板２１と第２金属板２２の間に充填されている。封止樹脂６０は、第１金属板２１と第２金属板２２の間の部材（半導体チップ１０、中間部材３０、スペーサ２３、第１接合材４１、第２接合材４２、および第３接合材４３）を封止している。封止樹脂６０は、第１金属板２１と第２金属板２２の間の部材に密着している。封止樹脂６０の材料としては、エポキシ樹脂を主成分として用いることができる。その他に、封止樹脂６０は、硬化剤、応力緩和剤、硬化促進剤、フィラー等を含んでいてもよい。 The sealing resin 60 is filled between the first metal plate 21 and the second metal plate 22. The sealing resin 60 is a member between the first metal plate 21 and the second metal plate 22 (semiconductor chip 10, intermediate member 30, spacer 23, first bonding material 41, second bonding material 42, and third bonding material. 43) is sealed. The sealing resin 60 is in close contact with a member between the first metal plate 21 and the second metal plate 22. As a material of the sealing resin 60, an epoxy resin can be used as a main component. In addition, the sealing resin 60 may include a curing agent, a stress relaxation agent, a curing accelerator, a filler, and the like.
　第１冷却器７１は、第１金属板２１の下方に配置されている。第１冷却器７１は、第１金属板２１を介して半導体チップ１０を冷却する。第２冷却器７２は、第２金属板２２の上方に配置されている。第２冷却器７２は、第２金属板２２を介して半導体チップ１０を冷却する。第１冷却器７１および第２冷却器７２としては、例えば水冷式の構成を用いることができる。 The first cooler 71 is disposed below the first metal plate 21. The first cooler 71 cools the semiconductor chip 10 via the first metal plate 21. The second cooler 72 is disposed above the second metal plate 22. The second cooler 72 cools the semiconductor chip 10 via the second metal plate 22. As the first cooler 71 and the second cooler 72, for example, a water-cooled configuration can be used.
　次に、半導体装置１の製造方法の一例について説明する。半導体装置１を製造するときは、まず、ニッケル（Ｎｉ）を用いて半導体チップ１０の裏面１０２をメタライズ処理する。これにより、半導体チップ１０の裏面１０２にＮｉ膜が形成される。また、ニッケル（Ｎｉ）を用いて中間部材３０の表面３０１をめっき処理する。これにより、中間部材３０の表面３０１にＮｉ膜が形成される。 Next, an example of a method for manufacturing the semiconductor device 1 will be described. When manufacturing the semiconductor device 1, first, the back surface 102 of the semiconductor chip 10 is metallized using nickel (Ni). Thereby, a Ni film is formed on the back surface 102 of the semiconductor chip 10. Further, the surface 301 of the intermediate member 30 is plated using nickel (Ni). Thereby, a Ni film is formed on the surface 301 of the intermediate member 30.
　次に、図２に示すように、Ｎｉ膜が形成された中間部材３０の表面３０１にＳｎ系のはんだペースト９１を配置し、はんだペースト９１の上にＮｉ膜が形成された半導体チップ１０を配置し、この状態で全体を加熱処理する。これにより、中間部材３０および半導体チップ１０に形成されたＮｉ膜とＳｎ系のはんだペースト９１とが反応して、ＮｉＳｎ化合物（Ｎｉ３Ｓｎ４）の第１接合材４１が形成される。また、半導体チップ１０と中間部材３０が、第１接合材４１により接合される。 Next, as shown in FIG. 2, an Sn-based solder paste 91 is disposed on the surface 301 of the intermediate member 30 on which the Ni film is formed, and the semiconductor chip 10 on which the Ni film is formed is disposed on the solder paste 91. In this state, the whole is heat-treated. As a result, the Ni film formed on the intermediate member 30 and the semiconductor chip 10 reacts with the Sn-based solder paste 91 to form the first bonding material 41 of the NiSn compound (Ni3Sn4). Further, the semiconductor chip 10 and the intermediate member 30 are bonded by the first bonding material 41.
　次に、図３に示すように、第１金属板２１の上にＳｎ系のはんだペースト９１を配置し、はんだペースト９１の上に半導体チップ１０が接合された中間部材３０を配置する。また、半導体チップ１０の上にＳｎ系のはんだペースト９１を配置し、はんだペースト９１の上にスペーサ２３を配置する。また、スペーサ２３の上にＳｎ系のはんだペースト９１を配置し、はんだペースト９１の上に第２金属板２２を配置し、この状態で全体を加熱処理する。これにより、はんだペースト９１が加熱されて第２接合材４２および第３接合材４３が形成される。また、中間部材３０と第１金属板２１が、第２接合材４２により接合される。また、半導体チップ１０とスペーサ２３、および、スペーサ２３と第２金属板２２が、第３接合材４３により接合される。なお、半導体装置１の製造方法においてはんだ付けを行うときには、プリフォームはんだを用いてもよい。 Next, as shown in FIG. 3, an Sn-based solder paste 91 is disposed on the first metal plate 21, and the intermediate member 30 to which the semiconductor chip 10 is bonded is disposed on the solder paste 91. An Sn-based solder paste 91 is disposed on the semiconductor chip 10, and the spacer 23 is disposed on the solder paste 91. Further, an Sn-based solder paste 91 is disposed on the spacer 23, and the second metal plate 22 is disposed on the solder paste 91. In this state, the whole is heat-treated. Thereby, the solder paste 91 is heated and the second bonding material 42 and the third bonding material 43 are formed. Further, the intermediate member 30 and the first metal plate 21 are joined by the second joining material 42. Further, the semiconductor chip 10 and the spacer 23, and the spacer 23 and the second metal plate 22 are bonded by the third bonding material 43. In addition, when performing soldering in the manufacturing method of the semiconductor device 1, preform solder may be used.
　次に、図４に示すように、上記の工程で接合されたものを金型１００の内部に配置し、金型１００の内部に樹脂を注入する。注入された樹脂が硬化すると、封止樹脂６０が形成される。以上のようにして、半導体装置１が製造される。 Next, as shown in FIG. 4, the material joined in the above process is placed inside the mold 100 and resin is injected into the mold 100. When the injected resin is cured, a sealing resin 60 is formed. The semiconductor device 1 is manufactured as described above.
　上記の構成を備える半導体装置１によれば、半導体チップ１０に通電すると半導体チップ１０が発熱して半導体装置１の温度が上がる。そうすると、半導体チップ１０、中間部材３０および第１金属板２１の温度が上がり、それぞれが膨張する。半導体チップ１０、中間部材３０および第１金属板２１では、それぞれの線膨張係数が異なるので膨張量が相違し、この膨張量の相違により、半導体チップ１０と中間部材３０の間の第１接合材４１および中間部材３０と第１金属板２１の間の第２接合材４２にひずみが生じる。このとき、半導体チップ１０と第１金属板２１の間に中間部材３０が配置され、第１接合材４１を介して中間部材３０が半導体チップ１０に接合されており、第２接合材４２を介して第１金属板２１が中間部材３０に接合されているため、第１接合材４１と第２接合材４２にひずみを分散できる。すなわち、もし半導体チップ１０と第１金属板２１の間に中間部材３０が配置されておらず、１種類の接合材により半導体チップ１０と第１金属板２１が接合されていると、半導体チップ１０と第１金属板２１の膨張量の相違が１種類の接合材に全て影響し、ひずみを分散することができない。しかしながら、上記の構成によれば、半導体チップ１０と中間部材３０が第１接合材４１により接合され、中間部材３０と第１金属板２１が第２接合材４２により接合されるので、半導体チップ１０と第１金属板２１の膨張量の相違の影響が中間部材３０を介して第１接合材４１と第２接合材４２に分散され、ひずみが分散される。また、半導体チップ１０を接合する第１接合材４１の剛性が第２接合材４２の剛性より大きいので、第１接合材４１による拘束力が第２接合材４２による拘束力よりも強くなる。これにより、第１接合材４１によって半導体チップ１０の変形を抑制でき、半導体装置１の寿命を高めることができる。また、第２接合材４２による拘束力が第１接合材４１による拘束力よりも弱いので、第２接合材４２が第１金属板２１の膨張に追従できる。これにより、第２接合材４２のクラックを抑制でき、半導体装置１の寿命を高めることができる。 According to the semiconductor device 1 having the above configuration, when the semiconductor chip 10 is energized, the semiconductor chip 10 generates heat and the temperature of the semiconductor device 1 rises. If it does so, the temperature of the semiconductor chip 10, the intermediate member 30, and the 1st metal plate 21 will rise, and each will expand | swell. The semiconductor chip 10, the intermediate member 30, and the first metal plate 21 have different linear expansion coefficients and therefore have different expansion amounts. Due to the difference in expansion amount, the first bonding material between the semiconductor chip 10 and the intermediate member 30. 41 and the second bonding material 42 between the intermediate member 30 and the first metal plate 21 are distorted. At this time, the intermediate member 30 is disposed between the semiconductor chip 10 and the first metal plate 21, and the intermediate member 30 is bonded to the semiconductor chip 10 via the first bonding material 41, and via the second bonding material 42. Since the first metal plate 21 is bonded to the intermediate member 30, the strain can be distributed to the first bonding material 41 and the second bonding material 42. That is, if the intermediate member 30 is not disposed between the semiconductor chip 10 and the first metal plate 21 and the semiconductor chip 10 and the first metal plate 21 are bonded by one type of bonding material, the semiconductor chip 10 The difference in expansion amount between the first metal plate 21 and the first metal plate 21 all affect one type of bonding material, and the strain cannot be dispersed. However, according to the above configuration, the semiconductor chip 10 and the intermediate member 30 are bonded by the first bonding material 41, and the intermediate member 30 and the first metal plate 21 are bonded by the second bonding material 42. And the influence of the difference in expansion amount of the first metal plate 21 are dispersed in the first bonding material 41 and the second bonding material 42 via the intermediate member 30, and the strain is dispersed. Further, since the rigidity of the first bonding material 41 for bonding the semiconductor chip 10 is larger than the rigidity of the second bonding material 42, the restraining force by the first bonding material 41 is stronger than the restraining force by the second bonding material 42. Thereby, the deformation | transformation of the semiconductor chip 10 can be suppressed by the 1st joining material 41, and the lifetime of the semiconductor device 1 can be improved. Further, since the restraining force by the second bonding material 42 is weaker than the restraining force by the first bonding material 41, the second bonding material 42 can follow the expansion of the first metal plate 21. Thereby, the crack of the 2nd joining material 42 can be suppressed and the lifetime of the semiconductor device 1 can be improved.
　また、第１接合材４１のヤング率が半導体チップ１０のヤング率より小さいので、第１接合材４１が半導体チップ１０よりも変形しやすく、半導体チップ１０が第１接合材４１により過度に拘束されることがない。これにより半導体チップ１０を適度に保持でき、半導体チップ１０の損傷を抑制できる。また、中間部材３０の平面積が半導体チップ１０の平面積より大きいので、第１接合材４１の接合面積を広くすることができる。これにより、半導体チップ１０を中間部材３０に確実に接合でき、半導体装置１の寿命を高めることができる。 Further, since the Young's modulus of the first bonding material 41 is smaller than the Young's modulus of the semiconductor chip 10, the first bonding material 41 is more easily deformed than the semiconductor chip 10, and the semiconductor chip 10 is excessively restrained by the first bonding material 41. There is nothing to do. Thereby, the semiconductor chip 10 can be held moderately and damage to the semiconductor chip 10 can be suppressed. Further, since the plane area of the intermediate member 30 is larger than the plane area of the semiconductor chip 10, the bonding area of the first bonding material 41 can be increased. Thereby, the semiconductor chip 10 can be reliably joined to the intermediate member 30, and the lifetime of the semiconductor device 1 can be increased.
　以上、一実施形態について説明したが、具体的な態様は上記実施形態に限定されるものではない。例えば、他の実施形態では、図５に示すように、中間部材３０に複数の貫通孔３６が形成されていてもよい。図５において、図１と同様の構成については同一の符号を付して説明を省略する。各貫通孔３６は、中間部材３０を厚さ方向に貫通している。貫通孔３６は、第１金属板２１から半導体チップ１０に向かう方向に沿って延びている。貫通孔３６は、半導体チップ１０の下方に位置している。複数の貫通孔３６は、半導体チップ１０の端部１０３の位置より内側の位置に形成されている。他の例では、複数の貫通孔３６は、半導体チップ１０の端部１０３の位置より内側の位置と外側の位置の両方に形成されていてもよい。貫通孔３６には、第２接合材４２が充填されている。貫通孔３６に充填された第２接合材４２は、第１接合材４１に密着している。このような構成によれば、中間部材３０に貫通孔３６が形成されているので、中間部材３０が変形しやすくなり、第２接合材４２のひずみを緩和できる。中間部材３０に形成される貫通孔３６の数は特に限定されるものではなく、少なくとも１つの貫通孔３６が中間部材３０に形成されていればよい。 As mentioned above, although one embodiment was described, a specific mode is not limited to the above-mentioned embodiment. For example, in another embodiment, as shown in FIG. 5, a plurality of through holes 36 may be formed in the intermediate member 30. In FIG. 5, the same components as those in FIG. Each through hole 36 penetrates the intermediate member 30 in the thickness direction. The through hole 36 extends along the direction from the first metal plate 21 toward the semiconductor chip 10. The through hole 36 is located below the semiconductor chip 10. The plurality of through holes 36 are formed at positions inside the position of the end portion 103 of the semiconductor chip 10. In another example, the plurality of through holes 36 may be formed at both an inner position and an outer position than the position of the end portion 103 of the semiconductor chip 10. The through hole 36 is filled with the second bonding material 42. The second bonding material 42 filled in the through hole 36 is in close contact with the first bonding material 41. According to such a configuration, since the through hole 36 is formed in the intermediate member 30, the intermediate member 30 is easily deformed, and the strain of the second bonding material 42 can be reduced. The number of through holes 36 formed in the intermediate member 30 is not particularly limited, and at least one through hole 36 may be formed in the intermediate member 30.
　また、上記実施形態では、平面視における中間部材３０の平面積が半導体チップ１０の平面積より大きかったが、この構成に限定されるものではない。他の実施形態では、平面視における中間部材３０の平面積が半導体チップ１０の平面積と同じ大きさであってもよい。 In the above embodiment, the plane area of the intermediate member 30 in plan view is larger than the plane area of the semiconductor chip 10, but the present invention is not limited to this configuration. In another embodiment, the plane area of the intermediate member 30 in plan view may be the same size as the plane area of the semiconductor chip 10.
　また、上記実施形態では、第１接合材４１の剛性が、第２接合材４２の剛性より大きい構成であったが、この構成に限定されるものではない。他の実施形態では、第１接合材４１の剛性が、第２接合材４２の剛性と同じであってもよい。また、上記実施形態では、第１接合材４１のヤング率が、第２接合材４２のヤング率より大きい構成であったが、他の実施形態では、第１接合材４１のヤング率が、第２接合材４２のヤング率と同じであってもよい。この場合、第１接合材４１の材質と第２接合材４２の材質は、同様の材質を用いることができる。 Moreover, in the said embodiment, although the rigidity of the 1st joining material 41 was a structure larger than the rigidity of the 2nd joining material 42, it is not limited to this structure. In other embodiments, the rigidity of the first bonding material 41 may be the same as the rigidity of the second bonding material 42. Moreover, in the said embodiment, although the Young's modulus of the 1st joining material 41 was a structure larger than the Young's modulus of the 2nd joining material 42, in another embodiment, the Young's modulus of the 1st joining material 41 is 1st. 2 It may be the same as the Young's modulus of the bonding material 42. In this case, the material of the 1st joining material 41 and the material of the 2nd joining material 42 can use the same material.
　以下、本明細書が開示する半導体装置の技術要素について説明する。なお、以下に記載する技術要素は、それぞれ独立した技術要素であって、単独であるいは各種の組合せによって技術的有用性を発揮するものである。 Hereinafter, technical elements of the semiconductor device disclosed in this specification will be described. Note that the technical elements described below are independent technical elements, and exhibit technical usefulness alone or in various combinations.
　本明細書が一例として開示する半導体装置では、第１接合材の剛性が第２接合材の剛性以上であってもよい。 In the semiconductor device disclosed in this specification as an example, the rigidity of the first bonding material may be greater than or equal to the rigidity of the second bonding material.
　本明細書が一例として開示する半導体装置では、第１接合材のヤング率が第２接合材のヤング率以上であってもよい。 In the semiconductor device disclosed in this specification as an example, the Young's modulus of the first bonding material may be greater than or equal to the Young's modulus of the second bonding material.
　本明細書が一例として開示する半導体装置では、半導体チップの端部の位置より内側の位置において、中間部材に、金属板から半導体チップに向かう方向に沿って延びる少なくとも１つの貫通孔が形成されていてもよい。 In the semiconductor device disclosed in this specification as an example, at least one through hole extending along a direction from the metal plate toward the semiconductor chip is formed in the intermediate member at a position inside the position of the end portion of the semiconductor chip. May be.
　本明細書が一例として開示する半導体装置では、第１接合材のヤング率が半導体チップのヤング率より小さくてもよい。中間部材の平面積が半導体チップの平面積より大きくてもよい。 In the semiconductor device disclosed in this specification as an example, the Young's modulus of the first bonding material may be smaller than the Young's modulus of the semiconductor chip. The plane area of the intermediate member may be larger than the plane area of the semiconductor chip.
　以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.
１　　：半導体装置
１０　：半導体チップ
２１　：第１金属板
２２　：第２金属板
２３　：スペーサ
３０　：中間部材
３６　：貫通孔
４１　：第１接合材
４２　：第２接合材
４３　：第３接合材
６０　：封止樹脂
７１　：第１冷却器
７２　：第２冷却器
９１　：はんだペースト
１００：金型 1: Semiconductor device 10: Semiconductor chip 21: 1st metal plate 22: 2nd metal plate 23: Spacer 30: Intermediate member 36: Through hole 41: 1st joining material 42: 2nd joining material 43: 3rd joining material 60 : Sealing resin 71: First cooler 72: Second cooler 91: Solder paste 100: Mold

Claims (4)

  1. 　半導体チップと、
    　前記半導体チップに第１接合材を介して接合された中間部材と、
    　前記中間部材に第２接合材を介して接合された金属板と、を備え、
    　前記中間部材の線膨張係数が、前記半導体チップの線膨張係数より大きく、かつ、前記金属板の線膨張係数より小さく、
    　前記第１接合材の剛性が前記第２接合材の剛性以上である、半導体装置。     A semiconductor chip;
    An intermediate member bonded to the semiconductor chip via a first bonding material;
    A metal plate joined to the intermediate member via a second joining material,
    The linear expansion coefficient of the intermediate member is larger than the linear expansion coefficient of the semiconductor chip and smaller than the linear expansion coefficient of the metal plate;
    A semiconductor device, wherein the rigidity of the first bonding material is equal to or higher than the rigidity of the second bonding material.
  2. 　前記第１接合材のヤング率が前記第２接合材のヤング率以上である、請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein a Young's modulus of the first bonding material is equal to or higher than a Young's modulus of the second bonding material.
  3. 　前記中間部材には、前記金属板から前記半導体チップに向かう方向に沿って延びる少なくとも１つの貫通孔が形成されている、請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the intermediate member is formed with at least one through hole extending along a direction from the metal plate toward the semiconductor chip.
  4. 　前記第１接合材のヤング率が前記半導体チップのヤング率より小さい、請求項１から３のいずれかに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein a Young's modulus of the first bonding material is smaller than a Young's modulus of the semiconductor chip.
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