WO2016031120A1 - Operational amplifier and charge amplifier using same - Google Patents

Abstract

The present invention provides a stable operational amplifier having an enhanced frequency characteristic and also provides a charge amplifier using the same. An operational amplifier comprises: first and second push-pull circuits (11), (12) connected in parallel between positive and negative power supply lines; first and second current/voltage conversion circuits (13), (14) to which the higher potential sides of the first and second push-pull circuits (11), (12) are connected and which are connected to the positive power supply line; third and fourth current/voltage conversion circuits (15), (16) to which the lower potential sides of the first and second push-pull circuits are connected and which are connected to the negative power supply line; a first output stage (17) to which the output sides of the first and third current/voltage conversion circuits are connected; a second output stage (18) to which the output sides of the second and fourth current/voltage conversion circuits are connected; and an final output stage (19) in which bipolar transistors having the same polarity are connected between the positive power supply line and the negative power supply line. An output from the first output stage is supplied to the base of the transistor on the higher potential side of the final output stage, while an output from the second output stage is supplied to the bases of the transistors on the lower potential side of the final output stage.

Description

Operational amplifier and charge amplifier using the same

The present invention relates to an operational amplifier capable of high-speed operation and a charge amplifier using the operational amplifier.

As sensors using the principle of measuring minute capacitance changes, there are various physical quantity sensors that detect various physical quantities using a MEMS (Micro Electro Mechanical System) structure that have been developed and studied in recent years.
The principle of the capacitance variable type physical quantity sensor is very simple. A weight and a minute spring supporting the weight are formed by a Si process or the like, and a fixed electrode is provided so as to face the weight. Since the weight is supported by the spring, it can move to some extent with respect to the external force, and when the external force is applied, the capacitance between the weight and the fixed electrode changes as a result. The principle of the capacitance variable physical quantity sensor using MEMS is to detect the displacement of the weight by reading this capacitance with a charge amplifier.

If the charge amplifier is configured using the operational amplifier to observe the capacitance change in this way, noise is reduced at a high frequency. Specifically, as an approximate trend, in order to improve the SN by one digit, it is necessary to increase the frequency by one digit. In other words, it is shown that a high SN can be achieved by adopting a circuit configuration capable of operating at a high frequency.

Current feedback operational amplifiers are known as operational amplifiers that can operate at high frequencies. This current feedback operational amplifier has a configuration shown in FIG. 10 when simplified. That is, it has a buffer BU in which complementary npn-type bipolar transistor Q101 and pnp-type bipolar transistor Q102 having emitters connected to each other are connected in series.

In the buffer BU, the collectors of the bipolar transistors Q101 and 102 are individually connected to the positive power supply line Lp and the negative power supply line Ln via the diodes D101 and D102 in the forward direction.
Two diodes D103 and D104 are connected in series in the forward direction between the bases of the bipolar transistors Q101 and Q102. Here, the anode of the diode D103 is connected to the constant current source CI101 connected to the positive power supply line Lp, and the cathode of the diode D104 is connected to the constant current source CI102 connected to the negative power supply line Ln.

A connection point between the cathode of the diode D103 and the anode of D104 is connected to the positive input terminal + tin. Further, the connection point between the emitters of the bipolar transistors Q101 and Q102 is connected to the negative side input terminal -tin.
Further, the connection point between the collector of the bipolar transistor Q101 of the buffer BU and the cathode of the diode D101 is connected to the base of a pnp bipolar transistor Q103 constituting the output stage. Similarly, the connection point between the collector of the bipolar transistor Q102 of the buffer BU and the anode of the diode D102 is connected to the base of an npn-type bipolar transistor Q104 constituting the output stage.

The collectors of the bipolar transistors Q103 and Q104 are connected to each other, the emitter of the bipolar transistor Q103 is connected to the positive power supply line Lp, and the emitter of the bipolar transistor Q104 is connected to the negative power supply line Ln.
Further, the connection point between the collectors of the bipolar transistors Q103 and Q104 is connected to the output terminal tout via the output stage buffer BA having a high impedance. A parallel circuit of a resistor R101 and a capacitor C101 is connected between a connection point between the collectors of the bipolar transistors Q103 and Q104 and between the input side of the output stage buffer BA and the ground.

Further, a load resistance R is connected between the negative side input terminal -tin and the ground, and a connection point between the load resistance R and the negative side input terminal -tin is connected to the output side of the output stage buffer BA via the feedback resistor Rf. To form a current feedback operational amplifier.
In this current feedback type operational amplifier, when the input voltage at the positive input terminal + tin increases, the increase in the current flowing into the load resistor R is folded as it is to increase the potential of the output stage buffer BA having a high impedance. When the potentials of the input terminals + tin and −tin become equal, the increase in current disappears, and the output is stabilized at that potential. In the current feedback operational amplifier, amplification is performed by switching the current, and the reason for the high speed is that the current of the bipolar transistor can be switched faster than the voltage.

By the way, as an operational amplifier that is applied to a charge amplifier that detects a minute change in capacitance, a stable operational amplifier that is fast and hardly oscillates is required.
For this purpose, for example, it is conceivable to apply the class AB push-pull drive circuit described in Patent Document 1 to an operational amplifier. As shown in FIG. 11, this class AB push-pull drive circuit uses two sets of the buffer BU shown in FIG. 10 described above, arranges these two sets of buffers BU1 and BU2 in parallel, and sets the buffer BU1. A connection point between the emitters of the bipolar transistors Q101 and Q102 and a connection point between the emitters of the bipolar transistors Q111 and Q112 of the buffer BU2 are connected to each other.

Then, the collectors of the bipolar transistors Q101 and Q111 of the buffers BU1 and BU2 are connected to the positive power supply line Lp through the current mirror circuits CM101 and CM103, respectively. The collectors of the bipolar transistors Q102 and Q112 of the buffers BU1 and BU2 are connected to the negative power supply line Ln through the current mirror circuits CM102 and CM104, respectively.

Further, the collectors of the output transistors Q105 and Q106 of the current mirror circuits CM101 and CM102 are connected to the positive output terminal + OUT, and the collectors of the output transistors Q107 and Q108 of the current mirror circuits 103 and Q104 are connected to the negative output terminal −OUT. Connecting.
Also, diode-connected pnp bipolar transistors Q109 and Q110 are connected between the bases of the bipolar transistors Q101 and Q102 of the buffer BU1, and the bases of the bipolar transistors Q109 and Q110 are connected to the positive input terminal + IN. Similarly, pnp-type bipolar transistors Q113 and Q114 that are diode-connected are connected between the bases of the bipolar transistors Q111 and Q112 of the buffer BU2, and the bases of the bipolar transistors Q113 and Q114 are connected to the negative-side input terminal −IN.

In this way, by configuring the operational amplifier as shown in FIG. 11, a class AB push-pull drive circuit can be configured. In this class AB push-pull drive circuit, the current I1 flowing into the emitter of the bipolar transistor Q101 constituting the buffer BU1 and the current I2 flowing out from the collector of the bipolar transistor Q102 increase and decrease exponentially and differentially. Similarly, the current I3 flowing into the emitter of the bipolar transistor Q111 constituting the buffer BU2 and the current I4 flowing out from the collector of the bipolar transistor Q112 increase and decrease exponentially and differentially. By inverting and adding the currents I1 and I2 and inverting and adding the currents I3 and I4, two types of class AB driving currents having a differential relationship with each other can be obtained from the output terminals + OUT and -OUT. In this case, a path difference related to signal amplification does not occur, the symmetry is good, a loop for class AB operation is not required, a phase difference between paths at high frequencies hardly occurs, and a stable class AB push-pull drive circuit is provided. Can be realized.

JP 07-249946 A

By the way, in the conventional class AB push-pull drive circuit described in Patent Document 1, a class AB push-pull operation can be performed while suppressing a phase difference between paths at high frequencies. As for the gain characteristic with respect to the frequency of the drive circuit, the frequency at which the gain increases in the negative direction from -3 dB is 18.5 MHz as shown by the broken line in FIG. On the other hand, the phase angle with respect to the frequency of the class AB push-pull drive circuit starts to decrease from 1 MHz as shown by the broken line in FIG. 6, and decreases by about −50 deg at 18.5 MHz. Here, since the phase angle is less than −180 deg, it is considered stable, so the upper limit of the operating frequency of the class AB push-pull drive circuit is limited to 18.5 MHz from the gain characteristic.

A charge amplifier that detects a minute capacitance change may require a frequency band higher than 18.5 MHz. In this case, when the operational amplifier is configured including the class AB push-pull drive circuit having the above configuration, there is an unsolved problem that the operating frequency exceeds the upper limit (18.5 MHz) of the frequency of the class AB push-pull drive circuit. .
Accordingly, the present invention has been made paying attention to the unsolved problems of the above-described conventional example, and an object thereof is to provide a stable operational amplifier having a higher frequency characteristic and a charge amplifier using the operational amplifier.

In order to achieve the above object, one aspect of an operational amplifier according to the present invention includes complementary first and second push-pull circuits connected in parallel between a positive power supply line and a negative power supply line, The first and second current-voltage conversion circuits connected to the positive power supply line by connecting the high potential sides of the first and second push-pull circuits, and the low potential sides of the first and second push-pull circuits. And third and fourth current-voltage conversion circuits connected to the negative power supply line. A first output stage to which the output sides of the first and third current-voltage converter circuits are connected; a second output stage to which the output sides of the second and fourth current-voltage converter circuits are connected; A final output stage having a push-pull circuit configuration by connecting bipolar transistors of the same polarity between the positive power supply line and the negative power supply line is provided. The output of the first output stage is supplied to the base of the high potential side bipolar transistor of the final output stage, and the output of the second output stage is supplied to the base of the low potential side bipolar transistor of the final output stage. Supply.
Moreover, one aspect of the charge amplifier according to the present invention uses the above-described operational amplifier as an operational amplifier constituting the integrating circuit.

According to one aspect of the present invention, one current-voltage conversion circuit is connected to each of the high-potential side and the low-potential side of the complementary first and second push-pull circuits, and is connected to the first push-pull circuit. Connecting the output sides of the two current-voltage conversion circuits connected to the first output stage, and connecting the output sides of the two current-voltage conversion circuits connected to the second push-pull circuit to the second output stage; By supplying the output sides of the first output stage and the second output stage to bipolar transistors of the same polarity that constitute the push-pull circuit of the final output stage, an operational amplifier that operates stably at a higher frequency is obtained. Can be configured.

Also, by configuring the charge amplifier using the operational amplifier having the above effect as the operational amplifier constituting the integration circuit, it is possible to reliably suppress the influence of external noise while ensuring the operation speed.

1 is a circuit diagram showing an example of an operational amplifier according to a first embodiment of the present invention. It is a characteristic diagram which shows the relationship between a bipolar transistor current and a voltage noise density when the electric current of a junction field effect transistor is 1 mA. It is a characteristic diagram which shows the relationship between a bipolar transistor current and a voltage noise density when the electric current of a junction field effect transistor is 10 mA. It is a circuit diagram which shows the modification of 1st Embodiment. FIG. 6 is a circuit diagram showing an embodiment in which the operational amplifier according to the first embodiment is applied to a charge amplifier according to the second embodiment of the present invention. 4 is a characteristic diagram showing frequency characteristics of the charge amplifiers of the present invention and the conventional example, where (a) is a gain characteristic diagram showing the relationship between frequency and gain, and (b) is a phase showing the relationship between frequency and phase angle. It is an angle characteristic diagram. It is a characteristic diagram which shows the power supply voltage dependence characteristic by the presence or absence of a cascode transistor. It is a circuit diagram which shows an example of the operational amplifier by the 3rd Embodiment of this invention. It is a circuit diagram which shows the modification of 3rd Embodiment. It is a circuit diagram which shows the prior art example used as the basis of an operational amplifier. It is a circuit diagram which shows the conventional operational amplifier.

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.
Further, the following embodiments exemplify devices for embodying the technical idea of the present invention, and the technical idea of the present invention is the material, shape, structure, arrangement, etc. of the component parts. Is not specified as follows. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

First, a first embodiment of an operational amplifier that represents one aspect of the present invention will be described.
The operational amplifier 1 has a first current-voltage conversion circuit 13 and a second current-voltage conversion circuit in which the high potential side of the first push-pull circuit 11 and the second push-pull circuit 12 arranged in parallel with the positive power supply line Lp. 14 is connected. Further, the low potential side of the first push-pull circuit 11 and the second push-pull circuit 12 is connected to the negative power supply line Ln through the third current-voltage conversion circuit 15 and the fourth current-voltage conversion circuit 16. .

In addition, a connection point between the first push-pull circuit 11 and the first current-voltage conversion circuit 13 and a connection point between the first push-pull circuit 11 and the third current-voltage conversion circuit 15 are individually provided. Are connected to the first output stage 17. Further, the connection point between the second push-pull circuit 12 and the second current-voltage conversion circuit 14 and the connection point between the second push-pull circuit 12 and the fourth current-voltage conversion circuit 16 are individually set. Are connected to the second output stage 18.

Further, the output side of the first output stage 17 and the output side of the second output stage 18 are connected to the final output stage 19.
The first push-pull circuit 11 includes an npn bipolar transistor Q11 and a pnp bipolar transistor Q12 whose emitters are connected to each other. The collector of the npn-type bipolar transistor Q11 is connected to the first current-voltage conversion circuit 13, and the collector of the pnp-type bipolar transistor Q12 is connected to the third current-voltage conversion circuit 15.

Further, the base of the npn type bipolar transistor Q11 and the base of the pnp type bipolar transistor Q12 are connected to the bias circuit 21 to constitute a class B push-pull circuit.
The bias circuit 21 includes an npn-type bipolar transistor Q13 and a pnp-type bipolar transistor Q14 that operate as diodes connected by connecting a collector and a base, respectively. The collector of npn-type bipolar transistor Q13 is connected to positive power supply line Lp via npn-type bipolar transistor Q16 cascode-connected to first n-channel junction field-effect transistor Q15, and the base of npn-type bipolar transistor Q11 It is connected to the.

The collector of the pnp bipolar transistor Q14 is connected to the negative power supply line Ln via the current mirror circuit 22, and is also connected to the base of the pnp bipolar transistor Q12.
The base of npn bipolar transistor Q13 is connected to the connection point between the collector of npn bipolar transistor Q13 and the base of npn bipolar transistor Q11. Similarly, the base of the pnp bipolar transistor Q14 is connected to the connection point between the collector of the pnp bipolar transistor Q14 and the base of the pnp bipolar transistor Q12.

The positive input terminal + tin is connected to the gate of the first n-channel junction field effect transistor Q15. In addition, a power supply circuit 23 is connected to a base which becomes a control terminal of the cascode-connected npn bipolar transistor Q16, and the power supply circuit 23 sets the base potential of the npn bipolar transistor Q16 to an intermediate potential between the ground potential and the power supply potential. Is set.

The second push-pull circuit 12 has the same configuration as the first push-pull circuit 11 described above, and has an npn-type bipolar transistor Q21 and a pnp-type bipolar transistor Q22 whose emitters are connected to each other. The collector of the npn-type bipolar transistor Q21 is connected to the positive power supply line Lp via the second current-voltage conversion circuit 14. The collector of the pnp bipolar transistor Q22 is connected to the negative power supply line Ln via the fourth current-voltage conversion circuit 16.

Further, the base of the npn-type bipolar transistor Q21 and the base of the pnp-type bipolar transistor Q22 are connected to the bias circuit 24 to constitute a class B push-pull circuit.
The bias circuit 24 includes an npn bipolar transistor Q23 and a pnp bipolar transistor Q24 that operate as diodes.
The collector of npn-type bipolar transistor Q23 is connected to positive power supply line Lp via npn-type bipolar transistor Q26 cascode-connected to second n-channel junction field-effect transistor Q25, and the base of npn-type bipolar transistor Q21 It is connected to the.
The collector of the pnp bipolar transistor Q24 is connected to the negative power supply line Ln via the current mirror circuit 22, and is also connected to the base of the pnp bipolar transistor Q22.
The base of npn bipolar transistor Q23 is connected to the connection point between the collector of npn bipolar transistor Q23 and the base of npn bipolar transistor Q21.
Similarly, the base of the pnp bipolar transistor Q24 is connected to the connection point between the collector of the pnp bipolar transistor Q24 and the base of the pnp bipolar transistor Q22.

The connection point between the emitters of the npn-type bipolar transistor Q11 and the pnp-type bipolar transistor Q12 of the first push-pull circuit 11, and the emitters of the npn-type bipolar transistor Q21 and the pnp-type bipolar transistor Q22 of the second push-pull circuit 12 are used. A connection point between them is connected via an emitter connection resistor Re.
The negative input terminal -tin is connected to the gate of the second junction field effect transistor Q25. Further, a power supply circuit 23 is connected to the base of the cascode-connected npn bipolar transistor Q26, and the power supply circuit 23 fixes the base potential of the npn bipolar transistor Q26 to an intermediate potential between the ground potential and the power supply potential. .

Note that the fixed potential of the cascode-connected npn-type bipolar transistors Q16 and Q26 is at least Vth + 1V in consideration of the operation (threshold voltage: Vth) of the n-channel junction field effect transistors Q15 and Q25. The upper limit voltage is set to ensure the power supply voltage -1V.
The first current-voltage conversion circuit 13 includes a pnp bipolar transistor Q31 having an emitter connected to the positive power supply line Lp and a collector connected to the first push-pull circuit 11. The collector and base of the pnp bipolar transistor Q31 are connected, and these connection points are connected to the first output stage 17 to constitute a current mirror circuit as will be described later.

The second current-voltage conversion circuit 14 includes a pnp bipolar transistor Q32 having an emitter connected to the positive power supply line Lp and a collector connected to the second push-pull circuit 12. The collector and base of the pnp bipolar transistor Q32 are connected, and these connection points are connected to the second output stage 18 to constitute a current mirror circuit as will be described later.

The third current-voltage conversion circuit 15 includes an npn-type bipolar transistor Q33 having an emitter connected to the negative power supply line Ln and a collector connected to the first push-pull circuit 11. The base and collector of the npn-type bipolar transistor Q33 are connected, and these connection points are connected to the first output stage 17 to constitute a current mirror circuit as will be described later.

The fourth current-voltage conversion circuit 16 includes an npn-type bipolar transistor Q34 having an emitter connected to the negative power supply line Ln and a collector connected to the second push-pull circuit 12. The base and collector of the npn-type bipolar transistor Q34 are connected, and these connection points are connected to the second output stage 18 to constitute a current mirror circuit as will be described later.

The current mirror circuit 22 includes an npn-type bipolar transistor Q35 interposed between the constant current source 31 and the negative power supply line Ln, an npn-type bipolar transistor Q36 having a base connected to the base of the npn-type bipolar transistor Q35, and Q37.
The npn-type bipolar transistor Q35 has a collector and a base connected to the constant current source 31, and an emitter connected to the negative power supply line Ln.

The npn bipolar transistor Q36 has a base connected to the base of the npn bipolar transistor Q35, and a collector connected to the base of the pnp bipolar transistor Q12 of the first push-pull circuit 11 and the collector and base of the pnp bipolar transistor Q14. The emitter is connected to the negative power supply line Ln.
The base of the npn bipolar transistor Q37 is connected to the base of the npn bipolar transistor Q35, and the collector is connected to the base of the pnp bipolar transistor Q22 of the second push-pull circuit 12 and the collector and base of the pnp bipolar transistor Q24. The emitter is connected to the negative power supply line Ln.

The first output stage 17 includes a pnp bipolar transistor Q41 having an emitter connected to the positive power supply line Lp, an npn having a collector connected to the collector of the pnp bipolar transistor Q41, and an emitter connected to the negative power supply line Ln. Type bipolar transistor Q42.
The base of the pnp bipolar transistor Q41 is connected to the connection point between the base and the collector of the pnp bipolar transistor Q31 of the first current-voltage conversion circuit 13, thereby forming a first current mirror circuit. In other words, the input side circuit of the first current mirror circuit constitutes the first current-voltage conversion circuit 13.
Further, the base of the npn-type bipolar transistor Q42 is connected to the connection point between the base and the collector of the npn-type bipolar transistor Q33 of the third current-voltage conversion circuit 15 to constitute a third current mirror circuit. In other words, the input current circuit of the third current mirror circuit constitutes the third current-voltage conversion circuit 15.

Similarly to the first output stage 17, the second output stage 18 also has a pnp bipolar transistor Q43 having an emitter connected to the positive power supply line Lp, a collector connected to the collector of the pnp bipolar transistor Q43, and an emitter. The npn bipolar transistor Q44 is connected to the negative power supply line Ln.
The base of the pnp bipolar transistor Q43 is connected to the connection point between the base and collector of the pnp bipolar transistor Q32 of the second current-voltage conversion circuit 14, thereby forming a second current mirror circuit. In other words, the input side circuit of the second current mirror circuit constitutes the second current-voltage conversion circuit 14.
Further, the base of the npn-type bipolar transistor Q44 is connected to the connection point between the base and the collector of the npn-type bipolar transistor Q34 of the fourth current-voltage conversion circuit 16, thereby forming a fourth current mirror circuit. In other words, the input current circuit of the fourth current mirror circuit constitutes the fourth current-voltage conversion circuit 16.

In the final output stage 19, two npn bipolar transistors Q51 and Q52 are connected in series between the positive power supply line Lp and the negative power supply line Ln by connecting the emitter of the npn bipolar transistor Q51 to the collector of the npn bipolar transistor Q52. It has the structure made.
The base of the npn bipolar transistor Q51 on the high potential side is connected to the output terminal serving as a connection point between the pnp bipolar transistor Q41 and the npn bipolar transistor Q42 in the first output stage 17.
In addition, the base of the npn bipolar transistor Q52 on the low potential side is connected to the output terminal serving as a connection point between the pnp bipolar transistor Q43 and the npn bipolar transistor Q44 of the second output stage 18.
Further, an output terminal tout is connected to a connection point between both npn-type bipolar transistors Q51 and Q52.

Further, a connection point between the base of the npn type bipolar transistor Q52 on the low potential side and the output terminal serving as a connection point of the pnp type bipolar transistor Q43 and the npn type bipolar transistor Q44 of the second output stage 18 and the negative power supply line Ln. An npn bipolar transistor Q53 is connected between them. The npn bipolar transistor Q53 has a collector connected to the output terminal of the second output stage 18 and the connection point of the npn bipolar transistor Q52, and an emitter connected to the negative power supply line Ln. The base of the npn-type bipolar transistor Q53 is connected to the connection point between the output terminal of the second output stage 18 and the base of the npn-type bipolar transistor Q52 to constitute a constant current circuit. It should be noted that phase compensation capacitors C5 and C6 are connected between npn-type bipolar transistors Q51 and Q52 between collectors and bases for preventing deterioration of the high frequency characteristics of the operational amplifier.

Further, a capacitor C7 for suppressing noise is connected between a connection point between the npn bipolar transistor Q23 and the junction field effect transistor Q25 in the second push-pull circuit 12 and a connection point between the output terminal tout of the final output stage 19. Has been.
At least the first push-pull circuit 11, the second push-pull circuit 12, the first current-voltage conversion circuit 13 to the fourth current-voltage conversion circuit 16, the first output stage 17 and the second output stage 18. The current output differential amplifier includes the final output stage 19, the junction field effect transistors Q15 and Q25, and the current mirror circuit 22.

Next, the operation of the first embodiment will be described.
In the first embodiment, the collector currents of the first push-pull circuit 11 and the second push-pull circuit 12 using complementary bipolar transistors Q11, Q12 and Q21, Q22 are used as the first current-voltage conversion circuit 13, respectively. The second current-voltage conversion circuit 14, the third current-voltage conversion circuit 15, and the fourth current-voltage conversion circuit 16 have a folded structure. Therefore, when the voltage at the positive input terminal + tin rises, the increase in current flowing into the emitter connection resistor Re is turned back as it is, and the buffers (Q41, Q42 and Q43 of the first output stage 17 and the second output stage 18). And the potential of Q44) is increased.

When the potentials of the positive side input terminal + tin and the negative side input terminal -tin become equal, the increase in current disappears, and the output is stabilized at that potential. In this embodiment, amplification is performed by switching the current, and the current of the bipolar transistor can be switched faster than the voltage, so that high-speed operation is possible.
At this time, the first push-pull circuit 11 and the second push-pull circuit 12 are provided, and these are used as a current path, thereby realizing a current feedback operational amplifier.
Four transistors Q11, Q12 and Q21, Q22 connected by an emitter connection resistor Re, a first current-voltage conversion circuit 13, a second current-voltage conversion circuit 14 and a third current-voltage conversion circuit arranged on the power supply side Since the first current mirror circuit to the fourth current mirror circuit constituted by the 15 and fourth current-voltage conversion circuit 16 and the first output stage 17 and the second output stage 18 are operated in current. It is very fast. Since the voltage is finally converted by the bipolar transistors Q51 and Q52 of the final output stage 19, the speed is limited in this portion. However, the area and the bias current of each bipolar transistor Q51 and Q52 are optimally set so that the speed is high. Amplification is possible.

In this way, the first push-pull circuit 11 and the second push-pull circuit 12 drive the npn-type bipolar transistors Q51 and Q52 of the final output stage 19 through the first output stage 17 and the second output stage 18. Therefore, a large driving force can be obtained as an operational amplifier, and the speed can be increased.
By connecting the input terminals + tin and −tin to the gates of the n-channel junction field effect transistors Q15 and Q25, the input impedance can be increased, and the first push-pull circuit 11 and the bipolar transistor can be used. Second push-pull circuit 12, first current-voltage conversion circuit 13, second current-voltage conversion circuit 14, third current-voltage conversion circuit 15, fourth current-voltage conversion circuit 16, first output stage 17 By configuring the second output stage 18 and the final output stage 19, it is possible to configure a current feedback operational amplifier with almost no loss in high-speed performance.

In order to realize a high SN, it is important to reduce the noise of the operational amplifier itself. For that purpose, it is important to appropriately set a bias current value to be applied to the transistor. In particular, when used in a charge amplifier, high-frequency voltage noise density is important.
In the case of non-feedback, the self-noise of the operational amplifier is given by the sum of noises generated in all devices, but is usually used with limited gain by applying feedback. In this case, noise generated from a device outside the negative feedback loop is corrected by the negative feedback and can be ignored in the frequency band where the negative feedback effect is present. Therefore, when considering noise, it is only necessary to focus on noise generated by devices in the feedback loop. That is, noise generated from the device from the positive input terminal + tin to the negative input terminal −tin may be considered. Specifically, in FIG. 1, the current path is Q15-Q11-Re-Q21-Q25, and the other is the current path of Q15-Q13-Q14-Q12-Re-Q22-Q24-Q23-Q25.

The voltage noise Vfet of the junction field effect transistors Q15 and Q25 is a function of the frequency f and can be expressed by the following equation (1).

Here, k is the Boltzmann constant, g _mJFET is the mutual conductance of the junction field effect transistor, and T is the absolute temperature. K _JFET is a constant attributed to the shape of the junction field effect transistor, and changes depending on each process.

Further, the voltage noise V _BJT of the bipolar transistor can be expressed by the following equation (2).

_{Here, g mBJT} transconductance, _{r b} of the bipolar transistor is the base resistance (usually about 5 [Omega). The voltage noise VR of the resistor can be expressed by the following formula (3), where _R is the resistance value.

Resistance r _d of the diodes in the small signal, the elementary charge q, the current through the diode as I _d, can be expressed by the following equation (4), which is intended on the model, physical It is not resistance. Therefore, it is not necessary to consider the contribution to thermal noise.

From the above, it is only necessary to add noise, but it should be noted that the bipolar transistors Q11 and Q12 (Q21, Q22) are in parallel because of the parallel noise. As a result, the total noise Vn can be expressed by the following equation (5).

Here, 2K _JFET / f is 1 / f noise, and if an appropriate junction field effect transistor is selected, noise that becomes a problem at the measurement frequency can be prevented from being generated. The other terms are the sum of the resistance components, and the thermal noise due to the resistance is calculated.

A common junction field effect transistor has a conductance gm of about Is / 1V (Is is a source current), and even a high-performance type has Is / 0.2V, whereas a bipolar transistor has a well-known conductance gm. Thus, Ic / 26 mV. This indicates that the equivalent resistance of the junction field effect transistor is 10 to 40 times higher than that of the bipolar transistor when the same current is passed.

For example, when a high-performance junction field effect transistor having a mutual conductance of about 5 mS (about 270 Ω in terms of resistance in the equation (5)) is used when the source current is 1 mA. Take the example.
FIG. 2 shows the result of calculating the voltage noise density of the operational amplifier of FIG. 1 while ignoring the 1 / f noise term in the equation (5) when the current I _JFET of the junction field effect transistor is 1 mA. As can be seen from FIG. 2, when the current I _{BPT of the} bipolar transistor is 0.1 mA or more, which is 1/10 of the current I _JFET of the junction field effect transistor, the current is almost constant. However, when the current _{IBPT of the} bipolar transistor is smaller than 0.1 mA, noise increases abruptly.
FIG. 3 shows the case where the current I _JFET of the junction field effect transistor is set to 10 mA, but when the current I _{BPT of the} bipolar transistor is reduced to 1 mA which is 1/10 of 1/10 of the current I _JFET of the junction field effect transistor, Noise increases.

Noise design is performed as follows. First, the current of the junction field effect transistor is determined from the amount of noise of the required device. This corresponds to setting the noise of the flat portion in FIGS. Here not only calculate two cases, but if the current _{I JFET} junction field effect transistor of Fig 2 is 1mA, 2.2nV / √Hz, the current _{I JFET} junction field effect transistor of FIG. 3 10 mA of In this case, 1 nV / √Hz.

Next, the current value of the bipolar transistor is determined. As is clear from FIGS. 2 and 3, even if the current I _{BPT of the} bipolar transistor is set to be higher than the current I _JFET of the junction field effect transistor, noise does not decrease and current consumption such as temperature rise increases. The harmful effects caused by this increase. Normally, the amount of current is reduced to reduce noise, but the noise increases when the current amount of the bipolar transistor becomes 1/10 or less of the current _IJFET of the junction field effect transistor. The meaning of disappears. For this reason, the current I _{BPT of the} bipolar transistor is set to a value that is equal to or slightly smaller than the current I _JFET of the junction field effect transistor, thereby suppressing the adverse effect of temperature rise due to an increase in current consumption while suppressing the voltage noise density. can do.

By the way, when a MOS field effect transistor is applied instead of the n-channel junction field effect transistors Q15 and Q25, the 1 / f noise of the MOS field effect transistor is large, so that the voltage noise density can be suppressed. It is impossible to construct an operational amplifier with low noise characteristics. In addition, when a MOS field effect transistor is applied in place of each bipolar transistor, the voltage noise density is further increased, and an operational amplifier having low noise characteristics cannot be constructed at all.

In the present embodiment, the connection point between the emitters of the bipolar transistors Q11 and Q12 connected in a complementary manner in the first push-pull circuit 11 and the emitters of the bipolar transistors Q21 and Q22 in a complementary connection in the second push-pull circuit 12 are used. The connection point is connected via an emitter connection resistor Re. As described above, by arranging the emitter connection resistor Re, even if the characteristics of the four bipolar transistors Q11, Q12 and Q21, Q22 that are connected in a complementary manner have a certain degree of variation, the emitter connection resistor Re absorbs the variation in the characteristics. A more stable circuit can be obtained.

By the way, when the emitter connection resistor Re is omitted and the connection point between the emitters of the complementary transistors Q11 and Q12 and the connection point between the emitters of the complementary transistors Q21 and Q22 are connected directly, the bipolar The current flowing through the connecting portion is not stable according to variations in the characteristics of the transistors Q11, Q12 and Q21, Q22, and normal operation is impaired.

Further, in the present embodiment, npn bipolar transistors Q16 and Q26 are cascode-connected to the positive power supply line Lp side of the n-channel junction field effect transistors Q15 and Q25, and the base potentials of the npn bipolar transistors Q16 and Q26 are set to the ground potential. It is fixed at an intermediate potential from the power supply potential.
For this reason, it is possible to prevent the bias voltages of the bias circuits 21 and 24 of the first push-pull circuit 11 and the second push-pull circuit 12 from being affected by power supply voltage fluctuations from the positive power supply line Lp. Therefore, the output voltage output from the connection point between the first push-pull circuit 11 and the first current-voltage conversion circuit 13 and the third current-voltage conversion circuit 15, the second push-pull circuit 12, The fluctuation of the output voltage output from the connection point between the second current-voltage conversion circuit 14 and the fourth current-voltage conversion circuit 16 can be suppressed.

In the first embodiment, the case where npn bipolar transistors Q16 and Q26 having the same polarity are connected between the n-channel junction field effect transistors Q15 and Q25 and the positive power supply line Lp has been described. However, the n-channel field effect transistors having the same polarity as the n-channel junction field effect transistors Q15 and Q25 may be used.

In the first embodiment, the case where the npn bipolar transistors Q16 and Q26 are cascode-connected between the n-channel junction field effect transistors Q15 and Q25 and the positive power supply line Lp has been described. However, the present invention is not limited to the above configuration, and a constant current source may be applied instead of the npn-type bipolar transistors Q16 and Q26.

In the first embodiment, the n-channel junction field effect transistors Q15 and Q25 and the npn bipolar transistors Q16 and Q26 are connected to the first push-pull circuit 11 and the second push-pull circuit 12 and the positive power supply line Lp. It was inserted between. However, the present invention is not limited to the configuration described above, and may be configured as shown in FIG.
That is, the current mirror circuit 22 is inserted between the bias circuits 21 and 24 of the first push-pull circuit 11 and the second push-pull circuit 12 and the positive power supply line Lp. Further, p-channel junction field effect transistors Q61 and Q62 are interposed between the bias circuits 21 and 24 of the first push-pull circuit 11 and the second push-pull circuit 12 and the negative power supply line Ln. Then, pnp bipolar transistors Q63 and Q64 having the same polarity are cascode-connected to the p-channel junction field effect transistors Q61 and Q62. In this case, the same effect as that of the first embodiment can be obtained. Of course, a p-channel junction field effect transistor may be applied instead of the pnp bipolar transistors Q63 and Q64.

In the first embodiment, the case where the final output stage 19 is configured by the npn-type bipolar transistors Q51 and Q52 has been described, but a pnp-type bipolar transistor may be applied instead. However, since the npn-type bipolar transistor can operate at a higher speed than the pnp-type bipolar transistor, the npn-type bipolar transistors Q51 and Q52 are applied to form a higher-speed operational amplifier as in the first embodiment. can do.

In this regard, in the configuration example of FIG. 1 in the first embodiment, the circuit of the final output stage 19 includes two npn-type bipolar transistors Q51 and Q52 between the positive power supply line Lp and the negative power supply line Ln. A circuit configuration having a configuration in which the emitter of npn-type bipolar transistor Q51 is connected in series with the collector of npn-type bipolar transistor Q52, that is, the npn-type bipolar transistor is used for both the high-potential side and the low-potential-side bipolar transistors. Therefore, the high-speed property of the npn-type bipolar transistor can be fully exhibited.

On the other hand, when the circuit of the final output stage 19 has a circuit configuration having a complementary connection configuration in which a pnp bipolar transistor and an npn bipolar transistor with collectors connected to each other are connected between a positive power supply line and a negative power supply line Since the overall operation of the combination of the low potential side npn type bipolar transistor and the high potential side pnp type bipolar transistor becomes slow when pulled toward the pnp type bipolar transistor, the high speed of the npn type bipolar transistor Sex cannot be fully demonstrated.

As described above, in the circuit configuration of the operational amplifier shown in FIG. 1 in the first embodiment, the circuit of the final output stage 19 is replaced with two npn-type bipolar transistors Q51 and Qn between the positive power supply line Lp and the negative power supply line Ln. Since Q52 is configured to be connected in series with the emitter of npn bipolar transistor Q51 connected to the collector of npn bipolar transistor Q52, it is particularly suitable for realizing a high-speed operational amplifier.

Next, a second embodiment of the present invention will be described with reference to FIG.
In the second embodiment, a differential charge amplifier is configured using the operational amplifier in the first embodiment described above.
That is, in the second embodiment, a parallel circuit of a feedback feedback resistor Rf and a capacitor Cf is connected between the inverting input terminal and the output terminal of the operational amplifier 1 of the first embodiment described above. .

The variable capacitors C _SENS M and C _SENS P of the variable capacitance sensor 60 are connected to the inverting input terminal and the non-inverting input terminal of the operational amplifier 1. The variable capacitance sensor 60 includes a pair of electrode portions each composed of a movable electrode and a fixed electrode facing each other that generate a capacitance change according to a physical quantity change, and a variable capacitance C _SENS M configured by one electrode portion is provided. A differential structure in which the variable capacitor C _SENS P formed by the other electrode portion decreases as the number increases is increased.
As this variable capacitance sensor 60, a physical quantity sensor that detects a physical quantity such as acceleration or vibration using a MEMS (Micro Electro Mechanical System) structure is applied, and both the variable capacitance C _SENS M and C _SENS P are, for example, 1 pF and a minute capacitance. Has been. For example, a capacitor Cpp of 10 pF is connected between one electrode of the variable capacitor C _SENS M and the inverting input terminal of the operational amplifier 1 and the ground. Similarly, one electrode of the variable capacitor C _SENS P For example, a capacitor Cpm of 10 pF is connected between the non-inverting input terminal of the operational amplifier 1 and the ground.

An AC oscillator 61 as a bias voltage generation circuit for outputting, for example, an AC carrier signal of ± 8 V at 100 kHz as a bias voltage is connected to the other electrode opposite to the operational amplifier 1 of each variable capacitor C _SENS M and C _SENS P. Has been.
Further, a multiplier 62 as a demodulation circuit is connected to the output side of the operational amplifier 1, and the AC carrier signal of the AC oscillator 61 is input to the multiplier 62. The capacitance detection signal demodulated by the multiplier 62 is subjected to noise removal by a low-pass filter 63 including a resistor R1 and a capacitor C1, and is output from an output terminal Tout.

Further, a parallel circuit of an adjustment trimmer capacitor Cpin and a resistor Rpin is connected between the variable capacitor C _SENSP of the variable capacitor sensor 60 and the non-inverting input terminal of the operational amplifier 1 and the ground. Here, the trimmer capacitor Cpin is adjusted so that the carrier signal of 100 kHz included in the input signal of the multiplier 62 that is the output of the charge amplifier 50 is minimized.

When the charge amplifier 50 is configured in this way, it is possible to measure a change in capacitance of the low-pass filter 63 connected to the output terminal Tout below a cutoff frequency (for example, 72.3 Hz).
FIG. 6 shows the result of measuring the frequency characteristic of the charge amplifier 50 of the present invention shown in FIG. 5 as the characteristic in the circuit configuration of the second embodiment in comparison with the characteristic of the charge amplifier of the conventional example.
First, as shown in FIG. 6A, the gain characteristic with respect to the frequency is 18.5 MHz in the conventional circuit when the frequency at which the gain starts to decrease in the negative direction from −3 dB is compared. In the circuit of the invention, the frequency is 58.4 MHz, which indicates that the speed can be increased about three times.
Next, as shown in FIG. 6B, the phase angle characteristic with respect to the frequency starts to decrease from 1 MHz in the conventional circuit and decreases to −50 deg at 18.5 MHz, whereas the circuit according to the present invention. Then, it starts to decrease from 1 MHz and decreases to −50 deg at 30 MHz.
Therefore, by using the operational amplifier 1 of the first embodiment to configure the charge amplifier 50 that detects a minute change in capacitance, it is possible to realize a high SN.

Further, in the circuit configuration of the second embodiment, the output values when the bipolar transistors Q16 and Q26 that are cascode-connected to the junction field effect transistors Q15 and Q25 constituting the operational amplifier 1 are present and when there are no bipolar transistors Q16 and Q26 are obtained. The output voltage was measured by changing the Vdd voltage, which is the operating power supply supplied to. The variable capacitance sensor 60 was kept stationary without applying an external force. The measurement results are shown in FIG.

As is apparent from FIG. 7, when there is a cascode-connected transistor, the output value is not changed even when the operating power supply Vdd is changed, and “0” V is maintained, but there is no cascode-connected transistor. The output change of about 1.5 mV was observed when the operating power supply Vdd changed by 1V.
This phenomenon occurs due to the difference between the positive and negative input capacities of the differential charge amplifier. It can be confirmed by circuit simulation that such a phenomenon does not occur when the capacitance balance is perfect, but in an actual circuit, the capacitance variation of the variable capacitance sensor 60 and the plus and minus gains are determined. There are variations in capacity. This variation is gain-adjusted with a trimmer capacitor Cpin to determine the zero point. However, since the input capacitance of the operational amplifier 1 depends on the source-drain voltages of the n-channel junction field effect transistors Q15 and Q25, the cascode connection In the case where there is no transistor, if the power supply voltage is changed, the capacity balance, that is, the gain balance is lost, and the output change phenomenon described above occurs.

As a result of examining the capacitance balance by simulation, it was found that there is a capacitance imbalance of about 0.1 pF in this embodiment. This level of imbalance can easily occur in manufacturing.
On the other hand, in the case of a high-resolution variable capacitance sensor, a resolution of about 5 uV is required. Therefore, when there is no cascode-connected transistor, the allowable power supply voltage fluctuation is about 5 mV in this embodiment. Such a power supply can be realized by, for example, a lead storage battery, but it is difficult to reduce the size of the sensor device.

Therefore, when applied to a high-resolution sensor, as in the first embodiment described above, transistors having the same polarity are cascaded on the drain side of the n-channel junction field effect transistors Q15 and Q25, that is, on the positive power supply line Lp side. By connecting, it is desirable to suppress the influence of fluctuations in the power supply voltage. As a result, an alkaline button battery, a coin-type lithium primary battery or the like having a large power supply voltage fluctuation rate can be used as the power source, and the sensor device can be miniaturized.
Next, a third embodiment of the present invention will be described with reference to FIG.

The operational amplifier according to the third embodiment has a two-stage amplifier circuit configuration in order to increase the open loop gain.
That is, in the third embodiment, the operational amplifier 1 has a two-stage amplifier circuit configuration in which a first amplification stage 70A and a second amplification stage 70B are provided, as shown in FIG.
The configuration of the first amplification stage 70A has the same configuration as that of the first embodiment described above, and includes the first push-pull circuit 11 and the second push-pull circuit 12, and the first current-voltage conversion circuit 13 to A fourth current-voltage conversion circuit 16, a first output stage 17 and a second output stage 18, and a final output stage 19 are provided.

The second amplification stage 70B, which is the final amplification stage, is interposed between the first output stage 17, the second output stage 18, and the final output stage 19. The second amplification stage 70B includes a third push-pull circuit 71 and a fourth push-pull circuit 72 having the same configuration as the first push-pull circuit 11 and the second push-pull circuit 12 described above. Yes. The second amplification stage 70B includes a fifth current-voltage conversion circuit 73 inserted between the high potential side of the third push-pull circuit 71 and the fourth push-pull circuit 72 and the positive power supply line Lp, and A sixth current-voltage conversion circuit 7374 is provided. Furthermore, the second amplification stage 70B also has a seventh current-voltage conversion circuit 75 interposed between the low potential side of the third push-pull circuit 71 and the fourth push-pull circuit 72 and the negative power supply line Ln. And 8 current-voltage conversion circuits 76. The second amplification stage 70B includes a third output stage 79 to which the output sides of the fifth current-voltage conversion circuit 73 and the seventh current-voltage conversion circuit 75 are connected, and the sixth current-voltage conversion circuit 74. And a fourth output stage 80 to which the output side of the eighth current-voltage conversion circuit 76 is connected.

The third push-pull circuit 71 includes an npn-type bipolar transistor Q71 and a pnp-type bipolar transistor Q72, whose emitters are connected to each other. The collector of the npn-type bipolar transistor Q71 is connected to the fifth current-voltage conversion circuit 73, and the collector of the pnp-type bipolar transistor Q72 is connected to the seventh current-voltage conversion circuit 75.

Further, the base of the npn-type bipolar transistor Q71 and the base of the pnp-type bipolar transistor Q72 are connected to the bias circuit 77. The bias circuit 77 includes a pnp bipolar transistor Q75 having an emitter connected to the collector of the pnp bipolar transistor Q41 constituting the first output stage 17 of the first amplification stage 70A, and a collector connected to the negative power supply line Ln. The npn bipolar transistor Q76 has a collector connected to the positive power supply line Lp and an emitter connected to the collector of the npn bipolar transistor Q42 constituting the first output stage 17 of the first amplification stage 70A.

The connection point between the emitter of the pnp bipolar transistor Q75 and the collector of the pnp bipolar transistor Q41 constituting the first output stage 17 (that is, the high potential side output section of the first output stage 17) is the third level. Is connected to the base of the npn-type bipolar transistor Q71 of the push-pull circuit 71 (that is, the high-potential side input section of the third push-pull circuit 71).
The connection point between the npn-type bipolar transistor Q76 and the npn-type bipolar transistor Q42 constituting the first output stage 17 (that is, the low-potential side output portion of the first output stage 17) is the third push-pull. The pnp bipolar transistor Q72 of the circuit 71 is connected to the base (that is, the low potential side input portion of the third push-pull circuit 71).

Further, the bases of the pnp bipolar transistor Q75 and the npn bipolar transistor Q76 are grounded via the capacitor C2.
Similar to the third push-pull circuit 71, the fourth push-pull circuit 72 includes an npn-type bipolar transistor Q73 and a pnp-type bipolar transistor Q74 whose emitters are connected to each other. The collector of the npn-type bipolar transistor Q73 is connected to the sixth current-voltage conversion circuit 74, and the collector of the pnp-type bipolar transistor Q74 is connected to the eighth current-voltage conversion circuit 76.

Also, the base of the npn bipolar transistor Q73 and the base of the pnp bipolar transistor Q74 are connected to the bias circuit 78. The bias circuit 78 includes a pnp bipolar transistor Q77 having an emitter connected to the collector of the pnp bipolar transistor Q43 constituting the second output stage 18 of the first amplification stage 70A, and a collector connected to the negative power supply line Ln. The npn bipolar transistor Q78 has a collector connected to the positive power supply line Lp and an emitter connected to the collector of the npn bipolar transistor Q44 constituting the second output stage 18 of the first amplification stage 70A.

The connection point between the emitter of the pnp bipolar transistor Q77 and the collector of the pnp bipolar transistor Q43 constituting the second output stage 18 (that is, the high potential side output portion of the second output stage 18) is the fourth. Of the push-pull circuit 72 is connected to the base of the npn-type bipolar transistor Q73 (that is, the high-potential side input section of the fourth push-pull circuit 72).
The connection point between the npn-type bipolar transistor Q78 and the npn-type bipolar transistor Q44 constituting the second output stage 18 (that is, the low-potential side output portion of the second output stage 18) is the fourth push-pull. The pnp bipolar transistor Q74 of the circuit 72 is connected to the base (that is, the low potential side input section of the fourth push-pull circuit 72).

Further, the bases of the pnp bipolar transistor Q77 and the npn bipolar transistor Q78 are grounded via the capacitor C3.
The fifth current-voltage conversion circuit 73 includes a pnp bipolar transistor Q81 having an emitter connected to the positive power supply line Lp and a collector connected to the third push-pull circuit 71. The collector and base of the pnp bipolar transistor Q81 are connected, and these connection points are connected to the third output stage 79, and a current mirror circuit is configured as will be described later.

The sixth current-voltage conversion circuit 74 includes a pnp bipolar transistor Q82 having an emitter connected to the positive power supply line Lp and a collector connected to the fourth push-pull circuit 72. The collector and base of the pnp bipolar transistor Q82 are connected, and these connection points are connected to the fourth output stage 80, so that a current mirror circuit is configured as will be described later.

The seventh current-voltage conversion circuit 75 includes an npn-type bipolar transistor Q83 having an emitter connected to the negative power supply line Ln and a collector connected to the third push-pull circuit 71. The collector and base of this npn-type bipolar transistor Q83 are connected, and these connection points are connected to the third output stage 79 to constitute a current mirror circuit as will be described later.

The eighth current-voltage conversion circuit 76 includes an npn-type bipolar transistor Q84 having an emitter connected to the negative power supply line Ln and a collector connected to the fourth push-pull circuit 72. The collector and base of this npn-type bipolar transistor Q84 are connected, and these connection points are connected to the fourth output stage 80 to constitute a current mirror circuit as will be described later.

The third output stage 79 includes a pnp bipolar transistor Q101 having an emitter connected to the positive power supply line Lp, an npn having a collector connected to the collector of the pnp bipolar transistor Q101, and an emitter connected to the negative power supply line Ln. Type bipolar transistor Q103.
The base of the pnp bipolar transistor Q101 is connected to the connection point between the base and collector of the pnp bipolar transistor Q81 of the fifth current-voltage conversion circuit 73, thereby forming a fifth current mirror circuit. In other words, the input side circuit of the fifth current mirror circuit constitutes the fifth current-voltage conversion circuit 73.
Further, the base of the npn-type bipolar transistor Q103 is connected to the connection point between the base and the collector of the npn-type bipolar transistor Q83 of the seventh current-voltage conversion circuit 75 to constitute a seventh current mirror circuit. In other words, the input side circuit of the seventh current mirror circuit constitutes the seventh current-voltage conversion circuit 75.

The fourth output stage 80 includes a pnp bipolar transistor Q102 having an emitter connected to the positive power supply line Lp, a collector connected to the collector of the pnp bipolar transistor Q102, and an emitter connected to the negative power supply line Ln. And an npn-type bipolar transistor Q104.
The base of the pnp bipolar transistor Q102 is connected to the connection point between the base and collector of the pnp bipolar transistor Q82 of the sixth current-voltage conversion circuit 74 to constitute a sixth current mirror circuit. In other words, the input current circuit of the sixth current mirror circuit constitutes the sixth current-voltage conversion circuit 74.
The base of the npn bipolar transistor Q104 is connected to the connection point between the base and collector of the npn bipolar transistor Q84 of the eighth current-voltage conversion circuit 76, thereby forming an eighth current mirror circuit. In other words, the input current circuit of the eighth current mirror circuit constitutes the eighth current-voltage conversion circuit 76.

As in the first embodiment described above, the final output stage 19 includes two npn bipolar transistors Q91 and Q92 between the positive power supply line Lp and the negative power supply line Ln, and the npn bipolar transistor Q91 has an npn bipolar emitter. The transistor Q92 is connected in series with the collector of the transistor Q92.
The base of the npn bipolar transistor Q91 on the high potential side is connected to the output terminal serving as a connection point between the pnp bipolar transistor Q101 and the npn bipolar transistor Q103 of the third output stage 79.
The base of the npn bipolar transistor Q92 on the low potential side is connected to the output terminal serving as a connection point between the pnp bipolar transistor Q102 and the npn bipolar transistor Q104 of the fourth output stage 80. Further, an output terminal tout is connected to a connection point between both npn-type bipolar transistors Q91 and Q92.

Further, a connection point between the base of the npn type bipolar transistor Q92 on the low potential side and the output terminal serving as a connection point between the pnp type bipolar transistor Q102 and the npn type bipolar transistor Q104 in the fourth output stage 80 and the negative power supply line Ln. An npn bipolar transistor Q94 is connected between them.
The npn bipolar transistor Q94 has a collector connected to the output terminal of the fourth output stage 80 and a connection point of the npn bipolar transistor Q92, and an npn bipolar transistor Q94 having an emitter connected to the negative power supply line Ln.
The base of the npn type bipolar transistor Q94 is connected to the connection point between the output terminal of the fourth output stage 80 and the base of the npn type bipolar transistor Q92 to constitute a constant current circuit. It should be noted that phase compensation capacitors C0 and C1 that prevent deterioration of the high-frequency characteristics of the operational amplifier are connected between npn-type bipolar transistors Q91 and Q92 between their respective collectors and bases.

Further, a capacitor that suppresses noise between a connection point between the npn-type bipolar transistor Q23 and the junction field effect transistor Q25 in the bias circuit 24 of the first amplification stage 70A and a connection point between the output terminal tout of the final output stage 19 C4 is connected.
In the third embodiment, the npn bipolar transistors Q16 and Q26 cascode-connected to the junction field effect transistors Q15 and Q25 in the first embodiment are omitted, but the first embodiment is omitted. Similarly to the above, npn bipolar transistors Q16 and Q26 may be provided.

As described above, according to the third embodiment, since the configuration of the first amplification stage 70A has the same configuration as that of the first embodiment described above, the first output stage of the first amplification stage 70A. A large driving force can be obtained from the 17 and the second output stage 18 while suppressing noise, and an amplified output that can increase the speed can be obtained.
The amplified output of the first output stage 17 output from the first amplification stage 70A is input to the bias circuit 77 of the third push-pull circuit 71 of the second amplification stage 70B, and the second output The amplified output of the output stage 18 is input to the bias circuit 78 of the fourth push-pull circuit 72 of the second amplification stage 70B. Therefore, the signals are amplified again by the third push-pull circuit 71 and the fourth push-pull circuit 72 and output to the final output stage 19, converted into a voltage by the final output stage 19, and output from the output terminal tout. .

By the way, when the operational amplifier is applied to the charge amplifier, when the feedback is adjusted to low noise (high signal-to-noise ratio), the gain (accurately, noise gain) is naturally about 20 dB. Therefore, the open loop gain (OLG) of the operational amplifier applied to the charge amplifier need not be a large value. The open loop gain (OLG) of the operational amplifier 1 of the first embodiment described above is about 65 dB.

However, 90 to 120 dB is required for normal amplifier applications other than charge amplifiers. Therefore, as in the third embodiment, the first amplification stage 70A having the configuration of the first embodiment and the second amplification stage 70B that amplifies the amplification output of the first amplification stage 70A are provided. By providing, it is possible to secure a current consumption of about 4.5 mA and an open loop gain (OLG) of 120 dB. Therefore, the operational amplifier according to the third embodiment can be used without problems for general amplification applications.

In the third embodiment, as in the first embodiment, the connection position of the junction field effect transistors Q15 and Q25 is on the negative power supply line Ln side of the pnp bipolar transistors Q14 and Q24 of the bias circuit. Can be connected. In this case, the current mirror circuit 22 may be connected to the positive power supply line Lp side.
In the configuration example of FIG. 8 in the third embodiment, the case where the final output stage 19 is configured by npn-type bipolar transistors Q91 and Q92 has been described. However, instead of these, a pnp-type bipolar transistor is applied. This point is the same as in the first embodiment. However, as described in the first embodiment, the npn-type bipolar transistor can operate at a higher speed than the pnp-type bipolar transistor. Therefore, the npn-type bipolar transistors Q91 and Q92 are not provided as in the configuration example of FIG. A faster operational amplifier can be configured when applied.

In this regard, in the configuration example of FIG. 8 in the third embodiment, the circuit of the final output stage 19 includes two npn-type bipolar transistors Q91 and Q92 between the positive power supply line Lp and the negative power supply line Ln. Circuit configuration having a configuration in which the emitter of npn-type bipolar transistor Q91 is connected in series with the collector of npn-type bipolar transistor Q92, that is, the npn-type bipolar transistor is used for both the high-potential side and low-potential-side bipolar transistors. Therefore, the high-speed property of the npn-type bipolar transistor can be fully exhibited.

On the other hand, when the circuit of the final output stage 19 has a circuit configuration having a complementary connection configuration in which a pnp bipolar transistor and an npn bipolar transistor with collectors connected to each other are connected between a positive power supply line and a negative power supply line Since the overall operation of the combination of the low potential side npn type bipolar transistor and the high potential side pnp type bipolar transistor becomes slow when pulled toward the pnp type bipolar transistor, the high speed of the npn type bipolar transistor Sex cannot be fully demonstrated.

As described above, the circuit configuration of the operational amplifier shown in FIG. 8 in the third embodiment is similar to the circuit configuration of the operational amplifier according to the first embodiment in that the circuit of the final output stage 19 is replaced with the positive power supply line Lp and Since the two npn bipolar transistors Q91 and Q92 are connected in series between the negative power supply line Ln and the emitter of the npn bipolar transistor Q91 connected to the collector of the npn bipolar transistor Q92, a high-speed operational amplifier Is particularly suitable for realizing the above.

In the third embodiment, the configuration of the operational amplifier having the two-stage amplifier circuit configuration in order to increase the open-loop gain is shown in FIG. 8, but the calculation having the two-stage amplifier circuit configuration in the present invention is shown in FIG. The configuration of the amplifier is not limited to the configuration example shown in FIG. 8, but may be the circuit configuration shown in FIG.
That is, in the configuration example of FIG. 9, the operational amplifier 1 has a two-stage amplifier circuit configuration in which the first amplifier stage 70A and the second amplifier stage 70C are provided.

The configuration of the first amplification stage 70A has the same configuration as that of the first embodiment described above, and includes the first push-pull circuit 11, the second push-pull circuit 12, and the first current-voltage conversion circuits 134 to A fourth current-voltage conversion circuit 6, a first output stage 17 and a second output stage 18, and a final output stage 19 are provided.
The second amplification stage 70 </ b> C, which is the final amplification stage, is interposed between the first output stage 17, the second output stage 18, and the final output stage 19. The second amplifying stage 70C includes a third push-pull circuit 71 and a fourth push-pull circuit 72 having the same configuration as the first push-pull circuit 11 and the second push-pull circuit 12 described above. A fifth current-voltage conversion circuit 73a interposed between the high potential side of the third push-pull circuit 71 and the fourth push-pull circuit 72 and the positive power supply line Lp; a third push-pull circuit 71; A sixth current-voltage conversion circuit 74a interposed between the low potential side of the fourth push-pull circuit 72 and the negative power supply line Ln is provided.

The third push-pull circuit 71 includes an npn-type bipolar transistor Q71 and a pnp-type bipolar transistor Q72, whose emitters are connected to each other. The collector of the npn type bipolar transistor Q71 is connected to the fifth current / voltage conversion circuit 73a, and the collector of the pnp type bipolar transistor Q72 is connected to the sixth current / voltage conversion circuit 74a.

The base of the npn-type bipolar transistor Q71 and the base of the pnp-type bipolar transistor Q72 are connected to the bias circuit 77. The bias circuit 77 has a pnp bipolar transistor Q75 and an npn bipolar transistor Q76.
In the pnp bipolar transistor Q75, the emitter is connected to the collector of the pnp bipolar transistor Q41 constituting the first output stage 17 of the first amplification stage 30A, and the collector is connected to the negative power supply line Ln. The npn-type bipolar transistor Q76 has a collector connected to the positive power supply line Lp, and an emitter connected to the collector of the npn-type bipolar transistor Q42 constituting the first output stage 17 of the first amplification stage 30A.

The connection point between the emitter of the pnp bipolar transistor Q75 and the collector of the pnp bipolar transistor Q41 constituting the first output stage 17 is connected to the base of the npn bipolar transistor Q71 of the third push-pull circuit 71. Yes. The connection point between the npn bipolar transistor Q76 and the npn bipolar transistor Q42 constituting the first output stage 17 is connected to the base of the pnp bipolar transistor Q72 of the third push-pull circuit 71.

Further, the bases of the pnp bipolar transistor Q75 and the npn bipolar transistor Q76 are grounded via the capacitor C2.
Similar to the third push-pull circuit 71, the fourth push-pull circuit 72 includes an npn-type bipolar transistor Q73 and a pnp-type bipolar transistor Q74 whose emitters are connected to each other. The collector of the npn-type bipolar transistor Q73 is connected to the fifth current-voltage conversion circuit 73a, and the collector of the pnp-type bipolar transistor Q74 is connected to the sixth current-voltage conversion circuit 74a.

The base of the npn type bipolar transistor Q73 and the base of the pnp type bipolar transistor Q74 are connected to the bias circuit 78. The bias circuit 78 includes a pnp bipolar transistor Q77 and an npn bipolar transistor Q78.
In the pnp bipolar transistor Q77, the emitter is connected to the collector of the pnp bipolar transistor Q43 constituting the second output stage 18 of the first amplification stage 30A, and the collector is connected to the negative power supply line Ln. The npn bipolar transistor Q78 has a collector connected to the positive power supply line Lp and an emitter connected to the collector of the npn bipolar transistor Q44 that constitutes the second output stage 18 of the first amplification stage 30A.

The connection point between the emitter of the pnp bipolar transistor Q77 and the collector of the pnp bipolar transistor Q43 constituting the second output stage 18 is connected to the base of the npn bipolar transistor Q73 of the fourth push-pull circuit 72. Yes. The connection point between the npn bipolar transistor Q78 and the npn bipolar transistor Q44 constituting the second output stage 18 is connected to the base of the pnp bipolar transistor Q74 of the fourth push-pull circuit 72.

Further, the bases of the pnp bipolar transistor Q77 and the npn bipolar transistor Q78 are grounded via the capacitor C3.
The fifth current-voltage conversion circuit 73a includes a pnp bipolar transistor Q81 and a pnp bipolar transistor Q82a. The pnp bipolar transistor Q81 has an emitter connected to the positive power supply line Lp and a collector connected to the third push-pull circuit 71. The npn bipolar transistor Q82 has an emitter connected to the positive power supply line Lp and a collector connected to the fourth push-pull circuit 72.
The bases of these pnp bipolar transistors Q81 and Q82a are connected to each other, and the connection point of both bases is connected to the collector of the pnp bipolar transistor Q82a to form a current mirror circuit.

The sixth current-voltage conversion circuit 74a includes an npn bipolar transistor Q83 and an npn bipolar transistor Q84a. The npn bipolar transistor Q83 has an emitter connected to the negative power supply line Ln and a collector connected to the third push-pull circuit 71. The pnp bipolar transistor Q84 has an emitter connected to the negative power supply line Ln and a collector connected to the fourth push-pull circuit 72.
The bases of these npn-type bipolar transistors Q83 and Q84a are connected to each other, and the connection point of both bases is connected to the collector of the npn-type bipolar transistor Q84a to form a current mirror circuit.

Further, the connection point between the collector of the npn-type bipolar transistor Q71 of the third push-pull circuit 71 and the collector of the pnp-type bipolar transistor Q81 of the fifth current-voltage conversion circuit 73a is the output terminal, and the pnp-type bipolar of the final output stage 19 is used. It is connected to the base of transistor Q91a. Similarly, the connection point between the collector of the pnp bipolar transistor Q72 of the third push-pull circuit 71 and the collector of the npn bipolar transistor Q83 of the sixth current-voltage conversion circuit 74a is the output terminal, and the npn type of the final output stage 19 It is connected to the base of bipolar transistor Q92.

Here, the final output stage 19 has a complementary connection configuration in which a pnp bipolar transistor 91a and an npn bipolar transistor Q92, whose collectors are connected to each other, are connected between the positive power supply line Lp and the negative power supply line Ln.
A pnp bipolar transistor Q93 is connected between the base of the pnp bipolar transistor Q91a and the positive power supply line Lp. The base of the pnp bipolar transistor Q93 is the connection point between the npn bipolar transistor Q71 of the third push-pull circuit 71 and the collector of the pnp bipolar transistor Q81 of the fifth current-voltage conversion circuit 73, and the final output. Connected between the base of the pnp bipolar transistor Q91a of the stage 19.
The pnp bipolar transistor Q93 and the pnp bipolar transistor Q91a of the final output stage 19 form a constant current circuit.

Similarly, an npn bipolar transistor Q94 is connected to the npn bipolar transistor Q92 between the base and the negative power supply line Ln as in the first embodiment. The npn bipolar transistor Q94 and the npn bipolar transistor Q92 constitute a constant current circuit.
Further, a capacitor that suppresses noise between a connection point between the npn-type bipolar transistor Q23 and the junction field effect transistor Q25 in the bias circuit 24 of the first amplification stage 70A and a connection point between the output terminal tout of the final output stage 19 C4 is connected.

In the configuration example of FIG. 9, the npn bipolar transistors Q16 and Q26 that are cascode-connected to the junction field effect transistors Q15 and Q25 in the first embodiment are omitted, but the first embodiment is omitted. Similarly to the above, npn bipolar transistors Q16 and Q26 may be provided.
As described above, according to the configuration example of FIG. 9, the configuration of the first amplification stage 70A has the same configuration as that of the first embodiment described above, and therefore the first output stage of the first amplification stage 70A. A large driving force can be obtained from the 17 and the second output stage 18 while suppressing noise, and an amplified output that can increase the speed can be obtained.

The amplified output of the first output stage 17 output from the first amplification stage 70A is input to the bias circuit 77 of the third push-pull circuit 71 of the second amplification stage 70C, and the second output The amplified output of the output stage 18 is input to the bias circuit 78 of the fourth push-pull circuit 72 of the second amplification stage 70C. Therefore, the signals are amplified again by the third push-pull circuit 71 and the fourth push-pull circuit 72 and output to the final output stage 19, converted into a voltage by the final output stage 19, and output from the output terminal tout. .

Further, as in the configuration example of FIG. 9, the first amplification stage 70A having the configuration of the first embodiment and the second amplification stage 70C for amplifying the amplification output of the first amplification stage 70A are provided. As a result, as in the configuration example of FIG. 8, it is possible to secure a current consumption of about 4.5 mA and an open loop gain (OLG) of 120 dB. Therefore, the operational amplifier according to the configuration example of FIG. 9 can be used without any problem for general amplification applications, similarly to the operational amplifier according to the configuration example of FIG.

In the configuration example of FIG. 9, as in the first embodiment described above, the connection position of the junction field effect transistors Q15 and Q25 is on the negative power supply line Ln side of the pnp bipolar transistors Q14 and Q24 of the bias circuit. Can be connected. In this case, the current mirror circuit 22 may be connected to the positive power supply line Lp side.

DESCRIPTION OF SYMBOLS 1 ... Operational amplifier, Lp ... Positive power supply line, Ln ... Negative power supply line, 11 ... 1st push pull circuit, 12 ... 2nd push pull circuit, 13 ... 1st current voltage conversion circuit, 14 ... 2nd Current voltage conversion circuit, 15 ... third current voltage conversion circuit, 16 ... fourth current voltage conversion circuit, 17 ... first output stage, 18 ... second output stage, 19 ... final output stage, Q11 to Q14 ... Bipolar transistor, Q15 ... Junction type field effect transistor, Q16 ... Cascode-connected bipolar transistor, Q21 to Q24 ... Bipolar transistor, 21,24 ... Bias circuit, 22 ... Current mirror circuit, Re ... Emitter connection resistance, Q25 ... Junction type Field effect transistor, Q26 ... Cascode-connected bipolar transistor, + tin ... Positive input terminal, -tin ... Negative electrode Input terminals, Q31 ~ Q37 ... bipolar transistors, Q41 ~ Q44 ... bipolar transistors, Q51 ~ Q53 ... bipolar transistor, Q61, Q62 ... junction field effect transistor, Q63, Q64 ... bipolar transistor, 50 ... charge _{amplifier, C SENS ...} Variable Capacitance, 60 ... variable capacitance sensor, 61 ... AC oscillator, 62 ... multiplier, 63 ... low pass filter, 70A ... first amplification stage, 70B, 70C ... second amplification stage, 71 ... third push-pull circuit, 72: Fourth push-pull circuit, 73, 73a: Fifth current-voltage conversion circuit, 74, 74a: Sixth current-voltage conversion circuit, 75: Seventh current-voltage conversion circuit, 76: Eighth current voltage Conversion circuit, 77, 78 ... bias circuit, 79 ... third output stage, 80 ... fourth output stage, Q71 to Q78 Bipolar transistor, Q81 ~ Q84, Q82a, Q84a ... bipolar transistor, Q91 ~ Q94, Q91a ... bipolar transistor, Q101 ~ Q104 ... bipolar transistor

Claims (13)

1. Complementary first and second push-pull circuits connected in parallel between the positive and negative power supply lines;
   A first current-voltage conversion circuit and a second current-voltage conversion circuit, which are connected to the positive power supply line by connecting a high potential side of the first push-pull circuit and the second push-pull circuit;
   A third current-voltage conversion circuit and a fourth current-voltage conversion circuit connected to the negative power supply line by connecting a low potential side of the first push-pull circuit and the second push-pull circuit;
   A first output stage to which output sides of the first current-voltage conversion circuit and the third current-voltage conversion circuit are connected;
   A second output stage to which the output sides of the second current-voltage conversion circuit and the fourth current-voltage conversion circuit are connected;
   A final output stage having a push-pull circuit configuration by connecting bipolar transistors of the same polarity between the positive power line and the negative power line;
   Supplying the output of the first output stage to the base of the high potential side bipolar transistor of the final output stage, and supplying the output of the second output stage to the low potential side bipolar transistor of the final output stage; An operational amplifier characterized by.
2. The final output stage is constituted by a push-pull circuit having two npn bipolar transistors in which one emitter is connected to the other collector between the positive power supply line and the negative power supply line. The operational amplifier according to 1.
3. The final output stage is constituted by a push-pull circuit having two pnp bipolar transistors in which one collector is connected to the other emitter between the positive power supply line and the negative power supply line. The operational amplifier according to 1.
4. A final amplification stage is interposed between the first output stage and the second output stage and the final output stage;
   The final amplification stage includes:
   Complementary third push-pull circuit and fourth push-pull circuit connected in parallel between the positive power line and the negative power line;
   A fifth current-voltage converter circuit and a sixth current-voltage converter circuit connected to the positive power supply line by connecting the high potential side of the third push-pull circuit and the fourth push-pull circuit;
   A seventh current-voltage conversion circuit and an eighth current-voltage conversion circuit connected to the negative power supply line by connecting the low potential side of the third push-pull circuit and the fourth push-pull circuit;
   A third output stage to which the output sides of the fifth current-voltage conversion circuit and the seventh current-voltage conversion circuit are connected;
   A fourth output stage to which the output sides of the sixth current-voltage conversion circuit and the eighth current-voltage conversion circuit are connected;
   The high-potential side input sections of the first output stage and the second output stage are connected to the high-potential side input sections of the third push-pull circuit and the fourth push-pull circuit, respectively. The low potential side input units of the first and second output stages are connected to the low potential side input units of the third push-pull circuit and the fourth push-pull circuit, respectively.
   The output of the third output stage is supplied to the base of the high potential side bipolar transistor of the final output stage, and the output of the fourth output stage is supplied to the base of the low potential side bipolar transistor of the final output stage. The operational amplifier according to any one of claims 1 to 3, wherein the operational amplifier is provided.
5. The fifth current-voltage conversion circuit includes a high potential side of the third push-pull circuit and an input side circuit of a fifth current mirror circuit connected between the positive power supply lines, and the sixth current The voltage conversion circuit includes a high potential side of the fourth push-pull circuit and an input side circuit of a sixth current mirror circuit connected between the positive power supply lines, and the seventh current-voltage conversion circuit includes: The eighth push-pull circuit is composed of an input side circuit of a seventh current mirror circuit connected between the low potential side of the third push-pull circuit and the negative power supply line, and the eighth current-voltage conversion circuit includes the fourth push-pull circuit. 5. The operational amplifier according to claim 4, comprising an input side circuit of an eighth current mirror circuit connected between a low potential side of a pull circuit and the negative power supply line.
6. The first current-voltage conversion circuit includes a high potential side of the first push-pull circuit and an input side circuit of a first current mirror circuit connected between the positive power supply lines, and the second current The voltage conversion circuit includes a high potential side of the second push-pull circuit and an input side circuit of a second current mirror circuit connected between the positive power supply lines, and the third current-voltage conversion circuit includes: The fourth push-pull circuit is constituted by an input side circuit of a third current mirror circuit connected between the low potential side of the first push-pull circuit and the negative power supply line, and the fourth current-voltage conversion circuit is configured by the second push-pull circuit. 6. The performance according to claim 1, comprising a low potential side of a pull circuit and an input side circuit of a fourth current mirror circuit connected between the negative power supply line. Amplifier.
7. The first push-pull circuit and the second push-pull circuit include a bias circuit including a diode interposed so that a current flows in a forward direction between the positive power supply line and the negative power supply line, and 2. An npn bipolar transistor having a base connected to a high potential side of the bias circuit and a pnp bipolar transistor having a base connected to a low potential side of the bias circuit. The operational amplifier according to any one of 6.
8. 8. The operational amplifier according to claim 7, wherein the diode of the bias circuit is composed of a diode-connected bipolar transistor.
9. The connection point between the emitters of the npn bipolar transistor and the pnp bipolar transistor is connected via a resistor in the first push-pull circuit and the second push-pull circuit. Operational amplifier.
10. N-channel or p-channel first and second junction field effect transistors, each of which controls a current of each bias circuit of the first push-pull circuit and the second push-pull circuit and has a gate connected to an input terminal. The operational amplifier according to claim 7, wherein the operational amplifier is provided.
11. The first junction field effect transistor and the second junction between the drain of the first junction field effect transistor and the second junction field effect transistor of n channel or p channel and the positive power supply line or the negative power supply line. 11. The operational amplifier according to claim 10, wherein a transistor having the same polarity as the junction field effect transistor is cascode-connected, and the potential of the control terminal of the transistor is fixed to an intermediate potential between the ground potential and the power supply potential.
12. A charge amplifier using the operational amplifier according to any one of claims 1 to 11 as an operational amplifier constituting an integrating circuit.
13. A charge amplifier using the operational amplifier according to claim 10 or 11 as an operational amplifier constituting an integrating circuit,
    A physical quantity sensor having a differential structure having a pair of electrode parts each composed of a movable electrode and a fixed electrode that generates a capacitance change according to a change in physical quantity, and one of the movable electrode and the fixed electrode of each of the pair of electrode parts A bias voltage generation circuit for generating a bias voltage to be supplied, and the other of the movable electrode and the fixed electrode of each of the pair of electrode portions is input to an input terminal, and between the movable electrode and the fixed electrode of each of the pair of electrode portions A charge amplifier characterized in that a difference between each minute electrostatic capacitance is inputted to the gates of the first and second junction field effect transistors of the operational amplifier.

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