WO2016019635A1 - Oled显示器件及其制作方法、显示装置 - Google Patents

Oled显示器件及其制作方法、显示装置 Download PDF

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WO2016019635A1
WO2016019635A1 PCT/CN2014/089430 CN2014089430W WO2016019635A1 WO 2016019635 A1 WO2016019635 A1 WO 2016019635A1 CN 2014089430 W CN2014089430 W CN 2014089430W WO 2016019635 A1 WO2016019635 A1 WO 2016019635A1
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cathode
anode
pattern
adhesive layer
layer
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PCT/CN2014/089430
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English (en)
French (fr)
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程鸿飞
乔勇
卢永春
先建波
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京东方科技集团股份有限公司
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Priority to EP14891613.3A priority Critical patent/EP3179529B1/en
Priority to US14/769,286 priority patent/US9735364B2/en
Publication of WO2016019635A1 publication Critical patent/WO2016019635A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/828—Transparent cathodes, e.g. comprising thin metal layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Embodiments of the present invention relate to an OLED display device, a method of fabricating the same, and a display device.
  • Organic Light Emitting Diode (OLED) display devices are a new generation of displays, which have many advantages compared with liquid crystal displays, such as self-illumination, fast response, wide viewing angle, etc., which can be used for flexible display and transparent display. , 3D display, etc.
  • the organic light-emitting device comprises an anode, a cathode and an organic functional layer.
  • the main working principle is that the carrier is injected into the organic functional layer and composited therein to emit light under the driving of the electric field formed by the anode and the cathode.
  • the cathode of the organic light-emitting device is generally prepared by using a thin layer of metallic silver, and the anode is generally prepared by using indium tin oxide (ITO). Due to the high resistivity of thin-layer metallic silver and ITO, especially for large-area shaped cathodes, the thin-layer metallic silver has a larger cathode resistivity and a larger IR drop, resulting in OLED devices. The actual driving voltage is greatly different from the power supply voltage. Therefore, on a large-sized OLED display, a large area of brightness unevenness may occur, which may affect the display effect.
  • ITO indium tin oxide
  • At least one embodiment of the present invention provides an OLED display device, a method for fabricating the same, and a display device, which avoids the problem of large transmission resistance of the cathode and the anode in the OLED display device.
  • At least one embodiment of the present invention provides an OLED display device including: a substrate substrate; an anode, a cathode formed on the substrate, and an organic functional layer between the cathode and the anode,
  • the anode and/or the cathode are topological insulators of a two-dimensional nanostructure, and the topological insulator of the two-dimensional nanostructure is adhered to the substrate by an adhesive layer.
  • At least one embodiment of the present invention provides a method of fabricating an OLED display device, comprising: forming a two-dimensional nanostructured anode pattern and/or a cathode pattern using a topological insulator; forming an anode, an organic functional layer, and a cathode, wherein the formation
  • the anode and/or the cathode are such that the anode pattern and/or the cathode pattern are adhered to the corresponding anode and/or cathode regions by an adhesive layer.
  • At least one embodiment of the present invention provides a display device, including any of the OLED display devices provided by the embodiments of the present invention.
  • 1 is a schematic diagram of an OLED display device
  • FIG. 2 is a schematic diagram of a method for fabricating an OLED display device according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a method for forming a cathode pattern of a two-dimensional nanostructured topological insulator according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a method for fabricating an OLED display device according to another embodiment of the present invention.
  • 10-package substrate 11-second substrate; 12-black matrix layer; 13-color film layer; 14-protective layer; 20-array substrate; 21-first substrate; 22-thin film transistor; 222-source; 223-drain; 23-anode; 24-pixel defining layer; 25-organic functional layer; 26-cathode; 30-filled layer.
  • FIG. 1 illustrates an OLED display including: an aligned array substrate 20 and a package substrate 10.
  • the array substrate 20 includes a first substrate 21, a thin film transistor 22 (including a gate electrode 221, a source electrode 222, and a drain electrode 223), an anode 23 connected to the drain electrode 223 of the thin film transistor 22, and an organic functional layer located above the anode 23. 25.
  • the package substrate 10 includes a second substrate 11, a color film layer 13, a black matrix layer 12, and a protective layer 14; a filler 30 is disposed between the array substrate 20 and the package substrate 10.
  • the organic functional layer 25 can be further subdivided into: a hole transport functional layer (HTL layer), a light emitting functional layer (EML layer), and electron transport. Functional layer (ETL layer), etc.
  • HTL layer hole transport functional layer
  • EML layer light emitting functional layer
  • ETL layer electron transport. Functional layer
  • Topological insulators are a new form of matter proposed in recent years.
  • the physical energy band structure of the topological insulator has a finite size energy gap at the Fermi level, but at its boundary or surface, it is energy-free, Dirac type, spin non-degenerate.
  • the conductive edge state which is the most unique property that distinguishes it from ordinary insulators. Such conductive edge states are stable, and the transmission of information can be through the spin of electrons, rather than passing charges like conventional materials. Therefore, the topological insulator has better electrical conductivity and does not dissipate, that is, does not generate heat.
  • At least one embodiment of the present invention provides an OLED display device comprising: a substrate substrate; and an anode, a cathode, and an organic functional layer formed between the cathode and the anode, wherein the anode and/or the cathode are A two-dimensional nanostructured topological insulator, and a two-dimensional nanostructured topological insulator is adhered to the substrate by an adhesive layer.
  • the base substrate may be a plain substrate that has not yet formed a functional structure or is formed with an array structure including a thin film transistor.
  • the anode and/or the cathode are topological insulators of two-dimensional nanostructures, that is, topological insulators in which only the anode is a two-dimensional nanostructure; or topological insulators in which only the cathode is a two-dimensional nanostructure; Both are topological insulators of two-dimensional nanostructures.
  • the topological insulator of the two-dimensional nanostructure is a nanometer-sized film formed by a topological insulator, and may be a two-dimensional nano film formed by a topological insulator, a two-dimensional nanosheet, a two-dimensional nanobelt, or the like.
  • Embodiments of the present invention provide an OLED display device, a manufacturing method thereof, and a display device.
  • the anode and/or cathode of the OLED display device are two-dimensional nanostructure topological insulators, and the two-dimensional nanostructure topological insulator has an ultra-high ratio.
  • the surface area and the controllability of the band structure can significantly reduce the proportion of bulk carriers and highlight the topological surface states, and thus the conductivity is better.
  • the anode and/or cathode of the OLED display device is a two-dimensional nanostructure topological insulator, and the transmission resistance of the anode and/or the cathode is small, in particular, the uniformity of the electrode integrally formed in a large area can be improved, thereby improving the brightness uniformity of the OLED display. To improve the display.
  • the topological insulator of the two-dimensional nanostructure is more suitable for the display device because of its high flexibility similar to the graphene structure and the high transmittance which is invisible to the naked eye.
  • the topological insulator includes HgTe, Bi x Sb 1-x , Sb 2 Te 3 , Bi 2 Te 3 , Bi 2 Se 3 , T l BiTe 2 , T l BiSe 2 , Ge 1 Bi 4 Te 7 , Ge 2 At least one of Bi 2 Te 5 , Ge 1 Bi 2 Te 4 , AmN, PuTe, a single layer of tin, and a single layer of tin variant material.
  • Ge 1 Bi 4 Te 7 , Ge 2 Bi 2 Te 5 and Ge 1 Bi 2 Te 4 are chalcogenides.
  • AmN and PuTe are topological insulators with strong interactions.
  • the topological insulator can also be other materials such as a ternary Hessler compound.
  • the topological insulator includes HgTe, Bi x Sb 1-x , Sb 2 Te 3 , Bi 2 Te 3 , Bi 2 Se 3 , T l BiTe 2 , T l BiSe 2 , Ge 1 Bi 4 Te 7 , Ge At least one of 2 Bi 2 Te 5 , Ge 1 Bi 2 Te 4 , AmN, PuTe, single-layer tin, and single-layer tin variant material, that is, the topological insulator may be HgTe or Bi x Sb 1-x or Sb 2 Te 3 or Bi 2 Te 3 or Bi 2 Se 3 or T l BiTe 2 or T l BiSe 2 or Ge 1 Bi 4 Te 7 or Ge 2 Bi 2 Te 5 or Ge 1 Bi 2 Te 4 or AmN or PuTe or a single layer of tin Or a single layer of tin variant material.
  • the topological insulator may also be a mixed material formed of a plurality of the above materials, and may be, for example, a mixed material formed of two of the above materials.
  • the topological insulator may also be a mixed material formed of three of the above materials and the like.
  • the topological insulator is a mixed material of at least two materials, it is also possible to improve the characteristics of the material after mixing by selecting materials having complementary characteristics.
  • the topological insulator can be a single layer of tin or a single layer of tin of a variant material.
  • Single-layer tin is a two-dimensional material with only one tin atom thickness. The level of atomic layer thickness makes it have good light transmittance. Similar to graphene, it has good toughness and high transmittance.
  • a single layer of tin atoms can reach 100% at room temperature and may become a superconductor material.
  • the single-layer tin variant material is formed by surface modification or magnetic doping of a single layer of tin.
  • Surface modification of a single layer of tin may be accomplished by adding functional groups such as -F, -Cl, -Br, -I and -OH to a single layer of tin.
  • the single-layer tin variant material is a tin-fluoride compound formed by surface modification of a single layer of tin with a fluorine atom.
  • F atoms are added to a single-layer tin atom structure, the conductivity of a single layer of tin can reach 100% at temperatures up to 100 ° C, and the properties are still stable.
  • the display device further includes a thin film transistor including a gate, a source, and a drain; the cathode is electrically connected to a drain of the thin film transistor, and the anode is a two-dimensional nanostructure top insulator; or The anode is electrically connected to the drain of the thin film transistor, and the cathode is a topological insulator of a two-dimensional nanostructure.
  • an anode 23 electrically connected to a drain 223 of a thin film transistor 22 is a conductive metal oxide ITO, and a cathode 26 is a metal Ag. Since the display component is in the process of fabrication, the electrode electrically connected to the drain is generally formed in a small area to form a plurality of pixels.
  • the anode 23 as in Figure 1 is typically a small area pixel electrode. Electrodes that are not electrically connected to the thin film transistor are generally formed in a large area, which is equivalent to a common electrode. That is, the cathode 26 as in Fig. 1 is generally a large-area shaped common electrode.
  • the electrode not electrically connected to the thin film transistor is a two-dimensional nanostructure topological insulator, which can improve the conductivity of the large-area electrode, and can reduce the actual driving voltage and the power supply voltage of the light-emitting unit. difference.
  • the thin film transistor includes a gate, a source, and a drain.
  • the above-mentioned gate, source and drain are the three electrodes of the thin film transistor, and the thin film transistors are classified into two types according to the positional relationship of the electrodes.
  • One type is the thin film transistor 22 shown in FIG. 1, the gate 221 is located under the source 222 and the drain 223, and this type is called a bottom gate type thin film transistor; the other is a gate at the source and the drain. Above, this type is called a top gate type thin film transistor.
  • the thin film transistor in the display device provided by at least one embodiment of the present invention may be a bottom gate thin film transistor or a top gate thin film transistor.
  • the OLED display may be as shown in FIG. 1 , and further includes other thin film or layer structures, such as a pixel defining layer 24 , a filling layer 30 between the array substrate 20 and the package substrate 10 , and the like.
  • the embodiments of the present invention only exemplify the film or layer structure related to the technology described in the embodiments of the present invention.
  • At least one embodiment of the present invention provides a display device comprising any of the OLED display devices according to at least one embodiment of the present invention.
  • the display device may be a display device such as an OLED display, and any display product or component such as a television, a digital camera, a mobile phone, a tablet computer, a watch, or the like including the display device.
  • At least one embodiment of the present invention provides a method of fabricating an OLED display device, as shown in FIG. 2, including the following steps 101-102.
  • Step 101 Form a two-dimensional nanostructured anode pattern and/or cathode pattern using a topological insulator.
  • the OLED display device When the OLED display device only has a cathode of a two-dimensional nanostructure, it is only necessary to form a cathode pattern of a two-dimensional nanostructure by using a topological insulator; when the OLED display device has only a topological insulator with a two-dimensional nanostructure as an anode, only the topology needs to be utilized.
  • the insulator forms a two-dimensional nanostructured anode pattern; when the cathode and anode of the OLED display device are both two-dimensional nanostructured topological insulators, the topological insulator is used to form a two-dimensional nanostructured cathode pattern and an anode pattern.
  • the manufacturing method of the above step 101 will be specifically described. As shown in FIG. 3, the following steps 1011 to 1013 are included.
  • Step 1011 Perform pattern etching on the substrate to form a pattern corresponding to the cathode.
  • the substrate may be mica, may also be SrTiO 3 (111), and other substrates on which the topological insulator film can be grown by molecular beam epitaxy.
  • the substrate is mica as an example for detailed description.
  • the substrate is patterned and etched to form a pattern corresponding to the cathode, and the same mask pattern as the cathode pattern may be used, and the mica substrate is plasma-etched under the mask of the mask to obtain the same pattern as the cathode pattern.
  • Mica base is patterned and etched to form a pattern corresponding to the cathode, and the same mask pattern as the cathode pattern may be used, and the mica substrate is plasma-etched under the mask of the mask to obtain the same pattern as the cathode pattern. Mica base.
  • the cathode pattern of the topological insulator that forms the two-dimensional nanostructure is taken as an example.
  • the anode pattern of the topological insulator that forms the two-dimensional nanostructure can be referred to the specific description of the cathode pattern, which will not be described in detail in the embodiments of the present invention.
  • Step 1012 forming a thin film of a two-dimensional nanostructured topological insulator on the surface of the patterned substrate.
  • a Bi 2 Se 3 film is grown by molecular beam epitaxy on the surface of the patterned mica substrate.
  • other topological insulator films can also be grown.
  • the top insulator is Bi 2 Se 3 as an example for detailed description.
  • Step 1013 removing the substrate to obtain a cathode pattern.
  • the mica substrate is dissolved to obtain a cathode pattern of a two-dimensional nanostructured topological insulator.
  • Step 102 forming an anode, an organic functional layer, and a cathode, wherein forming the anode and/or the cathode is to adhere the anode pattern and/or the cathode pattern to the corresponding anode region and/or cathode region through the adhesive layer.
  • the anode pattern of the two-dimensional nanostructured topological insulator may be adhered to the anode region through an adhesive layer, and the cathode may be prepared by metal, that is, the anode is only a two-dimensional nanostructure topological insulator; or, the two-dimensional nanostructure topological insulator
  • the cathode pattern is adhered to the cathode region through the adhesive layer, and the anode can be prepared by metal, that is, the cathode is only a two-dimensional nanostructure topological insulator; or the anode pattern of the two-dimensional nanostructure topological insulator can be adhered through the adhesive layer
  • the anode region has a cathode pattern of a two-dimensional nanostructured topological insulator adhered to the cathode region through an adhesive layer, that is, the cathode and the anode are two-dimensional nanostructure topological insulators.
  • the method further includes: forming a thin film transistor, and forming the thin film transistor specifically includes forming a gate, a source, and a drain.
  • the cathode is electrically connected to the drain of the thin film transistor, and forming the anode can be performed, for example, by forming a first adhesive layer and adhering the anode pattern to the anode region through the first adhesive layer. Or, anode and thin film crystal
  • the drains of the tubes are electrically connected to form a cathode, for example, by forming a second adhesive layer and adhering the cathode pattern to the cathode region through the second adhesive layer.
  • the electrode electrically connected to the drain may be a metal electrode or an ITO electrode or the like, and the electrode not electrically connected to the drain is a two-dimensional nanostructure topological insulator.
  • forming the first adhesive layer may be performed by forming a first adhesive layer on one surface of the anode pattern; then adhering the anode pattern to the anode region through the first adhesive layer specifically includes: forming a first adhesive layer The anode pattern is attached to the anode region on the base substrate.
  • forming the first adhesive layer may be performed by: forming a first adhesive layer on the anode region of the base substrate; and then adhering the anode pattern to the anode region through the first adhesive layer comprises: attaching the anode pattern to the first On an adhesive layer.
  • forming the second adhesive layer may be performed by forming a second adhesive layer on one side surface of the cathode pattern; then adhering the cathode pattern to the cathode region through the second adhesive layer specifically includes: forming a second adhesive layer The cathode pattern is attached to the cathode region on the base substrate.
  • forming the second adhesive layer may be performed by: forming a second adhesive layer in the cathode region of the base substrate; and then adhering the cathode pattern to the cathode region through the second adhesive layer comprises: attaching the cathode pattern to the first Two adhesive layers.
  • the method includes the following steps 201-205:
  • Step 201 forming a thin film transistor.
  • a gate electrode, an active layer, and a source and drain are formed by a patterning process.
  • Step 202 forming an anode electrically connected to the drain of the thin film transistor.
  • the anode may be formed by forming a conductive metal oxide thin film using ITO and by a patterning process.
  • Step 203 forming an organic functional layer.
  • HTL layer hole transporting functional layer
  • HIL layer hole injecting functional layer
  • EML layer light emitting functional layer
  • EIL layer electron injecting functional layer
  • ETL layer electron transport functional layer
  • Step 204 Form a cathode pattern of a two-dimensional nanostructured topological insulator.
  • Step 205 forming an adhesive layer on one side surface of the cathode pattern, and forming a cathode with an adhesive layer The pattern is attached to the cathode region on the base substrate.
  • the OLED display device formed by the above steps 201 to 205 has only the cathode as a two-dimensional nanostructure topological insulator.
  • the specific manufacturing steps are only provided as an example.
  • the foregoing step 204 is formed only before the step 205, and there is no necessary relationship between the steps and the other steps. Description.

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Abstract

一种OLED显示器件及其制作方法、显示装置，该OLED显示器件包括：衬底基板（21）以及形成在该衬底基板（21）上的阳极（23）、阴极（26）以及位于阴极（26）和阳极（23）之间的有机功能层（25），该阳极（23）和/或该阴极（26）为二维纳米结构的拓扑绝缘体，且该二维纳米结构的拓扑绝缘体通过黏着层粘附至该衬底基板（21）上。该OLED显示器件克服了OLED显示器件中由于金属电极的传输电阻大、压降较大，造成显示亮度不均的问题。

Description

OLED显示器件及其制作方法、显示装置 技术领域
本发明的实施例涉及一种OLED显示器件及其制作方法、显示装置。
背景技术
有机发光器件(Organic Light Emitting Diode，OLED)显示器件是新一代的显示器，与液晶显示器相比，具有很多优点，例如：自发光，响应速度快，宽视角等，可以用于柔性显示，透明显示，3D显示等。有机发光器件包括阳极、阴极以及有机功能层，其主要的工作原理是在阳极和阴极所形成电场的驱动下，载流子注入有机功能层且在其中复合而发光。
有机发光器件的阴极一般采用薄层金属银制备，阳极一般采用氧化铟锡(Indium tin oxide，ITO)制备。由于薄层金属银以及ITO的电阻率较高，尤其是对于大面积成型的阴极而言，采用薄层金属银制备的阴极电阻率较大，压降(IR drop)较大，造成OLED器件的实际驱动电压与电源电压有较大差异，因此在大尺寸的OLED显示器上，会出现大面积的亮度不均匀，影响显示效果。
发明内容
本发明至少一实施例提供一种OLED显示器件及其制作方法、显示装置，避免了OLED显示器件中阴极和阳极的传输电阻大的问题。
本发明至少一实施例提供了一种OLED显示器件，其包括：衬底基板以及形成在所述衬底基板上的阳极、阴极以及位于所述阴极和所述阳极之间的有机功能层，所述阳极和/或所述阴极为二维纳米结构的拓扑绝缘体，且所述二维纳米结构的拓扑绝缘体通过黏着层粘附在所述衬底基板上。
本发明至少一实施例提供了一种OLED显示器件的制作方法，其包括：利用拓扑绝缘体形成二维纳米结构的阳极图案和/或阴极图案；形成阳极、有机功能层以及阴极，其中，形成所述阳极和/或所述阴极是将所述阳极图案和/或所述阴极图案通过黏着层粘附在对应的阳极区和/或阴极区。
本发明至少一实施例提供了一种显示装置，包括本发明实施例提供的任一所述的OLED显示器件。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种OLED显示器件示意图；
图2为本发明一实施例提供的OLED显示器件的制作方法示意图；
图3为本发明一实施例提供的形成二维纳米结构的拓扑绝缘体的阴极图案的方法示意图；
图4为本发明另一实施例提供的OLED显示器件的制作方法示意图。
附图标记：
10-封装基板；11-第二衬底；12-黑矩阵层；13-彩色膜层；14-保护层；20-阵列基板；21-第一衬底；22-薄膜晶体管；221-栅极；222-源极；223-漏极；23-阳极；24-像素界定层；25-有机功能层；26-阴极；30-填充层。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1示出了一种OLED显示器，该OLED显示器包括：对合的阵列基板20以及封装基板10。阵列基板20包括第一衬底21、薄膜晶体管22(包括栅极221、源极222和漏极223)、与薄膜晶体管22的漏极223连接的阳极23、位于阳极23之上的有机功能层25、位于有机功能层25之上的阴极26。封装基板10包括第二衬底11、彩色膜层13、黑矩阵层12以及保护层14；阵列基板20和封装基板10之间设置有填充物30。有机功能层25还可以进一步细分为：空穴传输功能层(HTL层)、发光功能层(EML层)、电子传输 功能层(ETL层)等。
拓扑绝缘体(topological insulator)是近年来新提出的一种物质形态。拓扑绝缘体的体能带结构和普通绝缘体一样，都在费米能级处有一有限大小的能隙，但是在它的边界或表面却是无能隙的、狄拉克(Dirac)型、自旋非简并的导电边缘态，这是它有别于普通绝缘体的最独特的性质。这样的导电边缘态是稳定存在的，信息的传递可以通过电子的自旋，而不像传统材料通过电荷。因此，拓扑绝缘体的导电性能更好且不耗散即不发热。
本发明至少一实施例提供了一种OLED显示器件，包括：衬底基板以及形成在衬底基板上的阳极、阴极以及位于阴极和阳极之间的有机功能层，其中，阳极和/或阴极为二维纳米结构的拓扑绝缘体，且二维纳米结构的拓扑绝缘体通过黏着层粘附在衬底基板上。该衬底基板可以是尚未形成功能结构的素基板或形成有包括薄膜晶体管的阵列结构。
需要说明的是，阳极和/或阴极为二维纳米结构的拓扑绝缘体，即可以是仅阳极为二维纳米结构的拓扑绝缘体；或者仅阴极为二维纳米结构的拓扑绝缘体；还可以阴极和阳极均为二维纳米结构的拓扑绝缘体。
二维纳米结构的拓扑绝缘体即由拓扑绝缘体形成的纳米尺寸厚度的膜，可以是由拓扑绝缘体形成的二维纳米薄膜、二维纳米薄片、二维纳米带等。
本发明的实施例提供一种OLED显示器件及其制作方法、显示装置，所述OLED显示器件的阳极和/或阴极为二维纳米结构的拓扑绝缘体，二维纳米结构的拓扑绝缘体具有超高比表面积和能带结构的可调控性，能显著降低体态载流子的比例和凸显拓扑表面态，进而导电性能更好。
OLED显示器件的阳极和/或阴极为二维纳米结构的拓扑绝缘体，则阳极和/或阴极的传输电阻小，尤其可以改善大面积一体成型的电极的均一性，进而提高OLED显示器的亮度均匀性，改善显示效果。
需要说明的是，二维纳米结构的拓扑绝缘体因其与石墨烯结构类似具有较高的柔韧性，以及基本肉眼不可见的高透过率，使其更适用于显示器件。
例如，所述拓扑绝缘体包括HgTe、BixSb1-x、Sb2Te3、Bi2Te3、Bi2Se3、TlBiTe2、TlBiSe2、Ge1Bi4Te7、Ge2Bi2Te5、Ge1Bi2Te4、AmN、PuTe、单层锡以及单层锡变体材料中的至少一种。
Ge1Bi4Te7、Ge2Bi2Te5以及Ge1Bi2Te4属于硫属化物。AmN以及PuTe属 于具有强相互作用的拓扑绝缘体。当然，拓扑绝缘体还可以是三元赫斯勒化合物等其他材料。
更具体的，例如拓扑绝缘体包括HgTe、BixSb1-x、Sb2Te3、Bi2Te3、Bi2Se3、TlBiTe2、TlBiSe2、Ge1Bi4Te7、Ge2Bi2Te5、Ge1Bi2Te4、AmN、PuTe、单层锡以及单层锡变体材料中的至少一种，即拓扑绝缘体可以为HgTe或BixSb1-x或Sb2Te3或Bi2Te3或Bi2Se3或TlBiTe2或TlBiSe2或Ge1Bi4Te7或Ge2Bi2Te5或Ge1Bi2Te4或AmN或PuTe或单层锡或单层锡变体材料。或者，拓扑绝缘体还可以是上述材料中的多种形成的混合材料，例如可以是上述材料中的两种形成的混合材料。当然，拓扑绝缘体也可以是上述材料中的三种形成的混合材料等。而且，当拓扑绝缘体为至少两种材料形成的混合材料，则还可以通过选择具有互补特性的材料混合，以提高混合后材料的特性。
在本发明至少一实施例中，拓扑绝缘体可以为单层锡或单层锡的变体材料。单层锡为只有一个锡原子厚度的二维材料，原子层厚度的级别使其具有较好的光透过率；与石墨烯类似，具有较好的韧性，且透过率高。
单层锡原子在常温下导电率可以达到100％，可能成为一种超级导体材料。具体的，单层锡的变体材料是通过对单层锡进行表面修饰或磁性掺杂形成。对单层锡进行表面修饰可以是对单层锡添加-F,-Cl,-Br,-I和–OH等功能基实现其改性。
在本发明至少一实施例中，单层锡的变体材料为对单层锡进行氟原子的表面修饰，形成的锡氟化合物。当添加F原子到单层锡原子结构中时，单层锡在温度高达100℃时导电率能达到100％，且性质依然稳定。
在本发明至少一实施例中，显示器件还包括薄膜晶体管，薄膜晶体管包括栅极、源极和漏极；阴极与薄膜晶体管的漏极电连接，阳极为二维纳米结构的拓扑绝缘体；或者，阳极与薄膜晶体管的漏极电连接，阴极为二维纳米结构的拓扑绝缘体。
如图1所示的一种显示器件中，与薄膜晶体管22漏极223电连接的阳极23为导电金属氧化物ITO，阴极26为金属Ag。由于显示元器件在制作过程中，与漏极电连接的电极一般为小面积成型，形成多个像素。如图1中的阳极23一般为小面积的像素电极。不与薄膜晶体管电连接的电极一般为大面积成型，相当于公共电极。即如图1中的阴极26一般为大面积成型的公共电极。 对于大面积成型的电极来说，电阻大容易造成电极的压降大，发光单元的实际驱动电压与电源电压的差异大，表现为大面积的亮度不均匀。因此，在本发明至少一实施例中，不与薄膜晶体管电连接的电极为二维纳米结构的拓扑绝缘体，可以提高大面积电极的导电率，能够减小发光单元的实际驱动电压与电源电压的差异。
薄膜晶体管包括栅极、源极和漏极。上述的栅极、源极和漏极是薄膜晶体管的三个电极，根据电极的位置关系将薄膜晶体管分为两类。一类是如图1所示的薄膜晶体管22，栅极221位于源极222和漏极223的下面，这类被称为底栅型薄膜晶体管；一类是栅极位于源极和漏极的上面，这类被称为顶栅型薄膜晶体管。本发明至少一实施例提供的显示器件中的薄膜晶体管可以底栅型薄膜晶体管也可以是顶栅型薄膜晶体管。
需要说明的是，OLED显示器可以是如图1所示，还包括其他薄膜或层结构，例如像素界定层24，阵列基板20和封装基板10之间的填充层30等。本发明实施例仅列举与本发明的实施例所述的技术相关的薄膜或层结构，对于OLED显示器的具体设置可以参照已知技术，本发明不作具体限制。
本发明至少一实施例提供了一种显示装置，包括本发明至少一实施例提供的任一所述的OLED显示器件。所述显示装置可以为OLED显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、平板电脑、手表等任何具有显示功能的产品或者部件。
本发明至少一实施例提供了一种OLED显示器件的制作方法，如图2所示，包括下面的步骤101～102。
步骤101、利用拓扑绝缘体形成二维纳米结构的阳极图案和/或阴极图案。
当OLED显示器件只有阴极为二维纳米结构的拓扑绝缘体，则只需要利用拓扑绝缘体形成二维纳米结构的阴极图案；当OLED显示器件只有阳极为二维纳米结构的拓扑绝缘体，则只需要利用拓扑绝缘体形成二维纳米结构的阳极图案；当OLED显示器件的阴极和阳极均为二维纳米结构的拓扑绝缘体，则利用拓扑绝缘体形成二维纳米结构的阴极图案和阳极图案。
以利用拓扑绝缘体形成二维纳米结构的阴极图案为例，具体说明上述步骤101的制作方法，如图3所示，包括下面的步骤1011～步骤1013。
步骤1011、对基底进行图案化刻蚀，形成对应阴极的图案。
例如，基底可以是云母，还可以是SrTiO3(111)，以及通过分子束外延法可在其表面生长拓扑绝缘体薄膜的其他基底。本实施例中以所述基底为云母为例进行详细说明。
对基底进行图案化刻蚀形成对应阴极的图案，可以是采用与阴极图案相同的掩膜板，在掩膜板的掩膜下对云母基底进行等离子体刻蚀，得到与阴极图案相同的图案化的云母基底。
上述仅以形成二维纳米结构的拓扑绝缘体的阴极图案为例，形成二维纳米结构的拓扑绝缘体的阳极图案可参考形成阴极图案的具体说明，本发明实施例不作赘述。
步骤1012、在图案化的基底表面形成二维纳米结构的拓扑绝缘体的薄膜。
例如，在图案化的云母基底表面，通过分子束外延生长Bi2Se3薄膜。当然，还可以生长其他拓扑绝缘体薄膜，本实施例以拓扑绝缘体为Bi2Se3为例进行详细说明。
步骤1013、将基底去除，得到阴极图案。
将云母基底溶解掉，得到二维纳米结构的拓扑绝缘体的阴极图案。
步骤102、形成阳极、有机功能层以及阴极，其中，形成阳极和/或阴极是将阳极图案和/或阴极图案通过黏着层粘附在对应的阳极区和/或阴极区。
可以是将二维纳米结构的拓扑绝缘体的阳极图案通过黏着层粘附在阳极区，阴极可以采用金属制备，即仅阳极为二维纳米结构的拓扑绝缘体；或者，将二维纳米结构的拓扑绝缘体的阴极图案通过黏着层粘附在阴极区，阳极可以采用金属制备，即仅阴极为二维纳米结构的拓扑绝缘体；还可以是将二维纳米结构的拓扑绝缘体的阳极图案通过黏着层粘附在阳极区形，将二维纳米结构的拓扑绝缘体的阴极图案通过黏着层粘附在阴极区，即阴极和阳极均为二维纳米结构的拓扑绝缘体。
例如，在形成阳极、有机功能层以及阴极之前，即在上述步骤102之前所述方法还包括：形成薄膜晶体管，形成薄膜晶体管具体包括形成栅极、源极和漏极。
阴极与薄膜晶体管的漏极电连接，形成阳极例如可如下进行：形成第一黏着层，将阳极图案通过第一黏着层粘附在阳极区。或者，阳极与薄膜晶体 管的漏极电连接，形成阴极例如可如下进行：形成第二黏着层，将阴极图案通过第二黏着层粘附在阴极区。
使得与漏极电连接的电极可以是金属电极或ITO电极等，不与漏极电连接的电极为二维纳米结构的拓扑绝缘体。
例如，形成第一黏着层可如下进行：在阳极图案的一侧表面形成第一黏着层；则将所述阳极图案通过第一黏着层粘附在阳极区具体包括：将形成有第一黏着层的阳极图案贴附在衬底基板上的阳极区。
或者，形成第一黏着层可如下进行：在衬底基板的阳极区形成第一黏着层；则将所述阳极图案通过第一黏着层粘附在阳极区具体包括：将阳极图案贴附在第一黏着层上。
例如，形成第二黏着层可如下进行：在阴极图案的一侧表面形成第二黏着层；则将所述阴极图案通过第二黏着层粘附在阴极区具体包括：将形成有第二黏着层的阴极图案贴附在衬底基板上的阴极区。
或者，形成第二黏着层可如下进行：在衬底基板的阴极区形成第二黏着层；则将所述阴极图案通过第二黏着层粘附在阴极区具体包括：将阴极图案贴附在第二黏着层上。
下面，提供一具体实施例用于说明本发明实施例提供的显示器件的制作方法，如图4所示，所述方法包括下面的步骤201～205：
步骤201、形成薄膜晶体管。
例如，通过构图工艺形成栅极、有源层以及源漏极。
步骤202、形成与薄膜晶体管漏极电连接的阳极。
阳极可以是利用ITO形成导电金属氧化物薄膜并通过构图工艺形成。
步骤203、形成有机功能层。
例如，形成空穴传输功能层(HTL层)、空穴注入功能层(HIL层)、发光功能层(EML层)、电子注入功能层(EIL层)以及电子传输功能层(ETL层)。
步骤204、形成二维纳米结构的拓扑绝缘体的阴极图案。
形成二维纳米结构的拓扑绝缘体的阴极可参考上述步骤1011-步骤1013。
步骤205、在阴极图案的一侧表面形成黏着层，将形成有黏着层的阴极 图案贴附在衬底基板上的阴极区。
通过上述步骤201-步骤205形成的OLED显示装置仅阴极为二维纳米结构的拓扑绝缘体。当然，上述具体的制作步骤仅是提供的一种示例，例如上述步骤204仅是在步骤205之前形成，其与其他步骤之间没有必然的先后关系，本发明实施例仅以上述为例进行详细说明。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年8月5日递交的中国专利申请第201410381309.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (11)

  1. 一种OLED显示器件，包括：衬底基板以及形成在所述衬底基板上的阳极、阴极以及位于所述阴极和所述阳极之间的有机功能层，
    其中，所述阳极和/或所述阴极为二维纳米结构的拓扑绝缘体，且所述二维纳米结构的拓扑绝缘体通过黏着层粘附在所述衬底基板上。
  2. 根据权利要求1所述的显示器件，其中，所述拓扑绝缘体包括HgTe、BixSb1-x、Sb2Te3、Bi2Te3、Bi2Se3、TlBiTe2、TlBiSe2、Ge1Bi4Te7、Ge2Bi2Te5、Ge1Bi2Te4、AmN、PuTe、单层锡以及单层锡变体材料中的至少一种。
  3. 根据权利要求2所述的显示器件，其中，所述单层锡的变体材料为通过对单层锡进行表面修饰或磁性掺杂形成。
  4. 根据权利要求2所述的显示器件，其中，所述单层锡的变体材料为对单层锡进行氟原子的表面修饰形成的锡氟化合物。
  5. 根据权利要求1-4任一项述的显示器件，还包括薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极；
    其中，所述阴极与所述薄膜晶体管的漏极电连接，所述阳极为二维纳米结构的拓扑绝缘体；或者，
    所述阳极与所述薄膜晶体管的漏极电连接，所述阴极为二维纳米结构的拓扑绝缘体。
  6. 一种OLED显示器件的制作方法，包括：
    利用拓扑绝缘体形成二维纳米结构的阳极图案和/或阴极图案；
    形成阳极、有机功能层以及阴极，
    其中，形成所述阳极和/或所述阴极是将所述阳极图案和/或所述阴极图案通过黏着层粘附在对应的阳极区和/或阴极区。
  7. 根据权利要求6所述的制作方法，在形成阳极、有机功能层以及阴极之前，所述方法还包括：形成薄膜晶体管，所述形成薄膜晶体管包括形成栅极、源极和漏极；其中，
    所述阴极与所述薄膜晶体管的漏极电连接，形成第一黏着层，将所述阳极图案通过第一黏着层粘附在阳极区；或者，
    所述阳极与所述薄膜晶体管的漏极电连接，形成第二黏着层，将所述阴 极图案通过第二黏着层粘附在阴极区。
  8. 根据权利要求7所述的制作方法，其中，
    在所述阳极图案的一侧表面形成第一黏着层，将形成有第一黏着层的阳极图案贴附在所述衬底基板上的阳极区；或者，
    在所述衬底基板的阳极区形成第一黏着层，将阳极图案贴附在所述第一黏着层上。
  9. 根据权利要求7所述的制作方法，其中，
    在所述阴极图案的一侧表面形成第二黏着层，将形成有第二黏着层的阴极图案贴附在所述衬底基板上的阴极区；或者，
    在所述衬底基板的阴极区形成第二黏着层，将阴极图案贴附在所述第二黏着层上。
  10. 根据权利要求6所述的制作方法，其中，所述利用拓扑绝缘体形成二维纳米结构的阳极图案和/或阴极图案包括：
    对基底进行图案化刻蚀，形成对应阳极的图案或阴极的图案；
    在图案化的基底表面形成二维纳米结构的拓扑绝缘体的薄膜；
    将所述基底去除，得到二维纳米结构的拓扑绝缘体的阳极图案或阴极图案。
  11. 一种显示装置，包括如权利要求1-5任一项所述的OLED显示器件。
PCT/CN2014/089430 2014-08-05 2014-10-24 Oled显示器件及其制作方法、显示装置 WO2016019635A1 (zh)

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