WO2016008182A1 - 一种掩膜板、阵列基板制作方法及阵列基板 - Google Patents

一种掩膜板、阵列基板制作方法及阵列基板 Download PDF

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Publication number
WO2016008182A1
WO2016008182A1 PCT/CN2014/083742 CN2014083742W WO2016008182A1 WO 2016008182 A1 WO2016008182 A1 WO 2016008182A1 CN 2014083742 W CN2014083742 W CN 2014083742W WO 2016008182 A1 WO2016008182 A1 WO 2016008182A1
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WIPO (PCT)
Prior art keywords
light
array substrate
mask
trunk
disposed
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Ceased
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PCT/CN2014/083742
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English (en)
French (fr)
Inventor
施明宏
姜佳丽
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/416,831 priority Critical patent/US9842865B2/en
Publication of WO2016008182A1 publication Critical patent/WO2016008182A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a mask and a method for fabricating an array substrate using the mask and a corresponding array substrate. Background technique
  • the conventional HVA (High Vertical Alignment) pixel electrode is a Fine Slit (modified slit) structure.
  • the slit portion is not provided with the pixel electrode, which makes the portion of the portion less resistant to the electric field, and thus has less control power to the liquid crystal molecules. Therefore, dark streaks appear in this portion, thereby losing liquid crystal efficiency, thereby losing the transmittance of the liquid crystal panel.
  • a new pixel electrode having a three-dimensional structure has appeared. The pixel electrode of the three-dimensional structure covers the port area of the pixel unit.
  • the array substrate having the pixel electrodes having the above-described three-dimensional structure is formed, and etching of the insulating layers in the contact holes and the stereoscopic structure pixel electrodes is usually completed at the same time. That is to say, a vertical structure of the contact hole and the pixel electrode is simultaneously realized by using one mask. This method can effectively save the cost of the mask and the process, but partially etch away all of the insulating layers in the three-dimensional structure pixel electrode. If a shield electrode is added in order to increase the aperture ratio of the liquid crystal panel at this time, the shield electrode may be brought into contact with the pixel electrode. Therefore, in this case, the shield electrode cannot be added, and the aperture ratio of the liquid crystal panel is lowered.
  • the present invention provides a mask plate capable of forming a three-dimensional pixel electrode and capable of improving the opening ratio of the liquid crystal panel, and a corresponding array substrate manufacturing method and array substrate.
  • a mask is provided, the mask comprising:
  • An opaque region comprising an intermediate vertical trunk, an intermediate horizontal master, and a branch extending from the intermediate vertical trunk and the intermediate horizontal master, the intermediate vertical trunk and the intermediate level
  • the trunk forms a certain angle with the branch respectively;
  • the light transmitting region including a first light transmitting portion disposed between the branches,
  • the light-transmitting unit is disposed on the first light-transmitting portion, and the light interference unit is configured to process light having a first light intensity into light having a second light intensity, wherein the first light is strong In the second light intensity.
  • the light-transmitting region further includes a second light-transmitting portion for directly introducing the light of the first light intensity to form a contact corresponding to the array substrate hole.
  • the shape of the light-receiving unit is a grid shape, a strip shape or a sheet shape.
  • the light interference unit is disposed at an intermediate position of the first light transmitting portion.
  • the light ray unit is made of an opaque material or a semi-transparent material. According to another aspect of the present invention, there is provided a method of fabricating an array substrate, the insulating structure being formed using the mask sheet of any of the above.
  • the forming of the first metal conductive layer further includes forming a shield electrode.
  • an array substrate comprising: a substrate:
  • the pixel unit including,
  • the pixel electrode is disposed in the opening region, and an insulating structure is formed between the pixel electrode and the substrate, and the insulating structure is formed by etching using the mask plate according to any one of the above.
  • the insulating structure comprises an intermediate vertical main thousand, an intermediate horizontal trunk and branches extending from the intermediate vertical main thousand and the intermediate horizontal main thousand, the intermediate vertical trunk Forming an angle with the intermediate horizontal main thousand and its branch respectively, wherein a groove having a bottom surface of the insulating material is included between the adjacent two branches.
  • a shielding electrode in the same layer as the gate line is further disposed between the data line and the pixel electrode for shielding an electrical signal between the data line and the pixel electrode.
  • the light-receiving unit is disposed on the first light-transmitting portion of the light-transmitting region on the mask, so that the insulating material on the array substrate corresponding to the portion cannot be etched to the end, and the insulating material and the mask which are not etched at the portion
  • the insulating material on the array substrate corresponding to the opaque region on the board forms an insulating structure. Since the presence of the insulating structure can provide a shield electrode between the pixel electrode and the data line, the distance between the pixel electrode and the data line is shortened. This design improves the pixel
  • the aperture ratio of the unit improves the transmittance of the liquid crystal panel.
  • 1 is a plan view showing a conventional array substrate having a three-dimensional structure pixel electrode
  • FIG. 2 is a partial schematic view showing a mask corresponding to the pixel electrode of FIG. 1;
  • Figure 3 is a picture! a sectional structure diagram along the A-A direction
  • FIG. 4 is a partial schematic view showing an embodiment of a mask according to the present invention.
  • Figure 5 is a partial schematic view showing another embodiment of the mask according to the present invention.
  • FIG. 6 is a partial schematic view showing still another embodiment of the mask according to the present invention.
  • Figure 7 is a plan view showing an embodiment of an array substrate made by using any one of the masks of Figures 4 to 5 of the present invention.
  • Figure 8 is a cross-sectional structural view of Figure 7 along the B-B direction;
  • the steps illustrated in the flowchart of the Pf diagram may be performed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, The steps shown or described are performed in a different order than here.
  • FIG. 1 is a plan view showing a planar structure of an array substrate having a three-dimensional structure pixel electrode.
  • the array substrate includes a substrate 1 and a pixel unit.
  • the pixel unit includes a machine line 2 disposed on the substrate 1, and a data line 3,
  • the gate line 2 is disposed in parallel with the common electrode line 6. Both the epipolar line 2 and the common electrode line 6 are disposed perpendicular to the data line 3.
  • the TFT 4 is disposed on the gate line 2, and has a gate, a source, and a drain electrically connected to the gate line 2, the data line 3, and the pixel electrode 5, respectively. In one arrangement, the drain of the TFT 4 is connected to the pixel electrode 5 through the contact hole 7.
  • the pixel electrode 5 is disposed in an opening region formed by the electrode line 2, the data line 3, and the common electrode line 6.
  • the pixel electrode layer in the figure is supported by a "m"-shaped insulating structure.
  • the insulating structure includes an intermediate vertical stem, an intermediate horizontal stem, and branches extending therefrom.
  • the intermediate vertical stem, the intermediate horizontal stem and the branch are raised insulating portions which, together with the applied pixel electrode layer, are referred to as ribs 5a.
  • the portion between each of the ridges is divided into a groove 5b.
  • the bottom of the recess 5b includes only the pixel electrode layer. In this case, the applied pixel electrode layer is in direct contact with the substrate 1.
  • a mask pattern corresponding to the pixel electrode of FIG. 1 is formed.
  • the opaque region 5c in the figure corresponds to the rib 5a
  • the first light-transmitting portion in the figure 5d corresponds to the groove 513.
  • reference numeral 7a denotes that the second light transmitting portion corresponds to the contact hole 7 formed on the array substrate.
  • Figure 3 shows the cross-sectional structure of Figure 1 along A-A side. As shown in the figure, the entire surface of the insulating structure covers the pixel electrode layer. The pixel electrode layer supported by the insulating structure is also the pixel electrode 5. A gate insulating layer 8 covers the substrate 1. The deposition purification layer 9 covers the surface of the data line 3 and the pole insulating layer 8.
  • a mask plate as shown in Fig. 2 can be used to simultaneously realize the contact hole structure and the three-dimensional structure of the pixel electrode. That is to say, the contact hole and the m-shaped insulating structure are completed in the same process using a mask.
  • this method can effectively save the cost of the mask and the piercing process, the insulating material layer between the adjacent branches may be completely etched during the manufacturing process.
  • the transparent conductive material when the transparent conductive material is coated to form the pixel electrode layer, the transparent conductive material may be in direct contact with the substrate 1.
  • the insulating layer between the pixel electrode layer of the groove portion and the substrate 1 is completely etched away, causing the pixel electrode 5 to come into contact with the substrate 1.
  • a shield structure such as a shield electrode is often disposed between the pixel electrode 5 and the data line 3.
  • the shield electrode is used to shield the electrical signal between the pixel electrode 5 and the data line 3.
  • the pixel electrode 5 can be placed as close as possible to the data line 3, thereby expanding the area of the pixel unit opening area as much as possible.
  • the shield electrode and the twisted wire are usually formed in the same process. If the insulating layer of the groove portion of the pixel electrode of the three-dimensional structure is completely etched away, the pixel electrode 5 covered thereon is in contact with the substrate 1. Since the shield electrode is also in direct contact with the substrate 1 and is located between the pixel electrode 5 and the data line 3, it is possible to make contact with the pixel electrode layer on the groove without the bottom. During the pricking process, once the translation occurs between different layers, it may lead to the pixel electrode layer. Electrical contact with the shield electrode is not allowed in practice.
  • One solution that can be solved is to form a layer difference between the pixel electrode and the shield electrode. The following is a detailed description of how to form the layer difference in the fabrication of the array substrate by an improved mask.
  • the mask of the present invention includes an opaque region 5c and a light transmissive region.
  • the opaque region 5c is the same as that of FIG. 2, and also includes a middle vertical trunk, an intermediate horizontal master and a branch extending from the middle vertical trunk and the intermediate horizontal trunk, and the intermediate vertical trunk and the intermediate horizontal master are respectively extended therefrom The resulting branches form a certain angle.
  • the opaque region as a whole forms a "meter"-shaped pattern.
  • the light transmitting region is divided into a first light transmitting portion 5d and a second light transmitting portion 7a.
  • the first light transmitting portion 5d is disposed between the branches of the opaque region 5c.
  • An optical interference unit is disposed in the middle of the first light transmitting portion 5d.
  • the light interference unit can pass light of the first light intensity having a large light intensity to the light of the second light intensity having a small light intensity after passing through the first light transmitting portion 5d.
  • the above light ray unit may be made of an opaque material, and of course, it may be made of a semi-transparent material as needed.
  • the light-receiving unit is arranged in a grid shape as shown in FIG.
  • light is incident on the array substrate to be etched through the mesh portion.
  • the portion of the array substrate corresponding to the light-shielding portion of the grid can also be illuminated, so that the insulating layer corresponding to the portion on the array substrate can be etched away.
  • the light intensity of the through-light interference unit has been weakened, it is possible to ensure that a portion of the insulating material remains at the corresponding portion of the portion of the mask during the same etching time.
  • the size of the grid can be set according to actual needs, which is basically related to the thickness of the insulating material to be retained, the lithography time, and the applied light intensity.
  • the light interference unit is arranged in the shape of a strip as shown in FIG.
  • light can be incident on the array substrate to be etched through the strip gap.
  • the portion of the array substrate corresponding to the strip light-shielding portion can also be illuminated, so that the insulating layer corresponding to the portion on the array substrate can be etched away.
  • the transmitted light intensity is weakened, it is ensured that a part of the insulating material remains at the position corresponding to the portion of the mask during the same etching time.
  • the spacing between the strips can be set according to actual needs, which is substantially related to the thickness of the insulating material to be retained, the lithography time, and the applied illumination intensity.
  • a mesh or a bar-shaped optical interference unit may be disposed in contact with both sides of the branch to occupy the entire first light transmitting portion 5d, as shown in Figs.
  • a mesh or strip-like optical interference unit may be provided only between adjacent branches, which maintains a certain gap from both sides of the branch.
  • the light ray unit may also be disposed as a sheet-like structure along the length of the light-transmitting region, as shown in FIG.
  • light is incident on the array substrate to be etched through the light transmitting portions on both sides of the sheet structure.
  • the portion of the array substrate corresponding to the sheet structure can also be illuminated, so that the insulating layer corresponding to the portion on the array substrate can be etched.
  • the light intensity has been somewhat weakened, so the same etching time and At the initial light intensity, the insulating material on the portion of the array substrate corresponding to the optical interference unit of the sheet structure is not completely etched, thereby being compared with the insulating material which has previously retained a certain thickness.
  • the corresponding portion of the insulating layer is etched to the base portion.
  • the distance between the sheet-shaped optical interference unit and one side of the adjacent branch may be set to be between 0 acknowledged2 um and 0,5 U m.
  • the effective light-transmitting area of the optical interference unit may also be changed. Controlling the etching depth of the insulating material on the corresponding array substrate.
  • the shape of the arrangement of the light-receiving unit is not limited to the above-mentioned ones, and any shape setting that can affect the light intensity can be used as the light-based unit here.
  • the second light transmitting portions 7a corresponding to Figs. 4, 5, and 6, respectively, are disposed to be completely transparent. This portion can directly introduce the original light having the first light intensity, thereby correspondingly forming contact holes on the array substrate.
  • the use of the mask of the present invention to fabricate a corresponding array substrate mainly comprises the following steps.
  • a first metal film is deposited on the substrate to form a first metal conductive layer.
  • the gate lines and the common electrode lines are formed, and at the same time, the shield electrodes connected to the common electrode lines are formed.
  • a first insulating material and a semiconductor material are then deposited over the first metal conductive layer to form an intermediate layer.
  • a second metal film is then deposited over the intermediate layer to form a second metal conductive layer. Also included in the process is the formation of the source and drain of the TFT.
  • the insulating structure is then formed on the second metal conductive layer and the exposed intermediate layer using the mask as described above.
  • the insulating material on the array substrate corresponding to the opaque regions on the mask is not etched to form a raised structure under the condition of a positive photoresist.
  • the light transmitting region on the mask is provided as two types of a first light transmitting portion and a second light transmitting portion.
  • the first light transmitting portion is provided with a light ray unit. When the light of the first light intensity passes through the light interference unit, it becomes light of the second light intensity whose intensity is weakened.
  • An insulating structure having a three-dimensional structure is formed of an insulating material having a convex and concave structure.
  • the second light transmitting portion directly introduces the light of the first light intensity into the contact holes corresponding to the array substrate.
  • a transparent conductive village material is coated on the insulating structure to form a pixel electrode.
  • Figure 7 is a plan view showing an embodiment of an array substrate fabricated using the mask and method described above.
  • the array substrate includes a substrate 1 and a pixel unit.
  • the pixel unit includes a gate line 2, a data line 3, a TFT 4, a pixel electrode 5, and a common electrode line 6 which are disposed on the substrate 1.
  • the » line 2 is disposed in parallel with the common electrode line 6.
  • Both the gate line 2 and the common electrode line 6 are disposed perpendicular to the data line 3.
  • the TFT 4 is disposed on the epipolar line 2, and its drain, source, and drain are electrically connected to the «line 2, the data line 3, and the pixel electrode 5, respectively. Wherein the drain of the TFT 4 is in contact
  • the hole 7 is connected to the pixel electrode 5.
  • the TFT 4 is disposed on the gate line to avoid occupying the opening area of the pixel unit, and is advantageous for increasing the aperture ratio of the pixel unit.
  • the pixel electrode 5 is disposed in an opening region surrounded by the epipolar line 2, the common electrode line 6, and the data line 3.
  • a shield electrode 10 is provided between the pixel electrode 5 and the data lines 3 on both sides.
  • the insulating structure includes an intermediate vertical trunk, an intermediate horizontal trunk, and branches respectively extending from the two trunks.
  • the trunk and the branches constitute a "m"-shaped structure, and such a shape corresponds to the pattern of the opaque regions of the above-mentioned mask.
  • master and branch are used for both the reticle and the insulating structure.
  • the angle between each branch and the main thousand ranges from 30° to 60°.
  • the branch portion forms a ridge 5a with the pixel electrode material overlying it, and a groove 5b is formed between the rib 5a.
  • the rib 5a and the groove 5b are arranged one on another.
  • the width of the ridge 5a and the groove 5b is, for example, between 0, 6 um and 6 um.
  • Fig. 8 is a cross-sectional structural view taken along line B-B of Fig. 7.
  • the pixel electrode 5 and the substrate 1 are entirely separated by an insulating structure.
  • the m-shaped insulating structure is a three-dimensional structure including raised branches and trunks, and recessed portions between the respective branches.
  • the pixel electrode material and the convex portion coated on the insulating structure constitute the above-mentioned ridges.
  • the pixel electrode material coated on the insulating structure forms a groove with the recessed portion.
  • the shield electrode 10 can be provided between the data line 3 and the pixel electrode 5 in the present invention.
  • the setting of the shield electrode 0 can effectively shield the electrical signal interference between the data line 3 and the pixel electrode 5.
  • the distance between the pixel electrode 5 and the data line 3 can be set as small as possible. Since the pixel electrode 5 can be disposed close to the direction of the data line 3, the area of the pixel unit opening area is increased, thereby increasing the mouth rate of the pixel unit.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Liquid Crystal (AREA)

Abstract

一种掩膜板及对应的阵列基板制作方法和阵列基板，应用于液晶显示技术领域，该掩膜板包括不透光区域（5c）和透光区域，不透光区域（5c）包括中间竖直主干、中间水平主干及从中间竖直主干和中间水平主干延伸出的分支，中间竖直主干与中间水平主干分别与其分支形成一定夹角；透光区域包括设在分支之间的第一透光部分（5d），在第一透光部分（5d）上设置有光干涉单元，该光干涉单元用以将具有第一光强的光处理为具有第二光强的光，其中第一光强大于第二光强，第二透光部分（7a）用于将第一光强的光引入以形成对应阵列基板上的接触孔（7），上述设置提高了像素单元的开口率以及液晶面板的穿透率。

Description

一种掩膜板、 阵列基板制作方法及阵列基板 相关申请的交叉引用
本申请要求享有 2014年 7 .月 18日提交的名称为"一种掩模板、阵列基板制作方法及 阵列基板"的中国专利申请 CN201410344993.4的优先权， 该申请的全部内容通过引用并 入本文中。 技术领域
本发明涉及液晶显示技术领域， 具体地说， 涉及一种掩膜板及采用该掩膜板制作阵 列基板的方法和对应的阵列基板。 背景技术
传统的 HVA(High Vertical Alignment, 高垂直排列)像素电极为 Fine Slit (改进的狭 缝） 结构形式。 其中， 狭缝部分不设置像素电极， 这就使得该部分对电场的控刺力较差， 进而对液晶分子的控制力较差。 因此， 该部分就会出现暗纹， 从而损失液晶效率， 进而损 失液晶面板的穿透率。为改善液晶面板的穿透率， 出现了一种新的具有立体结构的像素电 极。 该立体结构的像素电极覆盖于像素单元的幵口区上。
制作具有以上所述立体结构的像素电极的阵列基板， 通常同时完成接触孔和立体结 构像素电极中绝缘层的蚀刻。也就是说，采用一道掩膜板同时实现接触孔和像素电极的立 体结构。此种做法可以有效节约掩膜板成本和制程 ^间，但会使立体结构像素电极中的部 分绝缘层被全部蚀刻掉。如果此时为了提高液晶面板的开口率而添加屏蔽电极，可能会导 致屏蔽电极与像素电极相接触。 因此， 在这种情况下无法添加屏蔽电极， 就会降低液晶靣 板的开口率。
基于上述情况， 亟需一种能形成立体结构像素电极且能提高液晶面板开口率的掩膜 板及其对应的阵列基板制作方法和阵列基板。 发明内容
为解决上述问题， 本发明提供了一种能形成立体结构像素电极且能提高液晶面板开 □率的掩膜板及其对应的阵列基板制作方法和阵列基板。 根据本发明的一个方面， 提供了一种掩模板， 所述掩膜板包括；
不透光区域， 所述不透光区域包括中间竖直主干、 中间水平主千及从所述中间竖直 主干和所述中间水平主千延伸出的分支，所述中间竖直主干与中间水平主干分别与所述分 支形成一定夹角；
透光区域， 所述透光区域包括设在所述分支之间的第一透光部分，
其中， 在所述第一透光部分上设置有光千涉单元， 所述光干涉单元用以将具有第一 光强的光处理为具有第二光强的光， 其中所述第一光强大于第二光强。
根据本发明的一个实施例， 所述透光区域还包括第二透光部分， 所述第二透光部分 用于直接将所述第一光强的光引入以形成对应于阵列基板上的接触孔。
根据本发明的一个实施例， 所述光千涉单元的形状为网格状、 条機状或片状。
根据本发明的一个实施例，所述光干涉单元贯穿设在所述第一透光部分的中间位置。 根据本发明的一个实施例， 所述光千涉单元用不透光材料或者半透光村料制成。 根据本发明的另一个方面， 还提供了一种制作阵列基板的方法， 采用以上任一项所 述的掩膜板形成绝缘结构体。
根据本发明的一个实施例， 在形成第一金属导电层时还包括形成屏蔽电极。
根据本发明的再一个方面， 还提供了一种阵列基板， 所述阵列基板包括； 基底：
在基底上形成的多个像素单元， 所述像素单元包括，
设置在开口区域的像素电极， 在所述像素电极与所述基底之间设有绝缘结构体， 所 述绝缘结构体由采用以上任一项所述的掩膜板蚀刻形成。
根据本发明的一个实施例， 所述绝缘结构体包括中间竖直主千、 中间水平主干及从 所述中间竖直主千和所述中间水平主千延伸出的分支，所述中间竖直主干与所述中间水平 主千分别与其分支形成一定夹角，其中，在相邻的两个分支之间包括具有绝缘材料的底面 的凹槽。
根据本发明的一个实施例， 在数据线与所述像素电极之间还设有与栅线同层的屏蔽 电极， 用以屏蔽所述数据线与所述像素电极之间的电信号。
本发明带来了以下有益效果：
本发明通过在掩膜板上透光区域的第一透光部分设置光千涉单元， 使得对应该部位 的阵列基板上的绝缘材料不能被蚀刻到底，该部位未被蚀刻的绝缘材料和掩膜板上不透光 区域对应的阵列基板上的绝缘材料形成绝缘结构体。由于绝缘结构体的存在能在像素电极 与数据线之间设置屏蔽电极，缩短了像素电极与数据线之间的距离。该种设计提高了像素 单元的开口率， 提高了液晶面板的穿透率。
本发明的其它特征和优点将在隨后的说明书中阐述， 并且， 部分地从说明书中变得 显而易见， 或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利 要求书以及附图中所特别指出的结构来实现和获得。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实施例或现有 技术描述中所需要的附图做简单的介绍：
图 1为现有的具有立体结构像素电极的阵列基板的平面结构图；
图 2为对应形成图 1中像素电极的掩膜板的局部图案示意图；
图 3为图！沿 A-A方向的剖面结构图；
图 4为本发明所述的掩膜板的一个实施例的局部图案示意图；
图 5为本发明所述的掩膜板的另一个实施例的局部图案示意图；
图 6为本发明所述的掩膜板的再一个实施例的局部图案示意图；
图 7为采用本发明所述的图 4-图 5中的任一掩膜板制成的阵列基板的一个实施例的 平面结构图；
图 8为图 7沿 B- B方向的剖面结构图；
其中， 1、 基底， 2、 極线， 3、 数据线， 4、 TFT (薄膜晶体管） ， 5、 像素电极， 5a、 凸条， 5b、 凹槽， 5c、 不透光区域， 5d、 第一透光部分， 6、 公共电极线， 7、 接触孔， 7a、 第二透光部分， 8、 概极绝缘层， 9、 沉积钝化层， 〗0、 屏蔽电极。 具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式， 借此对本发明如何应用技 术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的 是， 只要不构成冲突， 本发明中的各个实施例以及各实施例中的各个特征可以相互结合， 所形成的技术方案均在本发明的保护范围之内。
另外， 在 Pf†图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统 中抉行， 并且， 虽然在流程图中示出了逻辑顺序， 但是在某些情况下， 可以以不同于此处 的顺序抉行所示出或描述的步骤。
如图 1所示为现有的一种具有立体结构像素电极的阵列基板平面结构图。如图所示， 该阵列基板包括基底 1和像素单元。 像素单元包括设置于基底 1上的機线 2、 数据线 3、 TFT4、 像素电极 5和公共电极线 6。 其中， 栅线 2与公共电极线 6平行设置。 極线 2和 公共电极线 6均与数据线 3垂直设置。 TFT4设置于栅线 2上， 其栅极、 源极、 漏极分别 与栅线 2、 数据线 3和像素电极 5电连接。 在一种设置中， TFT4的漏极通过接触孔 7与 像素电极 5连接。像素电极 5设置在由極线 2、 数据线 3和公共电极线 6包围形成的开口 区域中。
图中的像素电极层由一 "米"字形的绝缘结构体来支撑。 该绝缘结构体包括中间竖 直主干、 中间水平主干和分别从中延伸而形成的分支。 中间竖直主干、 中间水平主干和分 支为凸起的绝缘部分， 其与所涂敷的像素电极层合起来称为凸条 5a。 各个凸条之间的部 分为凹槽 5b。在现有的像素电极结构中， 凹槽 5b底部只包括像素电极层。在这种情况下， 所涂敷的像素电极层与基底 1直接接触。
如图 2所示为对应形成图 1中像素电极的掩膜板图案。在采用正性光刻胶的条件下， 图中不透光区域 5c对应形成凸条 5a， 图中 5d为第一透光部分对应形成凹槽513。 图中标 注 7a为第二透光部分对应形成阵列基板上的接触孔 7。
如图 3所示为图 1沿 A-A方 | 的剖面结构图。 如图所示， 整个绝缘结构体表靣均覆 盖像素电极层。 由该绝缘结构体支撑的像素电极层也就是像素电极 5。栅极绝缘层 8覆盖 于基板 1上。 沉积纯化层 9覆盖于数据线 3和極极绝缘层 8表面。
制作如上所述的阵列基板 ^% 可采用如图 2所示的掩膜板同时实现接触孔结构和像 素电极的立体结构。也就是说， 接触孔、米字形的绝缘结构体采用一道掩膜板在同一制程 中完成。此种做法虽然能有效的节约掩膜板成本和刺程^间，但在制作过程中可能会使相 邻分支之间的绝缘材料层全部蚀刻掉。 这样在涂敷透明导电材料形成像素电极层的 ^候， 透明导电材料可能会与基底 1 直接接触。 如图 3所示， 凹槽部分的像素电极层与基板 1 之间的绝缘层被完全蚀刻掉， 导致像素电极 5与基板 1接触。
此外， 通常在液晶面板的设 过程中， 为增加像素单元的开口率， 往往在像素电极 5与数据线 3之间设置屏蔽结构， 如屏蔽电极。 屏蔽电极用于屏蔽像素电极 5与数据线 3 之间的电信号千扰。将像素电极 5与数据线 3之间的电信号千扰屏蔽掉，就可以减小两者 之间的距离。可将像素电极 5尽可能地靠近数据线 3设置，从而尽可能地扩大像素单元开 口区域的面积。
但是， 屏蔽电极与榲线通常在同一制程中形成。 如果立体结构的像素电极的凹槽部 分的绝缘层被完全蚀刻掉，覆盖于其上的像素电极 5就会与基底 1接触。由于屏蔽电极也 与基底 1直接接触，并位于像素电极 5和数据线 3之间， 因此其有可能与无底部的凹槽上 的像素电极层接触。在刺作过程中， 一旦不同层之间发生平移， 则有可能导致像素电极层 与屏蔽电极电性接触，这在实际中是不允许的。一种可以解决的办法是在像素电极与屏蔽 电极之间形成层差。以下详细介绍如何通过改进的掩模板来在阵列基板的制作中形成该层 差的技术方案。
本发明所述的掩膜板包括不透光区域 5c和透光区域。 其中， 不透光区域 5c与图 2 相同，也包括中间竖直主干、中间水平主千及从中间竖直主干和中间水平主干延伸出的分 支，中间竖直主干与中间水平主千分别与其延伸出的分支形成一定的夹角。在该掩模板中， 不透光区域整体形成 "米"字形的图案。
透光区域分为第一透光部分 5d和第二透光部分 7a。 其中， 第一透光部分 5d设置在 不透光区域 5c的分支之间。第一透光部分 5d中间设置有光干涉单元。该光干涉单元可将 具有较大光照强度的第一光强的光通过第一透光部分 5d后变为具有较小光照强度的第二 光强的光。上述光千涉单元可采用不透光材料制成， 当然， 也可根据需要采用半透光材料 制成。
在本发明的一个实施例中， 该光千涉单元设置为网格状， 如图 4所示。 在该图中， 光线通过网格部分射入到待蚀刻阵列基板上。这样， 网格中遮光部分所对应的阵列基板的 部位也能被光照到， 从而使得阵列基板上对应该部位的绝缘层可被蚀刻掉。但是， 由于透 ϋ光干涉单元的光强度己经减弱， 因此在相同的蚀刻时间里，可以保证掩模板的该部分所 对应的位置上还保留一部分的绝缘材料。网格的大小可根据实际需要进行设置，其基本上 与要保留的绝缘材料的厚度、 光刻时间以及施加的光照强度有关。
在本发明的另一个实施例中， 该光干涉单元设置为条機状， 如图 5所示。在该图中， 光线可通过条概间隙射入到待蚀刻阵列基板上。这样，条概遮光部分所对应的阵列基板的 部位也能被光照到，从而使得阵列基板上对应该部位的绝缘层可被蚀刻掉。与上面网格例 子类似， 由于透过的光强度巳经减弱， 因此在相同的蚀刻时间里， 可以保证掩模板的该部 分所对应的位置上还保留一部分的绝缘材料。 条栅之间的间距可根据实际需要进行设置， 其基本上与要保留的绝缘材料的厚度、 光刻时间以及施加的光照强度有关。
无论是网状的还是条栅状的光干涉单元， 其均可以设置成与分支的两侧相接触从而 占满整个第一透光部分 5d， 如图 4和 5所示。 然而， 实际中， 网状或条栅状的光干涉单 元也可以仅设在相邻分支之间， 其与分支的两侧之间保持一定间隙。
在本发明的另一个实施例中， 该光千涉单元还可设置为沿透光区域长度方向的片状 结构， 如图 6所示。在该图中， 光线 通过片状结构两侧的透光部分而射入到待蚀刻阵列 基板上。这样， 片状结构所对应的阵列基板的部位也能被光照到， 从而使得阵列基板上对 应该部位的绝缘层可被蚀刻。不过， 光强已有一定程度的减弱， 因此同样蚀刻的时间以及 初始光强下， 与片状结构的光干涉单元对应的阵列基板部分上的绝缘材料不会完全蚀刻， 从而相较于之前保留了一定厚度的绝缘村料。
在一个具体的例子中， 当光干涉单元为片状， 并贯穿相邻的两分支设置时， 为防止 透过光干涉单元的光强度较大而导致对应该部分的绝缘层蚀刻到基底部分,这里还可设置 片状的光干涉单元与相邻的分支的一侧的距离范围在 0„2um〜0,5Um之间。 实际中， 也可 通过改变光干涉单元的有效透光面积来控制对应阵列基板上绝缘材料的蚀刻深度。
当然， 光千涉单元的设置形状并不限于以上所述的几种， 凡能实现影响光照强度的 形状设置均可用作此处的光千涉单元。
分别对应图 4、 图 5和图 6中的第二透光部分 7a设置为完全透光。 该部分可将原始 的具有第一光强的光直接引入， 从而对应地形成阵列基板上的接触孔。
采用本发明所述的掩膜板来制作对应的阵列基板主要包括以下步骤。
首先在基底上沉积第一层金属膜用以形成第一金属导电层。 在形成第一金属导电层 的过程中， 形成栅线和公共电极线， 并同时形成与公共电极线连接的屏蔽电极。
然后在第一金属导电层上沉积第一绝缘材料和半导体材料来形成中间层。
然后在中间层上沉积第二层金属膜用以形成第二金属导电层。 在该过程中还包括形 成 TFT的源极与漏极。
之后采用上述的掩膜板在第二金属导电层和裸露的中间层上形成绝缘结构体。 在本 发明的一个实施例中，在采用正性光刻胶的条件下，对应掩膜板上不透光区域的阵列基板 上的绝缘材料不被蚀刻形成凸起结构。掩膜板上的透光区域设置为第一透光部分和第二透 光部分两种。第一透光部分设置有光千涉单元。当第一光强的光透过该光干涉单元时变为 强度减弱的第二光强的光。由于透过第一透光部分的光强减弱，使得对该部分的蚀刻深度 变浅，不会将该部分对应的阵列基板上的绝缘材料饨刻到底，则对应该部分形成凹陷结构。 由具有凸起和凹陷结构的绝缘材料形成具有立体结构的绝缘结构体。第二透光部分直接将 第一光强的光引入对应形成阵列基板上的接触孔。
最后， 在绝缘结构体上涂敷透明导电村料， 从而形成像素电极。
如图 7所示为采用以上所述的掩膜板和方法制作的阵列基板的一个实施例的平面结 构图。
在图 7中， 阵列基板包括基底 1和像素单元。 该像素单元包括设置于基底 1上的栅 线 2、 数据线 3、 TFT4、 像素电极 5和公共电极线 6。 其中， »线 2与公共电极线 6平行 设置。 栅线 2和公共电极线 6均与数据线 3垂直设置。 TFT4设置于極线 2上， 其榲极、 源极和漏极分别与 «线 2、 数据线 3和像素电极 5电连接。 其中， TFT4的漏极通过接触 孔 7与像素电极 5连接。 TFT4设置于栅线上， 可以避免占用像素单元的开□区域， 有利 于提高像素单元的开口率。像素电极 5设置亍由極线 2、 公共电极线 6和数据线 3包围形 成的开口区域中。 在像素电极 5与两侧的数据线 3之间设置有屏蔽电极 10。
像素电极 5与基底 1之间设有绝缘结构体。 该绝缘结构体包括中间竖直主干、 中间 水平主干和分别从两种主干中延伸而 ¾形成的分支。 主干和分支构成"米"字形结构， 这 样的形状与上述掩模板的不透光区域的图案相对应。为描述的方便起见，针对掩模板和绝 缘结构体均采用主千和分支这样的术语。但是，本领域的技术人员在阅读了本发明的全部 内容之后， 显然可以明白它们在不同的情况下所指的具体含义。
在绝缘结构体中，各个分支与主千的夹角范围为 30°〜60°。分支部分与覆盖于其上的 像素电极材料形成凸条 5a, 凸条 5a之间为凹槽 5b。 凸条 5a和凹槽 5b相间排列。 凸条 5a和凹槽 5b的宽度范围在例如 0,6um〜 ,6um之间。
下面，参照图 8来进一歩地详细明本发明的像素电极结构，其中， 图 8为图 7沿 B- B 方向的剖面结构图。 在该图中， 像素电极 5与基底 1之间全部由绝缘结构体而隔开。
由该剖面图可以得知， 米字形的绝缘结构体为立体结构， 其包括凸起的分支和主干， 以及各个分支之间的凹陷部分。该绝缘结构体上涂敷的像素电极材料与凸起部分构成上述 的凸条。 该绝缘结构体上涂敷的像素电极材料与凹陷部分形成凹槽。
由于凹槽表面的像素电极与基底之间具有绝缘材料，这就使得屏蔽电极 10与凹槽表 面的像素电极 5之间具有层差。即使在制作过程中不同层之间有位置偏差，也能避免屏蔽 电极 10与像素电极 5接触。 因此， 本发明中可以在数据线 3和像素电极 5之间设置屏蔽 电极 10。 屏蔽电极 0的设置可以有效屏蔽数据线 3和像素电极 5之间的电信号干扰。 在 这种情况下， 就可将像素电极 5与数据线 3之间的距离设置的尽可能小。 由于像素电极 5 可以向数据线 3的方向靠近设置， 因此提高了像素单元幵口区域的面积，进而提高了像素 单元的幵口率。
虽然本发明所公开的实施方式如上， 但所述的内容只是为了便于理解本发明而采用 的实施方式， 并非用以限定本发明。任何本发明所属技术领域内的技术人员， 在不脱离本 发明所公开的精神和范圏的前提下， 可以在实施的形式上及细节上作任何的修改与变化， 但本发明的专利保护范围， 仍须以所 Pf†的权利要求书所界定的范圏为准。

Claims

权利要求书
、 一种掩模板， 其中， 所述掩膜板包括：
不透光区域， 所述不透光区域包括中间竖直主干、 中间水平主干及从所述中间竖直 主千和所述中间水平主千延伸出的分支，所述中间竖直主干与中间水平主干分别与所述分 支形成一定夹角；
透光区域， 所述透光区域包括设在所述分支之间的第一透光部分，
其中， 在所述第一透光部分上设置有光千涉单元， 所述光干涉单元用以将具有第一 光强的光处理为具有第二光强的光， 其中所述第一光强大于第二光强。
2、 如权利要求 1所述的掩膜板， 其中， 所述透光区域还包括第二透光部分， 所述第 二透光部分用于直接将所述第一光强的光引入以形成对应于阵列基板上的接触孔。
3、 如权利要求 2所述的掩膜板， 其中， 所述光干涉单元的形状为网格状、 条栅状或 片状。
4、 如权利要求 3所述的掩膜板， 其中， 所述光干涉单元贯穿设在所述第一透光部分 的中间位置。
5、 如权利要求 1所述的掩膜板， 其中， 所述光千涉单元用不透光材料或者半透光材 料制成。
6、 一种制作阵列基板的方法， 其中， 采用一种掩膜板形成绝缘结构体， 所述掩模板 包括：
不透光区域， 所述不透光区域包括中间竖直主干、 中间水平主干及从所述中间竖直 主干和所述中间水平主千延伸出的分支，所述中间竖直主干与中间水平主干分别与所述分 支形成一定夹角；
透光区域， 所述透光区域包括设在所述分支之间的第一透光部分，
其中， 在所述第一透光部分上设置有光千涉单元， 所述光干涉单元用以将具有第一 光强的光处理为具有第二光强的光， 其中所述第一光强大于第二光强。
7、 如权利要求 6所述的方法， 其中， 所述掩模板的透光区域还包括第二透光部分， 所述第二透光部分用于直接将所述第一光强的光引入以形成对应于阵列基板上的接触孔。
8、 如权利要求 7所述的方法， 其中， 所述光千涉单元的形状为网格状、 条»状或片 状。
9、 如权利要求 8所述的方法， 其中， 所述光千涉单元贯穿设在所述第一透光部分的 中间位置。
10、 如权利要求 6所述的方法， 其中， 所述光干涉单元用不透光材料或者半透光材 料制成。
11、 如权利要求 6所述的方法， 其中， 在形成第一金属导电层^还包括形成屏蔽电 极。
12、 一种阵列基板， 其中， 所述阵列基板包括- 基底；
在基底上形成的多个像素单元， 所述像素单元包括，
设置在开口区域的像素电极， 在所述像素电极与所述基底之间设有绝缘结构体， 所 述绝缘结构体由一种掩膜板蚀刻形成， 所述掩模板包括- 不透光区域， 所述不透光区域包括中间竖直主干、 中间水平主干及从所述中间竖直 主干和所述中间水平主千延伸出的分支，所述中间竖直主干与中间水平主干分别与所述分 支形成一定夹角；
透光区域， 所述透光区域包括设在所述分支之间的第一透光部分，
其中， 在所述第一透光部分上设置有光千涉单元， 所述光干涉单元用以将具有第一 光强的光处理为具有第二光强的光， 其中所述第一光强大于第二光强。
13、 如权利要求 12所述的阵列基板， 其中， 所述掩模板的透光区域还包括第二透光 部分,所述第二透光部分用于直接将所述第一光强的光引入以形成对应于阵列基板上的接 触孔。
14、 如权利要求】 3所述的阵列基板， 其中， 所述光干涉单元的形状为网格状、 条栅 状或片状。
15、 如权利要求！ 4所述的阵列基板， 其中， 所述光干涉单元贯穿设在所述第一透光 部分的中间位置。
16、 如权利要求 12所述的阵列基板， 其中， 所述光干涉单元用不透光材料或者半透 光材料制成。
17、 如权利要求 12所述的阵列基板， 其中， 所述绝缘结构体包括中间竖直主干、 中 间水平主干及从所述中间竖直主千和所述中间水平主干延伸出的分支，所述中间竖直主千 与所述中间水平主千分别与其分支形成一定夹角，其中，在相邻的两个分支之间包括具有 绝缘材料的底面的凹槽。
18、 如权利要求 17所述的阵列基板， 其中， 在数据线与所述像素电极之间还设有与 »线同层的屏蔽电极， 用以屏蔽所述数据线与所述像素电极之间的电信号。
PCT/CN2014/083742 2014-07-18 2014-08-05 一种掩膜板、阵列基板制作方法及阵列基板 Ceased WO2016008182A1 (zh)

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