WO2015200101A1 - Inductive monitoring of conductive trench depth - Google Patents

Inductive monitoring of conductive trench depth Download PDF

Info

Publication number
WO2015200101A1
WO2015200101A1 PCT/US2015/036520 US2015036520W WO2015200101A1 WO 2015200101 A1 WO2015200101 A1 WO 2015200101A1 US 2015036520 W US2015036520 W US 2015036520W WO 2015200101 A1 WO2015200101 A1 WO 2015200101A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
sequence
layer
polishing
values
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2015/036520
Other languages
English (en)
French (fr)
Inventor
Wei Lu
Zhefu Wang
Zhihong Wang
Hassan G. Iravani
Dominic J. Benvegnu
Ingemar Carlsson
Boguslaw A. Swedek
Wen-Chiang Tu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to CN201910937866.8A priority Critical patent/CN111211052B/zh
Priority to KR1020177002030A priority patent/KR102383708B1/ko
Priority to CN201580029881.2A priority patent/CN106463380B/zh
Priority to JP2016574899A priority patent/JP6640754B2/ja
Publication of WO2015200101A1 publication Critical patent/WO2015200101A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/238—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/005—Control means for lapping machines or devices
    • B24B37/013—Devices or means for detecting lapping completion
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics

Definitions

  • An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive, or insulative layers on a silicon wafer.
  • a variety of fabrication processes require planarization of a layer on the substrate. For example, one fabrication step involves depositing a conductive filler layer on a patterned insulative layer to fill the trenches or holes in the insulative layer. The filler layer is then polished until the raised pattern of the insulative layer is exposed. After planarization, the portions of the conductive filler layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate.
  • polishing continues after the patterned insulative layer has been exposed, e.g., in order to reduce the depth of the conductive lines in the trenches. It would be desirable to reliably halt polishing of the substrate when the trenches have a target depth. However, due to the small line width of the trenches, it can be difficult to induce eddy currents in the conductive lines.
  • a recess 26 is formed in the platen 24, and optionally a thin section 36 can be formed in the polishing pad 30 overlying the recess 26.
  • the recess 26 and thin pad section 36 can be positioned such that regardless of the translational position of the carrier head they pass beneath substrate 10 during a portion of the platen rotation.
  • the polishing rate of the second zone can be increased (shown by line 172) such that the second zone will reach the target value 168 at substantially the same time as the second zone.
  • the polishing rates of both the first portion and the second portion of the substrate are adjusted so that endpoint is reached at both portions simultaneously.
  • the polishing rate of only the first portion or the second portion can be adjusted.

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
PCT/US2015/036520 2014-06-23 2015-06-18 Inductive monitoring of conductive trench depth Ceased WO2015200101A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201910937866.8A CN111211052B (zh) 2014-06-23 2015-06-18 导电沟槽深度的感应监测
KR1020177002030A KR102383708B1 (ko) 2014-06-23 2015-06-18 전도성 트렌치 깊이의 유도성 모니터링
CN201580029881.2A CN106463380B (zh) 2014-06-23 2015-06-18 导电沟槽深度的感应监测
JP2016574899A JP6640754B2 (ja) 2014-06-23 2015-06-18 導電性トレンチの深さの誘導性モニタリング

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/312,503 US9754846B2 (en) 2014-06-23 2014-06-23 Inductive monitoring of conductive trench depth
US14/312,503 2014-06-23

Publications (1)

Publication Number Publication Date
WO2015200101A1 true WO2015200101A1 (en) 2015-12-30

Family

ID=54870327

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/036520 Ceased WO2015200101A1 (en) 2014-06-23 2015-06-18 Inductive monitoring of conductive trench depth

Country Status (6)

Country Link
US (3) US9754846B2 (https=)
JP (1) JP6640754B2 (https=)
KR (1) KR102383708B1 (https=)
CN (2) CN106463380B (https=)
TW (2) TWI649799B (https=)
WO (1) WO2015200101A1 (https=)

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US11376704B2 (en) 2018-06-22 2022-07-05 Ebara Corporation Method of identifying trajectory of eddy current sensor, method of calculating substrate polishing progress, method of stopping operation of substrate polishing apparatus, method of regularizing substrate polishing progress, program for executing the same, and non-transitory recording medium that records program
US11833636B2 (en) 2019-10-03 2023-12-05 Ebara Corporation Substrate polishing apparatus, method of creating thickness map, and method of polishing a substrate

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US9754846B2 (en) * 2014-06-23 2017-09-05 Applied Materials, Inc. Inductive monitoring of conductive trench depth
TW201822953A (zh) 2016-09-16 2018-07-01 美商應用材料股份有限公司 基於溝槽深度的電磁感應監控進行的過拋光
US10427272B2 (en) * 2016-09-21 2019-10-01 Applied Materials, Inc. Endpoint detection with compensation for filtering
TWI816620B (zh) 2017-04-21 2023-09-21 美商應用材料股份有限公司 使用神經網路來監測的拋光裝置
TWI783037B (zh) * 2017-09-25 2022-11-11 美商應用材料股份有限公司 使用機器學習方式以產生製程控制參數的半導體製造
TWI825075B (zh) 2018-04-03 2023-12-11 美商應用材料股份有限公司 針對墊子厚度使用機器學習及補償的拋光裝置、拋光系統、方法及電腦儲存媒體
US11056351B2 (en) * 2018-08-31 2021-07-06 Synaptics Incorporated Process monitor for wafer thinning
US11009798B2 (en) 2018-09-05 2021-05-18 Micron Technology, Inc. Wafer alignment markers, systems, and related methods
US11251096B2 (en) 2018-09-05 2022-02-15 Micron Technology, Inc. Wafer registration and overlay measurement systems and related methods
CN118943037A (zh) 2018-09-26 2024-11-12 应用材料公司 针对原位电磁感应监测的边缘重建中的基板掺杂的补偿
JP7291558B2 (ja) * 2019-07-03 2023-06-15 株式会社荏原製作所 渦電流センサ
JP7507576B2 (ja) * 2020-03-17 2024-06-28 株式会社東京精密 研削装置
KR20250073489A (ko) 2020-05-14 2025-05-27 어플라이드 머티어리얼스, 인코포레이티드 연마 동안의 인-시튜 모니터링에 사용하기 위한 신경망을 훈련시키기 위한 기법 및 연마 시스템
TWI810069B (zh) 2020-06-08 2023-07-21 美商應用材料股份有限公司 用於在拋光相鄰導電層的堆疊期間的輪廓控制的系統、方法及電腦程式產品
JP7447284B2 (ja) * 2020-06-24 2024-03-11 アプライド マテリアルズ インコーポレイテッド 研磨パッドの摩耗補償による基板層の厚さの決定
US11980995B2 (en) * 2021-03-03 2024-05-14 Applied Materials, Inc. Motor torque endpoint during polishing with spatial resolution

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US20030223150A1 (en) * 2002-05-28 2003-12-04 Lee Edward Hin Pong Method of protecting the pole piece of a magnetic head during the ion mill patterning of the yoke
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11376704B2 (en) 2018-06-22 2022-07-05 Ebara Corporation Method of identifying trajectory of eddy current sensor, method of calculating substrate polishing progress, method of stopping operation of substrate polishing apparatus, method of regularizing substrate polishing progress, program for executing the same, and non-transitory recording medium that records program
US11833636B2 (en) 2019-10-03 2023-12-05 Ebara Corporation Substrate polishing apparatus, method of creating thickness map, and method of polishing a substrate

Also Published As

Publication number Publication date
JP2017520124A (ja) 2017-07-20
CN106463380B (zh) 2019-10-29
TW201603134A (zh) 2016-01-16
JP6640754B2 (ja) 2020-02-05
TWI701733B (zh) 2020-08-11
US10103073B2 (en) 2018-10-16
US20190035699A1 (en) 2019-01-31
US20150371913A1 (en) 2015-12-24
CN111211052A (zh) 2020-05-29
TWI649799B (zh) 2019-02-01
US20170365532A1 (en) 2017-12-21
US10741459B2 (en) 2020-08-11
CN111211052B (zh) 2023-09-19
KR20170018960A (ko) 2017-02-20
TW201929080A (zh) 2019-07-16
US9754846B2 (en) 2017-09-05
KR102383708B1 (ko) 2022-04-05
CN106463380A (zh) 2017-02-22

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