WO2015197017A1 - 制造含有导电通孔的基板的方法及导线基材集成体 - Google Patents

制造含有导电通孔的基板的方法及导线基材集成体 Download PDF

Info

Publication number
WO2015197017A1
WO2015197017A1 PCT/CN2015/082479 CN2015082479W WO2015197017A1 WO 2015197017 A1 WO2015197017 A1 WO 2015197017A1 CN 2015082479 W CN2015082479 W CN 2015082479W WO 2015197017 A1 WO2015197017 A1 WO 2015197017A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
strip
unidirectional
wires
wire
Prior art date
Application number
PCT/CN2015/082479
Other languages
English (en)
French (fr)
Inventor
申宇慈
Original Assignee
申宇慈
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 申宇慈 filed Critical 申宇慈
Publication of WO2015197017A1 publication Critical patent/WO2015197017A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates generally to integrated circuit semiconductor package technology, and more particularly to a method of fabricating a substrate comprising conductive vias.
  • the substrate including the conductive via holes can be further fabricated into a circuit substrate for an integrated circuit semiconductor package by fabricating a circuit and a pad on the upper and lower surfaces of the substrate including the conductive via.
  • TSV Through Silicon Via
  • TGV Through Substrate Via
  • TGV Through Glass Via
  • Silicon, glass, ceramic or organic material substrates have been widely used in integrated circuit semiconductor packaging technology, and are 3D integrated circuit semiconductors. Key components in the package. Circuit boards based on substrates containing vias are commonly used in 3D and 2.5D integrated circuit semiconductor packaging technologies and are components that integrate electronic product functions.
  • the substrate including the via holes includes a silicon substrate including a via hole, a glass substrate, a ceramic substrate, and an organic material substrate.
  • the manufacturing methods of the through-hole-containing substrates can be divided into two types: one is a substrate-based method, and the other is a via-based method.
  • the substrate based method basically comprises:
  • the via based method basically comprises:
  • the dot-shaped small metal pillars are then covered with a substrate material, and the carrier is removed and the upper and lower surfaces are polished to expose the dot-shaped small metal pillars to form a substrate having conductive via holes.
  • a substrate including a via hole is to further form a substrate including a via hole into a circuit substrate including a via hole through a circuit and a pad formed on the surface of the substrate, thereby placing the bit in the integrated circuit semiconductor package.
  • the electronic components on the upper surface of the substrate are connected to other electronic components or printed circuit boards under the substrate, and the circuit on the upper surface of the substrate can also directly communicate the electronic components located thereon and then other electronic components under the substrate.
  • the components or boards are connected.
  • the via hole is a conductive metal pillar embedded in the substrate and formed in a regular arrangement at a desired pitch;
  • the base material of the substrate serves as a carrier for holding the via holes and further fabricating the pads and pads thereon.
  • the diameter of the through hole cannot be very small, and the prior art manufactures the through hole smaller than 10 ⁇ m, and the substrate exceeding a certain thickness (for example, 100 ⁇ m or more) is very difficult;
  • the pitch of the via holes cannot be very small, and it is difficult and expensive to fabricate via holes having a pitch of less than 50 micrometers on a substrate having a thickness of 100 micrometers or more or more in the prior art;
  • the thickness of the substrate including the via holes is limited by the size and pitch of the via holes, and the smaller the pitch of the via holes, the thinner the substrate is.
  • the present invention is a further development of the Chinese invention patent applications CN201310651705.5 and CN201310737666.0 submitted by the applicant on December 5, 2013 and December 27, 2013.
  • the published patent application CN201310651705.5 discloses a method of fabricating a metal wire integrated body based on a metal line pattern array and further fabricating a substrate including a pattern array via.
  • the method comprises the following key steps: fabricating a metal line pattern array; forming a solid dielectric matrix between the spaces between and around the metal lines to form a metal line integrated body comprising a metal line pattern array;
  • the film is divided into a plurality of sheets to form a plurality of substrates including through holes of the pattern array.
  • the above-mentioned patent application CN201310737666.0 discloses the manufacture of a unidirectional conductive plate which is electrically conductive in the thickness direction based on a wire. method. The method comprises the following key steps: fabricating a wire assembly made of unidirectional closely arranged wires; dividing the wire assembly body into pieces to form a plurality of unidirectional conductive plates or substrates comprising conductive vias .
  • the method for manufacturing a substrate containing conductive vias of the present invention comprises the following key steps: making or providing a strip substrate comprising unidirectional wires, wherein the unidirectional wires are arranged at a set pitch along a strip direction;
  • the strip substrates containing the unidirectional wires are laminated together to form a columnar substrate having unidirectional wires arranged at a predetermined pitch in the substrate, wherein the unidirectional wires are laminated on the column substrate
  • the spacing of the directions is determined by the thickness of the strip substrate;
  • the column substrate containing the unidirectional wires is solidified into a whole by a set condition, thereby forming a wire substrate assembly containing the unidirectional wires;
  • the wire substrate assembly which has been solidified into a unitary body and includes unidirectional wires arranged at a predetermined pitch is divided into pieces, thereby forming a plurality of substrates containing conductive via holes.
  • the method for manufacturing a substrate containing conductive vias according to the present invention is characterized in that the strip substrate is a green ceramic strip, a strip glass or a strip polymer material, and the strip substrate comprises a metal wire or A wire printed through a conductive paste.
  • the manufacturing method is characterized in that the step of fabricating a strip-shaped substrate containing unidirectional wires is to print a unidirectionally aligned wire at a predetermined pitch on a strip substrate by a conductive paste, or in a strip substrate Lay the metal wires arranged in one direction at a set pitch.
  • the manufacturing method is characterized in that the step of producing a strip-shaped substrate containing a unidirectional wire is to embed a wire in a unidirectional arrangement at a predetermined pitch in a tape-like substrate while forming a tape-shaped substrate.
  • the utility model is characterized in that a metal wire is arranged at a set pitch on a strip substrate, and then the slurry of the strip substrate is covered on the strip substrate to form a strip substrate, and then the metal wire is included.
  • the strip substrate is peeled off from the strip substrate to form a strip substrate containing a buried metal wire.
  • the manufacturing method is characterized in that, when a tape-shaped substrate containing a unidirectional wire is produced, other devices are added, thereby forming a substrate containing both the conductive via and the buried device.
  • the manufacturing method is characterized in that the method further comprises the steps of: further curing a plurality of column units containing unidirectional wires together to form a wire substrate assembly including unidirectional wires via the column unit; .
  • a cylinder comprising unidirectional conductors, a cylinder containing other components, a cylinder having different shapes, and a cylinder composed of different materials.
  • the manufacturing method is characterized in that the method further comprises the following steps Step: a step of forming a circuit and a pad on the upper and lower surfaces of the substrate having the conductive via holes, thereby further forming a circuit substrate including the conductive via holes.
  • the wire substrate assembly produced by the manufacturing method comprises: a base material and a unidirectional wire embedded in the base material, wherein the unidirectional wires are arranged at a set interval.
  • the wire substrate assembly is characterized in that the base material further comprises other component strings.
  • the wire substrate assembly characterized in that the base material further comprises other columns arranged in the direction of the wire.
  • a key inventive concept is to form a cylinder including a unidirectionally aligned wire at a set pitch in a substrate via a strip substrate comprising unidirectional wires, referred to herein as a wire substrate assembly.
  • the size of the conductive vias and their spacing can be very small;
  • the unidirectional conductive plates can have any selected thickness;
  • the thickness of the substrate can be arbitrarily selected according to needs, and is not limited by the size of the conductive via and the spacing thereof;
  • Copper wires can be used in ceramic or glass substrates.
  • FIG. 1 is a schematic view of a belt-shaped substrate in an embodiment of the present invention, including a front view and a cross-sectional view;
  • FIG. 2 is a schematic view of a strip substrate including a unidirectional wire according to an embodiment of the present invention, including a front view and a cross-sectional view;
  • FIG. 3 is a schematic view showing a cross section of a plurality of strip-shaped substrates containing unidirectional wires stacked together in one embodiment of the present invention
  • FIG. 4 is a schematic view showing a wire substrate assembly body obtained by further curing a column formed by laminating a plurality of strip-shaped substrates containing unidirectional wires together in an embodiment of the present invention
  • FIG. 5 is a schematic view showing a plurality of substrates including conductive vias formed by dividing a wire substrate assembly into sheets in one embodiment of the present invention
  • FIG. 6 is a schematic view showing a circuit board and a pad formed on the upper and lower surfaces of a substrate having conductive vias, thereby further forming a circuit substrate including conductive vias according to an embodiment of the present invention
  • FIG. 7 is a cross-sectional view showing a wire substrate assembly including a plurality of wire array units in one embodiment of the present invention.
  • FIG. 8 is a schematic view showing a plurality of substrate units including conductive vias being solidified together in one embodiment of the present invention to form a substrate having conductive via holes through the substrate unit, which simultaneously illustrates that the edges are further formed by cutting the edges thereof. a step of forming a substrate containing conductive vias;
  • Figure 9 is a schematic view of a cylindrical unit including a unidirectional wire according to an embodiment of the present invention.
  • FIG. 10 and FIG. 11 are diagrams showing a plurality of columns including unidirectional wires integrated and solidified together in one embodiment of the present invention to form a wire substrate formed by integration of a column unit including unidirectional wires.
  • 12 and 13 are schematic views showing the simultaneous laying of other components and wires on a strip substrate in one embodiment of the present invention.
  • Figure 14 is a schematic illustration of a cross section of a plurality of strip substrates comprising unidirectional wires and other components laminated together to form a cylinder in accordance with one embodiment of the present invention
  • Figure 15 is a view showing that the wire included in the strip substrate is a metal wire which may be laid on the surface of the tape substrate or may be buried in the tape substrate;
  • Figure 16 is a schematic illustration of the fabrication of a tape substrate comprising a buried metal wire in accordance with one embodiment of the present invention.
  • like components have been given the same reference numerals. The drawings are not in actual proportions.
  • a strip-shaped substrate which represents a rectangular sheet-like material having a length much larger than a width; a plurality of strip-shaped substrates laminated together form a columnar substrate which can pass a set condition such as a certain Temperature and pressure, solidified into a whole;
  • a wire substrate assembly which represents a columnar substrate comprising unidirectional wires, wherein the unidirectional wires are arranged at a set spacing;
  • a substrate which represents a sheet of material, such as a piece of ceramic, a piece of glass, a piece of wafer, or a piece of polymeric material;
  • a conductive via which represents a conductive path embedded in the substrate and penetrating through the thickness direction of the substrate, such as a column metal;
  • a substrate comprising conductive vias which represents a substrate comprising conductive vias arranged at a set pitch or distributed in a set pattern
  • a circuit board including conductive vias which represents a substrate including conductive vias in which circuits and pads are further formed on the upper and lower surfaces.
  • 1, 2, 3, 4, 5, and 6 are schematic views of a method of fabricating a substrate including conductive vias in accordance with one embodiment of the present invention.
  • 1100 in Fig. 1 illustrates a step from a strip substrate, wherein numeral symbols 101 and 102 respectively represent front and cross-sectional views of a strip substrate; 1200 in Fig. 2 is illustrated in the strip substrate
  • the steps of making unidirectional wires arranged at a set pitch wherein the numerical symbols 101 and 102 are the same as those of FIG. 1, respectively representing a front view and a cross-sectional view of the strip substrate, and further numeral symbols 201 and 202 respectively represent A front view and a cross-sectional view of a unidirectional wire arranged at a set pitch; 1300 in FIG.
  • FIG. 3 illustrates a plurality of said strip-shaped substrates containing unidirectional wires laminated together to be formed in a substrate
  • the step of arranging the columnar substrates of the unidirectional wires at a set pitch, the spacing of the unidirectional wires in the direction of the column substrate stacking is determined by the thickness of the strip substrate, wherein the numeral symbols 102 and 202 are the same as the previous figures, respectively Representing a strip substrate and unidirectional conductors arranged at a set spacing, further numeral 301 represents the interface between the laminates; 1400 in Figure 4 illustrates the passage of the columnar substrate containing the unidirectional conductors.
  • FIG. 5 is a view of dividing the wire substrate assembly having the unidirectional wire arranged at a predetermined pitch in the substrate into a single piece, thereby a step of forming a plurality of substrates including conductive vias, wherein numeral symbols 501 and 502 respectively represent a substrate and a conductive via in the substrate having conductive vias, and numeral symbols 503 and 504 respectively represent A cross-sectional view of a substrate and a conductive via in a substrate having a conductive via; 1505 in FIG.
  • FIG. 6 illustrates that a circuit and a pad are formed on the upper and lower surfaces of the substrate having the conductive via, thereby further forming a conductive via
  • the strip substrate is a low temperature sintered green ceramic strip of 100 to 200 microns, and the unidirectional wire is printed on the green ceramic strip by a conductive paste, the unidirectional wire
  • the width and thickness are below 60 microns and 2 microns, respectively, and the spacing of the unidirectional wires is below 200 microns.
  • the strip substrate may have a width of less than 30 mm to form a conductor substrate cylinder or integrated body having a width of 30 mm or less; the width of the strip substrate may also be 100 mm.
  • a wire substrate assembly having a width of 100 mm or more is formed.
  • the advantage of selecting a strip substrate having a small width is that the columnar substrate formed by laminating together the strip substrates containing unidirectional wires can be cured or sintered more easily and with high quality.
  • the advantage of selecting a strip substrate having a large width is that the further prepared substrate containing the conductive via can directly use the existing production process, such as a wafer manufacturing process or a printed circuit board manufacturing process, to fabricate circuits and solder on a large scale. plate.
  • the second example is: the strip substrate is a low temperature sintered green ceramic strip of 100 to 300 microns, and the unidirectional wire is a metal wire laid on the green ceramic strip, such as a thin copper wire having a diameter of less than 20 microns, other Same as the first example.
  • a third example is that the strip substrate is a low temperature sintered green ceramic strip of 100 to 300 microns, and the unidirectional wire is a metal wire buried in the green ceramic tape, such as a thin copper wire having a diameter of less than 20 microns.
  • the unidirectional wire is a metal wire buried in the green ceramic tape, such as a thin copper wire having a diameter of less than 20 microns.
  • the others are the same as the first example.
  • Figure 7 illustrates a feature of a particular embodiment of the present invention, which shows a wire substrate assembly comprising a plurality of unidirectional wire units, the further divided substrate comprising conductive vias correspondingly comprising a plurality of a conductive via unit, after the circuit and the pad are formed thereon, further divided into a plurality of circuit substrate units including conductive vias along the unit, and each of the circuit substrate units including the conductive vias is applied In an integrated circuit semiconductor package.
  • Figure 8 illustrates another feature of a particular embodiment of the invention showing a substrate having conductive vias that are further fabricated into different shapes (e.g., circular) by cutting the edges of a substrate containing conductive vias.
  • the reason for this is to match the shape of the substrate in the current wafer fabrication process. If future wafer fabrication processes can make circuits and pads on square or rectangular substrates, this step of cutting a square or rectangular substrate containing conductive vias is not required.
  • FIG. 10 and FIG. 11 illustrate an important feature of a particular embodiment of the invention, which is characterized in that a plurality of cylindrical units containing unidirectional conductors are further cured together to form a plurality comprising a step of a wire substrate assembly or a cylinder assembly of a cylindrical unit, wherein the plurality of When the column units of the wires are brought together, some other columns, such as columns of different materials or shapes, and columns of other members may be added, thereby making a substrate containing conductive vias and other components.
  • Figure 9 illustrates a cylindrical unit containing unidirectional wires, wherein numeral 1530 represents a cylindrical unit containing unidirectional wires 532 in substrate 531. Numeral numeral 1540 in Fig.
  • FIG. 10 illustrates the arrangement of a plurality of column units 530 including unidirectional wires
  • numeral 1550 in Fig. 11 illustrates the connection of a plurality of column units 550 arranged in Fig. 10 through a connection.
  • Material 551 is cured together.
  • Figures 12, 13 and 14 illustrate another important feature of a particular embodiment of the invention, which shows that while the unidirectional conductor is placed on the strip substrate, some other components may be provided to Some other components are embedded in the wire substrate assembly, and by further division, it can be made into a substrate containing conductive vias and other buried components.
  • the numeral symbol 6000 in Fig. 12 illustrates a string of elements in which a plurality of elements 601 are strung together, and a connection point 603 of the element 601 and the wire 602 may be an electrically conductive connection, such as soldering; the numeral symbol 6100 in Fig.
  • FIG. 12 A front view 610 and a cross-sectional view 611 of a strip substrate are illustrated; numeral 7000 in Figure 13 illustrates a unidirectional wire 630, 631 (front view, cross-sectional view) and component string 600, 601 (front view, cross section) Figure 7) is simultaneously disposed on the strip substrate 620, 621 (front view, cross-sectional view); numeral 8000 in Figure 14 illustrates the lamination of a plurality of said strip-shaped substrates provided with unidirectional wires and component strings Together, a columnar substrate having unidirectional wires 632 and element strings 601 arranged at a predetermined pitch in the substrate 621 is formed, which can be further solidified into a whole by a set condition, thereby making a The unidirectional wire and the wire element substrate of the component string are integrated, and the substrate including the conductive via and the buried component is further formed by division.
  • Figure 15 illustrates another important feature of a particular embodiment of the invention, which shows that the unidirectional wire disposed on the strip substrate is a circular thin metal wire, such as a thin copper wire, wherein the metal wire can It can be laid on a strip substrate or embedded in a strip substrate.
  • Numeral symbol 9000 in Fig. 15 indicates that metal wires 911, 912 (front view, cross-sectional view) are laid on the strip-shaped substrate 901, 902 (front view, cross-sectional view), and numeral numeral 9300 indicates that the metal wire 932 is buried in the strip-shaped base.
  • the material 921, 922 front view, sectional view).
  • Figure 16 illustrates a method of embedding a metal wire in a strip substrate.
  • the numeral symbol 9310 in Fig. 16 indicates that the metal wires 931, 932 (front view, sectional view) are first laid on a strip substrate 941, 942 (front view, sectional view) at a predetermined pitch, and then in a strip shape.
  • the substrate 942 is covered with a slurry for forming a strip-shaped substrate and formed into a strip-shaped substrate 921, 922 (front view, cross-sectional view), and then a strip-shaped substrate 921, 922 including a metal wire 932 (front view, The cross-sectional view is peeled off from the strip substrate 942 to form a strip-shaped substrate 921, 922 containing the buried metal wires 932.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

制造包含导电通孔的基板的方法，以及由此得到的导线基材集成体。该方法包括：在带状基材上制作具有设定间距的单向导线；把多个含有单向导线的带状基材叠压在一起形成一个包含单向导线的基材柱体；固化基材柱体，从而制成在基材中包含单向导线的导线基材集成体；把导线基材集成体分割成片，从而制成多个包含导电通孔的基板。

Description

制造含有导电通孔的基板的方法及导线基材集成体
相关申请的交叉引用
本申请要求享有于2014年06月27日提交的名称为“制造含有导电通孔的基板的方法及导线基材集成体”的中国专利申请CN201410298168.5的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明一般地涉及集成电路半导体封装技术，特别地涉及制造包含导电通孔的基板的方法。通过在包含导电通孔的基板的上下表面制作电路和焊盘，可以把所述包含导电通孔的基板进一步制作成用于集成电路半导体封装的电路基板。
背景技术
有通孔的(TSV:Through Silicon Via,TSV:Through Substrate Via and TGV:Through Glass Via)硅，玻璃，陶瓷或有机材料基板在集成电路半导体封装技术中已有广泛的应用，是3D集成电路半导体封装中的关键元件。基于含有通孔的基板制成的电路基板通常用于3D和2.5D集成电路半导体封装技术中，是整合电子产品功能的元件。含有通孔的基板包括含有通孔的硅基板，玻璃基板，陶瓷基板和有机材料基板。目前，使用的含有通孔的基板的制造方法可以分为两类：一类是基于基板的方法，另一类是基于通孔的方法。
基于基板的方法基本上包括：
1)在基板上先开一些所需的孔；
2)然后用导电材料填充这些孔，从而形成一个含有导电通孔的基板。
基于通孔的方法基本上包括：
1)先在一个载体上制作一些点状的小金属柱；
2)然后用一个基板材料覆盖这些点状的小金属柱，再去掉所述的载体并打磨上下表面以露出点状的小金属柱，从而形成一个含有导电通孔的基板。
目前，含有通孔的基板的使用是通过制作于基板表面的电路和焊盘把含有通孔的基板进一步制作成含有通孔的电路基板，从而在集成电路半导体封装中把位 于基板上表面的电子元件与基板下方的其它电子元件或印刷电路板相连接，位于基板上表面的电路也可以使位于其上的电子元件先直接地进行通讯，然后再与基板下方的其它电子元件或电路板相连接。
在现有技术中的含有通孔的基板的基本特征包括：
1)基板的上下表面是平整的以便在其上进一步制作电路和焊盘；
2)通孔是一种导电的金属小柱，嵌入在基板中并按照所需的间距形成规则的排列；
3)基板的基体材料用作保持通孔和在其上进一步制作电路和焊盘的一种载体。
需要注意的是，这些现有技术中的含有导电通孔的基板在制造和使用上具有许多局限性。由于其制造工艺，一些局限性包括：
1)其制造是非常费时和昂贵的；
2)其中所述的金属小柱或通孔不包含绝缘外层；
3)由于是通过刻蚀，机械钻头或激光开孔，通孔的侧边不是很平整；
4)通孔的直径不能非常小，现有技术制造通孔小于10微米，并且超过一定厚度(如100微米以上)的基板是非常困难的；
5)通孔的间距不能非常小,(如现有技术在100微米以上厚度的基板上制造小于50微米间距的通孔是困难和昂贵的；
6)含有通孔的基板的厚度受到通孔尺寸和间距的限制，通孔间距越小，基板就得越薄。
发明内容
本发明是本申请人于2013年12月5日和2013年12月27日提交的中国发明专利申请CN201310651705.5和CN201310737666.0的进一步发展。所述的已提交的专利申请CN201310651705.5公开了一种基于金属线图形阵列制造金属线集成体，并进一步制造含有图形阵列通孔的基板的方法。该方法包括如下关键步骤：制作一个金属线图形阵列；在金属线之间和周围的空间制作固态介电基体，从而形成一个包含金属线图形阵列的金属线集成体；把所述金属线集成体分割成片，从而形成多个含有图形阵列通孔的基板。所述的已提交的专利申请CN201310737666.0公开了一种基于导线的在厚度方向导电的单向导电板的制造 方法。该方法包括如下关键步骤：制作一个经由单向紧密排列的导线制成的导线集成体；把所述导线集成体体分割成片，从而制成多个单向导电板或包含导电通孔的基板。
本发明的制造含有导电通孔的基板的方法，包括如下关键步骤：制作或提供含有单向导线的带状基材，其中所述单向导线沿着带状方向按设定间距排列；把多个含有所述单向导线的带状基材叠压在一起，从而制成在基材中含有按设定间距排列的单向导线的一个柱状基材，其中单向导线在柱状基材叠层方向的间距由带状基材的厚度决定；把所述含有单向导线的柱状基材通过设定的条件固化成一个整体，从而制成一个含有单向导线的导线基材集成体；把所述已固化成一个整体的在基材中含有按设定间距排列的单向导线的导线基材集成体分割成片，从而制成多个含有导电通孔的基板。
本发明的制造含有导电通孔的基板的方法，其特征在于，所述带状基材是生陶瓷带，带状玻璃或带状聚合物材料，带状基材包含的导线是金属线或是通过导电浆料印制的导线。所述制造方法，本发明的制造含有导电通孔的基板的方法，该方法进一步包含如下步骤：把所述含有导电通孔的基板通过切割其边缘进一步制作成不同形状的含有导电通孔的基板。所述制造方法，其特征在于，制作含有单向导线的带状基材的步骤是在带状基材上通过导电浆料印制按设定间距单向排列的导线，或在带状基材上铺设按设定间距单向排列的金属线。所述制造方法，其特征在于，制作含有单向导线的带状基材的步骤是在制作带状基材的同时，在带状基材中埋入按设定间距单向排列的导线，其特征在于，在一个带状衬底上先铺设按设定间距排列金属线，再在带状衬底上覆盖制作带状基材的浆料并制成带状基材，然后再把包含金属线的带状基材从所述带状衬底上剥离，从而制成含有埋入式金属线的带状基材。所述制造方法，其特征在于，在制作含有单向导线的带状基材时加入其它的器件，从而制成同时含有导电通孔和埋入式器件的基板。所述制造方法，其特征在于，该方法进一步包含如下步骤：把多个含有单向导线的柱体单元进一步固化在一起，从而制成一个经由柱体单元含有单向导线的导线基材集成体。所述制造方法中的经由把多个含有单向导线的柱体单元进一步固化在一起的步骤，其特征在于，其中的部分柱体与其它含有单向导线的柱体单元是不同的，如不包含单向导线的柱体，包含其它构件的柱体，具有不同形状的柱体，由不同材料构成的柱体。所述制造方法，其特征在于，该方法进一步包含如下步 骤：其包含在所述的含有导电通孔的基板的上下表面制作电路和焊盘的步骤，从而进一步制成含有导电通孔的电路基板。所述制造方法制成的导线基材集成体；包括：基体材料和嵌入在所述基体材料中的单向导线，其特征在于所述的单向导线按设定间距排列。所述导线基材集成体，其特征在于，所述基体材料进一步包含其它的元件串。所述导线基材集成体，其特征在于，所述基体材料进一步包含沿导线方向排列的其它柱体。
在本发明中，关键的发明构思是经由包含单向导线的带状基材制成一个在基材中包含按设定间距单向排列的导线的柱体，这里称作导线基材集成体。本发明的一些优点包括：
1)可便宜和快捷地制造含有导电通孔的基板；
2)导电通孔的尺寸及其间距可以非常小；所述单向导电板可具有任意选择的厚度；
3)基板的厚度可根据需要来任意选择的，不受导电通孔的尺寸及其间距的限制；
4)可在陶瓷或玻璃基板中使用铜导线。本发明中一些其它的优点，特征和相关的发明性概念会参照下面的附图说明在本发明的具体实施方式中加以详述。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1为本发明一个实施例中的带状基材的示意图，包括正视图和横截面图；
图2为本发明一个实施例中含有单向导线的带状基材的示意图，包括正视图和横截面图；
图3为本发明一个实施例中把多个含有单向导线的带状基材叠压在一起的横截面的示意图；
图4为本发明一个实施例中把多个含有单向导线的带状基材叠压在一起形成的柱体进一步固化后制成的导线基材集成体的示意图；
图5为本发明一个实施例中把导线基材集成体分割成片，从而制成多个含有导电通孔的基板的示意图；
图6为本发明一个实施例中在含有导电通孔的基板的上下表面制作电路和焊盘，从而进一步制成含有导电通孔的电路基板的示意图；
图7为本发明一个实施例中含有多个导线排列单元的导线基材集成体的横截面示意图；
图8为本发明一个实施例中把多个含有导电通孔的基板单元固化在一起，从而制成一个经由基板单元含有导电通孔的基板的示意图，其同时示意通过切割其边缘进一步制作成不同形状的含有导电通孔的基板的步骤；
图9为本发明一个实施例中包含单向导线的柱体单元的示意图；
图10和图11为本发明一个实施例中把多个包含单向导线的柱体集成并固化在一起，从而制成一个经由含有单向导线的柱体单元的集成而制成的导线基材集成体的示意图；
图12和13为本发明一个实施例中把其它元件和导线同时铺设在带状基材上的示意图；
图14为本发明一个实施例中把多个含有单向导线和其它元件的带状基材叠压在一起形成一个柱体的横截面的示意图；
图15示意包含在带状基材中的导线是金属线，其可以铺设在带状基材的表面，也可以埋入带状基材中；
图16为本发明一个实施例中制作包含埋入式金属线的带状基材的示意图；在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
为清楚地通过参照附图说明本发明的具体实施方式，首先对一些使用的术语解释如下：
1)带状基材，其代表一个长方形的片状材料，其长度比宽度大很多；多个叠压在一起的带状基材形成一个柱状基材，其可通过设定的条件，如一定的温度和压力，固化成一个整体；
2)单向导线，其代表沿着一个方向分布的多个导线；
3)导线基材集成体，其代表包含单向导线的一个柱状基材，其中的单向导线按设定间距排列；
4)基板，其代表一个片状材料，如一片陶瓷，一片玻璃，一片晶片，或一片聚合物材料；
5)导电通孔，其代表嵌在基板中并贯通基板厚度方向的导电通道，如柱状 金属；
6)含有导电通孔的基板，其代表含有按设定间距排列或按设定图案分布的导电通孔的基板；
7)含有导电通孔的电路基板，其代表在上下表面进一步制作有电路和焊盘的含有导电通孔的基板。
需要注意的是，以上的术语解释仅是为了说明的目的，而不限制本发明的范围和精神。
图1、图2、图3、图4、图5和图6为本发明一个实施例中制造含有导电通孔的基板的方法的示意图。图1中的1100示意从一个带状基材开始的步骤，其中数字符号101和102分别代表带状基材的正视图和和截面图；图2中的1200示意在所述的带状基材上制作按设定间距排列的单向导线的步骤，其中数字符号101和102与图1相同，分别代表所述带状基材的正视图和和截面图，进一步的数字符号201和202分别代表按设定间距排列的单向导线的正视图和和截面图；图3中的1300示意把多个所述含有单向导线的带状基材叠压在一起，从而制成在基材中含有按设定间距排列的单向导线的一个柱状基材的步骤，单向导线在柱状基材叠层方向的间距由带状基材的厚度决定，其中数字符号102和202与前图相同，分别代表带状基材和按设定间距排列的单向导线，进一步的数字符号301代表叠层之间的界面；图4中的1400示意把所述含有单向导线的柱状基材通过设定的条件(如一定的温度和压力)固化成一个整体，从而制成一个含有单向导线的导线基材集成体的步骤，其中数字符号401和402分别代表固化后的柱状基材和包含在所述固化后的柱状基材中的按设定间距排列的单向导线；图5中的1500示意把所述已固化成一个整体的在基材中含有按设定间距排列的单向导线的导线基材集成体分割成片，从而制成多个含有导电通孔的基板的的步骤，其中数字符号501和502分别代表在所述含有导电通孔的基板中的基材和导电通孔，数字符号503和504分别代表在所述含有导电通孔的基板中的基材和导电通孔的截面图；图6中的1505示意在所述的含有导电通孔的基板的上下表面制作电路和焊盘，从而进一步制成含有导电通孔的电路基板的步骤，其中进一步的符号A-A截面图位置，进一步的数字符号511和512分别代表制作在含有导电通孔的基板503和504的上下表面的电路和焊盘层。
图1、图2、图3、图4、图5和图6示意了一个本发明的具体的实施方式的 一个实施例，下面公开的是按照所述实施例的一些具体的应用的例子：
第一个例子是：带状基材是100到200微米的可低温烧结的生陶瓷带，单向导线是通过导电浆料印制在所述生陶瓷带上印刷导线，所述单向导线的宽度和厚度分别在60微米和2微米以下，所述单向导线的间距在200微米以下。在这个具体的实施例中，带状基材的宽度可以在30毫米以下，从而制成一个宽度在30毫米以下的导线基材柱体或集成体；带状基材的宽度也可以在100毫米以上，从而制成一个宽度在100毫米以上的导线基材集成体。选择宽度小的带状基材的好处是可以更容易和高质量地固化或烧结通过含有单向导线的带状基材叠压在一起形成的柱状基材。选择宽度大的带状基材的好处是其进一步制成的含有导电通孔的基板可以直接利用现有的生产工艺，如晶片制造工艺或印刷电路板制造工艺在其上大规模制作电路和焊盘。
第二个例子是：带状基材是100到300微米的可低温烧结的生陶瓷带，单向导线是铺设在所述生陶瓷带上金属线，如直径小于20微米的细铜线，其它的与第一个例子相同。
第三个例子是：带状基材是100到300微米的可低温烧结的生陶瓷带，单向导线是埋入在所述生陶瓷带中金属线，如直径小于20微米的细铜线，其它的与第一个例子相同。
图7示意了一个本发明的具体的实施方式中的一个特征，其表示一个导线基材集成体中包含多个单向导线单元，其进一步分割成的含有导电通孔的基板对应地包含多个导电通孔单元，在其上制作电路和焊盘后，其可沿着单元间进一步分割成多个含有导电通孔的电路基板单元，每一个所述含有导电通孔的电路基板单元将应用于一个集成电路半导体封装中。
图8示意了一个本发明的具体的实施方式中的另一个特征，其表示通过切割一个含有导电通孔的基板的边缘进一步制作成不同形状(如圆形)的含有导电通孔的基板。这样做的原因是为了配合目前的晶片制造工艺对基板形状的要求。如果将来的晶片制造工艺可以在方形或长方形的基板上制作电路和焊盘，这个把方形或长方形的含有导电通孔的基板切割成圆形的步骤就不需要了。
图9、图10和图11示意了一个本发明的具体的实施方式中的一个重要特征，其表示通过把多个含有单向导线的柱体单元进一步固化在一起，从而制成一个包含多个柱体单元的导线基材集成体或柱体集成体的步骤，其中在把多个含有单向 导线的柱体单元集中在一起时，可以加入部分其它的柱体，如不同材料或形状的柱体，包含其它构件的柱体，从而可制成即含有导电通孔又含有其它元件的基板。图9示意了一个含有单向导线的柱体单元，其中数字符号1530代表一个在基材531中含有单向导线532的柱体单元。图10中的数字符号1540示意把多个含有单向导线的柱体单元530排列在一起，图11中的数字符号1550示意把图10示意的排列在一起的多个柱体单元550通过一个连接材料551固化在一起。
图12、图13和图14示意了一个本发明的具体的实施方式中的另一个重要特征，其表示在带状基材上设置单向导线的同时，也可以设置一些其它的元件，从而把一些其它的元件埋入在导线基材集成体中，通过进一步的分割，其可制成即含有导电通孔又含有其它埋入式元件的基板。图12中的数字符号6000示意了一个元件串，其中的导线602把多个元件601串在一起，元件601和导线602的连接点603可以是导电连接，如焊接；图12中的数字符号6100示意了一个带状基材的正视图610和横截面图611；图13中的数字符号7000示意把单向导线630，631(正视图，截面图)和元件串600，601(正视图，截面图)同时设置在带状基材620，621(正视图，截面图)上；图14中的数字符号8000示意把多个所述的设置了单向导线和元件串的带状基材叠压在一起，从而制成在基材621中含有按设定间距排列的单向导线632和元件串601的一个柱状基材，其可进一步通过设定的条件固化成一个整体，从而制成一个含有单向导线和元件串的导线元件基材集成体，并通过分割进一步制成同时含有导电通孔和埋入式元件的基板。
图15示意了一个本发明的具体的实施方式中的另一个重要特征，其表示在带状基材上设置的单向导线是圆形的细金属线，如细铜线，其中的金属线可以铺设在带状基材上，也可以埋在带状基材中。图15中的数字符号9000示意金属线911，912(正视图，截面图)铺设在带状基材901，902(正视图，截面图)上，数字符号9300示意金属线932埋在带状基材921，922(正视图，截面图)中。
图16示意了一个在带状基材中埋入金属线的方法。图16中的数字符号9310示意先在一个带状衬底941，942(正视图，截面图)上先铺设按设定间距排列金属线931，932(正视图，截面图)，再在带状衬底942上覆盖制作带状基材的浆料并制成带状基材921，922(正视图，截面图)，然后再把包含金属线932的带状基材921，922(正视图，截面图)从带状衬底942上剥离，从而制成含有埋入式金属线932的带状基材921，922。
需要说明的是，以上参照实施例和附图说明对本发明的描述仅为举例说明，而不是限定本发明的精神和范围，熟悉此技术者当可据此进行修改而得到等效实施例。

Claims (14)

  1. 一种制造含有导电通孔的基板的方法，该方法包括：
    制作或提供含有单向导线的带状基材，其中所述单向导线沿着带状方向按设定间距排列；
    把多个含有所述单向导线的带状基材叠压在一起，从而制成在基材中含有按设定间距排列的单向导线的一个柱状基材，其中单向导线在柱状基材包含的带状基材的叠层方向的间距由带状基材的厚度决定；
    把所述含有单向导线的柱状基材通过设定的条件进一步固化成一个整体，从而制成一个含有单向导线的导线基材集成体；
    把所述已固化成一个整体的在基材中含有按设定间距排列的单向导线的导线基材集成体分割成片，从而制成多个含有导电通孔的基板。
  2. 如权利要求1所述的制造含有导电通孔的基板的方法，其中，所述带状基材是生陶瓷带，带状玻璃，带状玻璃陶瓷或带状聚合物材料，带状基材包含的导线是金属线或是通过导电浆料印制的导线。
  3. 如权利要求1所述的制造含有导电通孔的基板的方法，其中，包含把所述含有导电通孔的基板通过切割其边缘进一步制作成不同形状的含有导电通孔的基板的步骤。
  4. 如权利要求1所述的制造含有导电通孔的基板的方法，其中，制作含有单向导线的带状基材的步骤是在带状基材上通过导电浆料印制按设定间距单向排列的导线，或在带状基材上铺设按设定间距单向排列的金属线。
  5. 如权利要求1所述的制造含有导电通孔的基板的方法，其中，制作含有埋入式单向导线的带状基材的步骤是在制作带状基材的同时，在带状基材中埋入按设定间距单向排列的导线。
  6. 如权利要求5所述的制造含有导电通孔的基板的方法，其中，在一个带状衬底上先铺设按设定间距排列的金属线，再在带状衬底上覆盖制作带状基材的浆料并制成带状基材，然后再把包含金属线的带状基材从所述带状衬底上剥离，从而制成含有埋入式金属线的带状基材。
  7. 如权利要求1所述的制造含有导电通孔的基板的方法，其中，在制作含有单向导线的带状基材时加入其它的器件，从而制成同时含有导电通孔和埋入式器 件的基板。
  8. 如权利要求1所述的制造含有导电通孔的基板的方法，其中，包含把多个含有单向导线的柱体单元进一步固化在一起，从而制成一个包含多个柱体单元的柱体集成体的步骤。
  9. 如权利要求8所述的制造含有导电通孔的基板的方法，其中，其中的部分柱体与其它含有单向导线的柱体单元是不同的，如不包含单向导线的柱体，包含其它构件的柱体，具有不同形状的柱体，由不同材料构成的柱体。
  10. 如权利要求1所述的制造含有导电通孔的基板的方法，其中，包含把多个含有导电通孔的基板单元进一步固化在一起的步骤，从而制成一个含有多个基板单元的基板的步骤。
  11. 如权利要求1所述的制造含有导电通孔的基板的方法，其中，其包含在所述的含有导电通孔的基板的上下表面制作电路和焊盘，从而进一步制成含有导电通孔的电路基板的步骤。
  12. 一种在如权利要求1所述的方法中制成的导线基材集成体，包括：基体材料和嵌入在所述基体材料中的单向导线，其中所述的单向导线按设定间距排列。
  13. 如权利要求12所述的导线基材集成体，其中，所述基体材料进一步包含其它的元件。
  14. 如权利要求12所述的导线基材集成体，其中，所述基体材料进一步包含沿导线方向排列的其它柱体。
PCT/CN2015/082479 2014-06-27 2015-06-26 制造含有导电通孔的基板的方法及导线基材集成体 WO2015197017A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410298168.5A CN104124175A (zh) 2014-06-27 2014-06-27 制造含有导电通孔的基板的方法及导线基材集成体
CN201410298168.5 2014-06-27

Publications (1)

Publication Number Publication Date
WO2015197017A1 true WO2015197017A1 (zh) 2015-12-30

Family

ID=51769544

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/082479 WO2015197017A1 (zh) 2014-06-27 2015-06-26 制造含有导电通孔的基板的方法及导线基材集成体

Country Status (2)

Country Link
CN (1) CN104124175A (zh)
WO (1) WO2015197017A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104124175A (zh) * 2014-06-27 2014-10-29 申宇慈 制造含有导电通孔的基板的方法及导线基材集成体

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0676909A (ja) * 1992-08-28 1994-03-18 Bridgestone Corp 異方導電性コネクター及びその製造方法
JPH11233917A (ja) * 1998-02-16 1999-08-27 Sumitomo Metal Electronics Devices Inc 積層基板の製造方法
JP2001266669A (ja) * 2000-03-17 2001-09-28 Hitachi Cable Ltd 異方性導電シートの製造方法
TW569655B (en) * 2001-08-30 2004-01-01 Nitto Denko Corp Method for manufacturing anisotropically conductive connector
CN104124175A (zh) * 2014-06-27 2014-10-29 申宇慈 制造含有导电通孔的基板的方法及导线基材集成体

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681364B (zh) * 2013-12-19 2016-05-04 贵州振华风光半导体有限公司 无引线球脚表贴式高密度厚膜混合集成电路的集成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0676909A (ja) * 1992-08-28 1994-03-18 Bridgestone Corp 異方導電性コネクター及びその製造方法
JPH11233917A (ja) * 1998-02-16 1999-08-27 Sumitomo Metal Electronics Devices Inc 積層基板の製造方法
JP2001266669A (ja) * 2000-03-17 2001-09-28 Hitachi Cable Ltd 異方性導電シートの製造方法
TW569655B (en) * 2001-08-30 2004-01-01 Nitto Denko Corp Method for manufacturing anisotropically conductive connector
CN104124175A (zh) * 2014-06-27 2014-10-29 申宇慈 制造含有导电通孔的基板的方法及导线基材集成体

Also Published As

Publication number Publication date
CN104124175A (zh) 2014-10-29

Similar Documents

Publication Publication Date Title
US10045436B2 (en) Printed circuit board and method of manufacturing the same
CN108417559A (zh) 半导体封装装置及其制造方法
US20150090476A1 (en) Package carrier and manufacturing method thereof
TWI296492B (en) Un-symmetric circuit board and method for fabricating the same
TW201438537A (zh) 配線基板的製造方法
TW201251556A (en) Printed circuit board and method for manufacturing the same
TW201513761A (zh) 電路基板、電路基板的製造方法及電子機器
WO2016058543A1 (zh) 制造功能性基板的方法和功能性基板
CN107295746A (zh) 器件载体及其制造方法
TWI266375B (en) Semiconductor device and manufacture method thereof
US20150014849A1 (en) Coreless package structure and method for manufacturing same
JP4398683B2 (ja) 多層配線基板の製造方法
WO2015197017A1 (zh) 制造含有导电通孔的基板的方法及导线基材集成体
JP6099902B2 (ja) 配線基板の製造方法
WO2015081807A1 (zh) 制造含有图形阵列通孔的基板的方法和金属线集成体
WO2016129705A1 (ja) 積層回路基板の形成方法及びこれにより形成された積層回路基板
TWI677271B (zh) 線路基板及其製作方法
JP6409292B2 (ja) コイル装置
WO2016008360A1 (zh) 制造导线框架体的方法和导线框架体
JP5257518B2 (ja) 基板製造方法および樹脂基板
CN108461405B (zh) 线路载板及其制造方法
TW201626500A (zh) 電子封裝結構之製法
CN108281379B (zh) 一种用于制造包含导电通孔的基板的方法
CN108288611B (zh) 一种导线基材柱体
CN105023990B (zh) 一种基于无机物的复合led积层电路板的制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15811745

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15811745

Country of ref document: EP

Kind code of ref document: A1