WO2015184654A1 - 一种基于hsd结构的tft-lcd显示面板及制作方法 - Google Patents

一种基于hsd结构的tft-lcd显示面板及制作方法 Download PDF

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Publication number
WO2015184654A1
WO2015184654A1 PCT/CN2014/080122 CN2014080122W WO2015184654A1 WO 2015184654 A1 WO2015184654 A1 WO 2015184654A1 CN 2014080122 W CN2014080122 W CN 2014080122W WO 2015184654 A1 WO2015184654 A1 WO 2015184654A1
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tft
lines
segment
segment portion
line
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French (fr)
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杜鹏
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3454—Amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes

Definitions

  • the present invention relates to the field of liquid crystal panel design, and in particular to a TFT-LCD display panel of a HSD (Half Source Driving) structure and a manufacturing method thereof.
  • Background technique HSD (Half Source Driving) structure
  • liquid crystal panel of HSD structure In order to reduce the manufacturing cost of liquid crystal panel production, a liquid crystal panel of HSD structure emerged. This type of panel doubles the number of outlines and halve the number of data lines, thereby reducing the number of chips driving the data lines and reducing the cost.
  • the width of the ⁇ line is often set large when designing the liquid crystal panel.
  • the number of the liquid crystal panels of the HSD structure is doubled, and the width of the gate lines is increased, which causes the pixel area of the liquid crystal panel to be reduced, and the aperture ratio of the pixels is lowered, thereby adversely affecting the transmittance of the pixels.
  • the present invention provides a liquid crystal panel design in which an HSD structure can simultaneously improve pixel transmittance.
  • a TFT-LCD display panel based on an HSD structure comprising: a sub-pixel unit array;
  • each pair of gate lines is disposed between adjacent two rows of sub-pixel units, each of the gate lines includes repeatedly arranged segments, the segments having segmented portions of different widths, wherein a TFT element connected to the pixel electrode of the sub-pixel unit is disposed on the segment portion having a relatively large width;
  • a plurality of data lines are perpendicular to the polar lines, and two adjacent data lines are spaced apart by two or more sub-pixel units.
  • the segment comprises a first segment portion and a second segment portion, wherein a width of the first segment portion is greater than a width of the second segment portion.
  • each pair of machine wires are arranged such that a first segment portion of one of the contour lines is opposite to a second segment portion of the other pole line, and the second segment portion is different from the other A segmented portion is opposed such that the width of each of the pair of polar lines as a whole occupies in the row direction of the pixel unit.
  • the first segment portion and the second segment portion are joined such that the segments are flush on one side at the joint position.
  • the first segment portion and the second segment portion are joined such that the segments are not flush on both sides at the joint position, such that the two pairs are
  • the surrounded sub-pixel units are staggered in the horizontal direction.
  • the data line is spaced apart from a region where the source of each TFT element disposed on the electrode line is located, and the data line passes through each of the lead wires extending from the source and the source of each TFT element. connection.
  • the data line is disposed to be provided with a segmented portion of the TFT element on the meander line and serves as a source of the TFT.
  • a method for fabricating a TFT-LCD display panel based on an HSD structure including:
  • the patterned formation layer includes a plurality of pairs of horizontal lines arranged in a horizontal direction, each of the gate lines being repeatedly arranged by each segment, wherein the segments have different widths In the segmented part, different grid lines are separated by a certain distance, and the two machine lines in the pair are closely arranged in an electrically isolated manner;
  • the segment of the formed gate line comprises a first segment portion and a second segment portion, wherein the width of the first segment portion is greater than the width of the second segment portion, each Arranging the outlines into one of the grid lines
  • the first segment portion is opposite the second segment portion of the other pole line
  • the second segment portion is opposite to the first segment portion of the other gate line such that each pair of pole lines are entirely along the pixel unit
  • the width occupied by the row direction is the same.
  • the first segment portion and the second segment portion are formed such that the segment is flush on one side of the junction of.
  • the data line when the data line is formed, the data line is passed through a layer of semiconductor material formed on the previous outline, and the portion of the data line passing through the line is the source of the TFT element.
  • the gate lines are formed by repeatedly arranging segments having different widths, and a TFT element connected to the pixel electrode of the sub-pixel unit and a segment portion having a relatively small width are disposed on the segment portion having a relatively large width.
  • the width can be set as small as possible.
  • FIG. 1 is a display panel of a conventional HSI) structure.
  • Figure 2 is a view showing a display panel of the first embodiment of the present invention.
  • FIG. 3 is a layout view of the TFT electrode of Figure 2;
  • Figure 4 is a view showing a display panel of a second embodiment of the present invention.
  • Figure 5 is a view showing a display panel of a third embodiment of the present invention.
  • TFT switching element
  • sub-pixel unit 3, the first segment, 4, the second segment, 5, TFT gate, 6, TFT source, 7, TFT drain, 8.
  • Contact hole connection between TFT drain and pixel electrode.
  • the current LCD panel production adopts the HSD structure, which doubles the number of machine lines and reduces the number of corresponding data lines by 1/2.
  • the total number of signal lines in the display panel of the HSD structure is significantly reduced, thereby reducing the number of data line driving chips, and ultimately achieving the purpose of saving manufacturing costs.
  • the display panel of the conventional HSD structure is provided with a pole line in a horizontal direction and a data line in a vertical direction.
  • the area enclosed by the ⁇ line and the data line is a pixel area.
  • Each of the pixel regions includes S sub-pixel units, and each of the sub-pixel units is provided with a switching element (TFT) as indicated by reference numeral 1 in the drawing.
  • a plurality of sub-pixel units constitute an array of sub-pixel units.
  • the width of the traces is often increased to reduce the load of the traces.
  • Such an approach reduces the area of the light-transmissive area of the pixel region, i.e., reduces the aperture ratio, thereby reducing the pixel transmittance. This problem is exacerbated by the fact that the number of gate lines such as HSD is doubled.
  • the present invention proposes a new HSD-structured TFT-LCD display panel.
  • Figure 2 is a schematic view of a first embodiment of the present invention.
  • the outline is the multiple lines marked by G (n) in the figure and is set in pairs, arranged in the horizontal direction.
  • a sub-pixel array is placed between each pair of pole lines.
  • Each of the lines is formed by a plurality of segments of different widths that are repeatedly arranged.
  • Each segment includes a first segment portion and a second segment portion, as indicated by the reference numerals in Fig. 2, the label 3 is the first segment portion, and the label 4 is the second segment portion.
  • the width of the first segment portion is greater than the width of the second segment portion.
  • a first segmented portion of one of the pair of gate lines is disposed opposite the second segmented portion of the other of the servo lines, and the second segmented portion is disposed opposite the first segmented portion of the other of the gate lines.
  • the first segment portion and the second segment portion of each pair of gate lines form a complementary structure such that each pair of gate lines as a whole has a uniform width along the row direction of the pixel unit.
  • the first segment portion and the second segment portion are arranged flush at one side of the joint position such that the sub-pixel units on the same row are arranged on the same horizontal line.
  • the shape of the sub-pixel unit is regular, and each sub-pixel unit is easily arranged with each other, thereby avoiding the occurrence of dark lines as much as possible.
  • the data line is the multiple columns labeled D in Figure 2.
  • the data lines are vertically aligned, and the adjacent two data lines are separated by two columns of sub-pixel units.
  • the switching element TFT connected to the pixel electrode in the sub-pixel unit is provided. Placed on the first segmented portion of the grid line. This requires that the width of the first segment portion be such as to meet the requirements for setting the TFT.
  • the TFT is not required to be disposed on the second segment portion, and the width of the second segment portion can be minimized, and the total width of the two gate lines disposed in pairs is reduced, thereby increasing the area of the pixel region.
  • the TFT is disposed in the first segment portion of the gate line instead of being disposed in the pixel region, thereby avoiding the TFT occupying the area of the pixel region and increasing the light transmissive region of the pixel, thereby improving the pixel opening rate and the transmittance.
  • the drain of the TFT is connected to the pixel electrode through a lead.
  • FIG. 3 is an enlarged view showing a source, a drain, and a drain of the switching element TFT labeled with reference numeral 1 in FIG. 2 and a connection relationship between the data line and the pixel electrode.
  • Figure 4 is a schematic view of a second embodiment of the present invention.
  • the wiring structure of the machine line and the data line of the present embodiment is completely the same.
  • the difference from the previous embodiment is that, due to the difference in the arrangement of the segment portions of the machine line, the joint positions of the first segment portion and the second segment portion are not flush on both sides, so that the sub-pixel units on the same row are not in the The same horizontal line.
  • the sub-pixel units surrounded by the four grid lines and the two data lines are vertically arranged in a staggered arrangement in a horizontal direction, and are arranged in a zigzag shape.
  • the layout of the sub-pixel units is different, but the display effect of the first embodiment can be achieved.
  • FIG. 5 is a schematic diagram showing a third embodiment of the present invention.
  • the shape and arrangement of the gate lines in this embodiment are identical.
  • the difference lies in the setting of the TFT.
  • the data line is directly introduced into the region of the TFT source of the first segment of the squall line, and serves as the source of the TFT.
  • the ruler is to reduce the width of the first segment of the TFT, increase the area of the pixel region, and further improve the aperture ratio and transmittance of the pixel.
  • the design of the data line is not limited to the above. In two embodiments, the first embodiment of the present invention and other liquid crystal display panels having similar switching elements and data line connections can be employed.
  • fabricating the TFT-LCD display panel as described above includes the following steps.
  • the desired glass substrate is selected, and the glass substrate is washed.
  • a G metal layer having a certain thickness is formed on the glass substrate by a sputtering method, and the metal layer is patterned by ruthenium.
  • a layer of positive PR (photoresist) is applied to the metal layer.
  • a gate line pattern is formed on the metal layer, exposure processing is performed using a corresponding G-MASK (G layer mask).
  • G-MASK G layer mask
  • the non-transmissive region corresponding grid pattern is composed of segments of different widths.
  • the first segment portion of the light transmitting region is opposite to the second segment portion of the adjacent non-light transmitting region, and the second segment portion is opposite to the first segment portion of the adjacent non-light transmitting region, and the two non-light transmitting portions
  • the regions form a complementary structure such that the width occupied by each pair of non-transmissive regions in the row direction is uniform.
  • the first segmented portion of the non-transmissive region is flush with the side of the second segmented portion at the joint position.
  • the development process, the wet etching process, and the PR dissection process are performed to obtain a pattern of the epipolar G line layer flushed on the side in which the first segment portion and the second segment portion are repeatedly arranged. This layer pattern is shown in the layer labeled G in Figure 2.
  • I engineering is performed to form a semiconductor layer TFT channel related pattern.
  • the substrate obtained by the G project is washed, and the first layer of SiNx film (silicon nitride film) is formed by the iil CVD (chemical vapor deposition) film formation process.
  • a second layer of S Nx film, an intrinsic a-Si film (amorphous silicon film), and an n+a-Si film CP-doped amorphous silicon film are successively formed by a CVD film forming process.
  • a layer of PR is applied, and the corresponding I-MASK G layer mask is used for exposure treatment.
  • the ⁇ -MASK non-transmissive region corresponds to a TFT portion provided in a first segment portion having a large width on the approximate line, and then subjected to development processing, chirp processing, and PR dissection processing to obtain a width larger on the polar line.
  • a segmented portion of the TFT gate I layer pattern is shown in the layer labeled I in Figure 2.
  • D engineering is performed, which is used to form a data line related pattern.
  • the substrate obtained by the I process is cleaned, and a D metal layer is formed to form a source and a drain of the TFT, and a data line.
  • a layer of PR is coated on the D metal layer to perform D-MASK (D layer mask) exposure treatment.
  • the D MASK at this location sets the source and drain locations of the TFT and the non-transmissive region of the data port.
  • development processing, wet etching processing, and PR separation processing are performed to obtain a D layer pattern of the TFT source and drain electrodes and the data lines.
  • the layer pattern is as shown in the layer labeled D in Figure 2.
  • the engineering is performed, which is used to generate the contact hole pattern.
  • the substrate obtained by D engineering is cleaned, and a passivation layer is formed by a CVD film forming process.
  • a layer of PR is applied to the layer, and C-MASK ( C-layer mask) Exposure treatment, where C-MASK is the anti-plate, and the position of the connection pixel electrode and the connection terminal which are required to contact the hole pattern is irradiated.
  • the development process, the dry etching process and the PR separation process are performed to obtain a contact hole.
  • C layer pattern This layer pattern is shown in the layer labeled C in Fig. 2.
  • PI engineering is performed, which is used to generate pixel electrodes.
  • the substrate obtained in the C project was washed, and a ruthenium (indium tin oxide) film having a certain thickness was formed by sputtering.
  • a layer of PR is applied and exposed by PI-MASK (PI layer mask), where the PI-MASK setting needs to leave the ⁇ pattern portion as a non-transmissive region.
  • PI-MASK PI layer mask
  • the TFT LCD display panel described in the second embodiment is different from the process flow for producing the display panel described in the first embodiment in the G engineering step.
  • the corresponding G-MAS adopts different non-transmissive area settings such that the first segment portion of the polar line and the second segment portion are on both sides at the joint position. Not flush. This causes the sub-pixel units on the same line not to be on the same horizontal line, and the sub-pixel units are arranged in a horizontally alternating manner, and the arrangement shape is similar to a zigzag shape.
  • the data line change setting side 1 introduces the semiconductor layer where the source of the TFT is located, and uses the data line as the source of the TFT.

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  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种基于HSD结构的TFT-LCD显示面板，包括：亚像素单元阵列：若干对栅线，其中，每对栅线设在相邻的两行亚像素单元（2）之间，每条栅线由重复排列的具有不同宽度的分段相接合而构成，其中，在宽度相对大的分段部分上设置有与亚像素单元的像素电极相连的TFT元件（1）；多条数据线，其与所述栅线垂直，且相邻的两条数据线间隔有两列或两列以上的亚像素单元（2）。将TFT元件（1）的设置位置由像素区移至栅线上，增大了像素区的开口率，从而提高了穿透率。

Description

一种基于 HSD结构的 TFT LC )显示面板及制作方法 相关申请的交叉引用
本申请要求享有 2014年 6 .月 5日提交的名称为 "一种基于 HSD结构的 TFT- LCD显 示面板及制作方法"的中国专利申请 CN201410247733.5的优先权， 该申请的全部内容通 过引用并入本文中。 技术领域
本发明涉及液晶面板设计技术领域， 具体地说， 涉及一种 HSD (Half Source Driving, 半源极驱动） 结构的 TFT- LCD显示面板及制作方法。 背景技术
为降低液晶面板生产的制作成本， 一种 HSD结构的液晶面板应运而生。 该种面板将 概线的数量加倍， 而数据线的数量减半， 从而减少驱动数据线的芯片的数量， 达到降低成 本的目的。
为了避免搠线电阻电容延迟效应造成的像素充电不足，在进行液晶面板设计时，往往 搠线的宽度设置的很大。 HSD 结构的液晶面板的機线数量加倍， 同时栅线的宽度增大， 会使得液晶面板的像素区面积减小，像素的开口率降低，进而对像素的穿透率产生不利的 影响。
基于上述情况， 亟需一种采用 HSD结构的并能提高像素穿透率的液晶面板设计。 发明内容
为解决上述问题， 本发明提供了一种 HSD结构的同时能提高像素穿透率的液晶面板 设计。
根据本发明的一个方面， 其提供了基于 HSD结构的 TFT- LCD显示面板， 其包括- 亚像素单元阵列；
若干对極线， 其中， 每对栅线设在相邻的两行亚像素单元之间， 每条栅线包括重复排 列的分段， 所述分段具有不同宽度的分段部分， 其中， 在宽度相对大的分段部分上设置有 与亚像素单元的像素电极相连的 TFT元件； 多条数据线，其与所述極线垂直，且相邻的两条数据线间隔有两列或两列以上的亚像 素单元。
根据本发明的一个实施例， 所述分段包括第一分段部分和第二分段部分， 其中， 所述 第一分段部分的宽度大于第二分段部分的宽度。
根据本发明的一个实施例，每对機线排列成其中一条概线的第一分段部分与另一条極 线的第二分段部分相对，而第二分段部分与另一条 «线的第一分段部分相对，使得所述每 对極线整体上沿像素单元的行方向所占据的宽度一致。
根据本发明的一个实施例，所述第一分段部分与所述第二分段部分接合成使得所述分 段在接合位置处的一侧上是平齐的。
根据本发明的一个实施例，所述第一分段部分与所述第二分段部分接合成使得所述分 段在接合位置处的两侧上是不平齐的，使得由两对 «线所包围的亚像素单元沿水平方向交 错排列。
根据本发明的一个实施例， 所述数据线与極线上设置的各个 TFT元件的源极所在的 区具有间隔，并 所述数据线分别通过从中延伸的各条引线与各个 TFT元件的源极连接。
根据本发明的一个实施例， 所述数据线设置成经过所述榲线上设有 TFT元件的分段 部分并作为所述 TFT的源极。
根据本发明的另一个方面， 还提供了一种基于 HSD结构的 TFT- LCD显示面板的制 作方法， 包括：
提供基板，
在所述基板上图案化形成栅线层，图案化形成的概线层上包括水平向排列的若干对極 线， 每条栅线由各个分段重复排列构成， 其中所述分段具有不同宽度的分段部分， 不同的 栅线对之间相隔一定距离， 機线对内的两条機线以电隔离方式紧密设置；
在所述栅线中宽度相对大的分段部分上沉积半导体材料， 以形成半导体层； 形成多条数据线以及在所述半导体层上形成 TFT元件的源漏电极， 其中， 所形成的 数据线之间间隔开，并与所述若千对極线垂直交叉，所述源漏电极形成于所述半导体材料 在数据线层上形成纯化层- 在相邻的任一 »线对与相邻的任何两条数据线所包圈的空间里制作两个或两个以上 的亚像素电极。
根据本发明的一个实施例，形成的栅线的分段包括第一分段部分和第二分段部分，其 中，所述第一分段部分的宽度大亍第二分段部分的宽度，每对概线排列成其中一条栅线的 第一分段部分与另一条極线的第二分段部分相对，而第二分段部分与另一条栅线的第一分 段部分相对， 使得所述每对極线整体上沿像素单元的行方向所占据的宽度一致。
根据本发明的一个实施例， 图案化形成所述栅线时，将所述第一分段部分与所述第二 分段部分形成为使得所述分段在连接处的一侧上是平齐的。
根据本发明的一个实施例，形成数据线时，使所述数据线经过之前概线上形成的半导 体材料层， 并将经过機线的这部分数据线 为 TFT元件的源极。
本发明带来了以下有益效果：
本发明中栅线由重复排列的具有不同宽度的分段相接合而构成，在宽度相对大的分段 部分上设置与亚像素单元的像素电极相连的 TFT元件， 宽度相对较小的分段部分宽度可 以设置的尽可能小， 这样的设计可以减小 S条栅线的总宽度， 同时将 TFT元件的设置位 置由像素区移至栅线上， 增大了像素区的开口率， 从而提高像素的穿透率。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显 而易见， 或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要 求书以及 图中所特别指出的结构来实现和获得。 f†图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技 术描述中所需要的附图做简单的介绍- 图 I是传统的 HSI)结构的显示面板图；
图 2是本发明第一个实施例的显示面板图；
图 3是图 2 中 TFT电极布置结构图；
图 4本发明第二个实施例的显示面板图；
图 5本发明第三个实施例的显示面板图；
其中： 1、 开关元件 （TFT) ， 2、 亚像素单元， 3、 第一分段部分， 4、 第二分段部分， 5、 TFT栅极， 6、 TFT源极， 7、 TFT漏极， 8、 接触孔（TFT漏极与像素电极连接部位） 。 具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式,借此对本发明如何应用技术 手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是， 只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形 成的技术方案均在本发明的保护范围之内。 本发明中所使用的方位词如 "上" "下" "前" "后" 等不作为对各组成部分结构位置的限定。
此外， 在下面的描述中， 提供一些具体的细节， 例如长度、 宽度、 形状等， 以提供对 本发明的实施例的全面理解。然而， 相关领域的技术人员将明白， 本发明无需上述一个或 多个具体的细节便 实现， 或者也可采用其它方法、 组件、 材料等实现。 在其它示例中， 周知的结构、 材料或操作并未详细示出或描述以免模糊本发明的各个方面。
目前的液晶显示面板生产采用 HSD结构， 将機线的数量加倍， 相应的数据线的数量 减少 1/2。 与传统的液晶显示面板结构相比， HSD结构的显示面板中信号线的总数量会有 明显的减少， 从而实现减少数据线驱动芯片的数量， 最终达到节省制造成本的目的。如图 1所示为传统 HSD结构的显示面板， 该面板水平方向设置極线， 垂直方向设置数据线。 搠线与数据线围起来的区域为像素区。每个像素区包括 S个亚像素单元，每个亚像素单元 设有如 1图中标注 1所示的开关元件 （TFT) 。 多个亚像素单元组成亚像素单元阵列。
随着液晶显示面板尺寸的增大，面板上走线的电阻和寄生电容都会迅速增力^所以在 设计时，往往会把走线的宽度加大来降低走线的负载。这样的做法会使像素区的的透光区 面积减小， 即开口率减小， 从而降低像素的穿透率。 对亍 HSD这样的栅线数量加倍的靣 板， 这个问题会更加严重。
为了提高 HSD结构的 TFT- LCD显示面板的像素的穿透率， 本发明提出了一种新的 HSD结构的 TFT- LCD显示面板的设 i† -。
如图 2所示为本发明的第一个实施例的示意图。
概线为图中 G (n) 标注的多行并成对设置， 沿水平方向排列。 每对極线之间设置亚 像素单元阵列。每条機线由重复排列的不同宽度的分段相接合而构成。各个分段包括第一 分段部分和第二分段部分， 如图 2中标注所示， 标注 3为第一分段部分， 标注 4为第二分 段部分。其中第一分段部分的宽度大于第二分段部分的宽度。每对栅线中的一条搠线的第 一分段部分与另一条機线的第二分段部分相对设置，而第二分段部分与另一条栅线的第一 分段部分相对设置。每对栅线第一分段部分和第二分段部分形成互补结构，使得每对栅线 整体上沿像素单元的行方向所 ίΓ据的宽度一致。
如图 2所示，在该实施例中，第一分段部分与第二分段部分在一侧的接合位置处平齐 设置，使得同一行上的亚像素单元排列在同一条水平线上。这样使得亚像素单元的形状规 则， 各个亚像素单元相互之间容易配合设置， 尽可能的避免暗线的发生。
数据线为图 2中 D 标注的多列。 数据线垂直栅线排列， 相邻的两条数据线间隔 有两列亚像素单元。
再次如图 2所示， 在本实施例中， 与亚像素单元中像素电极相连的开关元件 TFT设 置于栅线的第一分段部分上。 这就需要第一分段部分的宽度要达到设置 TFT的要求。 第 二分段部分上不需设置 TFT, 可以将第二分段部分的宽度尽量减小， 成对设置的两条栅 线的总宽度减少， 进而增大像素区的面积。 将 TFT设置于栅线的第一分段部分中， 而不 是设置于像素区中， 可以避免 TFT 占据像素区的面积， 增加像素的透光区域， 从而提高 像素的幵口率和穿透率。 TFT 的源极所在区与对应数据线之间具有间隔， 两者之间通过 引线相互连接。 TFT的漏极通过引线与像素电极连接。 如图 3所示为图 2中标注 1的开 关元件 TFT的源极、 漏极和機极及与数据线、 像素电极连接关系的放大图。
如图 4所示为本发明的第二个实施例的示意图。
与本发明的第一个实施例相比，本实施例的機线和数据线的走线结构完全相同。与前 一实施例的区别在于， 由于機线分段部分设置的不同，第一分段部分和第二分段部分的接 合位置处两侧均不平齐，导致同一行上的亚像素单元并不在同一条水平线上。被四条栅线 和两条数据线所围的亚像素单元在水平方向上呈上下交错的排列， 排列形状类似锯齿形。 虽然本实施例中亚像素单元不在同一条水平线上排列， 亚像素单元的布局不同，但能达到 第一个实施例的显示效果。
如图 5所示为本发明的第三.个实施 ί到的示意图。
与本发明的第二个实施例相比，本实施例中栅线的形状和排列方式完全相同。不同的 地方在于 TFT的设置„ 如图 5所示， 将数据线直接引入榲线第一分段部分的 TFT源极所 在区， 并作为该 TFT的源极。 该设^可以缩小每个 TFT的尺才， 减小设置 TFT第一分段 部分的宽度， 丛而增大像素区的面积， 进一歩提高像素的开口率和穿透率。该种数据线的 设计方式不限于以上所述的第二个实施例，本发明的第一实施例及其他具有类似开关元件 与数据线连接方式的液晶显示面板均可以采用。
以第一个实施例为例， 制作如上所述的 TFT- LCD显示面板包括以下步骤。
首先选择所需的玻璃基板， 并将该玻璃基板洗净处理。
然后进入 G工程制作， 该工程用于形成扫描线相关的图案。 利用溅射方式在玻璃基 板上形成一定厚度的 G金属层， 该金属层用亍生成栅线图案。 在该金属层上涂布一层正 性 PR (光刻胶） 。 在该金属层上生成栅线图案时， 采用对应的 G- MASK (G层掩膜） 进 行曝光处理。在该 G- MASK上， 非透光区域对应栅线图案由不同宽度的分段相结合构成„ 各个分段包括宽度大的第一分段部分和宽度小的第二分段部分。其中一条非透光区域的第 一分段部分与相邻非透光区域的第二分段部分相对，第二分段部分与相邻非透光区域的的 第一分段部分相对，两条非透光区域形成互补结构，使得每对非透光区域沿行方向所占据 的宽度一致。 非透光区域的第一分段部分与第二分段部分在接合位置处的一侧上平齐设 置。 之后经显影处理、 湿刻处理和 PR剖离处理， 得到第一分段部分和第二分段部分重复 排列的一侧齐平的極线 G层图案。 该层图案如图 2中 G标注的图层显示。
然后进行 I工程制作， 该工程用于形成半导体层 TFT沟道相关图案。 将 G工程得到 的基板洗净， 利 iil CVD (化学气相沉积法）成膜工艺， 生成第一层 SiNx薄膜（硅氮化薄 膜） 。 再次洗净后连续采用 CVD成膜工艺生成第二层 S Nx薄膜、 本征 a- Si薄膜 （非晶 硅薄膜）和 n+a- Si薄膜 CP掺杂的非晶硅薄膜） 。然后涂布一层 PR, 采用对应的 I- MASK G层掩膜）进行曝光处理。 该 ί-MASK非透光区域对应概线上宽度大的第一分段部分设 置的 TFT部位， 之后经显影处理、千刻处理和 PR剖离处理， 得到设置于極线上宽度较大 的第一分段部分的 TFT栅极 I层图案。 该层图案如图 2中 I标注的图层显示。
然后进行 D工程制作， 该工程用于形成数据线相关的图案。 将 I工程得到的基板洗 净, 利^ S射方式形成 D金属层， 该金属层用于形成 TFT的源极和漏极， 以及数据线。 在 D金属层上涂布一层 PR, 进行 D- MASK (D层掩膜） 曝光处理。 该处的 D MASK设 置 TFT源极和漏极部位、 数据端口部位为非透光区域。 之后经显影处理、 湿刻处理和 PR 剖离处理， 得到 TFT源极和漏极、 数据线的 D层图案。 该层图案如图 2中 D标注的图层 显^。
然后进行（〕工程制作， 该工程用于生成接触孔图案。 将 D工程得到的基板冼净， 利 用 CVD成膜工艺， 生成钝化层。 在该层涂布一层 PR, 经 C- MASK ( C层掩膜） 曝光处 理， 此处 C- MASK为反板， 照射需要接触孔图案的连接像素电极和连线端子位置。 之后 经显影处理、 干刻处理和 PR 离处理， 得到具有接触孔的 C层图案。 该层图案如图 2中 C标注的图层显示。
最后进行 PI工程制作， 该工程用于生成像素电极。 将 C工程得到的基板洗净， 利用 溅射方式形成一定厚度的 ΠΌ (氧化铟锡） 膜。 涂布一层 PR, 经 PI-MASK ( PI层掩膜） 曝光处理， 此处 PI- MASK设置需要留下 ΓΓΟ图案部分为非透光区域。 之后经显影处理、 湿刻处理和 PR剖离处理， 得到具有亚像素电极的 PI层图案。 该层图案如图 2中 PI标注 的图层显示。
制作第二个实施例所述的 TFT LCD显示面板， 与制作第一个实施例所述的显示面板 的工艺流程在 G 工程步骤有所不同。 在第二个实施例的 G 工程制作过程中， 对应的 G-MAS 采用不同的非透光区域设置， 使得極线第一分段部分与第二分段部分在接合位 置处的两侧上是不平齐的。这就使得同一行上的亚像素单元并不在同一条水平线上，亚像 素单元在水平方向上呈上下交错的排列， 排列形状类似锯齿形。
制作第 个实施例的 TFT- LCD显示面板与制 第二个实施例的面板在 D工程歩骤中 有所不同。 在该实施例中， 数据线改变设置方 1 引入 TFT的源极所在的半导体层， 并将 数据线作为 TFT的源极。
应该理解的是，本发明所公开的实施例不限于这里所公开的特定结构、处理步骤或材 料，而应当延伸到相关领域的普通技术人员所理解的这些特征的等同替代。还应当理解的 是， 在此使用的术语仅用于描述特定实施例的目的， 而并不意味着限制。
说明书中提到的"一个实施例"或"实施例"意指结合实施例描述的特定特征、结构或特 性包括在本发明的至少一个实施例中。因此，说明书通篇各个地方出现的短语 "一个实施 例"或"实施例"并不一定均指同一个实施例。
为了方便， 在此使用的多个项目、 结构单元、 组成单元和 /或材料可出现在共同列表 中。然而， 这些列表应解释为该列表中的每个元素分别识别为单独唯一的成员。 因此， 在 没有反靣说明的情况下，该列表中没有一个成员可仅基于它们出现在共同列表中便被解释 为相同列表的任何其它成员的实际等同物。另夕卜，在此还可以连同针对各元件的替代一起 来参照本发明的各种实施例和示例。应当理解的是， 这些实施例、示例和替代并不解释为 彼此的等同物， 而被认为是本发明的单独自主的代表。
虽然上述示例用于说明本发明在一个或多个应用中的原理,但对于本领域的技术人员 来说， 在不背离本发明的原理和思想的情况下， 明显可以在形式上、用法及实施的细节上 作各种修改而不用付出创造性劳动。 因此， 本发明由所 的权利要求书来限定。

Claims

权利要求书
！、 一种基亍 HSD结构的 TFT- LCD显示面板， 其中， 所述面板包括：
亚像素单元阵列；
若干对機线， 其中， 每对栅线设在相邻的两行亚像素单元之间， 每条栅线包括重复 排列的分段， 所述分段具有不同宽度的分段部分， 其中， 在宽度相对大的分段部分上设置 有与亚像素单元的像素电极相连的 TFT元件；
多条数据线， 其与所述栅线垂直， 且相邻的两条数据线间隔有两列或两列以上的亚 像素单元。
2、 如权利要求 1所述的 TFT- LCD显示面板， 其中， 所述分段包括第一分段部分和 第二分段部分， 其中， 所述第一分段部分的宽度大于第二分段部分的宽度。
3、 如权利要求 2所述的 TFT- LCD显示面板， 其中， 每对栅线排列成其中一条概线 的第一分段部分与另一条栅线的第二分段部分相对，而第二分段部分与另一条栅线的第一 分段部分相对， 使得所述每对栅线整体上沿像素单元的行方向所占据的宽度一致。
4、 如权利要求 3所述的 TFT-LCD显示面板， 其中， 所述第一分段部分与所述第二 分段部分接合成使得所述分段在接合位置处的一侧上是平齐的。
5、 如权利要求 3所述的 TFT-LCD显示面板， 其中， 所述第一分段部分与所述第二 分段部分接合成使得所述分段在接合位置处的两侧上是不平齐的，使得由两对栅线所包围 的亚像素单元沿水平方向交错排列。
6、 如权利要求 1所述的 TFT- LCD显示面板， 其中， 所述数据线与栅线上设置的各 个 TFT元件的源极所在的区具有间隔， 并且所述数据线分别通过从中延伸的各条引线与 各个 TFT元件的源极连接。
7、 如权利要求 1所述的 TFT- LCD显示面板， 其中， 所述数据线设置成经过所述極 线上设有 TFT元件的分段部分并作为所述 TFT的源极。
8、 如权利要求 2所述的 TFT-LCD显示面板， 其中， 所述数据线设置成经过所述栅 线上设有 TFT元件的分段部分并作为所述 TFT的源极。
9、 如权利要求 3所述的 TFT- LCD显示面板， 其中， 所述数据线设置成经过所述栅 线上设有 TFT元件的分段部分并作为所述 TFT的源极。
10、如权利要求 4所述的 TFT- LCD显示面板， 其中， 所述数据线设置成经过所述極 线上设有 TFT元件的分段部分并作为所述 TFT的源极。
11、 如权利要求 5所述的 TFT-LCD显示面板， 其中， 所述数据线设置成经过所述栅 线上设有 TFT元件的分段部分并作为所述 TFT的源极。
12、 一种基于 HSD结构的 TFT- LCD显示面板的制作方法， 包括：
提供基板，
在所述基板上图案化形成栅线层， 图案化形成的栅线层上包括水平向排列的若干 对栅线， 每条栅线由各个分段重复排列构成， 其中所述分段具有不同宽度的分段部分， 不同的栅线对之间相隔一定距离， 極线对内的两条楊线以电隔离方式紧密设置- 在所述栅线中宽度相对大的分段部分上沉积半导体材料， 以形成半导体层； 形成多条数据线以及在所述半导体层上形成 TFT元件的源漏电极， 其中， 所形成 的数据线之间间隔开， 并与所述若千对«线垂直交叉， 所述源漏电极形成于所述半导 体材料丄：；
在数据线层上形成钝化层；
在相邻的任一栅线对与相邻的任何 S条数据线所包围的空间里制作两个或两个以 上的亚像素电极。
13、 如权利要求 12所述的制作方法， 其中， 形成的栅线的分段包括第一分段部分 和第二分段部分， 其中， 所述第一分段部分的宽度大于第二分段部分的宽度， 每对栅 线排列成其中一条栅线的第一分段部分与另一条栅线的第二分段部分相对， 而第二分 段部分与另一条極线的第一分段部分相对， 使得所述每对榲线整体上沿像素单元的行 方向所占据的宽度一致。
14、 如权利要求 13所述的刺作方法， 其中， 图案化形成所述概线时， 将所述第一 分段部分与所述第二分段部分形成为使得所述分段在连接处的一侧上是平齐的。
15、 如权利要求 12所述的制作方法， 其中， 形成数据线^ , 使所述数据线经过之前 概线上形成的半导体材料层， 并将经过栅线的这部分数据线作为 TFT元件的源极。
16、 如权利要求 13述的制作方法， 其中， 形成数据线时， 使所述数据线经过之前栅 线上形成的半导体材料层， 并将经过«线的这部分数据线作为 TFT元件的源极。
Π、 如权利要求 14所述的制作方法， 其中， 形成数据线时， 使所述数据线经过之前 概线上形成的半导体材料层， 并将经过栅线的这部分数据线作为 TFT元件的源极。
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