WO2015181933A1 - Module de mémoire, système de bus de mémoire et système informatique - Google Patents

Module de mémoire, système de bus de mémoire et système informatique Download PDF

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Publication number
WO2015181933A1
WO2015181933A1 PCT/JP2014/064332 JP2014064332W WO2015181933A1 WO 2015181933 A1 WO2015181933 A1 WO 2015181933A1 JP 2014064332 W JP2014064332 W JP 2014064332W WO 2015181933 A1 WO2015181933 A1 WO 2015181933A1
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Prior art keywords
controller
signal
module
sdram
flash memory
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PCT/JP2014/064332
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English (en)
Japanese (ja)
Inventor
雅行 本間
大志 隅倉
諭 村岡
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株式会社日立製作所
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Priority to PCT/JP2014/064332 priority Critical patent/WO2015181933A1/fr
Publication of WO2015181933A1 publication Critical patent/WO2015181933A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Definitions

  • the present invention relates to a memory module, a memory bus system, and a computer system in which a plurality of storage devices having different power supply voltage specifications are mounted on a substrate.
  • DRAM Dynamic Random Access Memorory
  • SDRAM Synchronous DRAM
  • TSV Through Silicon Via
  • PCIe Peripheral Component Interconnect Express
  • SSD Solid State Drive
  • An OS (Operating System) technology that enables applications to use SSDs as a virtual large memory space has also been developed.
  • DIMM dual-inline memory module
  • a non-volatile NAND flash as in Patent Document 1
  • a DIMM equipped with a plurality of devices hereinafter referred to as a prior art DIMM
  • a method of transmitting and receiving data to and from a NAND flash device by cable transmission using a serial interface has been proposed.
  • a technique related to a memory unit including a system memory controller coupled to a plurality of memory clock oscillators and a plurality of respective voltage controllers has been proposed (see Patent Document 2).
  • NAND flash device signal and power supply voltage specifications are different from SDRAM DIMM signal and power supply voltage specifications.
  • a NAND flash device is mounted on the DIMM board in addition to SDRAM, CPU (Central Processing Unit) and SDRAM It is not possible to directly connect the NAND flash device and the CPU by using the substrate wiring of the memory bus connected to the. For this reason, in the DIMM as the prior art, in addition to the CPU, a SAS controller for controlling the NAND flash device is mounted on the DIMM board. A new cable is arranged around the CPU instead of the memory bus.
  • the SDRAM-DIMM and the prior art DIMM require different voltages, and thus cannot share DC-DC.
  • the voltage difference from the SDRAM DIMM is eliminated on the DIMM.
  • DC-DC with higher output voltage than SDRAM DC-DC is installed as DC-DC for supplying power to NAND flash devices.
  • the DIMM size increases and physical mounting restrictions on the board occur.
  • a general DC-DC converter has a power efficiency of about 90%, if a DC-DC having a higher output voltage than a DC-DC for SDRAM is installed, the power required by a NAND flash device is higher than that originally required. About 10% extra power is required, resulting in an increase in power consumption.
  • the cost increases with the addition of DC-DC and cables.
  • An object of the present invention is to provide a memory module, a memory bus system, and a computer system that can share a power supply unit that supplies power to a power supply destination even if the voltage specification of the power supply destination is switched depending on the type of the power supply destination. It is to provide.
  • the present invention supplies power to a flash memory on a flash memory module or an SDRAM on an SDRAM module via a module socket, and the first controller or A power supply unit configured to supply power to the second controller, wherein the power supply unit determines type information for specifying a type of the module mounted on the module socket and a type of the controller mounted on the controller socket; Two or more different output voltages are selected from a plurality of different output voltages according to the determination result, and each selected output voltage is applied to the flash memory on the flash memory module or the SDRAM on the SDRAM module. And the first co And applying to the controller or the second controller.
  • the power supply unit that supplies power to the power supply destination can be shared.
  • FIG. 3 is a configuration diagram in the case where two board modules mounted with three packages of flash memory are connected to an SSD controller by a bus. It is a block diagram of the table which shows pin arrangement of the module for SDRAM and the module for flash memory. It is a block diagram of a voltage control switching register map. It is a block diagram of an I / O expander register map. It is a flowchart for demonstrating the process of a control microcomputer.
  • FIG. 1 is a configuration diagram showing an embodiment of a system board on which a CPU and an SSD controller are mounted.
  • a system board 101 is configured as a board on which a plurality of storage devices having different signal and power supply voltage specifications are mounted, and various devices constituting a computer system or a memory bus system are provided on the system board 101. It is installed.
  • auxiliary power supply 102 For example, on the system board 101, an auxiliary power supply 102, a voltage switching control register 103, a control microcomputer 104, an I / O expander ( Expander) 105 and main power supply 106 are mounted, auxiliary power supply 102 is connected to voltage switching control register 103, control microcomputer 104 and I / O expander 105, and control microcomputer 104 receives voltage via I2C bus 107.
  • the switching control register 103 and the I / O expander 105 are connected.
  • the CPU socket 122 includes, for example, an SSD controller 130 as a first controller (control device) that controls a storage device and an arithmetic unit.
  • a CPU 131 is mounted in 123 as a second controller (control device) that controls the storage device and an arithmetic unit.
  • the CPU socket 122 may be equipped with a CPU 131 as a control device for controlling the storage device. Also, a part of the SSD controller 130 or the CPU 131 can be used as an input / output interface.
  • SDRAM DIMM (hereinafter referred to as an SDRAM module) or NAND flash device DIMM (hereinafter referred to as a flash memory module) is mounted on the module sockets 124 to 126 as the modules 132 to 134. ... Are mounted with SDRAM or NAND flash devices (hereinafter referred to as flash memories) as storage devices or storage devices.
  • the module sockets 127 to 129 include, for example, SDRAM DIMMs (SDRAM modules) as the modules 135 to 137, and the modules 135 to 137 include, for example, SDRAMs as storage devices or storage devices. .
  • the voltage switching DC-DC converters 108 to 121 are connected to the main power source 106, respectively.
  • the voltage switching DC-DC converter 108 applies a voltage of 0.9 V or 1.0 V to the power supply core unit of the control device mounted on the CPU socket 122. 138 is powered.
  • the voltage switching DC-DC converters 109, 111, and 113 apply a voltage of 1.35V or 1.8V to the control device mounted on the CPU socket 122. Power is supplied to power supply I / O units 140 to 142 and power supply I / O units 152 to 154 of storage devices mounted in the modules 132 to 134.
  • the voltage switching DC-DC converters 110, 112, and 114 In response to the control signal from the I / O expander 105, the voltage switching DC-DC converters 110, 112, and 114 generate a voltage of 1.35V or 3.3V of the storage devices mounted on the modules 132 to 134, respectively. Power is supplied to the power supply core units 146 to 148.
  • the voltage switching DC-DC converter 115 supplies a fixed voltage of 0.9 V to the power supply core unit 139 of the control device mounted on the CPU socket 123.
  • the voltage switching DC-DC converters 116, 118, and 120 are mounted with a fixed voltage of 1.35 V on the I / O units 143 to 145 and the modules 135 to 137 of the control device mounted on the CPU socket 123. Power is supplied to the power supply I / O units 155 to 157 of the storage device.
  • the voltage switching DC-DC converters 117, 119, and 121 supply the fixed voltage of 1.35 V to the power supply core units 149 to 151 of the storage devices mounted on the modules 135 to 137, respectively.
  • the control device mounted on the CPU socket 122 and the control device mounted on the CPU socket 123 are connected via the CPU bus 158.
  • the voltage switching control register 103 is built in the CPU board setting memory (EEPROM) 165, and the voltage switching control register 103 stores information recorded in the voltage control switching register map.
  • the control microcomputer 107 is a computer device having information processing resources such as a CPU, a memory, and an input / output interface.
  • the control microcomputer 107 drives the main power supply 106 by the main power supply control signal 166 and also stores the voltage stored in the voltage switching control register 103.
  • information for controlling the voltage switching DC-DC converters 106 to 114 is acquired from the voltage switching control register 103, and the acquired information is stored in the register of the I / O expander 105. Store.
  • the output voltage of the voltage switching DC-DC converter 108 is managed according to the type of the control device (controller) mounted on the CPU socket 122, and the output voltages of the voltage switching DC-DC converters 109, 111, 113 are
  • the output voltages of the voltage switching DC-DC converters 110, 112, and 114 are managed according to the type of the modules 132 to 134 (or storage devices mounted on the modules 132 to 134) mounted in the module sockets 124 to 126. Management is performed according to the types of modules 132 to 134 (or storage devices mounted to the modules 132 to 134) mounted on the 124 to 126.
  • the I / O expander 105 outputs a control signal for controlling the voltage switching DC-DC converters 108 to 114 to the voltage switching DC-DC converters 108 to 114 based on the information stored in the register, and the voltage switching DC-DC. Control the output voltage of the DC converters 108-114.
  • the main power supply 106 is driven by a main power supply control signal 166 from the control microcomputer 107 and supplies power to the voltage switching DC-DC converters 108 to 121.
  • FIG. 2 is a block diagram of the SSD controller.
  • the SSD controller 130 is mounted on a CPU socket 122, and includes a CPU bus controller 191, a plurality of flash memory controllers (FMC) 192, an internal bus 194, and a control core (CPU core) 195.
  • the CPU bus controller 191 is connected to a CPU bus 158
  • each flash memory controller (FMC) 192 is connected to a plurality of module sockets 124 to 126 via memory buses 159 to 161, respectively.
  • the module socket 124 is mounted with a flash memory module 132A
  • the module socket 125 is mounted with a flash memory module 133A
  • the module socket 126 is mounted with a flash memory module 134A.
  • Each flash memory module 132A, 133A, 134A is equipped with a flash memory as a storage device.
  • the CPU bus controller 191 controls the CPU bus 158, exchanges data with the CPU 131 in the CPU socket 123 via the CPU bus 158, and communicates with the control core 195 and each flash memory controller 192 via the internal bus 194. Send and receive data.
  • Each flash memory controller 192 controls input / output of data to / from each flash memory via the memory buses 159 to 161.
  • the control core 195 converts a physical address and a logical address of the memory, and converts a data transmission request from the CPU bus 158 into an access to each flash memory controller 192.
  • the SSD controller 130 is composed of an FPGA (Field Programmable Gate Array) and is a flash memory module connected to the memory buses 159 to 161 in order to change the SDRAM capacity required for the system and the flash memory capacity.
  • the setting for mounting 132A, 133A, and 134A and the setting for mounting the SDRAM module can be switched. Further, the SSD controller 130 can be configured with the same specifications as the SSD of PCI connection from the system. For this reason, the software operating on the control core (CPU core) 195 has the same function as a pseudo PCI device, and can be used by a user with a standard PCI-SSD device driver.
  • the CPU 131 mounted in the CPU socket 122 is configured as a computer device having information processing resources such as a control core, a memory, and an input / output interface.
  • information processing resources such as a control core, a memory, and an input / output interface.
  • the CPU 131 is used. Controls input / output of data to / from SDRAM on the module.
  • FIG. 3 is a circuit diagram of the voltage switching DC-DC converter.
  • the voltage switching DC-DC converter 108 includes a DC-DC converter 201, a voltage adjustment circuit 202, and resistors 203 and 204.
  • the voltage adjustment circuit 202 includes AND logic components 205 and 206, and FETs. It consists of switches 207 and 208.
  • the switching DC-DC converters 109 to 114 have the same configuration as the voltage switching DC-DC converter 108 except that the resistance values of the resistors 203 and 204 are different.
  • the DC-DC converter 201 converts the DC voltage from the main power supply 106 into a DC voltage, and outputs the converted DC voltage to the CPU socket 122 from the output terminal (OUT).
  • a resistor 203 or a resistor 204 is connected to an adjustment pin (ADJ) 209 of the DC-DC converter 201 via an FET switch 207 or 208.
  • An AND logic component 205 is connected to the gate of the FET switch 207, an AND logic component 206 is connected to the gate of the FET switch 208, and each AND logic component 205, 206 is connected to the EN ( An enable signal 210 and a SEL (select) signal 211 are input.
  • the FET switch 207 When the level of the EN signal 210 is “H” and the level of the SEL signal 211 is “H”, the FET switch 207 is turned off, the FET switch 208 is turned on, and the adjustment pin (ADJ) of the DC-DC converter 201 is turned on.
  • a resistor 204 having a resistance value RB larger than the resistance value RA is connected to 209, and the voltage of the output terminal (OUT) of the DC-DC converter 201 becomes 1.0V.
  • the FET switch 207 is turned on, the FET switch 208 is turned off, and the adjustment pin ( ADJ) 209 is connected to a resistor 203 having a resistance value RA smaller than the resistance value RB, and the voltage of the output terminal (OUT) of the DC-DC converter 201 becomes 0.9V.
  • the output voltage of the DC-DC converter 201 is determined by the resistance value of the resistor 203 or the resistor 204 connected to the adjustment pin (ADJ) 209 of the DC-DC converter 201 via the FET switch 207 or 208.
  • FIG. 4 is a configuration diagram of a voltage switching DC-DC converter management table.
  • the voltage switching DC-DC converter management table 300 shows the output level of the I / O expander 105 and the voltage switching DC-DC converter 108 according to the control device mounted on the CPU socket 122. It is a table for managing output voltages, and includes a mounted device 301, an EN (signal) 302, a SEL (signal) 303, an R (resistance) 304, and a VOUT (output voltage) 305.
  • the level of the EN signal 210 is “L”
  • the level of the SEL signal 211 is “N / AL”
  • the adjustment pin (ADJ) 209 of the DC-DC converter 201 is applied. Is connected to a resistor (open) having an infinite resistance value, and the voltage of the output terminal (OUT) of the voltage switching DC-DC converter 108 becomes 0V.
  • the level of the EN signal 210 is “H”
  • the level of the SEL signal 211 is “L”
  • the adjustment pin (ADJ) 209 of the DC-DC converter 201 is set. Is connected to a resistor 203 having a resistance value RA, and the voltage of the output terminal (OUT) of the voltage switching DC-DC converter 108 becomes 0.9V.
  • the level of the EN signal 210 is “H”
  • the level of the SEL signal 211 is “H”
  • the adjustment pin (ADJ) of the DC-DC converter 201 is set.
  • 209 is connected to a resistor 204 having a resistance value RB, and the voltage of the output terminal (OUT) of the voltage switching DC-DC converter 108 becomes 1.0V.
  • the voltage switching DC-DC converter management table 310 shows the output level and the output level of the I / O expander 105 according to the modules (devices mounted on the modules) mounted on the module sockets 124 to 126.
  • the level of the EN signal 210 is “L”
  • the level of the SEL signal 211 is “N / AL”
  • the adjustment pin (ADJ) of the DC-DC converter 201 is ) 209 is connected to a resistor (open) having an infinite resistance value, and the voltage at the output terminal (OUT) of the voltage switching DC-DC converters 110, 112, 114 becomes 0V.
  • the level of the EN signal 210 is “H” and the level of the SEL signal 211 is “L”.
  • the resistor 203 having the resistance value RA is connected to the adjustment pin (ADJ) 209 of the DC-DC converter 201, and the voltage at the output terminal (OUT) of the voltage switching DC-DC converters 110, 112, 114 is 1. 35V.
  • the level of the EN signal 210 is “H” and the level of the SEL signal 211 is “ H ”, the resistor 204 having the resistance value RB is connected to the adjustment pin (ADJ) 209 of the DC-DC converter 201, and the voltage of the output terminal (OUT) of the voltage switching DC-DC converters 110, 112, 114 is 3.3V.
  • the voltage switching DC-DC converter management table 320 shows the output level of the I / O expander 105 according to the modules (storage devices mounted on the modules) mounted on the module sockets 124 to 126. And a table for managing output voltages of the voltage-switching DC-DC converters 109, 111, and 113, including a mounted device 321, an EN (signal) 322, a SEL (signal) 323, and an R (resistance) 324. , VOUT (output voltage) 325.
  • the level of the EN signal 210 is “L”
  • the level of the SEL signal 211 is “N / AL”
  • the adjustment pin (ADJ) of the DC-DC converter 201 is ) 209 is connected to a resistor (open) having an infinite resistance value, and the voltage at the output terminals (OUT) of the voltage switching DC-DC converters 109, 111, 113 becomes 0V.
  • a resistor 203 having a resistance value RA is connected to the adjustment pin (ADJ) 209 of the DC-DC converter 201, and the voltage at the output terminals (OUT) of the voltage switching DC-DC converters 109, 111, 113 is 1. 35V. This voltage is supplied to the memory buses 159 to 161.
  • the level of the EN signal 210 is “H” and the level of the SEL signal 211 is “ H ”, the resistor 204 having the resistance value RB is connected to the adjustment pin (ADJ) 209 of the DC-DC converter 201, and the voltage at the output terminals (OUT) of the voltage switching DC-DC converters 109, 111, 113 is 1.8V. This voltage is supplied to the memory buses 159 to 161.
  • the output voltages of the voltage switching DC-DC converters 108 to 114 can be automatically determined.
  • the resistor 203 is directly connected to the adjustment pin (ADJ) 209 of the DC-DC converter 201 without using the voltage adjustment circuit 202, and the resistance value of the resistor 203 is By adjusting the output voltage, the output voltage of the voltage switching DC-DC converter 115 can be set to 0.9V, and the output voltages of the voltage switching DC-DC converters 116 to 121 can be set to 1.35V.
  • FIG. 5 is a configuration diagram of a system board with an additional memory.
  • three module sockets 124 to 126 connected to the memory buses 159 to 161 are mounted on the system board 101, and connected to the memory buses 162 to 164, respectively.
  • Three module sockets 127 to 129 are mounted, and voltage switching DC-DC converters 109, 111, 113 and voltage switching DC-DC converters 110, 112, 114 are connected to the module sockets 124-126, respectively.
  • the voltage switching DC-DC converters 116 to 121 are connected to the module sockets 127 to 129, respectively.
  • three additional module sockets 124 to 126 connected to the additional memory buses 181 to 183 are mounted on the system board 101, and three additional module sockets connected to the additional memory buses 184 to 186 are mounted.
  • 127 to 129 are mounted in each of three, and additional voltage switching DC-DC converters 109 to 114 and 116 to 121 are mounted, and each of the additional module sockets 124 to 126 is connected to the additional voltage switching DC-DC.
  • Converters 109, 111, and 113 are connected to expansion voltage switching DC-DC converters 110, 112, and 114, respectively, and expansion module switching DC-DC converters 116 to 121 are connected to expansion module sockets 127 to 129, respectively. Is done.
  • the SSD controller 130 is mounted on the CPU socket 122, the CPU 131 is mounted on the CPU socket 123, and the flash memory is mounted on each of the module sockets 124 to 126 via the modules 132 to 134. SDRAMs are mounted in the sockets 127 to 129 via modules 135 to 137, respectively.
  • Three module sockets 124 to 126 are mounted on the system board 101.
  • the frequencies of the memory buses 159 to 161 and 181 to 183 used for communication between the SSD controller 130 and the flash memory are the same as when the SDRAM is mounted. Is 1.6 GHz, whereas when the flash memory is mounted, it is 400 MHz, which is relatively slow. Therefore, even if three module sockets 124 to 126 are mounted on the system board 101, the memory buses 159 to 161 and 181 to 183 can be used when the SDRAM and the flash memory are mounted.
  • FIG. 6 is a configuration diagram for explaining the relationship between buses and signal lines connected to the module and pins of the module board.
  • module sockets (DIMM sockets) 124 to 129 have 240 pins, and each of the module sockets 124 to 129 has, for example, 240 pins as SDRAM 132 to 137.
  • Module substrate 501 is mounted, and a plurality of SDRAMs 502 are mounted on each SDRAM module substrate 501.
  • the CPU 131 is connected to each module substrate 501 via the address bus 520 and the data bus 521, and is connected to the module substrate 501 # 0 via the one-to-one signal line 522. It is connected to the # 1 module substrate 501 via the pair 1 signal line 523.
  • Each module substrate 501 is connected with SPD (Serial Presence Detect) signal lines 524 and 525.
  • the # 0 module substrate 501 has 24 pins connected to the address bus 520, 108 pins connected to the data bus 521, 12 pins connected to the one-to-one signal line 522, and an SPD signal line. Seven pins are connected to 524.
  • the # 1 module board 501 has 24 pins connected to the address bus 520, 108 pins connected to the data bus 521, 12 pins connected to the one-to-one signal line 523, and an SPD signal line. Seven pins are connected to 525. That is, each module substrate 501 uses 132 pins for bus connection and 12 pins for one-to-one signals.
  • the number of pins for bus connection is 60 pins, which is less than 132 pins, but there are 20 pins for one-to-one signal, and 8 pins are insufficient.
  • the bus connection pins are 90 pins, which is smaller than 132 pins, but there are 30 one-to-one signal pins, and 18 pins are insufficient.
  • FIG. 6C is a configuration diagram of the module substrate in the present embodiment.
  • the module socket (DIMM socket) 124 is mounted with a flash memory module board 505 having 240 pins as the module 132, and the flash memory module board 505 has three packages of flash.
  • a memory 504, a plurality of selector logic components 508, and a plurality of AND logic components 510 are mounted.
  • the flash memory module substrate 505 is configured as a module substrate having the same pin specifications as the SDRAM module substrate 501. At this time, as will be described later, by forming a part of the one-to-one signal line as a bus wiring, the flash module substrate 505 has a three-package flash memory without a shortage of one-to-one signal pins. 504 can be mounted.
  • FIG. 7 is an explanatory diagram for explaining a connection relationship between the SSD controller and the module substrate, and is an explanatory diagram before a part of the one-to-one signal line is bus-wired.
  • the SSD controller 130 mounted on the CPU socket 122 includes WE0 (write enable), CLE0 (command latch enable), ALE0 (address latch enable), RE0 (read enable), DQ0 ( Data) and DQS0 (data strobe) via a bus 530 connected to each flash memory 504 on each flash memory module board 505, via a bus 531 including WE1, CLE1, ALE1, RE1, DQ1, and DQS1. Are connected to each flash memory 504 on each flash module substrate 505.
  • the SSD controller 130 also includes a CE (chip enable) signal line 540, a WP (write protect) signal line 541, an R / B (ready / busy) signal line 542, and a CE signal line 543.
  • WP signal signal line 544 and R / B signal signal line 545 are connected to flash memory 504 on # 0 flash memory module substrate 505, CE signal signal line 550, WP signal signal line 551, the flash memory 504 on the # 1 flash module substrate 505 via the R / B signal signal line 552, the CE signal signal line 553, the WP signal line 554, and the R / B signal signal line 555. Connected to.
  • the flash memory 504 on the # 0 flash memory module substrate 505 uses 15 pins for connection to the bus 530 and 15 pins for connection to the bus 531, and is connected to the signal lines 540 to 545. Ten pins are used for connection.
  • the flash memory 504 on the # 1 flash memory module substrate 505 uses 15 pins for connection to the bus 530, 15 pins for connection to the bus 531, and 10 for connection to the signal lines 550 to 555. Pins are used.
  • Each flash memory 504 has a total of 30 pins used for connection to the buses 530 and 531, and is connected to signal lines (one-to-one signal lines) 540 to 545 or signal lines (one-to-one signal lines) 550 to 555. A total of 10 pins are used.
  • the total number of pins for bus connection is 60 pins, which is less than 132 pins, but there are a total of 20 pins for one-to-one signals.
  • the flash memory 504 is mounted on a substrate having the same configuration as the SDRAM module substrate 501, eight pins are insufficient. Therefore, in this embodiment, as described below, a part of the one-to-one signal line is formed as a bus wiring.
  • FIG. 8 is an explanatory diagram for explaining the connection relationship between the SSD controller and the module substrate, and is an explanatory diagram in the case where the CE signal line is formed as a bus wiring.
  • the CE signal signal lines 540 and 550 are connected to each flash as one-to-one signal lines. Connected to memory 504.
  • each flash memory 504 uses two pins for connection with the CE signal signal lines 540 and 550.
  • the SSD controller 130 When a part of the CE signal signal lines 540 and 550 is bus-wired, as shown in FIG. 8B, the SSD controller 130 is provided with three OR logic components 509A to 509C as an encoding circuit.
  • an AND logic component 510 is arranged as a decoding circuit.
  • the input sides of the OR logic components 509 A to 509 C are connected to CE signal signal lines 540 and 550 and the SSD controller 130.
  • the output side of the OR logic component 509A is connected to one input side of each AND logic component 510 via the CE signal signal line 550, and the output side of the OR logic component 509B is connected to a bus-wired signal line 540A.
  • each AND circuit component 510 is connected to each flash memory 504.
  • each flash memory 504 asserts only one bit of a low-active CE (chip enable) signal at the same time. It is possible, and 2 bits out of 4 bits used for the CE signal can be used as a bus signal. Therefore, the CE signal is encoded by the encode circuit (OR logic components 509A to 509C), the encoded signal is decoded by the decode circuit (AND logic component 510), and the decoded signal is supplied to each flash memory 504. It is said. As shown in the truth value management table 330 in FIG.
  • a signal having the same logical value as the CE signal which is a one-to-one signal, is given to each flash memory 504 as a bus signal, so that the bus 530 has 2 Although the number of bits increases, the number of pins used for connection to the CE signal signal lines 540 and 550 in each flash memory 504 can be reduced from 4 pins to 2 pins.
  • the truth value management table 330 is a table for managing the truth value of the CE signal, and is composed of input-side truth values 331, 332, 333, and 334 and output-side truth values 335 and 336.
  • the truth value 331 on the input side is composed of the truth value of the CE signal signal line 540 on the encoder circuit input side
  • the truth value 332 on the input side is composed of the truth value of the CE signal signal line 550 on the encoder circuit input side. Is done.
  • the truth value 333 on the input side is composed of the truth value of the CE signal signal line 540 on the decode circuit input side (encode circuit output side)
  • the truth value 334 on the input side is the decode circuit input side (encode circuit output side).
  • the truth value 335 on the output side is composed of the truth value of the CE signal signal line 540 on the output side of the decode circuit
  • the truth value 336 on the output side is composed of the truth value of the CE signal signal line 550 on the output side of the decode circuit. Is done.
  • a part of the bus (memory bus) 350 is configured as a plurality of signal lines 540A and 540B wired as buses, and includes module sockets 124 to 126 and a CPU socket (controller socket) 122.
  • a signal transmitted through the two or more specific signal lines 540 and 550 is transmitted to the two or more specific signal lines 540 and 550 and the plurality of signal lines 540A and 540B wired as buses.
  • the OR logic components 509A to 509C and the plurality of AND logic components 510 are connected as a plurality of logic components that convert the signal to a signal having the same logical value and output the converted signal as a bus signal to the flash memory 504 or the SDRAM 502. Therefore, each flash memory 504 is used for connection with CE signal signal lines 540 and 550.
  • the Lupine can be reduced from 4 pin to 2 pin. The same configuration can be applied when the CPU 131 is mounted on the CPU socket 122 and the SDRAM 502 is mounted on the module.
  • FIG. 9 is an explanatory diagram for explaining a connection relationship between the SSD controller and the module substrate, and is an explanatory diagram when a WP (write protect) signal line (write inhibit signal line) is formed as a bus wiring.
  • WP write protect
  • FIG. 9A when each flash memory 504 on two flash memory module substrates 505 is connected to the SSD controller 130, the WP signal signal lines 541 and 551 are used as one-to-one signal lines. Connected to memory 504. In this case, each flash memory 504 uses one pin for connection with the CE signal signal lines 541 and 551.
  • the WP signal signal lines 541 and 551 are formed as bus wirings, as shown in FIG. 9B, a part of the bus 530 connected to the SSD controller 130 is connected to the Low fixed signal signal line 560 and the High fixed signal.
  • a selector logic component 508 is disposed in each flash memory 504, which is used as a signal line 561 for a signal.
  • the input side of the # 0 selector logic component 508 is connected to the WP signal signal lines 541 and 554 and the Low fixed signal signal line 560, and the # 1 selector logic component 508 includes the WP signal signal lines 541 and 554 and Connected to the high fixed signal signal line 561, the output side of each selector logic component 508 is connected to each flash memory 504.
  • the WP signal is a level signal and is used to identify the module substrate 505.
  • a high / low fixed signal is used instead of the WP signal, and the signal line wired as a bus is used as a signal line for transmitting the high / low fixed signal, thereby transmitting the WP signal.
  • One-to-one signal lines can be reduced. That is, as shown in the truth value management table 340 of FIG. 9C, a signal having the same logical value as that of the WP signal, which is a one-to-one signal, is used as a bus signal and is given to each flash memory 504, thereby providing a bus.
  • 530 increases by 2 bits, in each flash memory 504, the pins used for connection to the WP signal signal lines 541 and 551 can be reduced from 1 pin to 0, respectively.
  • the truth value management table 340 is a table for managing the truth value of the WP signal, and is composed of input-side truth values 341, 342, 343, and 344 and output-side truth values 345 and 346.
  • the truth value 341 on the input side is composed of the truth value of the WP signal signal line 541 on the input side of the selector logic component 508, and the truth value 342 on the input side is the WP signal signal line 554 on the input side of the selector logic component 508. Consists of truth values.
  • the truth value 343 on the input side is constituted by the truth value of the Low fixed signal signal line 560 on the input side of the selector logic component 508, and the truth value 344 on the input side is the signal line for High fixed signal on the input side of the selector logic component 508. It is composed of 561 truth values.
  • the truth value 345 on the output side is composed of the truth value on the output side of the selector logic component 508, and the truth value 346 on the output side is composed of the truth value on the output side of the selector logic component 508.
  • a part of the bus (memory bus) 350 is configured as a plurality of signal lines 560 and 561 wired as buses, and the module sockets 124 to 126 and the CPU socket (controller socket) 122 are connected to each other.
  • a signal that transmits two or more specific signal lines 541 and 551 is transmitted to two or more specific signal lines 541 and 551 and a plurality of signal lines 560 and 561 that are wired as buses.
  • the selector logic component 508 is connected as a plurality of logic components that convert this signal into a signal having the same logical value and output the converted signal as a bus signal to the flash memory 504 or the SDRAM 502, each flash memory 504 is connected. Therefore, the number of pins used for connection to the WP signal signal lines 541 and 551 can be reduced from 1 pin to 0 respectively. Kill.
  • the same configuration can be applied when the CPU 131 is mounted on the CPU socket 122 and the SDRAM 502 is mounted on the module.
  • FIG. 10 is an explanatory diagram for explaining a connection relationship between the SSD controller and the module substrate, and is an explanatory diagram in the case where the R / B signal line is formed as a bus wiring.
  • an R / B ready / busy
  • Signal signal lines 542 and 552 are connected to each flash memory 504 as one-to-one signal lines.
  • each flash memory 504 uses two pins for connection to the R / B signal signal lines 542 and 552.
  • Each input side of the AND logic components 512 and 513 arranged in the # 0 flash memory 504 is connected to the Low fixed signal signal line 560 or the R / B signal pin of the # 0 flash memory 504, and # 0
  • the output side of the AND logic component 512 arranged in the flash memory 504 is connected to the R / B signal signal line 542, and the output side of the AND logic component 513 arranged in the # 0 flash memory 504 is the R / B signal. Connected to the signal line 552.
  • Each input side of the AND logic components 512 and 513 arranged in the # 1 flash memory 504 is connected to the High fixed signal signal line 561 or the R / B signal pin of the # 1 flash memory 504, and # 1
  • the output side of the AND logic component 512 arranged in the flash memory 504 is connected to the R / B signal signal line 542, and the output side of the AND logic component 513 arranged in the # 1 flash memory 504 is connected to the R / B signal line 542. It is connected to the B signal signal line 552.
  • the R / B signal is a wired OR signal for wiring the output signal.
  • a High / Low fixed signal is used, and the signal line wired as a bus is used as a signal line for transmitting the High / Low fixed signal to transmit the R / B signal. Therefore, the one-to-one signal line can be reduced. That is, as shown in the truth value management table 350 in FIG. 10C, a signal having the same logical value as the R / B signal, which is a one-to-one signal, is used as a bus signal and given to each flash memory 504.
  • the bus 530 is increased by 4 bits, the pins used for connection to the R / B signal signal lines 542 and 552 in each flash memory 504 can be reduced from 2 pins to 0, respectively.
  • the truth value management table 350 is a table for managing the truth values of the R / B signal, and is composed of input-side truth values 351, 352, 353, and 354 and output-side truth values 355 and 356.
  • the truth value 351 on the input side is composed of the truth values on the input side of the AND logic components 512 and 513 arranged in the # 0 flash memory 504, and the truth value 352 on the input side is arranged in the # 1 flash memory 504.
  • Each AND logic component 512, 513 is composed of truth values on the input side.
  • the truth value 353 on the input side is composed of the truth values of the low fixed signal signal lines 560 on the input sides of the AND logic components 512 and 513 arranged in the # 0 flash memory 504, and the truth value 354 on the input side is It consists of the truth value of the high fixed signal signal line 561 on the input side of each AND logic component 512, 513 arranged in the # 1 flash memory 504.
  • the truth value 355 on the output side is composed of the truth value of the R / B signal signal line 542 on the output side of the AND logic component 512 arranged in each flash memory 504, and the truth value 356 on the output side is composed of each flash memory 504.
  • the R / B signal signal line 552 on the output side of the AND logic component 513 arranged at the truth value.
  • a part of the bus (memory bus) 350 is configured as a plurality of signal lines 560 and 561 wired as buses, and the module sockets 124 to 126 and the CPU socket (controller socket) 122 are connected.
  • specific two or more signal lines 542 and 552 and a plurality of signal lines 560 and 561 wired as buses are signals transmitted through the two or more specific signal lines 542 and 552. Since a plurality of AND logic components 512 and 513 are connected as a plurality of logic components that convert this signal into a signal having the same logical value and output the converted signal to the SSD controller 130 or the CPU 131 as a bus signal.
  • each flash memory 504 the pins used for connection to the R / B signal signal lines 542 and 552 are changed from 2 pins to 0 respectively. It can be reduced. The same configuration can be applied when the CPU 131 is mounted on the CPU socket 122 and the SDRAM 502 is mounted on the module.
  • FIG. 11 is a configuration diagram when two module boards are connected to the SSD controller by a bus.
  • a # 0 flash memory module substrate 505 is mounted with a # 0 memory unit 511
  • a # 1 module substrate 505 is mounted with a # 1 memory unit 511.
  • Each memory unit 511 includes a plurality of AND logic components 510, 512, and 513, a selector logic component 508, and a flash memory 504 in one package.
  • the SSD controller 130 has a plurality of OR logic circuit components 509A to 509C constituting an encoding circuit, and each flash memory module substrate 505 via a bus 530 including WE0, CLE0, ALE0, RE0, DQ0, and DQS0.
  • Each flash memory 504 is connected to each flash memory 504 and connected to each flash memory 504 on each flash memory module substrate 505 via a bus 531 including WE1, CLE1, ALE1, RE1, DQ1, and DQS1.
  • the SSD controller 130 is provided for each flash memory via the CE signal line 553, the WP signal signal lines 541 and 554, the R / B signal signal lines 552, 542, 545 and 555, and the CE signal line 550. It is connected to each flash memory 504 on the module substrate 505. Further, the SSD controller 130 is connected to the flash memory 504 on the # 0 flash memory module substrate 505 via the CE signal lines 543A, 540A, the WP signal signal line 544, and the Low fixed signal signal line 560. , The CE signal lines 543B and 540B, the WP signal signal line 551, and the high fixed signal signal line 561, are connected to the flash memory 504 on the # 1 flash memory module substrate 505.
  • the flash memory 504 on the # 0 flash memory module substrate 505 has 15 pins used for connection to the bus 530 and 15 pins used for connection to the bus 531, and is a signal line formed as a bus wiring. 14 pins are used for connection to 553, 541, 554, 552, 542, 545, and 555, and 4 pins are used for connection to the one-to-one signal lines 543A, 544, 540A, and 560.
  • the flash memory 504 on the # 1 flash memory module substrate 505 has 15 pins used for connection to the bus 530 and 15 pins used for connection to the bus 531, and signal lines 553 and 541 wired as buses. 14 pins are used for connection to 554, 552, 542, 545, 555, and 4 pins are used for connection to the one-to-one signal lines 543B, 551, 540B, 561.
  • Each flash memory 504 uses a total of 30 pins for connection to buses 530 and 531, and uses a total of 14 pins for connection to signal lines 553, 541, 554, 552, 542, 545, and 555 that are wired as buses. Thus, a total of 44 pins are used for the bus connection, and a total of 4 pins are used for the connection with the one-to-one signal lines 543A, 544, 540A, 560 or the signal lines 543B, 551, 540B, 561.
  • each flash memory 504 uses a total of 44 pins for bus connection, but uses only 4 pins for connection to a one-to-one signal line. For this reason, by forming a part of the one-to-one signal line as a bus wiring, each flash memory 504 can reduce the number of pins required for connection to the one-to-one signal line from 10 pins to 4 pins. Two packages of flash memory 504 can be mounted on each of the modules 132 to 134.
  • FIG. 12 is a configuration diagram of the signal number comparison table.
  • the signal number comparison table 360 includes a standard type in which a part of the signal line is not bus-wired and the signal number when the flash memory 504 is mounted on the module 132 in one package. A comparison result with an example in which a part of the line is bus-wired is recorded.
  • the flash memory 504 has 10 pins for connection to a signal line that transmits a one-to-one signal, and 30 pins for connection to a bus that transmits a bus signal.
  • the flash memory 504 uses 4 pins for connection to a signal line for transmitting a one-to-one signal, and 44 pins for connection to a bus for transmitting a bus signal. I understand.
  • Each of the modules 132 to 134 has 12 pins used for connection with a signal line for transmitting a one-to-one signal and 132 pins used for connection with a bus for transmitting a bus signal.
  • Three packages of flash memory 504 can be mounted on the modules 132 to 134.
  • FIG. 13 is a configuration diagram in the case where two module boards on which three packages of flash memory are mounted are connected to the SSD controller by a bus.
  • three # 0 memory units 511 and three SPD devices 512 are mounted on the # 0 module board 505, and the # 1 memory unit 511 is mounted on the # 1 module board 505.
  • Three SPD devices 512 are mounted.
  • Each memory unit 511 includes a plurality of AND logic components 510, 512, and 513, a selector logic component 508, and a flash memory 504 in one package.
  • Each SPD 512 recognizes the specification of each module substrate 505 and transfers an error signal to the SSD controller 130 when an error occurs in each module substrate 505.
  • the SSD controller 130 is connected to the # 0 memory unit 511 and the # 1 memory unit 511 via the bus 570, and is connected to the # 0 memory unit 511 and the # 1 memory unit 511 via the bus 571. Are connected to the # 0 memory unit 511 and the # 1 memory unit 511 via the bus 572.
  • the SSD controller 130 is connected to the # 0 memory unit 511 and the # 1 memory unit 511 via the one-to-one signal lines 580 and 581, and is connected to the # 1 memory line 582 and 583 via the one-to-one signal lines 582 and 583.
  • the SSD controller 130 is connected to the three memory units 511 of # 0 via the Low fixed signal signal line 560, and is connected to the three memory units of # 1 via the High fixed signal signal line 561. 511 is connected. Further, the SSD controller 130 is connected to the # 0 SPD device 512 and the # 1 SPD device 512 via the EVENT signal line 586.
  • the bus 570 includes, for example, buses 530 and 531 and signal lines 553, 541, 554, 552, 542, 545, and 555 wired as buses
  • the signal line 580 includes, for example, signal lines 543A
  • the signal line 581 includes, for example, signal lines 543B, 551, and 540B.
  • the # 0 memory unit 511 connected to the bus 570 among the memory units 511 on the # 0 flash memory module substrate 505 uses 3 pins for connection to the signal line 580, and is connected to the bus 570. 44 pins are used for connection, and 1 pin is used for connection to the low fixed signal signal line 560.
  • the # 0 memory unit 511 connected to the bus 571 uses 3 pins for connection to the signal line 582, uses 44 pins for connection to the bus 571, and connects to the low fixed signal signal line 560. One pin is used.
  • the # 0 memory unit 511 connected to the bus 572 uses 3 pins for connection to the signal line 584, uses 44 pins for connection to the bus 572, and connects to the low fixed signal signal line 560. One pin is used. In the entire three # 0 memory units 511, 10 pins are used for connection to signal lines for transmitting one-to-one signals, and 132 pins are used for connections to buses for transmitting bus signals.
  • the # 1 memory unit 511 connected to the bus 570 uses 3 pins for connection to the signal line 581, uses 44 pins for connection to the bus 570, and connects to the high fixed signal signal line 561. One pin is used.
  • the # 1 memory unit 511 connected to the bus 571 uses 3 pins for connection to the signal line 583, uses 44 pins for connection to the bus 571, and connects to the high fixed signal signal line 561. One pin is used.
  • the # 1 memory unit 511 connected to the bus 572 uses 3 pins for connection to the signal line 585, uses 44 pins for connection to the bus 572, and connects to the high fixed signal signal line 561. One pin is used. In the entire three # 1 memory units 511, 10 pins are used for connection with signal lines for transmitting one-to-one signals, and 132 pins are used for connection with buses for transmitting bus signals.
  • Each module board 505 is provided with 10 pins used for connection with signal lines for transmitting one-to-one signals and 132 pins used for connection with buses for transmitting bus signals.
  • Three memory units 511 each having one package of flash memory 504 can be mounted on the substrate 505.
  • FIG. 14 is a configuration diagram of a table showing the pin arrangement of the SDRAM module and the flash memory module.
  • information indicating the relationship between pins (# 1 to 60, # 121 to 180) of the SDRAM module 501 and one-to-one communication lines or buses is recorded in a table 600.
  • Information indicating the relationship between the pins (# 1 to 60, # 121 to 180) of the memory module 505 and the one-to-one communication line or bus is recorded, and the pins (# 61 to # 61) of the SDRAM module 501 are recorded in the table 620.
  • the table 630 includes the pins (# 61 to 120, # 181 to 240) and 1 of the flash memory module 505. Information indicating the relationship with the one-to-one communication line or bus is recorded.
  • FIG. 15 is a configuration diagram of the voltage control switching register map.
  • the voltage control switching register map 380 is stored in the voltage switching control register 103 as a map generated based on the information recorded in the power switching DC-DC converter management tables 300, 310, 320, and is offset 380A. 380B, bit 380C, data 380D, and description 380E.
  • the voltage control switching register map 380 records information when the system board 101 has a 2-socket configuration.
  • Information relating to the SEL signal (control signal) applied to the module and type information for specifying the types of the controllers 132 to 134 mounted on the module sockets 124 to 126 and the controller mounted on the CPU socket (controller socket) 122 are stored. Is done. This type information is, for example, “0” when the CPU 131 is mounted on the CPU socket 122, and “1” when the SSD controller 130 is mounted on the CPU socket 122. Further, when the SDRAM module 501 is mounted as the modules 132 to 134 in the module sockets 124 to 126, it is “0”, and when the flash memory module 505 is mounted, it is “1”.
  • FIG. 16 is a configuration diagram of the I / O expander register map.
  • an I / O expander register map 390 is a map managed by the control microcomputer 104 and stored in the register of the I / O expander register 105, and includes an offset 390A, a bit 390B, and data 390C. , 390D.
  • the offset 0x02 stores information related to the EN signal applied to each voltage switching DC-DC converter 108-114
  • the column of offset 0x03 stores the SEL signal applied to each voltage switching DC-DC converter 108-114.
  • one I / O expander 105 corresponds to one CPU socket in which the CPU 131 or the SSD controller 130 can be mounted.
  • a 4-CPU socket configuration that is, in the configuration of one CPU 131 and three SSD controllers 130, three I / O expanders 105 are arranged on the system board 101.
  • FIG. 17 is a flowchart for explaining the processing of the control microcomputer. This process is executed by the CPU in the control microcomputer 104.
  • the control microcomputer 104 accesses the voltage switching control register 103, refers to the voltage control switching register map 380, and reads the number of CPU sockets stored in the offset 0x30 column of the voltage control switching register map 380.
  • S1 The read value (the number of CPU sockets) is substituted into a variable X (S2), and the number of CPU sockets on which the CPU 131 or the SSD controller 130 can be mounted is determined from the value of the variable X (S3).
  • step S3 If it is determined in step S3 that the variable X is not 0, the control microcomputer 104 reads the information related to the EN signal stored in the offset 0x51 column of the voltage control switching register map 380, and reads the read information as I / O. Of the registers of the expander 105, the data is written into the offset 0x02 field of the I / O expander register map 390 (S4).
  • the control microcomputer 104 ends the DC-DC voltage switching process and the process in this routine.
  • the I / O expander 105 sends the information to the voltage switching DC-DC converters 108 to 114.
  • An EN signal and a SEL signal are output as control signals.
  • each of the voltage switching DC-DC converters 108 to 114 outputs an output voltage suitable for the power supply voltage of each power supply destination to each power supply destination.
  • the main power supply 106, the I / O expander 105, and the voltage switching DC-DC converters 108 to 114 constitute a power supply unit, and are stored in the register (storage unit) of the I / O expander 105.
  • the type information is discriminated, two or more different output voltages are selected from a plurality of different output voltages according to the discrimination result, and the selected output voltages are respectively selected from the flash memory 504 on the flash memory module or the SDRAM 502 on the SDRAM module. And applied to the SSD controller 130 or the CPU 131.
  • the I / O expander 105 determines the type information stored in the register (storage unit) of the I / O expander 105, and a plurality of control signals (EN signals) having different control information according to the determination result. SEL signal), and the voltage switching DC-DC converters 108 to 114 receive the control signal from the I / O expander 105.
  • the output voltage specified by the control information of the received control signal is selected from two or more different output voltages that match the power supply voltage of the power supply destination, and each selected output voltage is flashed on the flash memory module.
  • the voltage switching DC-DC converter 108 receives a control signal from the I / O expander 105
  • the voltage switching DC-DC converter 108 receives the control signal from a plurality of different controller output voltages (0.9V and 1.0V).
  • the controller output voltage selected by the control information of the control signal is selected, and the controller output voltage is output to the power supply core unit 138 of the SSD controller 130 or the CPU 131.
  • the voltage switching DC-DC converters 110, 112, 114 When the voltage switching DC-DC converters 110, 112, 114 receive the control signal from the I / O expander 105, the voltage switching DC-DC converters 110, 112, 114 have received the output voltage from a plurality of different storage devices (1.35 V and 3.3 V).
  • the storage device output voltage specified by the control information of the control signal is selected, and the selected storage device output voltage is used to supply power to the power supply core of the flash memory 504 on the flash memory module or to the SDRAM 502 on the SDRAM module. It is configured as a storage device voltage switching unit that outputs to the core unit.
  • the control signal received from a plurality of different common output voltages (1.35V and 1.8V).
  • the shared output voltage specified by the control information of the flash memory 504 on the SSD controller 130 and the flash memory module or the power supply I / O unit of the flash memory 504 on the SSD controller 130 or the SDRAM 502 on the SDRAM module on the SDRAM 131 is selected. It is configured as a shared voltage switching unit that outputs to the power feeding I / O unit.
  • the power supply unit that supplies power to the power supply destination can be shared. That is, the output voltage of the voltage switching DC-DC converter 108 is managed according to the type of control device (controller) mounted on the CPU socket 122, and the output voltage of the voltage switching DC-DC converters 109, 111, 113 is the module.
  • the output voltages of the voltage switching DC-DC converters 110, 112, and 114 are managed according to the type of the modules 132 to 134 (or storage devices mounted to the modules 132 to 134) mounted in the sockets 124 to 126.
  • modules 132 to 134 are managed according to the type of modules 132 to 134 (or storage devices mounted to the modules 132 to 134) mounted on the CPU 126, the SSD controller 130 or the CPU 131 is mounted on the CPU socket 122, or the module 1 Even or flash memory 504 or SDRAM502 is mounted from 2 to 134, may share the respective voltage switching DC-DC converters 108-114. Therefore, the configuration of the system board 101 can be simplified, and the power consumption can be reduced with the reduction in the number of voltage switching DC-DC converters.
  • SDRAM 502 which is a high-speed volatile memory
  • flash memory 504 which is low-speed but nonvolatile and inexpensive per bit
  • SDRAM 502 and flash memory 504 can be mounted on the system board 101, respectively, and the capacity of the SDRAM 502 and flash memory 504 can be flexibly increased with the same device. Therefore, it is possible to provide an information processing apparatus or a computer system that is lower in cost.
  • the present invention can also be applied to a nonvolatile memory embedded DIMM that may be put to practical use in the future generations of MRAM and FRAM (registered trademark).
  • the SSD controller 130 and the CPU 131 are configured as an arithmetic device that executes arithmetic processing according to a program stored in the memory, and the plurality of flash memories 504 and the plurality of SDRAMs 502 are included in the arithmetic device. It can be configured as a storage device that stores data to be accessed. Also, part of the SSD controller 130 and the CPU 131 can be configured as an input / output interface.
  • the voltage switching DC-DC converter for supplying power to the control device (controller) mounted on the CPU socket 122 and the storage device mounted on the modules 132 to 134, these control device (controller) and storage device Depending on the specifications of the power supply voltage, two types of voltage switching DC-DC converters having different output voltages or three or more types of voltage switching DC-DC converters may be used.
  • each of the above-described configurations, functions, etc. may be realized by hardware by designing a part or all of them, for example, by an integrated circuit.
  • Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor.
  • Information such as programs, tables, and files for realizing each function is stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), an IC (Integrated Circuit) card, an SD (Secure Digital) memory card, a DVD ( It can be recorded on a recording medium such as Digital Versatile (Disc).
  • the memory bus, the one-to-one signal line, or the control line indicates what is considered necessary for the explanation, and not all memory buses, the one-to-one signal line, or the control line are necessarily shown in the product. . In practice, almost all the components are connected to each other.

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Abstract

L'invention concerne un module de mémoire, comprenant : des supports de modules sur lesquels sont montés soit des modules de mémoire flash soit des modules de SDRAM ; un support de contrôleur sur lequel est monté soit un premier contrôleur qui contrôle la mémoire flash soit un second contrôleur qui contrôle la SDRAM ; une unité source d'alimentation qui alimente en courant, par le biais des supports de modules, soit la mémoire flash située sur les modules de mémoire flash soit la SDRAM située sur les modules de SDRAM, et qui alimente en courant, par le biais du support de contrôleur, soit le premier contrôleur soit le second contrôleur ; et une unité de mémorisation qui mémorise des informations de types qui spécifie les types des modules qui sont montés sur les supports de modules et le type de contrôleur qui est monté sur le support de contrôleur. L'unité source d'alimentation en courant évalue les informations de types qui sont mémorisées dans l'unité de mémorisation, sélectionne au moins deux tensions de sortie différentes conformément au résultat de l'évaluation parmi plusieurs tensions de sortie différentes, et communique chacune des tensions de sortie sélectionnées soit à la mémoire flash soit à la mémoire SDRAM et soit au premier contrôleur soit au second contrôleur.
PCT/JP2014/064332 2014-05-29 2014-05-29 Module de mémoire, système de bus de mémoire et système informatique WO2015181933A1 (fr)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000020393A (ja) * 1995-10-13 2000-01-21 Seigun Handotai Kofun Yugenkoshi メモリデバイスにアクセスするための方法及びメモリアクセッシングデバイス
JP2004310700A (ja) * 2003-04-01 2004-11-04 Ati Technologies Inc メモリデバイスにおいてデータを反転させるための方法および装置
JP2008046989A (ja) * 2006-08-18 2008-02-28 Fujitsu Ltd メモリ制御装置
JP2008293096A (ja) * 2007-05-22 2008-12-04 Shinko Electric Ind Co Ltd メモリインタフェースおよびメモリシステム
JP2011048550A (ja) * 2009-08-26 2011-03-10 Nec Corp コンピュータのメモリ再配置制御方法およびプログラム並びにコンピュータシステム
JP2012503835A (ja) * 2008-09-26 2012-02-09 ネットアップ，インコーポレイテッド Ｒｄｍａを用いて複数の仮想マシンに不揮発性ソリッドステートメモリへの共用アクセスを提供するシステム及び方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000020393A (ja) * 1995-10-13 2000-01-21 Seigun Handotai Kofun Yugenkoshi メモリデバイスにアクセスするための方法及びメモリアクセッシングデバイス
JP2004310700A (ja) * 2003-04-01 2004-11-04 Ati Technologies Inc メモリデバイスにおいてデータを反転させるための方法および装置
JP2008046989A (ja) * 2006-08-18 2008-02-28 Fujitsu Ltd メモリ制御装置
JP2008293096A (ja) * 2007-05-22 2008-12-04 Shinko Electric Ind Co Ltd メモリインタフェースおよびメモリシステム
JP2012503835A (ja) * 2008-09-26 2012-02-09 ネットアップ，インコーポレイテッド Ｒｄｍａを用いて複数の仮想マシンに不揮発性ソリッドステートメモリへの共用アクセスを提供するシステム及び方法
JP2011048550A (ja) * 2009-08-26 2011-03-10 Nec Corp コンピュータのメモリ再配置制御方法およびプログラム並びにコンピュータシステム

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