WO2015176836A1 - Dispositif et procédé de génération de bits aléatoires - Google Patents

Dispositif et procédé de génération de bits aléatoires Download PDF

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Publication number
WO2015176836A1
WO2015176836A1 PCT/EP2015/054895 EP2015054895W WO2015176836A1 WO 2015176836 A1 WO2015176836 A1 WO 2015176836A1 EP 2015054895 W EP2015054895 W EP 2015054895W WO 2015176836 A1 WO2015176836 A1 WO 2015176836A1
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WO
WIPO (PCT)
Prior art keywords
combinatorial
input
bijection
output
bits
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PCT/EP2015/054895
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German (de)
English (en)
Inventor
Markus Dichtl
Original Assignee
Siemens Aktiengesellschaft
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Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO2015176836A1 publication Critical patent/WO2015176836A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes

Definitions

  • the present invention relates to an apparatus and method for generating one or more random bits. For example, a random bit sequence is generated which is used as a binary random number.
  • the proposed apparatus and methods for generating random bits are used, for example, the implementation of random number generator ⁇ ren.
  • the invention enables the generation of a true random bits.
  • random bit sequences are necessary as binary random numbers. It is desirable , in particular for mobile applications, to operate as little hardware as possible.
  • Known measures for generating random numbers are, for example, pseudo-random number generators, analogue random sources, ring oscillators and their modifications.
  • pseudo-random number generators seeds are used, from which deterministic pseudorandom numbers are calculated.
  • a physical random number generator is usually used.
  • Noise sources such as the noise of zener diodes, are amplified and digitized as analogue random sources.
  • the Ver ⁇ connection is usually only be realized by consuming digital with analog circuitry.
  • Fibonacci and Galois ring oscillators generate random waveforms faster than classical ring oscillators.
  • various digital gates such as XOR and NOT gates are used.
  • FPGAs Field Programmable Gate Arrays
  • FPGAs Field Programmable Gate Arrays
  • an apparatus for generating random bits comprising a plurality of imaging devices, each of the plurality of imaging devices is set up, one of a plurality of input signals fabric ⁇ th input bit using a combinatorial
  • the imaging devices of the plurality of imaging devices are linked together, and at least one imaging device is implemented as a combinational ⁇ combinatorial bijection such that a change of state of an input signal of at least one from ⁇ school has a maximum Avalanche effect.
  • a state change of a nowadaysssig ⁇ sound will be then ready to at least one imaging device in the middle to a maximum number of output signals of the at least one imaging device, can mean the average, that over all possible input bit each with a state change of the input signals of the Minim ⁇ averaging an imaging device.
  • the number of imaging devices used can be kept low, as a result of which the power consumption compared with other randombit generators is reduced.
  • all imaging devices are configured as maximum avalanche effect bijections.
  • all imaging devices are implemented as a combinatorial bijection with maximum avalanche effect of the type that a change in state of an input signal Signal of a respective imaging device is imaged on the average to a maximum number of output signals of the respective imaging device.
  • "on average” means that one of the input signals of the respective imaging device is averaged over all possible input bit patterns with one state change in each case
  • the imaging devices may be logic or combinatorial gates that each realize a bijective mapping or combinatorial bijection of n input signals to n output signals.
  • the input signals fluctuate between levels which can be assigned to logic states such as bits 1 or high or 0 or low. Under one
  • bijective mapping is understood to mean a one-one Abbil ⁇ connection between the 2 n possible values of the logical input signals, and the 2 n logical values of the output signals.
  • At least one combinatorial figure is configured such that imaged a ⁇ output signals under application of a jitter and a lo cal ⁇ function to the output signals.
  • the hardware implementation of combinatorial bijection by the imaging devices may result
  • Jitter ie fluctuations, in the temporal course of signal edges result.
  • This jitter is then perform the logical function, ie, the bijective mapping the combination of n input signals, or bit values on n output signals, or bit values, respectively continued and akkumu ⁇ distinguishes itself through the passes through the imaging devices.
  • Bijections therefore lead to a particularly high "amplification” of the jitter and therefore strong "randomness” or randomization.
  • Ci and c ⁇ are arbitrary (binary) constant values.
  • a detection of the random bits derived from the signal forms takes place, for example, by sampling, for example clocked or at predetermined other times, and serves to derive a bit value H or L which has a high entropy or randomness due to the strongly fluctuating random signal.
  • Output mapping means to apply which signal edges count.
  • the resulting bit value (s) may be understood as a random bit. Due to the predetermined level changes, for example, from a logic low level (0) to a logic high level (1) or vice versa, is due to the logical bijections with avalanche effect a passage through the signal change by the b
  • Chain of imaging devices set in motion.
  • the sampling in each case picks up a random level, which is assigned by the detection device to a respective random bit value. Random bit detection takes place, for example, both with a level change from zero to one and subsequently back to zero again.
  • the detection device is set up to detect the output signals of a last imaging device of the plurality of interconnected imaging devices as random bits.
  • a linear chain of combinatorial mapping devices is provided, wherein the input side of the chain level changes for Er ⁇ witnessing signal edges are coupled, and the output side true random signals are sampled.
  • the detection device has, for example, a buffer element, in particular a T flip-flop.
  • a buffer element in particular a T flip-flop.
  • flip-flops in particular T-flip-flops
  • the acquisition of the output signals and a mapping to logical random levels can be carried out in a cost-effective manner.
  • one or more counters for detecting signal edges or state changes of individual signals.
  • a T-flip-flop is particularly suitable for counting rising or falling signal edges modulo 2.
  • the imaging devices are such MITEI ⁇ Nander concatenated, that no feedback occurs.
  • the device does not have to continuously perform switching operations in a digital circuit implementation, which limits power consumption.
  • the device does not develop "oscillations" or signal transitions do not propagate in a circle, for example, the output signals are all forward coupled, Preferably, none of the output signals is causally independent of itself by being fed back.
  • the imaging devices are so linked together in embodiments in that no feedback loop ⁇ fe is formed such that a state change Minim ⁇ least an output signal of an imaging device is supplied as a change of state of at least one input signal of another imaging device.
  • feedback paths may be provided, but preference ⁇ as not lead to oscillations.
  • further circuits such as logic gates or delay elements, may be provided from a first to a last mapping device, which may be referred to as output mapping.
  • the imaging devices are set up in such a way that their signal transit times are the same. The same signal propagation times reduce the risk that jitter contributions can compensate each other. It also facilitates implementation in the manner of ASICs or FPGAs.
  • the Abönseinrich- obligations are adapted to all the possible state changes at the respective outputs all within a tolerance interval of 100 ps, and preferably within 50 ps ⁇ SUC gene.
  • at least one imaging device includes a lookup table or a Nachschla ⁇ getabelle for implementing combinatorial bijection. It is also possible that all imaging devices are provided with one or more respective lookup tables. Lookup tables can be easily read and require only a small amount of hardware.
  • first of all fixed levels can be applied as a first input bit pattern to the inputs of one of the imaging devices, preferably the first mapping device of the chain, in order to start from a well-defined state change. At least one of these fixed levels is then switched to another fixed value, resulting in a second input bit pattern. Subsequently, the concatenated application of the combinatory mappings to the signals results in an n or p bit wide random bit signal. The return to the first input bit pattern results in a subsequent new random bit signal.
  • the predetermined number n of input be ⁇ relationship as output signals of at least three. In exporting approximately ⁇ form is the bit width or the number n, p ⁇ relationship of predetermined input or output signals to the imaging means ⁇ four or more.
  • a method for generating random bits is presented, in which a plurality of combinatorial
  • Bijections are chained sequentially, wherein a respective combinatorial bijection maps an input bit pattern having a plurality of input bits into an output bit pattern having a plurality of output bits, and at least one of the plurality of combinatorial bijections has a large one
  • Causing avalanche effect and a bijection is particularly chosen such that a change in state of an input output bits at least one combinatorial bijection is to a maximum number of output bits, wherein can be called in the middle that on any Occasion ⁇ chen input bit with in each case a change in state of one of the input bits of the at least one combinatorial bijection is averaged.
  • the choice of a bijection with in particular maximum is particularly chosen such that a change in state of an input output bits at least one combinatorial bijection is to a maximum number of output bits, wherein can be called in the middle that on any Occasion ⁇ chen input bit with in each case a change in state of one of the input bits of the at least one combinatorial bijection is averaged.
  • the apparatus for generating random bits is Example ⁇ as adapted for implementing the method.
  • all combinatorial bijections can be implemented such that a state change of an input bit for a respective combinatorial bijection in the
  • Means is mapped to a maximum number of output bits of the respec ⁇ gen combinatorial bijection, wherein on average means in particular means that is averaged over all possible decisionssbit ⁇ pattern with a change in state of the input bits of the respective combinatorial bijection.
  • Ci and Ci are arbitrary (binary) constant values.
  • At least four combinatorial bijections are concatenated successively.
  • Embodiments include between three and twenty concatenated combinatory bijections or imaging devices, preferably between three and ten, and in certain embodiments only four or five.
  • the choice and implementation of Bijetationen allows a particularly on ⁇ low-wall and power-saving design with only a few hardware elements.
  • the combinatorial mappings are preferably linked together in such a way that no feedback loop is produced.
  • a state change of at least one output signal of an imaging device is supplied as a change in state of at least one input signal to another imaging device, which for example is signal path upstream in the chain.
  • the combinatorial bijections are preferably linked only forwards, or the imaging devices are connected in series one behind the other and operated without feedback.
  • the method can be implemented on or in an FPGA or ASIC device via suitable description languages, for example VHDL or Verilog.
  • the imaging devices are preferably set up such that state changes on an input signal of the n input signals as a function of the combinatorial bijection at the same time change state in one or more of the output signals as simultaneously as possible cause.
  • Fig. 1 is a schematic representation of anwhosbei ⁇ game for a device for generating random bits
  • Fig. 2 shows schematic representations of combinatorial bijections, bit patterns and signals in the operation of the apparatus of Fig. 1 and a method for generating random bits.
  • Fig. 1 shows a schematic representation of a first embodiment of an apparatus for generating random bits.
  • the device 1 is designed in the manner of a chain of imaging devices 2 ⁇ - 2 m .
  • the combinatorial digital circuits 2i - 2 m can also function as logic gates or imaging devices for a respective combinatorial Figure Ki - K m verstan ⁇ be, wherein the pictures are bijection, so egg godeutig represent n input bits to n output bits.
  • a starting device 3 which provides specified values for the input signals ESu-ESi n for the first imaging device 2i and, based thereon, generates level changes for these input start signals.
  • the da ⁇ by resulting signal edges are continued through the chain of figures.
  • a detection or scanning device 4 is coupled, which detects the output signals A m i - A mn the last imaging device 2 m .
  • latches or flip-flops 6 are used to detect the signal ⁇ make within the random waveform. From the detected levels, a random bit or a random number ZB can be derived, which can be output by the scanning device 4.
  • n p.
  • the sampling can be triggered by a clock signal CK.
  • the random bit signal or random bit pattern ZB thus generated can be supplied to an optional evaluation device 9.
  • the evaluation device 9 subjects the detected random bits ZB, for example by means of statistical methods, to postprocessing in order to compensate skewness in the generated random bits. This gives the output true random bits ZB ⁇ .
  • a skew of generated random bits denotes the ratio of the components of zeros and ones. In an idea ⁇ len skewness a distribution of random bits of 1 and 0 with a probability of 0.5 is present. A skew of 2% means that a probability for an H level or a one is 0.52.
  • the inputs and outputs are not explicitly indicated.
  • An ever ⁇ stays awhile imaging device 2 ⁇ insofar receives En - Ei n input signals corresponding to one input bit and indicates - Ai p output signals of which form an output bit.
  • FIG. 1 only the input bit pattern EBMi and output bit pattern ABMi are explicitly indicated for the first mapping device 2i.
  • the connection between input and output signals is realized via a combinatorial mapping K ⁇ , which is a bijection with a maximum
  • Avalanche effect is set up. It can be seen in the lung ⁇ depicting the Fig. 1, that the Ki to K m combinatorial pictures done sequentially concatenated.
  • the imaging devices 2i - 2 m are such as combinatorial bijections Ki - K implemented m that, on average, a state change of the respective on a
  • Input present signal E ki - E kn leads to a maximum number of state changes in the output signals A ki - A kn .
  • jitter accumulated in the signals En to E mn and An to A m _i, n, respectively, accumulate and multiply as they pass through the linked imaging devices
  • Each input signal E j i -E n is considered to be a bit value x i -x n
  • each output signal A j i -A n is taken as a bit value y i -y n .
  • the above-indicated function or bijection F provides a change of the resulting output bit pattern from 1110 to 0000.
  • a threefold multiplication of the state change is obtained X4 with the assumed input bit pattern on yi, Y2, and V3.
  • the bijection is now preferably such con ⁇ ted in that they averaged over all such one-bit tosbitmuster modus the maximum number of state changes in the output bits causes.
  • n channels result with random signal forms, which are caused by the jitter caused by the switching elements constituting the digital imaging devices.
  • the schematically indicated device for generating random bits 1 can be realized, in particular, at low cost in FPGA or ASIC devices.
  • ring oscillators can be at a higher data rate random bits produce because of the particular random beneficiaries ⁇ tigende jitter using the plurality of channels is n times verviel- of CSP.
  • a Randallzah ⁇ lengenerator can be realized with a high random bit-generating frequency at low cost.
  • the proposed device and the underlying method are particularly suitable for implementation in ASICs.
  • the logical functions of the imaging devices preferably have the same logical depth in order to achieve the same signal transit time of the combinatorial mappings.
  • lookup tables can also be dispensed with.
  • the inven- tion also enabling fast random ⁇ bit generation with low hardware cost.

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Abstract

L'invention concerne un dispositif (1) permettant de générer des bits aléatoires (ZB). Ledit dispositif comprend une pluralité de systèmes de représentation (21 - 2m), chaque système parmi la pluralité de systèmes de représentation (21 - 2m) étant mis au point pour représenter, à l'aide d'une bijection combinatoire (K1 - Km), un modèle de bits d'entrée (EBM1 - EBMm) formé à partir de plusieurs signaux d'entrée (E11 - Emn) en un modèle de bits de sortie (ABM1 - ABMm) formé par des signaux de sortie (A11 - Amn). Les systèmes de représentation (21 - 2m) de la pluralité de systèmes de représentation (21 - 2m) sont chaînés les uns aux autres et au moins un système de représentation (2j) implémente une bijection combinatoire (Kj) avec un fort effet d'avalanche, en particulier d'une manière telle qu'un changement d'état d'un signal d'entrée (Ej1 - Ejn) du ou des systèmes de représentation (2j) soit représenté en moyenne sur un nombre maximal de signaux de sortie (Aj1 - Ajn) du ou des systèmes de représentation (2j). En moyenne signifie qu'une moyenne est calculée sur tous les modèles de bits d'entrée (EBMj) possibles avec un changement d'état d'un des signaux d'entrée (Ej1 - Ejn) du ou des systèmes de représentation (2j). Avec un procédé de génération de bits aléatoires (ZB), une pluralité de bijections combinatoires (K1 - Km) sont exécutées les unes après les autres d'une manière chaînée, les bijections (K1 - Km) contribuant le plus possible à un effet d'avalanche maximal.
PCT/EP2015/054895 2014-05-21 2015-03-10 Dispositif et procédé de génération de bits aléatoires WO2015176836A1 (fr)

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DE102014209689.8A DE102014209689A1 (de) 2014-05-21 2014-05-21 Vorrichtung und Verfahren zum Erzeugen von Zufallsbits
DE102014209689.8 2014-05-21

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US20160371059A1 (en) * 2015-06-17 2016-12-22 Nxp B.V. Digital true random number generator based on s-boxes

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US7898283B1 (en) * 2009-08-31 2011-03-01 Farinaz Koushanfar Lightweight secure physically unclonable functions
DE102013222218A1 (de) * 2013-10-31 2014-05-22 Siemens Aktiengesellschaft Konstruieren einer Schaltung geeignet zur Erzeugung von Zufallsbits und Schaltung zur Erzeugung von Zufallsbits

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US5231667A (en) * 1990-12-10 1993-07-27 Sony Corporation Scrambling/descrambling circuit
US20090189667A1 (en) * 2008-01-30 2009-07-30 Advantest Corporation Jitter injection circuit, pattern generator, test apparatus, and electronic device

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ANONYMOUS: "Avalanche effect - Wikipedia, the free encyclopedia", 30 March 2015 (2015-03-30), XP055192759, Retrieved from the Internet <URL:http://en.wikipedia.org/wiki/Avalanche_effect> [retrieved on 20150601] *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160371059A1 (en) * 2015-06-17 2016-12-22 Nxp B.V. Digital true random number generator based on s-boxes
US9891888B2 (en) * 2015-06-17 2018-02-13 Nxp B.V. Digital true random number generator based on S-boxes

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