WO2015174613A1

WO2015174613A1 - Time register, time calculation device using same, time calculation method, time-digital conversion device, and time-digital conversion method

Info

Publication number: WO2015174613A1
Application number: PCT/KR2015/001185
Authority: WO
Inventors: 조성환; 김광석; 유원식
Original assignee: 한국과학기술원
Priority date: 2014-05-13
Filing date: 2015-02-05
Publication date: 2015-11-19

Abstract

A time register according to an embodiment of the present invention comprises: an in (IN) signal input unit for receiving an input signal having a first time interval; a trigger signal input unit for receiving a trigger signal; an enable (EN) generation unit for generating an EN signal in response to the input signal and the trigger signal; a set (SET) signal input unit for receiving a set signal; and a series delay gate circuit unit for receiving the EN signal and transmitting the SET signal. Accordingly, the present invention can design a time register capable of storing time information and a clock synchronous addition or subtraction. Further, the present invention can provide a time register which can improve a time resolution together with a processing time by using a series delay gate circuit in implementing the time register, and provide a time-digital conversion device, a time-digital conversion method, a time calculation device, and a time calculation method.

Description

Time register, time computing device, time computing method, time-to-digital converter and time-to-digital conversion method

The present invention relates to a time computing device, and more particularly, to a time computing device, a time computing method, a time-to-digital conversion device and a time-to-digital conversion method that can perform a time operation using a time register. It is about.

With the recent development of semiconductor process technology, the supply voltage of circuits is lowering and the characteristics of MOSFETs, which are individual devices, are deteriorating. Therefore, the circuit design using the existing voltage-based signal processing method becomes more and more difficult. Recently, many studies have been conducted on time-based signal processing as an alternative circuit design method. Time-based signal processing is a technique that processes a signal by converting an input signal into an interval of two edges or a width of a single pulse on the time axis. Therefore, the transition time of the digital signal is reduced, and the time-based resolution is increased. Accordingly, there is a need for a study on performance improvement for time calculation, as well as a study on a circuit operating on a time basis, for subtracting or adding a clock synchronized pulse time.

However, in order to measure the time of a pulse and provide subtraction or addition of time information, a complicated process is required. Therefore, it is very difficult to design a time computing device having a high resolution and a high processing speed that can be used in a practical industrial environment.

The present invention is to solve the above-described problems, it is easy to add or subtract time information using a time register (Time Register), time register and time computing device using the same to improve the time resolution and processing speed, It is an object of the present invention to provide a time calculation method, a time-digital conversion device and a time-digital conversion method.

Time-to-digital converter according to an embodiment of the present invention for solving the above problems is a pulse generator for generating an input pulse signal; And a pipe stage unit configured to receive the input pulse signal and perform a time delay operation for each stage according to a pipeline, wherein the pipe stage unit includes a plurality of stage circuits, and the stage circuits accumulate time information. And a time register using a delay gate circuit.

According to another aspect of the present invention, there is provided a method of converting a time-digital signal into an input pulse signal; Storing first time information on a serial delay gate cycle of a time register as the input pulse signal is applied; Generating a first output code from the first time information; Generating a time reference corresponding to the first output code and generating a residual signal corresponding to the time reference; And amplifying and outputting the residual signal.

Time register according to an embodiment of the present invention for solving the above problems is an IN signal input unit for receiving an input signal having a first time interval; A trigger signal input unit for receiving a trigger signal; An enable (EN) generator for generating an enable (EN) signal in response to the input signal and the trigger signal; A set signal input unit for receiving a set signal; And a serial delay gate circuit unit receiving the enable signal and propagating the SET signal.

In order to solve the above problems, a time adder according to an exemplary embodiment of the present invention sequentially receives a first pulse signal having a first time interval Ta and a second pulse signal having a second time interval Tb. An input unit to perform; And a first series delay gate circuit unit, accumulating time information of the first pulse signal and the second pulse signal sequentially input, and at the first limit time at which the limit signal is output from the first series delay gate circuit unit. A first time register configured to output a first output signal obtained by subtracting the accumulated time of the first time interval Ta and the second time interval Tb; And a second series delay gate circuit unit, having a time interval of Ta + Tb accumulated in time information of the first output signal and subtracted from a second limit time at which a limit signal is output from the second series delay gate circuit unit. And a second time register for outputting two output signals.

A time subtractor according to an embodiment of the present invention for solving the above problems, the first input unit for receiving a first pulse signal having a first time interval Ta; A first series delay gate circuit unit, and accumulating time information Ta of the first pulse signal and subtracting the accumulated Ta time from a first limit time at which the limit signal of the first series delay gate circuit unit is output; A first time register for outputting an output signal; A second input unit sequentially receiving a second pulse signal having a second time interval Tb and the first output signal; And a second series delay gate circuit portion, wherein Ta is accumulated in time information of the first output signal and the second pulse signal and subtracted from a second limit time at which a limit signal of the second series delay gate circuit portion is output. And a second time register for outputting a second output signal having a time interval of Tb.

According to an embodiment of the present invention, it is possible to design a time register capable of clock synchronous storage, addition or subtraction of time information.

In addition, the present invention provides a time register that can improve the time resolution and processing speed by using a serial delay gate circuit in the time register implementation, time-digital conversion device, time-digital conversion using the same A method, a time calculating device, and a time calculating method can be provided. Accordingly, the design of the time-digital conversion device, the time-digital conversion method, the time calculation device, and the time calculation method is facilitated.

In addition, the time register according to an embodiment of the present invention is not only various time-to-digital converters, but also circuits such as an All Digital Phase Locked Loop (ADPLL) circuit or a Digital Phase Locked Loop. Applicable to

1 is a block diagram illustrating a time register according to an exemplary embodiment of the present invention, and FIG. 2 is an implementation circuit and an input / output timing diagram of a time register according to an exemplary embodiment of the present invention.

3 is a diagram schematically illustrating input and output timing of the time register 100 according to an exemplary embodiment of the present invention.

4 illustrates the configuration and input / output configuration of the subtractor 200 and the adder 300 using the time register 100 according to an embodiment of the present invention.

5 illustrates a series gate cell according to an embodiment of the present invention.

6 and 7 illustrate comparison result data when the tilted delay gate cell 151B is applied to the time register 100 according to an exemplary embodiment of the present invention.

8 is a block diagram illustrating a time-to-digital converter 400 according to an embodiment of the present invention.

9 is a block diagram and a circuit diagram of the stage circuit 420 constituting the pipe stage unit 420A according to the embodiment of the present invention.

10 shows a detailed configuration of the time amplifier 423.

11 illustrates a detailed configuration of the line-delay time-digital converter 430 according to an embodiment of the present invention.

12 illustrates a transfer curve curve of the time-to-digital converter 400 according to an embodiment of the present invention.

13 and 14 illustrate flowcharts and circuit operations for explaining a time-to-digital conversion method for each stage of the time-to-digital converter 400 according to an exemplary embodiment of the present invention.

15 is a timing diagram illustrating the overall operation of the time-to-digital converter 400 according to an embodiment of the present invention.

16 is a diagram for describing an example in which the time-to-digital converter 400 is implemented as a chip according to an exemplary embodiment.

17 to 21 are experimental result data of the time-digital converter 400 according to an embodiment of the present invention.

The following merely illustrates the principles of the invention. Therefore, those skilled in the art, although not explicitly described or illustrated herein, can embody the principles of the present invention and invent various devices that fall within the spirit and scope of the present invention. In addition, all conditional terms and embodiments listed herein are in principle clearly intended to be understood only for the purpose of understanding the concept of the invention and are not to be limited to the specifically listed embodiments and states. do.

In addition, it is to be understood that all detailed descriptions, including the specific embodiments, as well as the principles, aspects, and embodiments of the present invention, are intended to include structural and functional equivalents thereof. In addition, these equivalents should be understood to include not only equivalents now known, but also equivalents to be developed in the future, that is, all devices invented to perform the same function regardless of structure.

Thus, for example, it should be understood that the block diagrams herein represent a conceptual view of example circuitry embodying the principles of the invention. Similarly, all flowcharts, state transitions, pseudocodes, and the like are understood to represent various processes performed by a computer or processor, whether or not the computer or processor is substantially illustrated on a computer readable medium and whether the computer or processor is clearly shown. Should be.

The functionality of the various elements shown in the figures, including functional blocks represented by a processor or similar concept, can be provided by the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functionality may be provided by a single dedicated processor, by a single shared processor or by a plurality of individual processors, some of which may be shared.

In addition, the explicit use of terms presented in terms of processor, control, or similar concept should not be interpreted exclusively as a citation to hardware capable of running software, and without limitation, ROM for storing digital signal processor (DSP) hardware, software. (ROM), RAM, and non-volatile memory are to be understood to implicitly include. Other hardware for the governor may also be included.

In the claims of this specification, components expressed as means for performing the functions described in the detailed description include all types of software including, for example, a combination of circuit elements or firmware / microcode, etc. that perform the functions. It is intended to include all methods of performing a function which are combined with appropriate circuitry for executing the software to perform the function. The invention, as defined by these claims, is equivalent to what is understood from this specification, as any means capable of providing such functionality, as the functionality provided by the various enumerated means are combined, and in any manner required by the claims. It should be understood that.

The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. There will be. In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 and 2, the time register 100 according to an exemplary embodiment of the present invention includes an IN signal input unit 110, a trigger signal input unit 120, a SET signal input unit 130, and an An EN signal generator 140 and a series delay gate circuit 150.

As shown in FIG. 1, the time register 100 according to an embodiment of the present invention includes a series delay gate circuit 150, and the series delay gate circuit 150 includes a plurality of delay gate cells or delays connected in series. And gated delay line circuits. Each delay gate cell connected in series may serve to accumulate time information according to an enable (EN) signal input. According to the enable (EN) signal input to the delay gate cells, the stepwise transfer of the SET signal input to the SET signal input unit 130 may be controlled.

More specifically, the IN signal input unit 110 receives an input pulse of the time register 100 and transmits the input pulse to the enable signal generator. The IN signal input unit may receive an input pulse having an input time T_IN from the outside in response to the time information to be stored in the time register. In addition, according to an embodiment of the present disclosure, the in signal input unit 110 may add a predetermined offset time to the input signal T_IN in order to prepare for the case where a narrow time pulse is input. .

In addition, the trigger signal input unit 120 receives the trigger pulse and delivers the trigger pulse to the enable (EN) signal generator. The trigger signal may include a clock signal, for example. The trigger signal input to the trigger signal input unit 120 may be a pulse signal having a predetermined length and may correspond to a clock signal for storing time information of the time register 100.

The enable signal generator 140 generates an enable signal according to the trigger pulse and the in signal, and applies the enabled signal to the series delay gate circuit 150.

In the SET signal input unit 130, a SET signal for driving the time register may be input, and the SET signal may be applied as an input signal of the serial delay gate circuit 150. The driving of the time register 100 may be started according to the SET signal input. When the IN signal is HIGH and the SET signal is HIGH, the SET signal is applied to the series delay gate circuit 150 to propagate through each delay gate circuit. PROPAGATION). However, when the IN signal is turned low, propagation of the SET signal may be stopped. However, when the trigger signal is input again while the IN signal is LOW, the propagation of the SET signal may be resumed. The propagation of the SET signal may be terminated by outputting the limit signal FULL SIGNAL from the serial delay gate circuit 150. According to an embodiment, when the limit signal is output, the SET signal is changed to LOW and the time register 100 may be initialized.

Meanwhile, the series delay gate circuit 150 may be configured as a circuit in which a plurality of delay gates are connected in series as shown in FIG. 2A.

As an enable (EN) signal is applied to the delay gates, the series delay gate circuit 150 accumulates time information by sequentially operating the plurality of delay gate cells, and limits the time information when the accumulated time information reaches a limit value. Signals (FULL SIGNAL, FS) can be output.

In addition, in order to accumulate time information, the series delay gate circuit 150 may use a phase delay. As shown in FIG. 2B, in each delay gate cell (or delay gate line), an input pulse is generated according to an enable signal generated by a trigger signal and an IN signal. It can be seen that the phase (pulse) increases constantly in response to the time interval of. As shown in FIG. 2A, when the time at which the limit signal of the series delay gate circuit 150 is output due to the accumulation of input pulses is T_FS, when the phase delayed by each delay gate cell is τ_Q, It can be said that the time T_FS = N * τ_Q until the limit signal is output.

In addition, as shown in FIG. 2B, when the IN signal and the trigger signal are applied to the series delay gate circuit 150 as 0, and the enable signal is not applied, the phase is presently present. You can see that it stays with the value. If the enable (EN) signal is applied until the phase 2τ_Q is stopped, the phase of the series delay gate circuit 150 may be maintained at 2τ_Q until the phase is increased again by the trigger signal. By using the increase and sustain timing of the phase delay, the time information storage function of the time register 100 may be implemented.

In addition, by the phase delay and maintenance of the series delay gate circuit 150, the time T_FS at which the limit signal is output can be controlled. Here, T_FS may be a predetermined time according to the characteristics and the number of delay gate cells. In this case, by simply increasing the number of delay gate cells, the time limit accumulated in the series delay gate circuit 150 may be easily increased.

The output unit 160 may output the output T_OUT of the time register 100 configured as described above. Here, the output T_OUT can be designated as T_OUT = T_FS-T_IN when the input waveform IN signal is expressed as T_IN. The output unit 160 may acquire and output time information stored in the time register 100 by calculating T_OUT as described above. In addition, the output unit 160 may be configured to output T_IN itself by continuously inputting T_OUT to the time register 100 again.

As shown in FIG. 3A, when a signal having a time interval of T_IN is input to an IN input of the time register 100 according to an exemplary embodiment of the present invention, an output time of the time register 100 is input. The information T_OUT may be calculated by T_FS-T_IN.

This can be explained in more detail through the timing diagram of FIG. 3 (b). When an input pulse having a time interval of T_IN is received, the time register 100 according to an embodiment of the present invention may maintain time information as long as T_IN time until the trigger signal of the next clock is received. When the trigger signal is received, the time register 100 may delay the time only from the accumulated time T_IN to the limit time T_FS and output the limit signal FS. Therefore, the time information stored in the time register 100 may be output as a value obtained by subtracting T_IN from T_FS.

Meanwhile, the adder 200 or the subtractor 300 using the time register 100 according to an embodiment of the present invention may be implemented.

4 illustrates a configuration of an adder 200 and a subtractor 300 and an input / output configuration using the time register 100 according to an exemplary embodiment of the present invention.

First, the adder 200 will be described. The adder 200 according to an exemplary embodiment of the present invention includes an input unit 210, a first time register 100A, a second time register 100B, and an output unit 220. .

The input unit 210 may sequentially receive the first pulse signal having the first time interval Ta and the second pulse signal having the second time interval Tb and transmit the same to the first time register 100A.

The first time register 100A accumulates time information of the first pulse signal and the second pulse signal sequentially input, and subtracts the accumulated time of Ta and Tb from the limit time T_FS at which the limit signal is output. The first output signal T_FS-(Ta + Tb) is output and transferred to the second time register 100B.

Then, the second time register 100B accumulates the time information of the transmitted first output signal, and outputs the second output signal T_FS-(T_FS-(Ta + Tb)) subtracted from the limit time. )

Accordingly, a second output signal having a Ta + Tb time interval to which the first time interval Ta of the first pulse signal sequentially input and the second time interval Tb of the second pulse signal are added may be output to the outside. Therefore, the adder 200 according to an exemplary embodiment of the present invention may be implemented by cascading the first time register 100A and the second time register 100B dependently.

And, when the subtractor 300 is described, the subtractor 300 according to the embodiment of the present invention includes a first input unit 310, a first time register 100C, a second input unit 320, and a second time register 100D. ) And an output unit 330.

The first input unit 310 may receive the first pulse signal having the first time interval Ta and transmit it to the first time register 100C.

The first time register 100A accumulates the input first pulse signal time information Ta, and calculates the first output signal T_FS-Ta obtained by subtracting the accumulated time Ta from the limit time T_FS at which the limit signal is output. The output is transmitted to the second input unit 320.

The second input unit 320 sequentially receives the second pulse signal having the second time interval Tb and the first output signal, and transfers the second output signal to the second time register 100B. To this end, the second input unit 320 may include at least one logic gate.

Then, the second time register 100B accumulates the time information of the transmitted first output signal and the second pulse signal, and subtracts the second output signal T_FS-(T_FS-Ta) + Tb)) Output to the output.

Accordingly, a second output signal having a Ta − Tb time interval obtained by subtracting the first time interval Ta of the first pulse signal sequentially input and the second time interval Tb of the second pulse signal may be output to the outside. Therefore, the adder 200 according to an exemplary embodiment of the present invention may be implemented by cascading the first time register 100A and the second time register 100B dependently.

As described above, the time register 100 according to the embodiment of the present invention may be easily implemented in the form of the adder 200 and the subtractor 300 by the characteristic thereof, and may easily store time information and synchronize clocks. do.

5 illustrates a direct gate cell according to an embodiment of the present invention.

On the other hand, the series delay gate circuit 150 of the time register 100 according to the embodiment of the present invention may be composed of delay gate cells connected in series, as shown in Figure 5 (a) a general delay gate cell 151A It can be implemented in the form of.

However, when the plurality of delay gate cells 151A are connected, an error may occur due to a gating imbalance. In particular, a phase error may occur when propagation of a SET signal is not properly performed in a period where time information is maintained.

In order to reduce such an error, the delay gate cell is implemented in the form of a skewed gated delay cell (151B) for preventing an error as shown in FIG. Can be. The tilted delay gate cell 151B uses a plurality of input units (IN [n-5], IN [n-3], IN [n-1], etc.) to which the SET signal is input to propagate the SET signal. The control unit may include an output unit configured to transfer a plurality of input SET signals through a plurality of paths and to output the next delay gate cell 151B. According to such a configuration, it is possible to reduce time error of the input / output signal.

Referring to FIG. 6, FIG. 6 is a graph showing an error time versus an input time, and the maximum error time difference in the case of applying a tilted delay gate cell 151B for transmitting a signal through multiple paths (B) is a general delay gate. It can be seen that the cell 151A is much smaller than the case (A).

In addition, Figure 7 is a Monte Carlo simulation results according to various environmental conditions, the time error of the time register 100 according to an embodiment of the present invention is a change in all environmental conditions (voltage 1,2V + -0.05V, temperature 0 ~ 80 degrees, etc.), it can be seen that it is only within about 0.5 picoseconds (ps).

Meanwhile, a time-to-digital converter (TDC) using the time register 100 according to the present embodiment may be implemented.

Referring to FIG. 8, the time-to-digital converter 400 according to an embodiment of the present invention may include a pulse generator 410, a pipe stage unit 420A, a line delay time-digital converter 430, and a digital error report. Government 440.

As shown in FIG. 8, the pulse generator 410 receives a start signal and a stop signal, generates a pulse signal Tin according to the time difference, and transmits the generated pulse signal Tin to the pipe stage unit 420A. . In addition, the pulse generator 410 may apply an operation clock signal for driving the time-to-digital converter 400 to each component. Also, for error correction, the pulse generator 410 may add an offset time to the time difference between the start signal and the stop signal and transmit the offset time to the pipe stage unit 420A.

The start signal applied to the pulse generator 410 may be periodically applied from an external system, and the pulse generator 410 extracts the operation clock signal into an external clock from the periodically applied start signal, and the external clock thereof. Can be transmitted as a clock signal of each component.

However, when the start signal is not periodic, the pulse generator 410 may generate and apply an operation clock signal to each component.

In addition, the time-to-digital converter 400 according to an embodiment of the present invention includes a pipe stage unit 420A which performs time delay calculation for each pipeline to the plurality of stage circuits 420 based on the applied pulse signal Tin. can do. For example, if four time delay operations are performed in three pipelines as shown in FIG. 8, 4 * 4 * 4 = 64 stage operations may be performed. Accordingly, it is possible to improve the time resolution of the time-to-digital converter 400 without using a general Vernier delay line circuit or the like.

On the other hand, the time delay operation for each stage performed in each pipe may be performed by a plurality of stage circuits 420 included in the pipe stage unit 420. In addition, the conversion speed may be improved according to the pipeline operation performed on each pipe. A detailed circuit configuration for this purpose will be described later with reference to FIG. 9.

The time information output from the pipe stage unit 420A may be transmitted to the digital error correction unit 440 and the line delay time-digital converter 430.

The line delay time-digital converter 430 may serve as a final stage of time delay, and may function as a conventional pipe-line analog-to-digital converter (ADC) circuit.

The digital error correction unit 440 receives the output signal of the pipe stage unit 420A and the output of the line delay time-digital converter 430 to correct for offset errors that may occur in a general time-digital converter. do. The digital error correction unit 440 may output the corrected time-digital conversion signal to the outside.

As illustrated in FIG. 9, the stage circuit 420 according to an embodiment of the present invention may include a time register 100, a first time-digital converter 421, a first digital-time converter 422, and a time. An amplifier 423 is included.

The configuration of the time register 100 is as described above, receives an input pulse, maintains and stores time information as the first time Tin according to the time of the received input pulse, and stores the stored first time as the first time. Output to the time-digital converter 421.

The first time-digital converter 421 quantizes the first time, generates a first output code, and outputs the first output code to the first digital-time converter 422.

Thereafter, the first digital-time converter 422 generates a time reference Tref according to the first output code, and transmits the time reference Tref to the time amplifier 423.

The time amplifier 423 amplifies the residual signal Tout and delivers the residual signal to the next stage circuit 420.

When the stage circuit 420 as shown in FIG. 9 is performed four times, a signal of 4 * (Tin−Dout * Tref) may be output according to the first time and the residual signal. The digital error correction unit 440 collects a time signal of a first bit, for example, 2.5 bits, from each stage circuit 420 to perform error correction processing, and converts time information of a second bit, for example, 9 bits. You can generate and output

9, the stage circuit 420 according to the embodiment of the present invention may include a first time-digital converter 421 connected to a plurality of delay gate cells included in the time register 100. And the first digital-time converter 422 may be implemented.

Accordingly, the first time-digital converter 421 may improve the operation speed and directly output the first output code by setting the quantization level.

In addition, the first digital-time converter 422 may receive the first output code signal to generate a time reference (Tref) signal. The first digital-time converter 422 may include a plurality of switches connected to the delay line to determine the reference level.

In addition, as shown in the lower part of FIG. 9, the time register 100, the first time-digital converter 421, and the first digital time converter 422 described above may be used to reduce the complexity and the complexity of the integrated circuit. Each core may be connected using one delay line.

10 illustrates a detailed configuration of the time amplifier 423. As illustrated in FIG. 10, the time amplifier 423 sequentially delays, merges and outputs a plurality of received pulse signals. It may be implemented in the form of a time amplifier (PT-TA). 10 illustrates an example implemented as a pulse train time amplifier for connecting, amplifying and outputting four first time input Tins. To this end, the time amplifier 423 may include at least three time delay circuits and an OR gate circuit for delayed signal merging. This allows accurate gain settings without calibration and broadens the linear range of the input signal.

According to such a pipeline configuration of the stage circuit 420, the dynamic range DR of the time-to-digital converter 400 according to the embodiment of the present invention is the entire time-digital converter 421. Can be extended according to the number. In addition, since the temporal resolution can be defined by dividing the quantization level of each first time-digital converter 421 by the gain sum of the entire time-digital converter, it is easily scalable.

11 illustrates a detailed configuration of the line-delay time-digital converter 430 according to an embodiment of the present invention, and includes a time register 100 and a part of the time register 100 for performing a last stage role. The second time-digital converter 431 may be connected to the plurality of delay gate cells. Operation of the other components except for the last flip flop FF is similar to that of the stage circuit 420 and thus will be omitted.

As shown in FIG. 12, the transfer curve curve may have an inverted shape as the output of the time register 100 according to an embodiment of the present invention is a compensative value. Therefore, the output between the even and odd stages may be inverted for each stage. Accordingly, the digital error compensator 440 may perform a process of correcting different inverted outputs for each stage as a normal output.

13 and 14, when the input signal is first applied to the time-to-digital converter 400 (S100), an enable (EN) signal is applied to the time register and a first time according to the input signal is stored. (S110).

As shown in FIG. 14A, the first input signal may include four pulses having a phase having a first magnitude. The four pulses may be the signal delivered in the previous stage, and the first magnitude may be 1.1τ_Q, for example. In addition, 4.4τ_Q whose phase is increased by four times the first magnitude may be stored and maintained in the time register 100 as time information corresponding to the first time.

The time-digital converter 400 generates a first output code based on the stored first time (S120).

As shown in FIG. 14B, the first time-digital converter 421 may generate and output an output code '001' corresponding to the first time according to a setting.

The time-digital converter 400 generates a time reference corresponding to the first output code and outputs a residual signal (S130).

As shown in FIG. 14C, the first time-digital converter 421 may select an appropriate node for acquiring the limit signal FULL SIGNAL of the time register 100 based on the first output code. have. As the trigger signal is received by the time register 100, the first time-digital converter 421 may acquire a time reference including a trigger time and a limit signal generation time. The first time-digital converter 421 may obtain a residual signal corresponding to a time difference from the trigger time to the limit signal acquisition time. For example, the first time-digital converter 421 may obtain a residual signal such as 1.6τ_Q by calculating 6τ_Q-4.4τ_Q.

The time-digital converter 400 amplifies and outputs the residual signal (S140).

As illustrated in FIG. 14D, the time amplifier 423 may sequentially delay, merge, and output a plurality of received pulse signals in a pulse train form. FIG. 14D illustrates an example in which four residual signal inputs 1.6τ_Q are connected and output.

As shown in FIG. 15, when the SET signal is applied to the time-to-digital converter 400, the time-to-digital converter 400 is initialized. Then, the input signal is received as a tin pulse, and the clock signal is received as each pulse is received. As received, the pipeline stage stage circuits 420 may operate, and the finally amplified residual signal may be output in synchronization with a clock.

Referring to FIG. 16, when the time-to-digital converter 400 is implemented on a chip, a clock generator, a first stage circuit, a second stage circuit, a third stage circuit, and a flash time-digital converter circuit may be used. It can be implemented on a small chip including and a logic circuit. According to this configuration, the time-to-digital converter 400 may be implemented on a standardized CMOS chip, and may reduce power consumption.

As shown in Figs. 17-21, the dynamic range of the input signal recorded 578 ps, which is the time register 100 using the delay-line and delay gate cells as described above. It can be achieved by the operation of. In addition, the operation speed and time resolution were also improved, recording 250MSamples / s and 1.12ps. As a result of the figure-of-merit analysis, the power consumption is reduced and the performance of the time-to-digital converter is improved. In addition, it can be confirmed that the digital error compensation has a strong accuracy against noise and errors.

Meanwhile, the above-described method according to various embodiments of the present disclosure may be implemented in program code and provided to each server or devices in a state of being stored in various non-transitory computer readable mediums.

The non-transitory readable medium refers to a medium that stores data semi-permanently and is readable by a device, not a medium storing data for a short time such as a register, a cache, a memory, and the like. Specifically, the various applications or programs described above may be stored and provided in a non-transitory readable medium such as a CD, a DVD, a hard disk, a Blu-ray disk, a USB, a memory card, a ROM, or the like.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the specific embodiments described above, but the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

Claims

An IN signal input unit configured to receive an input signal having a first time interval;

A trigger signal input unit for receiving a trigger signal;

An enable (EN) generator for generating an enable (EN) signal in response to the input signal and the trigger signal;

A set signal input unit for receiving a set signal; And

And a serial delay gate circuit configured to receive the enable signal and propagate the SET signal.
The method of claim 1,

The series delay gate circuit

And a plurality of delay gate cells connected in series for accumulating time information according to an input signal having the first time interval.
The method of claim 2,

The series delay gate circuit

Accumulate time information by varying a phase according to operations of the plurality of delay gate cells;

And outputting a limit signal when the accumulated time information reaches a limit value.
The method of claim 3,

And an output unit configured to output first time information corresponding to the first time interval based on a difference value between the threshold time at which the limit signal is output and the trigger time.
An input unit sequentially receiving a first pulse signal having a first time interval Ta and a second pulse signal having a second time interval Tb;

A first serial delay gate circuit unit and accumulates time information of the first pulse signal and the second pulse signal sequentially input, and at a first limit time at which a limit signal is output from the first serial delay gate circuit unit; A first time register configured to output a first output signal obtained by subtracting the accumulated time of the first time interval Ta and the second time interval Tb; And

A second series delay gate circuit unit, having a time interval of Ta + Tb, which is accumulated in time information of the first output signal and subtracted from a second limit time at which a limit signal is output from the second series delay gate circuit unit; 2. A time computing device comprising a second time register for outputting an output signal.
The method of claim 5,

And the first series delay gate circuit unit or the second series delay gate circuit unit includes a plurality of delay gate cells connected in series to accumulate time information of an input pulse signal having a predetermined time interval.
The method of claim 6,

The first series delay gate circuit unit or the second series delay gate circuit unit may vary the phase according to the operations of the plurality of delay gate cells to accumulate the time information, and when the accumulated time information reaches a threshold value, a limit signal. Time computing device that outputs.
A first input unit configured to receive a first pulse signal having a first time interval Ta;

A first series delay gate circuit unit, and accumulating time information Ta of the first pulse signal and subtracting the accumulated Ta time from a first limit time at which the limit signal of the first series delay gate circuit unit is output; A first time register for outputting an output signal;

A second input unit sequentially receiving a second pulse signal having a second time interval Tb and the first output signal; And

A second serial delay gate circuit portion, and accumulating time information of the first output signal and the second pulse signal and subtracting Ta − Tb from a second limit time at which a limit signal of the second serial delay gate circuit portion is output; And a second time register configured to output a second output signal having a time interval of.
The method of claim 8,

And the first series delay gate circuit unit or the second series delay gate circuit unit includes a plurality of delay gate cells connected in series to accumulate time information of an input pulse signal having a predetermined time interval.
The method of claim 9,

The first series delay gate circuit unit or the second series delay gate circuit unit may vary the phase according to the operations of the plurality of delay gate cells to accumulate the time information, and when the accumulated time information reaches a threshold value, a limit signal. Time computing device that outputs.
Sequentially receiving a first pulse signal having a first time interval Ta and a second pulse signal having a second time interval Tb;

Accumulating time information of the first pulse signal and the second pulse signal which are sequentially input; Outputting a first output signal obtained by subtracting the accumulated time of the two time intervals Tb; And

Accumulating time information of the first output signal and outputting a second output signal having a time interval of Ta + Tb subtracted from a second limit time at which a limit signal is output by a second series delay gate circuit unit; Operation method.
Receiving a first pulse signal having a first time interval Ta;

Accumulating time information Ta of the first pulse signal and outputting a first output signal obtained by subtracting the accumulated Ta time from a first limit time at which a limit signal of a first series delay gate circuit part is output;

Sequentially receiving a second pulse signal having a second time interval (Tb) and the first output signal; And

Accumulating time information of the first output signal and the second pulse signal, and outputting a second output signal having a time interval of Ta − Tb subtracted from a second limit time at which the limit signal of the second serial delay gate circuit part is output; And a second time register.
A pulse generator for generating an input pulse signal; And

A pipe stage unit which receives the input pulse signal and performs time delay calculation for each stage according to a pipeline; Including,

The pipe stage unit includes a plurality of stage circuits,

The stage circuit

A time register for storing time information by an operation of a serial delay gate circuit portion for accumulating time information;

Time-to-digital converter.
The method of claim 13,

The stage circuit

A first time-digital converter configured to quantize the input first time to generate a first output code;

A first digital-time converter configured to generate a time reference including a trigger time according to the first output code, and obtain a residual signal; And

And a time amplifier for amplifying and outputting the residual signal.

Time-to-digital converter.
The method of claim 14,

The first time-digital converter and the first digital-time converter are connected to a portion of a serial delay gate circuit of the time register and disposed on the same delay-line. .
The method of claim 13,

The time register,

An IN signal input unit configured to receive an input signal having a first time interval;

A trigger signal input unit for receiving a trigger signal;

An enable (EN) generator for generating an enable (EN) signal in response to the input signal and the trigger signal;

A set signal input unit for receiving a set signal; And

The serial delay gate circuit unit receives the enable signal and propagates the set signal.

Time-to-digital converter.
The method of claim 16,

The series delay gate circuit part

A plurality of delay gate cells connected in series to accumulate the time information according to an input signal having the first time interval

Time-to-digital converter.
The method of claim 17,

The series delay gate circuit part

And varying a phase according to the operations of the plurality of delay gate cells to accumulate time information, and output a limit signal when the accumulated time information reaches a limit value.
The method of claim 18,

The time register is

And an output unit configured to output first time information corresponding to the first time interval based on a difference value between the threshold time at which the limit signal is output and the trigger time.
Receiving an input pulse signal;

Storing first time information in a serial delay gate circuit of a time register as the input pulse signal is applied;

Generating a first output code from the first time information;

Generating a time reference corresponding to the first output code and generating a residual signal corresponding to the time reference; And

Amplifying and outputting the residual signal.
The method of claim 20,

Applying the output residual signal to a next stage;

And the input pulse signal is a residual signal output from a previous stage circuit.
The method of claim 21,

And said residual signal is obtained based on a difference value between a threshold time and a trigger time of said series delay gate circuit designated by said time reference.