WO2015174613A1 - Registre d'horloge, dispositif de calcul de temps l'utilisant, procédé de calcul de temps, dispositif de conversion temps-numérique et procédé de conversion temps-numérique - Google Patents

Registre d'horloge, dispositif de calcul de temps l'utilisant, procédé de calcul de temps, dispositif de conversion temps-numérique et procédé de conversion temps-numérique Download PDF

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Publication number
WO2015174613A1
WO2015174613A1 PCT/KR2015/001185 KR2015001185W WO2015174613A1 WO 2015174613 A1 WO2015174613 A1 WO 2015174613A1 KR 2015001185 W KR2015001185 W KR 2015001185W WO 2015174613 A1 WO2015174613 A1 WO 2015174613A1
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Prior art keywords
time
signal
output
delay gate
gate circuit
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PCT/KR2015/001185
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English (en)
Korean (ko)
Inventor
조성환
김광석
유원식
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한국과학기술원
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Priority claimed from KR1020140057479A external-priority patent/KR101614883B1/ko
Priority claimed from KR1020140078642A external-priority patent/KR101666275B1/ko
Application filed by 한국과학기술원 filed Critical 한국과학기술원
Publication of WO2015174613A1 publication Critical patent/WO2015174613A1/fr

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an ac
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
    • G07C1/00—Registering, indicating or recording the time of events or elapsed time, e.g. time-recorders for work people

Definitions

  • the present invention relates to a time computing device, and more particularly, to a time computing device, a time computing method, a time-to-digital conversion device and a time-to-digital conversion method that can perform a time operation using a time register. It is about.
  • Time-based signal processing is a technique that processes a signal by converting an input signal into an interval of two edges or a width of a single pulse on the time axis. Therefore, the transition time of the digital signal is reduced, and the time-based resolution is increased. Accordingly, there is a need for a study on performance improvement for time calculation, as well as a study on a circuit operating on a time basis, for subtracting or adding a clock synchronized pulse time.
  • the present invention is to solve the above-described problems, it is easy to add or subtract time information using a time register (Time Register), time register and time computing device using the same to improve the time resolution and processing speed, It is an object of the present invention to provide a time calculation method, a time-digital conversion device and a time-digital conversion method.
  • Time-to-digital converter for solving the above problems is a pulse generator for generating an input pulse signal; And a pipe stage unit configured to receive the input pulse signal and perform a time delay operation for each stage according to a pipeline, wherein the pipe stage unit includes a plurality of stage circuits, and the stage circuits accumulate time information. And a time register using a delay gate circuit.
  • a method of converting a time-digital signal into an input pulse signal Storing first time information on a serial delay gate cycle of a time register as the input pulse signal is applied; Generating a first output code from the first time information; Generating a time reference corresponding to the first output code and generating a residual signal corresponding to the time reference; And amplifying and outputting the residual signal.
  • Time register for solving the above problems is an IN signal input unit for receiving an input signal having a first time interval; A trigger signal input unit for receiving a trigger signal; An enable (EN) generator for generating an enable (EN) signal in response to the input signal and the trigger signal; A set signal input unit for receiving a set signal; And a serial delay gate circuit unit receiving the enable signal and propagating the SET signal.
  • a time adder sequentially receives a first pulse signal having a first time interval Ta and a second pulse signal having a second time interval Tb.
  • a first series delay gate circuit unit accumulating time information of the first pulse signal and the second pulse signal sequentially input, and at the first limit time at which the limit signal is output from the first series delay gate circuit unit.
  • a first time register configured to output a first output signal obtained by subtracting the accumulated time of the first time interval Ta and the second time interval Tb; And a second series delay gate circuit unit, having a time interval of Ta + Tb accumulated in time information of the first output signal and subtracted from a second limit time at which a limit signal is output from the second series delay gate circuit unit. And a second time register for outputting two output signals.
  • a time subtractor for solving the above problems, the first input unit for receiving a first pulse signal having a first time interval Ta; A first series delay gate circuit unit, and accumulating time information Ta of the first pulse signal and subtracting the accumulated Ta time from a first limit time at which the limit signal of the first series delay gate circuit unit is output; A first time register for outputting an output signal; A second input unit sequentially receiving a second pulse signal having a second time interval Tb and the first output signal; And a second series delay gate circuit portion, wherein Ta is accumulated in time information of the first output signal and the second pulse signal and subtracted from a second limit time at which a limit signal of the second series delay gate circuit portion is output. And a second time register for outputting a second output signal having a time interval of Tb.
  • time register capable of clock synchronous storage, addition or subtraction of time information.
  • the present invention provides a time register that can improve the time resolution and processing speed by using a serial delay gate circuit in the time register implementation, time-digital conversion device, time-digital conversion using the same A method, a time calculating device, and a time calculating method can be provided. Accordingly, the design of the time-digital conversion device, the time-digital conversion method, the time calculation device, and the time calculation method is facilitated.
  • time register is not only various time-to-digital converters, but also circuits such as an All Digital Phase Locked Loop (ADPLL) circuit or a Digital Phase Locked Loop. Applicable to
  • FIG. 1 is a block diagram illustrating a time register according to an exemplary embodiment of the present invention
  • FIG. 2 is an implementation circuit and an input / output timing diagram of a time register according to an exemplary embodiment of the present invention.
  • FIG. 3 is a diagram schematically illustrating input and output timing of the time register 100 according to an exemplary embodiment of the present invention.
  • FIG. 4 illustrates the configuration and input / output configuration of the subtractor 200 and the adder 300 using the time register 100 according to an embodiment of the present invention.
  • FIG 5 illustrates a series gate cell according to an embodiment of the present invention.
  • 6 and 7 illustrate comparison result data when the tilted delay gate cell 151B is applied to the time register 100 according to an exemplary embodiment of the present invention.
  • FIG. 8 is a block diagram illustrating a time-to-digital converter 400 according to an embodiment of the present invention.
  • FIG. 9 is a block diagram and a circuit diagram of the stage circuit 420 constituting the pipe stage unit 420A according to the embodiment of the present invention.
  • FIG. 11 illustrates a detailed configuration of the line-delay time-digital converter 430 according to an embodiment of the present invention.
  • FIG. 12 illustrates a transfer curve curve of the time-to-digital converter 400 according to an embodiment of the present invention.
  • FIG. 13 and 14 illustrate flowcharts and circuit operations for explaining a time-to-digital conversion method for each stage of the time-to-digital converter 400 according to an exemplary embodiment of the present invention.
  • 15 is a timing diagram illustrating the overall operation of the time-to-digital converter 400 according to an embodiment of the present invention.
  • 16 is a diagram for describing an example in which the time-to-digital converter 400 is implemented as a chip according to an exemplary embodiment.
  • 17 to 21 are experimental result data of the time-digital converter 400 according to an embodiment of the present invention.
  • components expressed as means for performing the functions described in the detailed description include all types of software including, for example, a combination of circuit elements or firmware / microcode, etc. that perform the functions. It is intended to include all methods of performing a function which are combined with appropriate circuitry for executing the software to perform the function.
  • the invention, as defined by these claims, is equivalent to what is understood from this specification, as any means capable of providing such functionality, as the functionality provided by the various enumerated means are combined, and in any manner required by the claims. It should be understood that.
  • FIG. 1 is a block diagram illustrating a time register according to an exemplary embodiment of the present invention
  • FIG. 2 is an implementation circuit and an input / output timing diagram of a time register according to an exemplary embodiment of the present invention.
  • the time register 100 includes an IN signal input unit 110, a trigger signal input unit 120, a SET signal input unit 130, and an An EN signal generator 140 and a series delay gate circuit 150.
  • the time register 100 includes a series delay gate circuit 150, and the series delay gate circuit 150 includes a plurality of delay gate cells or delays connected in series. And gated delay line circuits. Each delay gate cell connected in series may serve to accumulate time information according to an enable (EN) signal input. According to the enable (EN) signal input to the delay gate cells, the stepwise transfer of the SET signal input to the SET signal input unit 130 may be controlled.
  • EN enable
  • the IN signal input unit 110 receives an input pulse of the time register 100 and transmits the input pulse to the enable signal generator.
  • the IN signal input unit may receive an input pulse having an input time T_IN from the outside in response to the time information to be stored in the time register.
  • the in signal input unit 110 may add a predetermined offset time to the input signal T_IN in order to prepare for the case where a narrow time pulse is input. .
  • the trigger signal input unit 120 receives the trigger pulse and delivers the trigger pulse to the enable (EN) signal generator.
  • the trigger signal may include a clock signal, for example.
  • the trigger signal input to the trigger signal input unit 120 may be a pulse signal having a predetermined length and may correspond to a clock signal for storing time information of the time register 100.
  • the enable signal generator 140 generates an enable signal according to the trigger pulse and the in signal, and applies the enabled signal to the series delay gate circuit 150.
  • a SET signal for driving the time register may be input, and the SET signal may be applied as an input signal of the serial delay gate circuit 150.
  • the driving of the time register 100 may be started according to the SET signal input.
  • the IN signal is HIGH and the SET signal is HIGH, the SET signal is applied to the series delay gate circuit 150 to propagate through each delay gate circuit. PROPAGATION).
  • the IN signal is turned low, propagation of the SET signal may be stopped.
  • the trigger signal is input again while the IN signal is LOW, the propagation of the SET signal may be resumed.
  • the propagation of the SET signal may be terminated by outputting the limit signal FULL SIGNAL from the serial delay gate circuit 150.
  • the limit signal is output, the SET signal is changed to LOW and the time register 100 may be initialized.
  • the series delay gate circuit 150 may be configured as a circuit in which a plurality of delay gates are connected in series as shown in FIG. 2A.
  • the series delay gate circuit 150 As an enable (EN) signal is applied to the delay gates, the series delay gate circuit 150 accumulates time information by sequentially operating the plurality of delay gate cells, and limits the time information when the accumulated time information reaches a limit value. Signals (FULL SIGNAL, FS) can be output.
  • the series delay gate circuit 150 may use a phase delay.
  • FIG. 2B in each delay gate cell (or delay gate line), an input pulse is generated according to an enable signal generated by a trigger signal and an IN signal. It can be seen that the phase (pulse) increases constantly in response to the time interval of.
  • T_FS time at which the limit signal of the series delay gate circuit 150 is output due to the accumulation of input pulses
  • ⁇ _Q the phase delayed by each delay gate cell
  • T_FS N * ⁇ _Q until the limit signal is output.
  • the phase of the series delay gate circuit 150 may be maintained at 2 ⁇ _Q until the phase is increased again by the trigger signal.
  • T_FS may be a predetermined time according to the characteristics and the number of delay gate cells. In this case, by simply increasing the number of delay gate cells, the time limit accumulated in the series delay gate circuit 150 may be easily increased.
  • the output unit 160 may output the output T_OUT of the time register 100 configured as described above.
  • the output unit 160 may acquire and output time information stored in the time register 100 by calculating T_OUT as described above.
  • the output unit 160 may be configured to output T_IN itself by continuously inputting T_OUT to the time register 100 again.
  • FIG. 3 is a diagram schematically illustrating input and output timing of the time register 100 according to an exemplary embodiment of the present invention.
  • an output time of the time register 100 is input.
  • the information T_OUT may be calculated by T_FS-T_IN.
  • the time register 100 may maintain time information as long as T_IN time until the trigger signal of the next clock is received.
  • the time register 100 may delay the time only from the accumulated time T_IN to the limit time T_FS and output the limit signal FS. Therefore, the time information stored in the time register 100 may be output as a value obtained by subtracting T_IN from T_FS.
  • the adder 200 or the subtractor 300 using the time register 100 may be implemented.
  • FIG. 4 illustrates a configuration of an adder 200 and a subtractor 300 and an input / output configuration using the time register 100 according to an exemplary embodiment of the present invention.
  • the adder 200 includes an input unit 210, a first time register 100A, a second time register 100B, and an output unit 220. .
  • the input unit 210 may sequentially receive the first pulse signal having the first time interval Ta and the second pulse signal having the second time interval Tb and transmit the same to the first time register 100A.
  • the first time register 100A accumulates time information of the first pulse signal and the second pulse signal sequentially input, and subtracts the accumulated time of Ta and Tb from the limit time T_FS at which the limit signal is output.
  • the first output signal T_FS-(Ta + Tb) is output and transferred to the second time register 100B.
  • the second time register 100B accumulates the time information of the transmitted first output signal, and outputs the second output signal T_FS-(T_FS-(Ta + Tb)) subtracted from the limit time. )
  • a second output signal having a Ta + Tb time interval to which the first time interval Ta of the first pulse signal sequentially input and the second time interval Tb of the second pulse signal are added may be output to the outside. Therefore, the adder 200 according to an exemplary embodiment of the present invention may be implemented by cascading the first time register 100A and the second time register 100B dependently.
  • the subtractor 300 when the subtractor 300 is described, the subtractor 300 according to the embodiment of the present invention includes a first input unit 310, a first time register 100C, a second input unit 320, and a second time register 100D. ) And an output unit 330.
  • the first input unit 310 may receive the first pulse signal having the first time interval Ta and transmit it to the first time register 100C.
  • the first time register 100A accumulates the input first pulse signal time information Ta, and calculates the first output signal T_FS-Ta obtained by subtracting the accumulated time Ta from the limit time T_FS at which the limit signal is output. The output is transmitted to the second input unit 320.
  • the second input unit 320 sequentially receives the second pulse signal having the second time interval Tb and the first output signal, and transfers the second output signal to the second time register 100B.
  • the second input unit 320 may include at least one logic gate.
  • the second time register 100B accumulates the time information of the transmitted first output signal and the second pulse signal, and subtracts the second output signal T_FS-(T_FS-Ta) + Tb)) Output to the output.
  • a second output signal having a Ta ⁇ Tb time interval obtained by subtracting the first time interval Ta of the first pulse signal sequentially input and the second time interval Tb of the second pulse signal may be output to the outside. Therefore, the adder 200 according to an exemplary embodiment of the present invention may be implemented by cascading the first time register 100A and the second time register 100B dependently.
  • the time register 100 may be easily implemented in the form of the adder 200 and the subtractor 300 by the characteristic thereof, and may easily store time information and synchronize clocks. do.
  • FIG 5 illustrates a direct gate cell according to an embodiment of the present invention.
  • the series delay gate circuit 150 of the time register 100 may be composed of delay gate cells connected in series, as shown in Figure 5 (a) a general delay gate cell 151A It can be implemented in the form of.
  • an error may occur due to a gating imbalance.
  • a phase error may occur when propagation of a SET signal is not properly performed in a period where time information is maintained.
  • the delay gate cell is implemented in the form of a skewed gated delay cell (151B) for preventing an error as shown in FIG. Can be.
  • the tilted delay gate cell 151B uses a plurality of input units (IN [n-5], IN [n-3], IN [n-1], etc.) to which the SET signal is input to propagate the SET signal.
  • the control unit may include an output unit configured to transfer a plurality of input SET signals through a plurality of paths and to output the next delay gate cell 151B. According to such a configuration, it is possible to reduce time error of the input / output signal.
  • 6 and 7 illustrate comparison result data when the tilted delay gate cell 151B is applied to the time register 100 according to an exemplary embodiment of the present invention.
  • FIG. 6 is a graph showing an error time versus an input time, and the maximum error time difference in the case of applying a tilted delay gate cell 151B for transmitting a signal through multiple paths (B) is a general delay gate. It can be seen that the cell 151A is much smaller than the case (A).
  • Figure 7 is a Monte Carlo simulation results according to various environmental conditions
  • the time error of the time register 100 according to an embodiment of the present invention is a change in all environmental conditions (voltage 1,2V + -0.05V, temperature 0 ⁇ 80 degrees, etc.), it can be seen that it is only within about 0.5 picoseconds (ps).
  • TDC time-to-digital converter
  • FIG. 8 is a block diagram illustrating a time-to-digital converter 400 according to an embodiment of the present invention.
  • the time-to-digital converter 400 may include a pulse generator 410, a pipe stage unit 420A, a line delay time-digital converter 430, and a digital error report. Government 440.
  • the pulse generator 410 receives a start signal and a stop signal, generates a pulse signal Tin according to the time difference, and transmits the generated pulse signal Tin to the pipe stage unit 420A.
  • the pulse generator 410 may apply an operation clock signal for driving the time-to-digital converter 400 to each component.
  • the pulse generator 410 may add an offset time to the time difference between the start signal and the stop signal and transmit the offset time to the pipe stage unit 420A.
  • the start signal applied to the pulse generator 410 may be periodically applied from an external system, and the pulse generator 410 extracts the operation clock signal into an external clock from the periodically applied start signal, and the external clock thereof. Can be transmitted as a clock signal of each component.
  • the pulse generator 410 may generate and apply an operation clock signal to each component.
  • the time delay operation for each stage performed in each pipe may be performed by a plurality of stage circuits 420 included in the pipe stage unit 420.
  • the conversion speed may be improved according to the pipeline operation performed on each pipe. A detailed circuit configuration for this purpose will be described later with reference to FIG. 9.
  • the time information output from the pipe stage unit 420A may be transmitted to the digital error correction unit 440 and the line delay time-digital converter 430.
  • the line delay time-digital converter 430 may serve as a final stage of time delay, and may function as a conventional pipe-line analog-to-digital converter (ADC) circuit.
  • ADC pipe-line analog-to-digital converter
  • the digital error correction unit 440 receives the output signal of the pipe stage unit 420A and the output of the line delay time-digital converter 430 to correct for offset errors that may occur in a general time-digital converter. do.
  • the digital error correction unit 440 may output the corrected time-digital conversion signal to the outside.
  • FIG. 9 is a block diagram and a circuit diagram of the stage circuit 420 constituting the pipe stage unit 420A according to the embodiment of the present invention.
  • the stage circuit 420 may include a time register 100, a first time-digital converter 421, a first digital-time converter 422, and a time.
  • An amplifier 423 is included.
  • the configuration of the time register 100 is as described above, receives an input pulse, maintains and stores time information as the first time Tin according to the time of the received input pulse, and stores the stored first time as the first time. Output to the time-digital converter 421.
  • the first time-digital converter 421 quantizes the first time, generates a first output code, and outputs the first output code to the first digital-time converter 422.
  • the first digital-time converter 422 generates a time reference Tref according to the first output code, and transmits the time reference Tref to the time amplifier 423.
  • the time amplifier 423 amplifies the residual signal Tout and delivers the residual signal to the next stage circuit 420.
  • a signal of 4 * (Tin ⁇ Dout * Tref) may be output according to the first time and the residual signal.
  • the digital error correction unit 440 collects a time signal of a first bit, for example, 2.5 bits, from each stage circuit 420 to perform error correction processing, and converts time information of a second bit, for example, 9 bits. You can generate and output
  • the stage circuit 420 may include a first time-digital converter 421 connected to a plurality of delay gate cells included in the time register 100. And the first digital-time converter 422 may be implemented.
  • the first time-digital converter 421 may improve the operation speed and directly output the first output code by setting the quantization level.
  • the first digital-time converter 422 may receive the first output code signal to generate a time reference (Tref) signal.
  • the first digital-time converter 422 may include a plurality of switches connected to the delay line to determine the reference level.
  • the time register 100, the first time-digital converter 421, and the first digital time converter 422 described above may be used to reduce the complexity and the complexity of the integrated circuit.
  • Each core may be connected using one delay line.
  • the time amplifier 423 sequentially delays, merges and outputs a plurality of received pulse signals. It may be implemented in the form of a time amplifier (PT-TA). 10 illustrates an example implemented as a pulse train time amplifier for connecting, amplifying and outputting four first time input Tins. To this end, the time amplifier 423 may include at least three time delay circuits and an OR gate circuit for delayed signal merging. This allows accurate gain settings without calibration and broadens the linear range of the input signal.
  • the dynamic range DR of the time-to-digital converter 400 is the entire time-digital converter 421. Can be extended according to the number.
  • the temporal resolution can be defined by dividing the quantization level of each first time-digital converter 421 by the gain sum of the entire time-digital converter, it is easily scalable.
  • FIG. 11 illustrates a detailed configuration of the line-delay time-digital converter 430 according to an embodiment of the present invention, and includes a time register 100 and a part of the time register 100 for performing a last stage role.
  • the second time-digital converter 431 may be connected to the plurality of delay gate cells. Operation of the other components except for the last flip flop FF is similar to that of the stage circuit 420 and thus will be omitted.
  • FIG. 12 illustrates a transfer curve curve of the time-to-digital converter 400 according to an embodiment of the present invention.
  • the transfer curve curve may have an inverted shape as the output of the time register 100 according to an embodiment of the present invention is a compensative value. Therefore, the output between the even and odd stages may be inverted for each stage. Accordingly, the digital error compensator 440 may perform a process of correcting different inverted outputs for each stage as a normal output.
  • FIG. 13 and 14 illustrate flowcharts and circuit operations for explaining a time-to-digital conversion method for each stage of the time-to-digital converter 400 according to an exemplary embodiment of the present invention.
  • the first input signal may include four pulses having a phase having a first magnitude.
  • the four pulses may be the signal delivered in the previous stage, and the first magnitude may be 1.1 ⁇ _Q, for example.
  • 4.4 ⁇ _Q whose phase is increased by four times the first magnitude may be stored and maintained in the time register 100 as time information corresponding to the first time.
  • the time-digital converter 400 generates a first output code based on the stored first time (S120).
  • the first time-digital converter 421 may generate and output an output code '001' corresponding to the first time according to a setting.
  • the time-digital converter 400 generates a time reference corresponding to the first output code and outputs a residual signal (S130).
  • the first time-digital converter 421 may select an appropriate node for acquiring the limit signal FULL SIGNAL of the time register 100 based on the first output code. have.
  • the first time-digital converter 421 may acquire a time reference including a trigger time and a limit signal generation time.
  • the first time-digital converter 421 may obtain a residual signal corresponding to a time difference from the trigger time to the limit signal acquisition time.
  • the first time-digital converter 421 may obtain a residual signal such as 1.6 ⁇ _Q by calculating 6 ⁇ _Q-4.4 ⁇ _Q.
  • the time-digital converter 400 amplifies and outputs the residual signal (S140).
  • the time amplifier 423 may sequentially delay, merge, and output a plurality of received pulse signals in a pulse train form.
  • FIG. 14D illustrates an example in which four residual signal inputs 1.6 ⁇ _Q are connected and output.
  • 15 is a timing diagram illustrating the overall operation of the time-to-digital converter 400 according to an embodiment of the present invention.
  • the time-to-digital converter 400 when the SET signal is applied to the time-to-digital converter 400, the time-to-digital converter 400 is initialized. Then, the input signal is received as a tin pulse, and the clock signal is received as each pulse is received. As received, the pipeline stage stage circuits 420 may operate, and the finally amplified residual signal may be output in synchronization with a clock.
  • 16 is a diagram for describing an example in which the time-to-digital converter 400 is implemented as a chip according to an exemplary embodiment.
  • time-to-digital converter 400 when the time-to-digital converter 400 is implemented on a chip, a clock generator, a first stage circuit, a second stage circuit, a third stage circuit, and a flash time-digital converter circuit may be used. It can be implemented on a small chip including and a logic circuit. According to this configuration, the time-to-digital converter 400 may be implemented on a standardized CMOS chip, and may reduce power consumption.
  • 17 to 21 are experimental result data of the time-digital converter 400 according to an embodiment of the present invention.
  • the dynamic range of the input signal recorded 578 ps, which is the time register 100 using the delay-line and delay gate cells as described above. It can be achieved by the operation of. In addition, the operation speed and time resolution were also improved, recording 250MSamples / s and 1.12ps. As a result of the figure-of-merit analysis, the power consumption is reduced and the performance of the time-to-digital converter is improved. In addition, it can be confirmed that the digital error compensation has a strong accuracy against noise and errors.
  • the above-described method according to various embodiments of the present disclosure may be implemented in program code and provided to each server or devices in a state of being stored in various non-transitory computer readable mediums.
  • the non-transitory readable medium refers to a medium that stores data semi-permanently and is readable by a device, not a medium storing data for a short time such as a register, a cache, a memory, and the like.
  • a non-transitory readable medium such as a CD, a DVD, a hard disk, a Blu-ray disk, a USB, a memory card, a ROM, or the like.

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Abstract

Un registre d'horloge selon un mode de réalisation de la présente invention comporte : une unité d'entrée de signal d'entrée (IN) pour recevoir un signal d'entrée ayant un premier intervalle de temps ; une unité d'entrée de signal de déclenchement pour recevoir un signal de déclenchement ; une unité de génération de validation (EN) pour générer un signal EN en réponse au signal d'entrée et au signal de déclenchement ; une unité d'entrée de signal de mise à 1 (SET) pour recevoir un signal de mise à 1 ; une unité de circuit de porte à retard série pour recevoir le signal EN et transmettre le signal SET. Par conséquent, la présente invention peut concevoir un registre d'horloge pouvant stocker des informations de temps et une addition ou soustraction synchrone d'horloge. En outre, la présente invention peut fournir un registre d'horloge qui peut améliorer la résolution temporelle conjointement avec une durée de traitement en utilisant un circuit de porte à retard série dans la mise en œuvre du registre d'horloge, ainsi qu'un dispositif de conversion temps-numérique, un procédé de conversion temps-numérique, un dispositif de calcul de temps et un procédé de calcul de temps.
PCT/KR2015/001185 2014-05-13 2015-02-05 Registre d'horloge, dispositif de calcul de temps l'utilisant, procédé de calcul de temps, dispositif de conversion temps-numérique et procédé de conversion temps-numérique WO2015174613A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020140057479A KR101614883B1 (ko) 2014-05-13 2014-05-13 타임 레지스터, 이를 이용한 시간 연산 장치 및 시간 연산 방법
KR10-2014-0057479 2014-05-13
KR1020140078642A KR101666275B1 (ko) 2014-06-26 2014-06-26 타임 레지스터를 이용한 시간-디지털 변환 장치 및 그 방법
KR10-2014-0078642 2014-06-26

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JPH08184686A (ja) * 1994-12-28 1996-07-16 Nec Ic Microcomput Syst Ltd パルス間隔計測装置
JP2005030957A (ja) * 2003-07-08 2005-02-03 Matsushita Electric Ind Co Ltd タイマ装置
KR20050071689A (ko) * 2002-11-14 2005-07-07 화이어 스톰, 아이엔씨. 전원 변환기 회로 및 방법
KR20120107041A (ko) * 2010-09-30 2012-09-28 애플 인크. 백엔드 프로세싱 로직을 가지는 이미지 신호 프로세서를 이용하여 이미지 데이터를 프로세싱하기 위한 시스템 및 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08184686A (ja) * 1994-12-28 1996-07-16 Nec Ic Microcomput Syst Ltd パルス間隔計測装置
KR20050071689A (ko) * 2002-11-14 2005-07-07 화이어 스톰, 아이엔씨. 전원 변환기 회로 및 방법
JP2005030957A (ja) * 2003-07-08 2005-02-03 Matsushita Electric Ind Co Ltd タイマ装置
KR20120107041A (ko) * 2010-09-30 2012-09-28 애플 인크. 백엔드 프로세싱 로직을 가지는 이미지 신호 프로세서를 이용하여 이미지 데이터를 프로세싱하기 위한 시스템 및 방법

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