KR101666275B1 - A time-digital conversion appratus using a time register and a time-digital conversion method for using the time register - Google Patents

Abstract

Another time-to-digital converter according to an embodiment of the present invention includes: a pulse generator for generating an input pulse signal; And a pipeline stage for receiving the input pulse signal and performing a time delay calculation for each stage according to the pipeline; Wherein the pipeline stage portion includes a plurality of stage circuits, and the stage circuit includes a time register for storing time information by operation of a serial delay gate circuit portion for accumulating time information.

Description

TECHNICAL FIELD [0001] The present invention relates to a time-to-digital conversion apparatus using a time register and a time-digital conversion apparatus using the time register.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-to-digital conversion apparatus and a method thereof, and more particularly, to a time-to-digital conversion apparatus and a method thereof capable of performing a time operation using a time register.

Recently, as the semiconductor process technology is developed, the supply voltage of the circuit is lowered and the characteristics of the MOSFET, which is an individual device, are deteriorating. Therefore, the circuit design using the existing voltage-based signal processing method becomes increasingly difficult. Recently, much research has been conducted on time-based signal processing as an alternative circuit design method. Time-based signal processing is a technique for processing signals by converting an input signal to an interval of two edges or a width of a single pulse on the time axis. Therefore, the transition time of the digital signal is reduced, and the time-based resolution is increased. Therefore, there is a need for a study on the performance improvement of the time operation for the subtraction or addition of the clock synchronized pulse time in addition to the study on the circuit operating in the time base.

However, complicated processing is required to measure the time of pulses and to provide subtraction or addition of time information. It is very difficult to design a time arithmetic device having a high resolution and a high processing speed that can be used in a practical industrial environment.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a time register which can easily add or subtract time information by using a time register, Time calculation method.

According to an aspect of the present invention, there is provided a time-to-digital converter including: a pulse generator for generating an input pulse signal; And a pipeline stage unit for receiving the input pulse signal and performing a time delay calculation for each stage according to a pipeline, wherein the pipeline stage unit includes a plurality of stage circuits, And a time register using a delay gate circuit.

According to an aspect of the present invention, there is provided a time-to-digital conversion method comprising: receiving an input pulse signal; Storing the first time information in the serial delay gate circuit of the time register as the input pulse signal is applied; Generating a first output code from the first time information; Generating a time reference corresponding to the first output code and generating a residual signal corresponding to the time reference; And amplifying and outputting the residual signal.

According to an aspect of the present invention, there is provided a time register including: an IN signal input unit receiving an input signal having a first time interval; A trigger signal input unit for receiving a trigger signal; An enable (EN) generator for generating an enable (EN) signal in response to the input signal and the trigger signal; A SET signal input unit for receiving a set signal; And a serial delay gate circuit portion receiving the enable signal and propagating the SET signal.

According to the embodiment of the present invention, it is possible to design a time register capable of storing, adding, or subtracting time information clockwise synchronously.

In addition, the present invention provides a time register that can improve time resolution and processing speed by using a serial delay gate circuit in a time register implementation, and provides a time arithmetic unit and a time arithmetic method using the same . This facilitates the design of the time calculation device and the time calculation method.

In addition, the time register according to the embodiment of the present invention may include various digital circuits such as an all digital phase locked loop (ADPLL) circuit or a digital phase locked loop . ≪ / RTI >

FIG. 1 is a block diagram showing a time register according to an embodiment of the present invention, and FIG. 2 is a timing diagram and an input / output timing diagram of a time register according to an embodiment of the present invention.
3 is a diagram for schematically explaining the input / output timing of the time register 100 according to the embodiment of the present invention.
4 shows the configuration and input / output configuration of the subtractor 200 and the adder 300 using the time register 100 according to the embodiment of the present invention.
5 illustrates a series gate cell according to an embodiment of the present invention.
FIGS. 6 and 7 are diagrams for explaining comparison result data when the delay gate cell 151B inclined to the time register 100 according to the embodiment of the present invention is applied.
FIG. 8 is a block diagram illustrating a time-to-digital converter 400 according to an embodiment of the present invention.
Fig. 9 shows a block diagram and a circuit diagram of a stage circuit 420 constituting a pipe stage portion 420A according to the embodiment of the present invention.
Fig. 10 shows a detailed configuration of the time amplifier 423.
11 shows a detailed configuration of the line-delay time-digital converter 430 according to the embodiment of the present invention.
12 shows a transfer curve curve of the time-to-digital converter 400 according to an embodiment of the present invention.
FIG. 13 shows a flowchart and a circuit operation for explaining a time-to-digital conversion method for each stage of the time-to-digital converter 400 according to an embodiment of the present invention.
FIG. 14 is a timing chart for explaining the overall operation of the time-to-digital converter 400 according to the embodiment of the present invention.
FIG. 15 is a diagram for explaining an example in which the time-to-digital converter 400 according to the embodiment of the present invention is implemented as a chip.
16 to 20 are experimental result data of the time-to-digital converter 400 according to the embodiment of the present invention.

The following merely illustrates the principles of the invention. Thus, those skilled in the art will be able to devise various apparatuses which, although not explicitly described or shown herein, embody the principles of the invention and are included in the concept and scope of the invention. Furthermore, all of the conditional terms and embodiments listed herein are, in principle, only intended for the purpose of enabling understanding of the concepts of the present invention, and are not to be construed as limited to such specifically recited embodiments and conditions do.

It is also to be understood that the detailed description, as well as the principles, aspects and embodiments of the invention, as well as specific embodiments thereof, are intended to cover structural and functional equivalents thereof. It is also to be understood that such equivalents include all elements contemplated to perform the same function irrespective of the currently known equivalents as well as the equivalents to be developed in the future, i.e., the structure.

Thus, for example, it should be understood that the block diagrams herein represent conceptual views of exemplary circuits embodying the principles of the invention. Similarly, all flowcharts, state transition diagrams, pseudo code, and the like are representative of various processes that may be substantially represented on a computer-readable medium and executed by a computer or processor, whether or not the computer or processor is explicitly shown .

The functions of the various elements shown in the figures, including the functional blocks depicted in the processor or similar concept, may be provided by use of dedicated hardware as well as hardware capable of executing software in connection with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, a single shared processor, or a plurality of individual processors, some of which may be shared.

Also, the explicit use of terms such as processor, control, or similar concepts should not be interpreted exclusively as hardware capable of running software, and may be used without limitation as a digital signal processor (DSP) (ROM), random access memory (RAM), and non-volatile memory. Other hardware may also be included.

In the claims hereof, the elements represented as means for performing the functions described in the detailed description include all types of software including, for example, a combination of circuit elements performing the function or firmware / microcode etc. , And is coupled with appropriate circuitry to execute the software to perform the function. It is to be understood that the invention defined by the appended claims is not to be construed as encompassing any means capable of providing such functionality, as the functions provided by the various listed means are combined and combined with the manner in which the claims require .

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, in which: There will be. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a time register according to an embodiment of the present invention, and FIG. 2 is a timing diagram and an input / output timing diagram of a time register according to an embodiment of the present invention.

1 and 2, a time register 100 according to an embodiment of the present invention includes an IN signal input unit 110, a trigger signal input unit 120, a SET signal input unit 130, An enable (EN) signal generator 140 and a series delay gate circuit 150.

The time register 100 according to an embodiment of the present invention includes a serial delay gate circuit 150, as shown in FIG. 1, and the serial delay gate circuit 150 includes a plurality of delay gate cells or a delay Gated delay cell (or gated delay line) circuits. Each of the delay gate cells connected in series can accumulate time information according to an enable (EN) signal input. The stepwise transmission of the SET signal input to the SET signal input unit 130 can be controlled according to an enable (EN) signal input to the delay gate cells.

More specifically, the IN signal input unit 110 receives the input pulse of the time register 100 and transmits the input pulse to the enable (EN) signal generator. The IN signal input unit can receive an input pulse having a predetermined length of time T_IN from the outside corresponding to the time information to be stored in the time register. According to the embodiment of the present invention, the IN signal input unit 110 may preferably add a predetermined offset time to the input signal T_IN in order to prepare for a case where a narrow time pulse is input .

Also, the trigger signal input unit 120 receives the trigger pulse and transmits it to the enable (EN) signal generator. The trigger signal may include, for example, a clock signal. The trigger signal input to the trigger signal input unit 120 may be a pulse signal having a predetermined length and may correspond to a clock signal for storing time information of the time register 100.

The enable (EN) signal generator 140 generates an enable (EN) signal in accordance with the trigger pulse and the IN signal, and applies the generated enable signal to the serial delay gate circuit 150.

A SET signal for driving the time register may be input to the SET signal input unit 130 and a SET signal may be applied to the input signal of the serial delay gate circuit 150. [ The driving of the time register 100 can be started according to the SET signal input. If the IN signal is high and the SET signal is high then the SET signal is applied to the serial delay gate circuit 150 and propagates through each delay gate circuit PROPAGATION. However, when the IN signal changes to LOW, the propagation of the SET signal can be stopped. However, if the IN signal is LOW and the trigger signal is input again, the propagation of the SET signal can be resumed. The propagation of the SET signal may be terminated by outputting the limit signal (FULL SIGNAL) at the serial delay gate circuit 150. According to one embodiment, when the limit signal is output, the SET signal is changed to LOW, and the time register 100 can be initialized.

On the other hand, the series delay gate circuit 150 may be composed of a circuit in which a plurality of delay gates are serially connected as shown in FIG. 2 (a).

As the enable (EN) signal is applied to the delay gates, the serial delay gate circuit 150 sequentially operates the plurality of delay gate cells to accumulate time information, and when the accumulated time information reaches the threshold value, Signal (FULL SIGNAL, FS).

And, to accumulate time information, the serial delay gate circuit 150 may utilize a phase delay. 2 (b), in each delay gate cell (or delay gate line), an input pulse is generated in accordance with an enable (EN) signal generated by a trigger signal and an IN signal, It can be seen that the pulse increases constantly in correspondence with the time interval of FIG. As shown in FIG. 2 (a), assuming that the time at which the limit signal of the serial delay gate circuit 150 is output when the input pulses are accumulated is T_FS, if the phase delayed by each delay gate cell is τ_Q, The time T_FS = N * τ_Q until the limit signal is output can be obtained.

2 (b), when the IN signal and the trigger signal are applied with 0 and the enable signal is not applied to the serial delay gate circuit 150, Quot; value. ≪ / RTI > If the enable (EN) signal up to phase 2τ_Q is applied and then stopped, the phase of the serial delay gate circuit 150 can be maintained at 2τ_Q until the phase again increases by the trigger signal. The time information storage function of the time register 100 can be implemented by using the increase and the maintaining timing of the phase delay.

Further, by the phase delay and the holding of the series delay gate circuit 150, the time T_FS at which the limit signal is output can be controlled. Here, T_FS may be a predetermined time depending on the characteristics and the number of delayed gate cells. In this case, by simply increasing the number of delay gate cells, there is an advantage that the time limit accumulated in the serial delay gate circuit 150 can be easily increased.

On the other hand, the output T_OUT of the time register 100 having such a configuration can be outputted from the output unit 160. Here, the output T_OUT can be designated as T_OUT = T_FS - T_IN when the input waveform (IN) signal is expressed as T_IN. The output unit 160 can obtain and output time information stored in the time register 100 by calculating T_OUT as described above. Also, the output unit 160 may be configured such that T_OUT is continuously input to the time register 100 again to output T_IN itself.

3 is a diagram for schematically explaining the input / output timing of the time register 100 according to the embodiment of the present invention.

3 (a), when a signal having a time interval of T_IN is input to the IN input of the time register 100 according to the embodiment of the present invention, the output time of the time register 100 The information T_OUT can be computed as T_FS - T_IN.

This can be explained in more detail through the timing diagram of Fig. 3 (b). The time register 100 according to the embodiment of the present invention can maintain the time information by the T_IN time until the next clock trigger signal is received when the input pulse having the T_IN time interval is received. When the trigger signal is received, the time register 100 may delay the time from the accumulated time T_IN to the limit time T_FS and output the limit signal FS. Therefore, the time information stored in the time register 100 can be output as a value obtained by subtracting T_IN from T_FS.

Meanwhile, the adder 200 or the subtracter 300 using the time register 100 according to the embodiment of the present invention can be implemented.

4 shows the configuration and input / output configuration of the adder 200 and the subtracter 300 using the time register 100 according to the embodiment of the present invention.

The adder 200 according to the embodiment of the present invention includes an input unit 210, a first time register 100A, a second time register 100B, and an output unit 220 .

The input unit 210 may sequentially receive the first pulse signal having the first time interval Ta and the second pulse signal having the second time interval Tb and may transmit the first pulse signal and the second pulse signal to the first time register 100A.

The first time register 100A accumulates the time information of the first pulse signal and the second pulse signal which are sequentially input, and outputs the result of subtracting the accumulated time of Ta and Tb at the limit time T_FS at which the limit signal is outputted 1 output signal T_FS - (Ta + Tb) to the second time register 100B.

Then, the second time register 100B accumulates the time information of the transmitted first output signal and subtracts the second output signal T_FS - (T_FS - (Ta + Tb) .

Accordingly, the second output signal having the Ta + Tb time interval in which the first time interval Ta of the sequentially input first pulse signal and the second time interval Tb of the second pulse signal are added can be output to the outside. Therefore, the adder 200 according to the embodiment of the present invention can be implemented by connecting the first time register 100A and the second time register 100B in a dependent manner.

The subtractor 300 according to the embodiment of the present invention includes a first input unit 310, a first time register 100C, a second input unit 320, a second time register 100D And an output unit 330.

The first input unit 310 may receive the first pulse signal having the first time interval Ta and transmit the first pulse signal to the first time register 100C.

The first time register 100A accumulates the inputted first pulse signal time information Ta and outputs a first output signal T_FS-Ta obtained by subtracting the accumulated time of Ta from the threshold time T_FS at which the limit signal is output And transmits it to the second input unit 320.

The second input unit 320 sequentially receives the second pulse signal having the second time interval Tb and the first output signal and transmits the second pulse signal to the second time register 100B. To this end, the second input unit 320 may include at least one logic gate.

Then, the second time register 100B accumulates the time information of the transmitted first output signal and the second pulse signal, and subtracts the second output signal T_FS - (T_FS - Ta + Tb))) To the output unit.

Accordingly, the second output signal having the Ta - Tb time interval obtained by subtracting the first time interval Ta of the sequentially input first pulse signal and the second time interval Tb of the second pulse signal may be output to the outside. Therefore, the adder 200 according to the embodiment of the present invention can be implemented by connecting the first time register 100A and the second time register 100B in a dependent manner.

As described above, the time register 100 according to the embodiment of the present invention can be easily implemented in the form of the adder 200 and the subtractor 300 according to the characteristics thereof, and can easily store time information and synchronize clocks do.

5 shows a prior art gate cell according to an embodiment of the present invention.

Meanwhile, the serial delay gate circuit 150 of the time register 100 according to the embodiment of the present invention may be composed of a series-connected delay gate cell, and as shown in FIG. 5 (a), a general delay gate cell 151A, As shown in FIG.

However, when a plurality of delay gate cells 151A are connected, an error may occur due to gating unbalance. In particular, when the SET signal is not propagated properly in the interval in which the time information is maintained, a phase error may occur.

In order to reduce such an error, according to the embodiment of the present invention, the delay gate cell is implemented in the form of a skewed gated delay cell (151B), which is a slope for preventing an error as shown in FIG. 5B . The inclined delay gate cell 151B includes a plurality of input units IN [n-5], IN [n-3], IN [n-1], and the like for inputting a SET signal And may have an output unit for transmitting a plurality of input SET signals through a plurality of paths and outputting the signals to the next delay gate cell 151B. According to this configuration, it is possible to reduce a time error and the like of the input / output signal.

FIGS. 6 and 7 are diagrams for explaining comparison result data when the delay gate cell 151B inclined to the time register 100 according to the embodiment of the present invention is applied.

Referring to FIG. 6, FIG. 6 is a graph showing an error time versus input time. In the case where a delay gate cell 151B having a tilt for transmitting a signal through a plurality of paths is applied, the maximum error time difference in FIG. It can be confirmed that it is much smaller than (A) when the cell 151A is applied.

7 is a Monte-Carlo simulation result according to various environmental conditions. The time error of the time register 100 according to an embodiment of the present invention is a time error of all environmental conditions (voltage 1,2V + -0.05 V, 80 < 0 > C, etc.) of about 0.5 picoseconds (ps).

Meanwhile, a time-to-digital converter (TDC) using the time register 100 according to the embodiment of the present invention can be implemented.

FIG. 8 is a block diagram illustrating a time-to-digital converter 400 according to an embodiment of the present invention.

8, a time-to-digital converter 400 according to an embodiment of the present invention includes a pulse generating unit 410, a pipe stage unit 420A, a line delay time-to-digital converting unit 430, (440).

8, the pulse generating unit 410 receives a start signal and a stop signal, generates a pulse signal Tin according to the time difference, and transmits the pulse signal Tin to the pipe stage unit 420A . In addition, the pulse generator 410 may apply an operation clock signal for driving the time-to-digital converter 400 to each component. In order to correct the error, the pulse generating unit 410 may add the offset time to the time difference between the start signal and the stop signal, and may transmit the offset time to the pipe stage unit 420A.

The start signal applied to the pulse generator 410 may be periodically applied from the external system. The pulse generator 410 extracts the operation clock signal from the start signal periodically applied to the external clock, To the clock signal of each component.

However, if the start signal is not periodic, the pulse generator 410 may itself generate an operation clock signal and apply it to each component.

The time-to-digital converter 400 according to the embodiment of the present invention includes a pipe stage unit 420A for performing a pipeline-based time delay calculation on the plurality of stage circuits 420 based on the applied pulse signal Tin can do. For example, when a four-stage time delay operation is performed in three pipelines as shown in FIG. 8, 4 * 4 * 4 = 64 stage operations can be performed. Thus, it is possible to improve time resolution of the time-to-digital converter 400 without using a general Vernier delay line circuit or the like.

On the other hand, the stage-by-stage time delay calculation performed in each pipe can be performed by the plurality of stage circuits 420 included in the pipe stage portion 420. Also, the conversion speed can be improved according to the pipeline operation performed in each of such pipes. A concrete circuit configuration for this purpose will be described later with reference to FIG.

The time information output from the pipe stage unit 420A may be transmitted to the digital error correction unit 440 and the line delay time-to-digital conversion unit 430. [

The line delay time-to-digital converter 430 may serve as the last stage of the time delay and may serve as a conventional pipeline analog-to-digital converter (ADC) circuit.

The digital error correcting unit 440 receives the output signal of the pipe stage unit 420A and the output of the line delay time-to-digital converting unit 430 and performs correction for an offset error that may occur in a general time-to-digital converter do. The digital error correcting unit 440 can output the corrected time-to-digital converted signal to the outside.

Fig. 9 shows a block diagram and a circuit diagram of a stage circuit 420 constituting a pipe stage portion 420A according to the embodiment of the present invention.

9, the stage circuit 420 according to the embodiment of the present invention includes a time register 100, a first time-to-digital conversion section 421, a first digital-to-time conversion section 422, And an amplifier 423.

The configuration of the time register 100 is as described above. The time register 100 receives input pulses, and maintains and stores time information at a first time (Tin) according to the time of the received input pulses. To the time-to-digital converter 421.

The first time-to-digital conversion unit 421 quantizes the first time, generates a first output code, and outputs the first output code to the first digital-to-time conversion unit 422.

Then, the first digital-to-time conversion unit 422 generates a time reference Tref according to the first output code, and transmits the time reference Tref to the time amplifier 423.

The time amplifier 423 amplifies the residual signal Tout and transfers the residual signal to the next stage circuit 420.

When the stage circuit 420 shown in FIG. 9 is performed four times, the output of the stage circuit 420 may be a signal of 4 * (Tin - Dout * Tref) according to the first time and the residual signal. The digital error correction unit 440 performs error correction processing by collecting a first bit, for example, a 2.5-bit time signal from each stage circuit 420, and outputs a second bit, for example, Can be generated and output.

9, the stage circuit 420 according to the embodiment of the present invention includes a first time-to-digital converter 421 connected to a plurality of delay gate cells included in the time register 100, And a first digital-to-time conversion unit 422. The first digital-to-

Accordingly, the first time-to-digital conversion unit 421 can improve its operation speed and can directly output the first output code by setting the quantization level.

In addition, the first digital-to-time converter 422 may receive the first output code signal and generate a time reference (Tref) signal. The first digital-to-time converter 422 may include a plurality of switches coupled to the delay line to determine a reference level.

9, the time register 100, the first time-to-digital conversion section 421, and the first digital time conversion section 422 are provided for the purpose of implementing the integrated circuit and reducing the complexity, Each core can be connected using one delay line.

10 shows a detailed configuration of the time amplifier 423. As shown in FIG. 10, the time amplifier 423 sequentially delays a plurality of received pulse signals, and outputs a pulse train Time amplifier (PT-TA). In FIG. 10, a description is given of an example implemented by a pulse train time amplifier that connects and amplifies and outputs four first time inputs Tin. To this end, the time amplifier 423 may include at least three time delay circuits and an OR gate circuit for delayed signal merging. Therefore, accurate gain setting is possible without calibration and linear range of input signal can be widened.

According to the pipeline configuration of the stage circuit 420, the dynamic range DR of the time-to-digital converter 400 according to the embodiment of the present invention can be obtained by the entire first time- It can be expanded according to the number. Also, the temporal resolution can be defined by dividing the quantization level of each first time-to-digital conversion unit 421 by the sum of the gains of the first time-to-digital conversion unit 421, and thus can be easily extended.

11 shows a detailed configuration of the line-delay time-to-digital converter 430 according to the embodiment of the present invention. The time register 100 and the part of the time register 100, And a second time-to-digital conversion unit 431 connected to the plurality of delay gate cells. The operation of the other components except the last flip-flop FF is similar to that of the stage circuit 420, so that it is omitted.

12 shows a transfer curve curve of the time-to-digital converter 400 according to an embodiment of the present invention.

As shown in FIG. 12, the transmission curve curve may have a form in which the output of the time register 100 according to the embodiment of the present invention is inverted according to a competing value. Thus, the output between the even-numbered stage and the odd-numbered stage can be inverted for each stage. Accordingly, the digital error compensator 440 can perform a process of correcting different inversion outputs to the normal output for each of the stages.

FIG. 13 shows a flowchart and a circuit operation for explaining a time-to-digital conversion method for each stage of the time-to-digital converter 400 according to an embodiment of the present invention.

13, when the input signal is first applied (S100), the time-to-digital converter 400 applies an enable (EN) signal to the time register and stores a first time corresponding to the input signal (S110) .

As shown in FIG. 13 (a), the input signal initially input may include four pulses having a phase of a first magnitude. The four pulses may be the signal transmitted in the previous stage, and the first magnitude may be, for example, 1.1? Q. Then, in the time register 100, 4.4τ_Q whose phase is increased by 4 times the first magnitude can be stored and held as time information corresponding to the first time.

Then, the time-to-digital converter 400 generates a first output code based on the stored first time (S120).

As shown in FIG. 13 (b), the first time-to-digital conversion unit 421 can generate and output an output code '001' corresponding to the first time according to the setting.

The time-to-digital converter 400 generates a time reference corresponding to the first output code and outputs a residual signal (S130).

As shown in Fig. 13C, the first time-to-digital conversion section 421 can select an appropriate node to acquire the limit signal (FULL SIGNAL) of the time register 100 based on the first output code have. As the trigger signal is received by the time register 100, the first time-to-digital converter 421 may obtain a time reference including a trigger time and a time at which the limit signal is generated. The first time-to-digital converter 421 can acquire a residual signal corresponding to a time difference from the trigger time to the limit signal acquisition time. For example, the first time-to-digital converter 421 may calculate a residual signal such as 1.6τ_Q by calculating 6τ_Q - 4.4τ_Q.

Then, the time-to-digital converter 400 amplifies and outputs the residual signal (S140).

As shown in FIG. 13 (d), the time amplifier 423 can sequentially delay and combine the received plurality of pulse signals and output them in the form of a pulse train. FIG. 13 (d) shows an example in which four residual signal inputs 1.6τ_Qs are connected and output.

FIG. 14 is a timing chart for explaining the overall operation of the time-to-digital converter 400 according to the embodiment of the present invention.

14, when the SET signal is applied to the time-to-digital converter 400, the time-to-digital converter 400 is initialized. Then, the input signal is received as a Tin pulse, and as each pulse is received, As it is received, the pipeline-specific stage circuits 420 operate, and finally the amplified residual signal can be output in synchronization with the clock.

FIG. 15 is a diagram for explaining an example in which the time-to-digital converter 400 according to the embodiment of the present invention is implemented as a chip.

15, when a time-to-digital converter 400 according to an embodiment of the present invention is implemented on a chip, a clock generator, a first stage circuit, a second stage circuit, a third stage circuit, and a flash time- And a logic circuit. With such a configuration, the time-to-digital converter 400 can be implemented on a standardized CMOS chip, and power consumption can be reduced.

16 to 20 are experimental result data of the time-to-digital converter 400 according to the embodiment of the present invention.

16 to 20, the dynamic range of the input signal is recorded at 578 ps, which is the time register 100 using delay-line and delay gate cells as described above, Lt; / RTI > In addition, it was confirmed that the operating speed and the time resolution were improved to 250 MS samples / s and 1.12 ps. As a result of the figure-of-merit analysis, the power consumption is reduced and the performance of the time-to-digital converter is improved. Also, it can be confirmed that digital error compensation has strong accuracy against noise and error.

Meanwhile, the method according to various embodiments of the present invention described above may be implemented in program code and provided to each server or devices in a state stored in various non-transitory computer readable media.

A non-transitory readable medium is a medium that stores data for a short period of time, such as a register, cache, memory, etc., but semi-permanently stores data and is readable by the apparatus. In particular, the various applications or programs described above may be stored on non-volatile readable media such as CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM,

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It should be understood that various modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.

Claims (11)

A pulse generator for generating an input pulse signal; And
A pipeline stage for receiving the input pulse signal and performing a time delay calculation for each stage according to the pipeline; Lt; / RTI >
Wherein the pipe stage portion includes a plurality of stage circuits,
The stage circuit
And a time register for storing time information by operation of a serial delay gate circuit unit for accumulating time information,
The time register
An IN signal input unit receiving an input signal having a first time interval;
A trigger signal input unit for receiving a trigger signal;
An enable (EN) generator for generating an enable (EN) signal in response to the input signal and the trigger signal;
A SET signal input unit for receiving a set signal; And
And the serial delay gate circuit portion receiving the enable signal and propagating the SET signal,
Wherein the serial delay gate circuit includes a plurality of input units to which the SET signal is input and a plurality of input units to which the SET signal is input to accumulate time information according to a phase delay according to propagation of the SET signal, And a plurality of delay gate cells, each of which is implemented in the form of a skewed gated delay cell, the output of which transmits a SET signal to a next delay gate cell through a plurality of paths,
Time-to-digital converter. The method according to claim 1,
The stage circuit
A first time-to-digital converter for quantizing the input first time to generate a first output code;
A first digital-to-time converter for generating a time reference including a trigger time according to the first output code and acquiring a residual signal; And
And a time amplifying unit for amplifying and outputting the residual signal
Time-to-digital converter. 3. The method of claim 2,
Wherein the first time-to-digital converter and the first digital-to-time converter are connected to a part of the serial delay gate circuit of the time register and are arranged on the same delay-line. . delete delete The method according to claim 1,
The series delay gate circuit portion
The time-to-digital converter outputs the limit signal when the accumulated time information reaches the threshold value by varying the phase according to the operation of the plurality of delay gate cells. The method according to claim 6,
The time register
And an output unit outputting first time information corresponding to the first time period based on a difference value between a limit time and a trigger time at which the limit signal is output. Receiving an input pulse signal;
Storing the first time information in the serial delay gate circuit portion of the time register as the input pulse signal is applied;
Generating a first output code from the first time information;
Generating a time reference corresponding to the first output code and generating a residual signal corresponding to the time reference; And
And amplifying and outputting the residual signal,
The time register
An IN signal input unit receiving an input signal having a first time interval;
A trigger signal input unit for receiving a trigger signal;
An enable (EN) generator for generating an enable (EN) signal in response to the input signal and the trigger signal;
A SET signal input unit for receiving a set signal; And
And the serial delay gate circuit portion receiving the enable signal and propagating the SET signal,
Wherein the serial delay gate circuit includes a plurality of input units to which the SET signal is input and a plurality of input units to which the SET signal is input to accumulate time information according to a phase delay according to propagation of the SET signal, And a plurality of delay gate cells which are implemented in the form of a skewed gated delay cell in which an output unit for transmitting a SET signal through a plurality of paths and outputting the signal to a next delay gate cell is included
Time-to-digital conversion method. 9. The method of claim 8,
Further comprising the step of applying the output residual signal to a next stage,
Wherein the input pulse signal is a residual signal output from a previous stage circuit. 10. The method of claim 9,
Wherein the serial delay gate circuit unit accumulates time information by varying a phase according to an operation of the plurality of delay gate cells and outputs a limit signal when the accumulated time information reaches a threshold value,
Wherein said residual signal applied to said next stage corresponds to a time difference from a trigger time to said limit signal acquisition time. A recording medium on which a program for causing a computer to execute the method recorded in any one of claims 8 to 10 is recorded.

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