WO2015172505A1 - 一种离子注入的方法 - Google Patents

一种离子注入的方法 Download PDF

Info

Publication number
WO2015172505A1
WO2015172505A1 PCT/CN2014/088373 CN2014088373W WO2015172505A1 WO 2015172505 A1 WO2015172505 A1 WO 2015172505A1 CN 2014088373 W CN2014088373 W CN 2014088373W WO 2015172505 A1 WO2015172505 A1 WO 2015172505A1
Authority
WO
WIPO (PCT)
Prior art keywords
graphite
mask layer
film
ion implantation
substrate
Prior art date
Application number
PCT/CN2014/088373
Other languages
English (en)
French (fr)
Inventor
田慧
皇甫鲁江
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2015172505A1 publication Critical patent/WO2015172505A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks

Definitions

  • Embodiments of the present disclosure relate to a method of ion implantation.
  • CMOS Complementary Metal Oxide Semiconductor
  • the ion implantation process generally utilizes a photoresist as a mask layer for ion implantation, covers a specified area, and ion-implants the exposed semiconductor layer.
  • the implanted ions have a certain energy
  • the photoresist is subjected to continuous collision of ions to accumulate energy, thereby generating a thermal effect, resulting in a photoresist mask.
  • the layer carbonization is hard and deformed, and at the same time, the mask layer remains due to the difficulty in removing the photoresist.
  • Embodiments of the present disclosure provide a method of ion implantation that can effectively block bombardment of high-energy ions while avoiding the problem of hardening deformation of a mask layer caused by thermal effects, and is easy to remove, thereby improving product yield.
  • a method of ion implantation comprises: preparing a graphite film on a surface of a substrate; forming a graphite mask layer by one patterning process; and performing ion implantation using the graphite mask layer as a mask.
  • the forming a graphite mask layer by one patterning process includes: coating a photoresist on the graphite film, forming a photoresist pattern layer by a photolithography process;
  • the photoresist pattern layer is a mask, and the graphite film is dry etched to form a graphite mask a layer; removing the photoresist pattern layer.
  • the method of removing the photoresist pattern layer includes wet stripping.
  • the preparing a graphite film on a surface of a substrate includes: depositing the graphite film on a surface of a semiconductor substrate; wherein the semiconductor substrate comprises a conductor/insulating substrate and is located at the conductor/ A semiconductor film that insulates a surface of the substrate; or the semiconductor substrate is a semiconductor substrate.
  • the method prior to preparing the graphite film on the surface of the substrate, the method further includes: cleaning the semiconductor substrate.
  • the method further includes: removing the graphite mask layer, and cleaning the semiconductor substrate after ion implantation .
  • the removing the graphite mask layer includes: removing the graphite mask layer by dry etching; wherein the dry etching comprises plasma etching.
  • the plasma etch comprises an oxygen plasma etch.
  • the preparing the graphite film on the surface of the substrate comprises: preparing the graphite film on the surface of the substrate by magnetron sputtering or plasma enhanced chemical vapor deposition.
  • the graphite film has a thickness of 10 to 150 nm.
  • An embodiment of the present disclosure provides a method of ion implantation, comprising: preparing a graphite film on a surface of a substrate; forming a graphite mask layer by one patterning process; and performing ion implantation using the graphite mask layer as a mask. Based on this, when the graphite mask layer is used as a mask of the ion implantation process, since the graphite film has sufficient hardness and good thermal conductivity, the graphite mask layer can be effectively used in the process of ion implantation.
  • FIG. 1 is a flow chart 1 of an ion implantation process according to an embodiment of the present disclosure
  • FIGS. 2(a) to 2(c) are schematic diagrams showing a process of ion implantation according to an embodiment of the present disclosure
  • FIG. 3 is a flow chart of a method for preparing a graphite mask layer according to an embodiment of the present disclosure
  • FIGS. 4(a) to 4(c) are schematic views showing a process of forming a graphite mask layer according to an embodiment of the present disclosure
  • FIG. 5 is a second flow chart of an ion implantation process according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a method of ion implantation, as shown in FIG. 1, the method includes:
  • a graphite film 200 is prepared on the surface of the substrate 10.
  • the graphite film 200 can be prepared by a physical vapor deposition method or a chemical vapor deposition method.
  • the method for preparing the graphite film is not limited as long as a uniform and flat film layer can be formed.
  • the graphite mask layer 20 is formed by one patterning process.
  • the graphite mask layer 20 refers to a graphite film which actually has a mask function.
  • the graphite mask layer 20 can serve as a barrier layer for ion implantation; on the basis of this, the graphite mask layer 20 can have a suitable thickness in order to ensure a good masking effect.
  • the thickness of the graphite mask layer 20 is related to the depth of ion implantation and energy.
  • ion implantation is performed using the graphite mask layer 20 as a mask.
  • the graphite film is selected as the material of the mask layer, which is mainly based on the graphite film having sufficient hardness and good thermal conductivity, so as to effectively block the bombardment of ions, and at the same time, can quickly dissipate heat without causing hardening deformation of the mask layer. The problem.
  • the graphite mask layer 20 when the graphite mask layer 20 is applied to an ion implantation process, its ion blocking effect can be effectively exerted, but this does not mean that the graphite mask layer 20 is not suitable for other processes;
  • the graphite mask layer 20 can be applied to any process that requires a mask as needed, and the application of the graphite mask layer 20 is not limited in the embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a method of ion implantation, comprising: preparing a graphite film 200 on a surface of a substrate 10; forming a graphite mask layer 20 by a patterning process; and performing ion implantation using the graphite mask layer 20 as a mask.
  • a method of ion implantation comprising: preparing a graphite film 200 on a surface of a substrate 10; forming a graphite mask layer 20 by a patterning process; and performing ion implantation using the graphite mask layer 20 as a mask.
  • the bombardment of ions can simultaneously and quickly and efficiently dissipate heat and heat, thereby avoiding the problem of hardening deformation of the mask layer caused by thermal effect, improving the yield of the product; further, in the subsequent process, the graphite mask layer 20 is easy to remove, A mask layer residue will appear.
  • the preparing the graphite film 200 on the surface of the substrate 10 may include preparing the graphite film 200 by magnetron sputtering or plasma enhanced chemical vapor deposition.
  • the preparation process parameters of the graphite film 200 may depend on its microstructure and actual thickness.
  • the film prepared by magnetron sputtering has the advantages of strong film-based bonding force, high film purity, good compactness and good film formation uniformity; film prepared by plasma enhanced chemical vapor deposition has film thickness and composition uniformity. Good, good film density, strong adhesion of the film layer.
  • the graphite film 200 may have a thickness of 10 to 150 nm.
  • the graphite film 200 When the thickness of the film layer is between 10 and 150 nm, the graphite film 200 has good adhesion and does not cause film peeling due to stress concentration; further, after the graphite mask layer 20 is formed The graphite mask layer 20 has a strong blocking ability and can effectively block the bombardment of high-energy ions; further, in the subsequent process, the graphite mask layer 20 is easily removed without leaving a mask layer.
  • the forming the graphite mask layer 20 by one patterning process may include:
  • a photoresist 300 is coated on the graphite film 200, and a photoresist pattern layer 30 is formed by one photolithography process.
  • the photolithography process may specifically include pre-baking, exposure, development, post-baking; after exposure and display After the shadowing, the photoresist 300 forms a photoresist remaining portion and a photoresist removing portion, that is, the photoresist pattern layer 30 described above.
  • the photoresist 300 may be a positive photoresist or a negative photoresist; depending on the type of the photoresist 300, the type of developer required may also be different.
  • the graphite film 200 is dry etched using the photoresist pattern layer 30 as a mask to form a graphite mask layer 20.
  • the photoresist pattern layer 30 can serve as a mask for preparing the graphite mask layer 20, and the corresponding graphite film 200 of the photoresist removal portion is exposed and exposed, and the photoresist is partially covered. The graphite film 200 is not affected.
  • dry etching is employed in etching the graphite film 200.
  • dry etching has good anisotropy, that is, only vertical etching, no lateral undercut; thus ensuring that the etched film can accurately replicate the geometry exactly matching the mask layer.
  • Graphics. Dry etching can greatly improve the anisotropy of etching, accurately control the shape of the sidewall profile, and have good etching uniformity.
  • the photoresist pattern layer 30 is removed as shown in FIG. 2(b).
  • the photoresist pattern layer 30 may be removed; wherein the photoresist pattern layer 30 may be removed by wet stripping or ashing.
  • both wet stripping and ashing treatment can be used to remove the photoresist; however, the ashing treatment may cause some damage to the photoresist-coated film layer, and the ashing treatment is more suitable for removing carbonized hair.
  • Hard photoresist since the photoresist pattern layer 30 has not been subjected to ion implantation, there is no problem that the carbonization hardens, and therefore, in one embodiment according to the present disclosure, the photoresist pattern layer 30 is removed by wet stripping. .
  • the wet stripping may be performed by a photoresist-specific stripping solution, and the components thereof mainly include nitric acid, sulfuric acid, oxalic acid, and the like.
  • the graphite mask layer 20 can be prepared.
  • the use of the graphite mask layer 20 as a mask for ion implantation can effectively block the bombardment of ions.
  • the preparing the graphite film 200 on the surface of the substrate 10 may include depositing the graphite film 200 on a surface of the semiconductor substrate 10; wherein the semiconductor substrate 10 may include a conductor/insulating substrate a substrate and a semiconductor film on a surface of the conductor/insulating substrate; or the semiconductor substrate 10 may be a semiconductor substrate.
  • the conductor substrate 10 When the semiconductor substrate 10 includes a conductor/insulating substrate and a semiconductor film on the conductor/insulating substrate, the conductor substrate may be a metal substrate, and the insulating substrate may be a glass substrate
  • the semiconductor film may be a polysilicon film, a tantalum film, or a silicon germanium film, or a gallium arsenide film.
  • the semiconductor substrate 10 When the semiconductor substrate 10 is a semiconductor substrate, the semiconductor substrate may be a silicon substrate, a germanium substrate, or a silicon germanium substrate, or a gallium arsenide substrate or the like.
  • the semiconductor substrate 10 is cleaned before the graphite film 200 is prepared on the surface of the substrate 10.
  • the semiconductor substrate 10 may be cleaned in an ultrasonic cleaning apparatus using an organic solvent such as ethanol or acetone.
  • an organic solvent such as ethanol or acetone.
  • the graphite mask layer 20 after ion implantation using the graphite mask layer 20 as a mask, the graphite mask layer 20 should also be removed, and the ion-implanted semiconductor substrate 10 should be cleaned.
  • the graphite mask layer 20 has correspondingly a small amount of implanted ions in the interior thereof, and these implanted ions are present in the lattice gap of the graphite crystal. That is, these implanted ions are present in the graphite mask layer 20 with the graphite crystal as a carrier. Therefore, when the graphite mask layer 20 is removed, the implanted ions lose the attached carrier while being removed.
  • the method of removing the graphite mask layer 20 may be dry etching or wet etching.
  • the dry etching reaction product is a volatile gas, and the dry etching can remove the graphite mask layer 20 more efficiently without causing the mask layer to remain; in addition, the dry etching has a relatively high reaction. Efficiency, which can effectively save process time.
  • the graphite mask layer 20 is removed by dry etching; wherein the dry etching may include plasma etching.
  • the principle of the plasma etching is as follows: in a low pressure environment, the reaction gas is ionized and forms a plasma under excitation of radio frequency power; the plasma is composed of electrons and charged ions, and The gas in the chamber, under the impact of electrons, can absorb energy and form a large number of active reactive groups in addition to being converted into ions; the active reactive group chemically reacts with the surface of the substance to be etched and forms a volatile The reaction product; the reaction product is detached from the surface of the etched material and is withdrawn from the cavity by a vacuum system.
  • the plasma etching may include any etching capable of generating an oxygen plasma; the graphite mask layer may be formed by chemically reacting the oxygen plasma with the graphite and generating a volatile substance. 20 removed.
  • the graphite mask layer 20 is removed using an oxygen plasma etch in one embodiment in accordance with the present disclosure.
  • the oxygen plasma can be formed by ionization directly from oxygen, and thus has a relatively high purity and does not form by-products.
  • the semiconductor substrate 10 after ion implantation needs to be cleaned.
  • the semiconductor substrate 10 can be cleaned by a combination of an organic cleaning liquid, ultraviolet light, and deionized water.
  • the ion implantation process is fully described below by way of example. As shown in FIG. 5, the ion implantation process may include the following steps.
  • the semiconductor substrate 10 is cleaned.
  • the semiconductor substrate 10 includes a glass substrate and polysilicon located on the surface of the glass substrate.
  • a graphite film 200 is prepared on the surface of the semiconductor substrate 10.
  • the graphite film 200 has a thickness of 10 to 150 nm.
  • the graphite film 200 can be deposited here by magnetron sputtering.
  • a photoresist 300 is coated on the graphite film 200, and a photoresist pattern layer 30 is formed by one photolithography process.
  • the photoresist 300 is a positive photoresist.
  • the photoresist 300 may be subjected to exposure and development to form a photoresist removing portion and a photoresist remaining portion, that is, the above-described photoresist pattern layer 30.
  • the graphite film 200 is etched using the photoresist pattern layer 30 as a mask to form a graphite mask layer 20.
  • the graphite film 200 can be etched by an oxygen plasma.
  • the photoresist pattern layer 30 is removed as shown in FIG. 2(b).
  • the photoresist stripping liquid can be wet-peeled by a special stripping solution for photoresist; wherein the stripping liquid for the photoresist mainly includes nitric acid, sulfuric acid and oxalic acid.
  • ion implantation is performed using the graphite mask layer 20 as a mask.
  • the graphite mask layer 20 is removed, and the semiconductor substrate 10 after ion implantation is washed.
  • the graphite mask layer 20 can be removed here by oxygen plasma etching.
  • the ion implantation process can be completed.
  • the ion implantation using the graphite mask layer 20 as a mask can not only effectively block the bombardment of ions, but also quickly and efficiently conduct heat dissipation, thereby avoiding hardening deformation of the mask layer caused by thermal effects, and the graphite masking
  • the film layer 20 is easily removed by plasma etching, and there is no mask layer remaining, so that the yield of the product can be greatly improved.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

一种离子注入的方法，涉及半导体技术领域，可有效地阻挡离子的轰击，同时避免热效应引起的掩膜层硬化变形的问题，且易于去除，从而提高产品的良率；所述方法包括：在基板表面制备石墨薄膜，通过一次构图工艺形成石墨掩膜层，以所述石墨掩膜层为掩膜进行离子注入；用于离子注入工艺。

Description

一种离子注入的方法 技术领域
本公开的实施例涉及一种离子注入的方法。
背景技术
随着半导体技术的飞速发展，为了达到更快的运算速度、更大的数据存储量以及更多的功能，半导体器件正向更高的元件密度和集成度的方向发展。半导体器件的特征尺寸已经达到深亚微米级甚至更小，尤其对于纳米级的CMOS(Complementary Metal Oxide Semiconductor，互补型金属氧化物半导体)器件，晶体管的密度在大幅度提高，因此离子注入工艺也变得越来越为重要；与此同时，大剂量的离子注入也成为一种趋势。
在发明人已知的技术中，离子注入工艺通常利用光刻胶作为离子注入的掩模层，对指定的区域进行覆盖阻挡，并对暴露出来的半导体层进行离子注入。在此过程中，由于注入的离子具有一定的能量，当这些高能离子注入到光刻胶层时，光刻胶便会受到离子的连续撞击而累积能量，从而产生热效应，导致光刻胶掩模层碳化发硬并且变形，同时还会造成光刻胶难以去除而产生的掩模层残留现象。
发明内容
本公开的实施例提供一种离子注入的方法，可有效地阻挡高能离子的轰击，同时避免热效应引起的掩膜层硬化变形的问题，且易于去除，从而提高产品的良率。
本公开的实施例采用如下技术方案：
一种离子注入的方法，包括：在基板表面制备石墨薄膜；通过一次构图工艺形成石墨掩膜层；以所述石墨掩膜层为掩膜进行离子注入。
在根据本公开的一个实施例中，所述通过一次构图工艺形成石墨掩膜层包括：在所述石墨薄膜上涂覆光刻胶，通过一次光刻工艺形成光刻胶图案层；以所述光刻胶图案层为掩膜，对所述石墨薄膜进行干法刻蚀，形成石墨掩膜 层；去除所述光刻胶图案层。
在根据本公开的一个实施例中，所述光刻胶图案层的去除方法包括湿法剥离。
在根据本公开的一个实施例中，所述在基板表面制备石墨薄膜包括：在半导体基板的表面沉积所述石墨薄膜；其中，所述半导体基板包括导体/绝缘衬底基板和位于所述导体/绝缘衬底基板表面的半导体薄膜；或者，所述半导体基板为半导体衬底基板。
在根据本公开的一个实施例中，在基板表面制备石墨薄膜之前，所述方法还包括：清洗所述半导体基板。
在根据本公开的一个实施例中，在以所述石墨掩膜层为掩膜进行离子注入之后，所述方法还包括：去除所述石墨掩膜层，并清洗离子注入后的所述半导体基板。
在根据本公开的一个实施例中，所述去除所述石墨掩膜层包括：采用干法刻蚀去除所述石墨掩膜层；其中，所述干法刻蚀包括等离子体刻蚀。
在根据本公开的一个实施例中，所述等离子体刻蚀包括氧气等离子体刻蚀。
在根据本公开的一个实施例中，所述在基板表面制备石墨薄膜包括：通过磁控溅射或者等离子体增强化学气相沉积法在基板表面制备所述石墨薄膜。
在根据本公开的一个实施例中，所述石墨薄膜的厚度为10-150nm。
本公开实施例提供一种离子注入的方法，包括：在基板表面制备石墨薄膜；通过一次构图工艺形成石墨掩膜层；以所述石墨掩膜层为掩膜进行离子注入。基于此，当采用所述石墨掩膜层作为离子注入工艺的掩膜时，由于石墨薄膜具有足够的硬度和良好的导热性能，因此在离子注入的过程中，所述石墨掩膜层可以有效地阻挡离子的轰击，同时能够快速高效地导热散热，从而避免热效应引起的掩膜层硬化变形的问题，提高产品的良率；此外，在后续的工艺中，所述石墨掩膜层易于去除，不会出现掩膜层残留。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本公开实施例提供的一种离子注入的工艺流程图一；
图2(a)至2(c)为本公开实施例提供的一种离子注入的过程示意图；
图3为本公开实施例提供的一种石墨掩膜层的制备方法流程图；
图4(a)至4(c)为本公开实施例提供的一种石墨掩膜层的形成过程示意图；
图5为本公开实施例提供的一种离子注入的工艺流程图二。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开的实施例提供一种离子注入的方法，如图1所示，所述方法包括：
如图2(a)所示，在基板10表面制备石墨薄膜200。
所述石墨薄膜200可以通过物理气相沉积法或者化学气相沉积法进行制备。
本公开实施例对于所述石墨薄膜的制备方法不做限定，只要可以形成均匀平坦的膜层即可。
如图2(b)所示，通过一次构图工艺形成石墨掩膜层20。
在本文中，所述石墨掩膜层20是指实际上具有掩膜作用的石墨薄膜。
在离子注入的过程中，所述石墨掩膜层20可以作为离子注入的阻挡层；在此基础上，为了保证良好的掩膜效果，所述石墨掩膜层20可以具有适当的厚度。所述石墨掩膜层20的厚度与离子注入的深度以及能量有关。
如图2(c)所示，以所述石墨掩膜层20为掩膜进行离子注入。
这里选用所述石墨薄膜作为掩膜层的材料，主要是基于石墨薄膜具有足够的硬度和良好的导热性能，从而可以有效的阻挡离子的轰击，同时能够快速散热，不会引起掩膜层硬化变形的问题。
需要说明的是，当所述石墨掩膜层20应用于离子注入工艺时，可以有效的发挥其离子阻挡作用，但这并不代表所述石墨掩膜层20不适用于其它工艺；也就是说，所述石墨掩膜层20可以根据需要应用于任何需要进行掩膜的工艺过程，本公开实施例对于所述石墨掩膜层20的应用场合不做限定。
本公开实施例提供一种离子注入的方法，包括：在基板10表面制备石墨薄膜200；通过一次构图工艺形成石墨掩膜层20；以所述石墨掩膜层20为掩膜进行离子注入。当采用所述石墨掩膜层20作为离子注入工艺的掩膜时，由于石墨薄膜具有足够的硬度和良好的导热性能，因此在离子注入的过程中，所述石墨掩膜层20可以有效地阻挡离子的轰击，同时能够快速高效的导热散热，从而避免热效应引起的掩膜层硬化变形的问题，提高产品的良率；此外，在后续的工艺中，所述石墨掩膜层20易于去除，不会出现掩膜层残留。
在根据本公开的一个实施例中，所述在基板10表面制备石墨薄膜200可以包括：通过磁控溅射或者等离子体增强化学气相沉积法制备所述石墨薄膜200。
所述石墨薄膜200的制备工艺参数可以根据其微观结构和实际厚度而定。
通过磁控溅射法制备的薄膜具有膜基结合力强、薄膜纯度高、致密性好以及成膜均匀性好等优点；通过等离子体增强化学气相沉积法制备的薄膜具有膜厚和成分均匀性好、薄膜致密性好、膜层的附着力强等优点。
在根据本公开的一个实施例中，所述石墨薄膜200的厚度可以为10-150nm。
当膜层的厚度在10-150nm之间时，所述石墨薄膜200具有良好的附着力，且不会发生应力集中引起的膜层脱落现象；进一步的，在形成所述石墨掩膜层20之后，所述石墨掩膜层20具有较强的阻挡能力，可以有效地阻挡高能离子的轰击；此外，在后续工艺中，所述石墨掩膜层20易于去除，不会出现掩膜层残留。
例如，如图3所示，所述通过一次构图工艺形成石墨掩膜层20可以包括：
如图4(a)和4(b)所示，在所述石墨薄膜200上涂覆光刻胶300，通过一次光刻工艺形成光刻胶图案层30。
所述光刻工艺具体可以包括前烘、曝光、显影、后烘；在经过曝光和显 影之后，所述光刻胶300便会形成光刻胶保留部分和光刻胶去除部分，即上述的光刻胶图案层30。
所述光刻胶300可以为正性光刻胶或者负性光刻胶；根据所述光刻胶300的类型的不同，所需要的显影液的类型也随之不同。
如图4(c)所示，以所述光刻胶图案层30为掩膜，对所述石墨薄膜200进行干法刻蚀，从而形成石墨掩膜层20。
所述光刻胶图案层30可以作为制备所述石墨掩膜层20的掩膜，所述光刻胶去除部分对应的石墨薄膜200暴露在外而会受到刻蚀，所述光刻胶保留部分覆盖的石墨薄膜200不受影响。
在根据本公开的一个实施例中，在对所述石墨薄膜200进行刻蚀时采用干法刻蚀。相比于湿法刻蚀，干法刻蚀具有良好的各向异性，即只有垂直刻蚀，没有横向钻蚀；这样便可以保证被刻蚀薄膜能够精确复制出与掩膜层完全一致的几何图形。干法刻蚀可以大幅度提高刻蚀的各向异性，精确控制侧壁剖面的形状，且具有良好的刻蚀均匀性。
参考图2(b)所示，去除所述光刻胶图案层30。
在所述石墨掩膜层20的图案形成之后，便可以将所述光刻胶图案层30去除；其中，可以采用湿法剥离或者灰化处理去除所述光刻胶图案层30。
在本文中，湿法剥离和灰化处理均可用于去除所述光刻胶；但灰化处理可能会对光刻胶覆盖的膜层产生一定的损伤，且灰化处理更适用于去除碳化发硬的光刻胶。基于此，由于所述光刻胶图案层30尚未经过离子注入，不存在碳化发硬的问题，因此，在根据本公开的一个实施例中，采用湿法剥离去除所述光刻胶图案层30。
所述湿法剥离可以采用光刻胶专用的剥离液，其成分主要包括硝酸、硫酸和草酸等。
通过上述步骤，便可以制备得到所述石墨掩膜层20。采用所述石墨掩膜层20作为离子注入的掩膜，可以有效地阻挡离子的轰击。
在根据本公开的一个实施例中，所述在基板10表面制备石墨薄膜200可以包括：在半导体基板10的表面沉积所述石墨薄膜200；其中，所述半导体基板10可以包括导体/绝缘衬底基板和位于所述导体/绝缘衬底基板表面的半导体薄膜；或者，所述半导体基板10可以为半导体衬底基板。
当所述半导体基板10包括导体/绝缘衬底基板和位于所述导体/绝缘衬底基板上的半导体薄膜时，所述导体衬底基板可以为金属基板，所述绝缘衬底基板可以为玻璃基板，所述半导体薄膜可以为多晶硅薄膜、或锗薄膜、或硅锗薄膜、或镓砷薄膜等。
当所述半导体基板10为半导体衬底基板时，所述半导体衬底基板可以为硅衬底、或锗衬底、或硅锗衬底、或镓砷衬底等。
在根据本公开的一个实施例中，所述在基板10表面制备石墨薄膜200之前，对所述半导体基板10进行清洗。
例如，可以采用乙醇或丙酮等有机溶剂在超声波清洗设备中对所述半导体基板10进行清洗。当然，在所述半导体基板10清洗完成后还应进行干燥化处理。
通过对所述半导体基板10的表面进行清洗，便可以获得清洁的基板表面，这样有利于所述石墨薄膜200的沉积，并能有效提高基板与薄膜之间的膜基结合力以及成膜的均匀性。
在根据本公开的一个实施例中，在以所述石墨掩膜层20为掩膜进行离子注入之后，还应去除所述石墨掩膜层20，并清洗离子注入后的所述半导体基板10。
这里需要说明的是，所述石墨掩膜层20在经过离子注入之后，其内部也相应地存在微量的注入离子，且这些注入离子存在于石墨晶体的晶格间隙中。也就是说，这些注入离子是以所述石墨晶体为载体而存在于所述石墨掩膜层20中的。因此，当去除所述石墨掩膜层20时，所述注入离子失去了所依附的载体，同时被去除。
这里，所述石墨掩膜层20的去除方法可以是干法刻蚀或者湿法刻蚀。干法刻蚀的反应产物是挥发性气体，采用干法刻蚀可以更加高效地去除所述石墨掩膜层20而不会造成掩膜层残留；此外，干法刻蚀具有相对较高的反应效率，因而可以有效地节省工艺时间。
在本公开的一个实施例中，采用干法刻蚀去除所述石墨掩膜层20；其中，所述干法刻蚀可以包括等离子体刻蚀。
所述等离子体刻蚀的原理如下：在低压环境中，反应气体在射频功率的激发下产生电离并形成等离子体；该等离子体由电子和带电的离子组成，反 应腔内的气体在电子的撞击下，除了转变成离子外，还能吸收能量并形成大量的活性反应基团；该活性反应基团和需要进行刻蚀的物质表面发生化学反应并形成挥发性的反应生成物；该反应生成物脱离被刻蚀物质的表面，并被真空系统抽出腔体。
基于上述原理，所述等离子体刻蚀可以包括任何能够产生氧气等离子体的刻蚀；通过所述氧气等离子体和所述石墨发生化学反应并生成挥发性物质，便可以将所述石墨掩膜层20去除。
在此基础上，在根据本公开的一个实施例中采用氧气等离子体刻蚀去除所述石墨掩膜层20。这里，所述氧气等离子体可以直接由氧气发生电离而形成，因此具有相对较高的纯度，且不会形成副产物。
进一步的，在去除所述石墨掩膜层20之后，还需将离子注入后的所述半导体基板10进行清洗。这里可以通过有机清洗液、紫外光照和去离子水的结合来对所述半导体基板10进行清洗。通过清洗离子注入后的所述半导体基板10，可以有效的降低后续工艺过程中颗粒污染物的累积，从而提高产品的良率。
下面举例对所述离子注入工艺进行完整的描述。如图5所示，所述离子注入工艺可以包括如下步骤。
清洗半导体基板10。
这里，所述半导体基板10包括玻璃基板和位于所述玻璃基板表面的多晶硅。
参考图2(a)所示，在半导体基板10的表面制备石墨薄膜200。
例如，所述石墨薄膜200的厚度为10-150nm。
这里可以通过磁控溅射法沉积所述石墨薄膜200。
参考图4(a)和4(b)所示，在所述石墨薄膜200上涂覆光刻胶300，并通过一次光刻工艺形成光刻胶图案层30。
例如，所述光刻胶300为正性光刻胶。
这里，所述光刻胶300经过曝光和显影可以形成光刻胶去除部分和光刻胶保留部分，即上述的光刻胶图案层30。
参考图4(c)所示，以所述光刻胶图案层30为掩膜，对所述石墨薄膜200进行刻蚀，从而形成石墨掩膜层20。
这里可以通过氧气等离子体对所述石墨薄膜200进行刻蚀。
参考图2(b)所示，去除所述光刻胶图案层30。
这里可以采用光刻胶专用剥离液对其进行湿法剥离；其中，所述光刻胶专用剥离液主要包括硝酸、硫酸和草酸。
参考图2(c)所示，以所述石墨掩膜层20为掩膜进行离子注入。
在此情况下，高能离子便会直接注入到未被所述石墨掩膜层20覆盖的多晶硅的内部，从而改善所述多晶硅半导体层的性能。
去除所述石墨掩膜层20，并清洗离子注入后的所述半导体基板10。
这里可以通过氧气等离子体刻蚀去除所述石墨掩膜层20。
通过上述步骤，便可以完成所述离子注入工艺。例如，以所述石墨掩膜层20为掩膜进行离子注入，不仅可以有效地阻挡离子的轰击，还能快速高效的导热散热，从而避免热效应引起的掩膜层硬化变形，且所述石墨掩膜层20易于通过等离子体刻蚀进行去除，不会存在掩膜层残留，这样便可以大大提高产品的良率。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。
本公开要求于2014年5月15日递交的中国专利申请第201410205401.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的一部分。

Claims (10)

  1. 一种离子注入的方法，包括：
    在基板表面制备石墨薄膜；
    通过一次构图工艺形成石墨掩膜层；以及
    以所述石墨掩膜层为掩膜进行离子注入。
  2. 根据权利要求1所述的方法，其中，所述通过一次构图工艺形成石墨掩膜层包括：
    在所述石墨薄膜上涂覆光刻胶，通过一次光刻工艺形成光刻胶图案层；
    以所述光刻胶图案层为掩膜，对所述石墨薄膜进行干法刻蚀，形成所述石墨掩膜层；以及
    去除所述光刻胶图案层。
  3. 根据权利要求2所述的方法，其中，采用湿法剥离去除所述光刻胶图案层。
  4. 根据权利要求1至3任一项所述的方法，其中，所述在基板表面制备石墨薄膜包括：在半导体基板的表面沉积所述石墨薄膜；
    其中，所述半导体基板包括导体/绝缘衬底基板和位于所述导体/绝缘衬底基板表面的半导体薄膜；或者，
    所述半导体基板为半导体衬底基板。
  5. 根据权利要求1至4中任何一项所述的方法，其中，在基板表面制备石墨薄膜之前，所述方法还包括：
    清洗所述半导体基板。
  6. 根据权利要求1至5中任何一项所述的方法，其中，在以所述石墨掩膜层为掩膜进行离子注入之后，所述方法还包括：
    去除所述石墨掩膜层，并清洗离子注入后的所述半导体基板。
  7. 根据权利要求6所述的方法，其中，所述去除所述石墨掩膜层包括：
    采用干法刻蚀去除所述石墨掩膜层；其中，所述干法刻蚀包括等离子体刻蚀。
  8. 根据权利要求7所述的方法，其中，所述等离子体刻蚀包括氧气等离子体刻蚀。
  9. 根据权利要求1至8中任何一项所述的方法，其中，所述在基板表面制备石墨薄膜包括：通过磁控溅射或者等离子体增强化学气相沉积法在基板表面制备所述石墨薄膜。
  10. 根据权利要求1至9中任何一项所述的方法，其中，所述石墨薄膜的厚度为10-150nm。
PCT/CN2014/088373 2014-05-15 2014-10-11 一种离子注入的方法 WO2015172505A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410205401.0A CN103972062A (zh) 2014-05-15 2014-05-15 一种离子注入的方法
CN201410205401.0 2014-05-15

Publications (1)

Publication Number Publication Date
WO2015172505A1 true WO2015172505A1 (zh) 2015-11-19

Family

ID=51241428

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/088373 WO2015172505A1 (zh) 2014-05-15 2014-10-11 一种离子注入的方法

Country Status (2)

Country Link
CN (1) CN103972062A (zh)
WO (1) WO2015172505A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114460819A (zh) * 2022-01-14 2022-05-10 北京量子信息科学研究院 用于电子束曝光的对准标记及其制备方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103972062A (zh) * 2014-05-15 2014-08-06 京东方科技集团股份有限公司 一种离子注入的方法
CN109824010A (zh) * 2019-01-21 2019-05-31 北京师范大学 一种基于离子注入技术的微纳颗粒二维图形化吸附工艺

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1288584A (zh) * 1998-01-09 2001-03-21 纳幕尔杜邦公司 用于生产电子发射体的等离子体处理方法
KR20060134596A (ko) * 2005-06-23 2006-12-28 주식회사 하이닉스반도체 반도체 소자의 제조방법
US20100055882A1 (en) * 2008-09-03 2010-03-04 The Government of the United States of America, as rpresented by the Secretary of the Navy Junction Termination Extension with Controllable Doping Profile and Controllable Width for High-Voltage Electronic Devices
CN203536373U (zh) * 2013-10-24 2014-04-09 中电电气（扬州）光伏有限公司 离子注入机的新型掩膜
CN103972062A (zh) * 2014-05-15 2014-08-06 京东方科技集团股份有限公司 一种离子注入的方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6440863B1 (en) * 1998-09-04 2002-08-27 Taiwan Semiconductor Manufacturing Company Plasma etch method for forming patterned oxygen containing plasma etchable layer
DE10153310A1 (de) * 2001-10-29 2003-05-22 Infineon Technologies Ag Photolithographisches Strukturierungsverfahren mit einer durch ein plasmaunterstützes Abscheideeverfahren hergestellten Kohlenstoff-Hartmaskenschicht diamantartiger Härte
CN101903978B (zh) * 2007-12-21 2014-11-19 朗姆研究公司 用于注入光刻胶的保护层
CN102683184B (zh) * 2012-05-04 2016-01-27 上海华力微电子有限公司 一种离子注入阻挡层的制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1288584A (zh) * 1998-01-09 2001-03-21 纳幕尔杜邦公司 用于生产电子发射体的等离子体处理方法
KR20060134596A (ko) * 2005-06-23 2006-12-28 주식회사 하이닉스반도체 반도체 소자의 제조방법
US20100055882A1 (en) * 2008-09-03 2010-03-04 The Government of the United States of America, as rpresented by the Secretary of the Navy Junction Termination Extension with Controllable Doping Profile and Controllable Width for High-Voltage Electronic Devices
CN203536373U (zh) * 2013-10-24 2014-04-09 中电电气（扬州）光伏有限公司 离子注入机的新型掩膜
CN103972062A (zh) * 2014-05-15 2014-08-06 京东方科技集团股份有限公司 一种离子注入的方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114460819A (zh) * 2022-01-14 2022-05-10 北京量子信息科学研究院 用于电子束曝光的对准标记及其制备方法
CN114460819B (zh) * 2022-01-14 2024-01-26 北京量子信息科学研究院 用于电子束曝光的对准标记及其制备方法

Also Published As

Publication number Publication date
CN103972062A (zh) 2014-08-06

Similar Documents

Publication Publication Date Title
US10438797B2 (en) Method of quasi atomic layer etching
US9805948B2 (en) Selective etching process of a mask disposed on a silicon substrate
TWI716378B (zh) 蝕刻方法
US10707088B2 (en) Method of processing target object
TW200952069A (en) Plasma processing method and computer readable storage medium
KR20160030378A (ko) 서브-해상도 스케일들로 상이한 임계 치수들을 패터닝하기 위한 방법
TWI713486B (zh) 蝕刻方法（二）
WO2015172505A1 (zh) 一种离子注入的方法
CN106158595B (zh) 半导体器件的形成方法
JPH06177092A (ja) 半導体装置の製造方法
CN111627808B (zh) 半导体结构及其形成方法
WO2015172510A1 (zh) 一种去除光刻胶的方法
WO2009085694A2 (en) Protective layer for implant photoresist
JP2009076711A (ja) 半導体装置の製造方法
JP5642427B2 (ja) プラズマ処理方法
US8962494B2 (en) Method of manufacturing dual gate oxide devices
CN105702569A (zh) 刻蚀方法
CN109585290B (zh) 半导体器件及其形成方法
TW201729285A (zh) 蝕刻方法
CN108172513A (zh) 使用具有由不含氧材料形成的顶板的室进行蚀刻
JP7202489B2 (ja) プラズマ処理方法
CN103928313A (zh) 一种小尺寸图形的制作方法
CN106206284B (zh) 改进型蚀刻工艺
JP2011029562A (ja) 半導体ウェハ端面の処理方法および半導体装置の製造方法
TWI744003B (zh) 鉑的圖案化方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14892136

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) - 1205A (10.05.2017)

122 Ep: pct application non-entry in european phase

Ref document number: 14892136

Country of ref document: EP

Kind code of ref document: A1