WO2015169051A1

WO2015169051A1 - Variable gain amplifier

Info

Publication number: WO2015169051A1
Application number: PCT/CN2014/088559
Authority: WO
Inventors: 谷东明; 李萌; 高洋
Original assignee: 华为技术有限公司
Priority date: 2014-05-09
Filing date: 2014-10-14
Publication date: 2015-11-12
Also published as: CN103973249A; CN103973249B

Abstract

A variable gain amplifier is provided by an embodiment of the present invention. The variable gain amplifier includes a first-stage amplifier circuit composed of a first self-bias transistor load, an adjustable resistance load, a first pair of differential tubes, a first resistor and a current source, wherein all of them are connected in sequence; and the variable gain amplifier also includes a second-stage amplifier circuit composed of a second pair of differential tubes, a second self-bias transistor load, a second resistance load and a third resistance load. The variable gain amplifier adopts the structure of the two-stage amplifier circuit, so that a higher gain could be realized and a gain regulating circuit could be simplified.

Description

Variable gain amplifier

Technical field

Embodiments of the present invention relate to the field of electronic technologies, and in particular, to a variable gain amplifier.

Background technique

The residual amplifier is disposed between the stages of the analog-to-digital converter (ADC) of the multi-stage structure, and is used for amplifying the residual signal of the upper stage to facilitate processing of the next-stage sub-ADC. . The residual amplifier greatly affects the performance of the ADC such as noise, speed and linearity, and takes up most of the power consumption of the ADC.

The traditional margin amplifier is implemented by an op amp-based feedback structure. In order to meet the speed and accuracy of the ADC and the stability of its own feedback, the gain and bandwidth of the op amp need to be large enough, so the power consumption is also large. In addition, in the deep sub-micron process of integrated circuits, the operational amplifiers meeting the system requirements are becoming more and more difficult due to the reduction of the device's intrinsic gain and power supply voltage.

Summary of the invention

The present invention provides a variable gain amplifier to achieve higher gain and to simplify the gain adjustment circuit.

In a first aspect, an embodiment of the present invention provides a variable gain amplifier including a first self-biased transistor load and an adjustable resistance load, a first differential pair tube, a first resistor, and a current source that are sequentially connected;

Wherein the first self-biasing transistor load provides a common mode level for a first stage output of the variable gain amplifier, the adjustable resistance load is for receiving a control signal, and adjusting the said signal based on the control signal a gain of the variable gain amplifier; the first differential pair tube is for receiving an input signal and amplifying the input signal to obtain a result of the first stage output; the first resistor is for increasing a linearity of the variable gain amplifier The current source is used to provide a bias current when the variable gain amplifier is in operation.

In a first possible implementation manner of the first aspect, the first self-bias transistor load includes a first transistor and a second transistor, a gate of the first transistor and the second crystal a gate connection of the tube, a third end of the adjustable resistance load being connected between a gate of the first transistor and a gate of the second transistor, a drain of the first transistor and the a first end of the adjustable resistance load is connected, a source of the first transistor is connected to a first end of the power source, and a drain of the second transistor is connected to a second end of the adjustable resistance load, the second transistor a source connected to the first end of the power source;

The first differential pair tube includes a third transistor and a fourth transistor, a drain of the third transistor is coupled to a first end of the adjustable resistance load, and a source of the third transistor is coupled to the first a first end of the resistor is connected, a gate of the third transistor is a first signal input end, a drain of the fourth transistor is connected to a second end of the adjustable resistance load, a source of the fourth transistor Connected to the second end of the first resistor, the gate of the fourth transistor is a second signal input end; the first signal input end and the second signal input end are configured to receive the input signal, The first end and the second end of the adjustable resistance load are used to provide a result of the first stage output;

The current source includes a fifth transistor, a sixth transistor, and a seventh transistor, which are sequentially connected to the gate. The drain of the fifth transistor is connected to an external bias current source, and the source of the fifth transistor is connected to the second end of the power source. a drain of the sixth transistor is connected to a first end of the first resistor, a source of the sixth transistor is connected to a second end of the power source, and a drain of the seventh transistor is opposite to the first resistor The second end is connected, and the source of the seventh transistor is connected to the second end of the power source.

With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner, the first self-bias transistor load is a P-type metal oxide semiconductor MOS transistor load; a differential pair tube is an N-type metal oxide semiconductor MOS differential pair tube; the fifth transistor, the sixth transistor, and the seventh transistor are both NMOS transistors; and the first end of the power source is a positive voltage terminal of the power source, The second end of the power source is a ground terminal or a power supply negative voltage terminal.

With reference to the first aspect or the first possible implementation manner of the first aspect, in a third possible implementation, the first self-bias transistor load is an NMOS transistor load; the first differential pair transistor is a PMOS a differential transistor; the fifth transistor, the sixth transistor, and the seventh transistor are all PMOS transistors; the second end of the power supply is a power positive voltage terminal, and the first end of the power supply is a ground terminal or a power supply negative Voltage terminal.

Combining the first aspect to the third possible implementation of the first aspect, in the fourth possible In an implementation manner, the variable gain amplifier further includes a second differential pair transistor, a second self-bias transistor load, a second resistive load, and a third resistive load;

The second differential pair tube includes an eighth transistor and a ninth transistor, a gate of the eighth transistor is connected to a drain of the third transistor, and a drain of the eighth transistor is opposite to the second a first end of the resistive load is connected, a source of the eighth transistor is connected to the first end of the power source, a gate of the ninth transistor is connected to a drain of the fourth transistor, and the ninth transistor is a drain is connected to the second end of the third resistive load, a source of the ninth transistor is connected to the first end of the power source; a gate of the eighth transistor and a gate of the ninth transistor are used Receiving the result of the first stage output;

The second self-biasing transistor load includes a tenth transistor and a eleventh transistor, a gate of the tenth transistor is connected to a gate of the eleventh transistor, a drain of the tenth transistor is a first end of the second resistive load is connected, a source of the tenth transistor is connected to the second end of the power source, and a drain of the eleventh transistor is connected to the second end of the third resistive load a source of the eleventh transistor is connected to the second end of the power source;

a second end of the second resistive load is coupled to the first end of the third resistive load, and a second end of the second resistive load and a first end of the third resistive load are coupled to the first end Between the gate of the ten transistor and the gate of the eleventh transistor, the first end of the second resistive load and the second end of the third resistive load provide a result of the second stage output.

With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner, when the first end of the power source is a power positive voltage terminal, the second end of the power source is a ground terminal or a power supply negative voltage terminal The second self-bias transistor load is an NMOS transistor load, and the second differential pair transistor is a PMOS differential pair.

With reference to the fourth possible implementation manner of the first aspect, in a sixth possible implementation, when the second end of the power source is a power positive voltage terminal, the first end of the power source is a ground terminal or a power supply negative voltage terminal. The second self-bias transistor load is a PMOS transistor load, and the second differential pair transistor is an NMOS differential pair.

In conjunction with the fourth to sixth possible implementations of the first aspect, in a seventh possible implementation, the second resistive load and the third resistive load are fixed resistors having the same resistance.

Combining the first aspect to the seventh possible implementation of the first aspect, in the eighth possible In an implementation manner, the adjustable resistance load includes a plurality of switches and a plurality of resistors, each of the plurality of switches receiving one of the control signals and being opened by the control bit Or off to enable or disable the resistor corresponding to the switch.

In conjunction with the eighth possible implementation of the first aspect, in a ninth possible implementation, the plurality of control bits in the control signal are in the form of a thermometer code.

The variable gain amplifier provided by the embodiment of the invention includes a first self-bias transistor load and an adjustable resistance load, a first differential pair tube, a first resistor and a current source, which are sequentially connected, and further includes A second stage amplifying circuit composed of a second differential pair transistor, a second self-biasing transistor load, a second resistive load, and a third resistive load. The variable gain amplifier adopts a two-stage amplifying circuit structure, realizes higher gain, and simplifies the gain adjusting circuit.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description of the drawings used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor.

1 is a schematic diagram of Embodiment 1 of a variable gain amplifier of the present invention;

2 is a schematic diagram showing the implementation of an adjustable resistance load in a variable gain amplifier of the present invention;

3 is a schematic diagram of Embodiment 2 of a variable gain amplifier of the present invention;

4 is a schematic diagram of Embodiment 3 of a variable gain amplifier of the present invention;

FIG. 5 is a flowchart of Embodiment 1 of a gain calibration method according to the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

1 is a schematic diagram of a first embodiment of a variable gain amplifier of the present invention. The first self-biased transistor load PMOS1 and PMOS2, the adjustable resistance load R1, the first differential pair transistor NMOS1 and NMOS2, the first resistor R0, and the current source NMOS3, NMOS4 and NMOS5 are included;

Wherein the first self-bias transistor loads PMOS1 and PMOS2 provide a common mode level for the first stage output of the variable gain amplifier, the adjustable resistance load R1 is for receiving a control signal, and based on the control Signaling the gain of the variable gain amplifier; the first differential pair transistors NMOS1 and NMOS2 are for receiving an input signal and amplifying the input signal to obtain a result of the first stage output; the first resistor R0 is for The linearity of the variable gain amplifier is increased; the current sources NMOS3, NMOS4, and NMOS5 are used to provide a bias current when the variable gain amplifier operates.

Specifically, the first self-bias transistor load includes a first transistor PMOS1 and a second transistor PMOS2, and a gate of the first transistor PMOS1 is connected to a gate of the second transistor PMOS2, the adjustable resistance load The third end VM of R1 is connected between the gate of the first transistor PMOS1 and the gate of the second transistor PMOS2, the drain of the first transistor PMOS1 and the first of the adjustable resistance load R1 The terminal P is connected, the source of the first transistor PMOS1 is connected to the first end of the power source V _dd , and the drain of the second transistor PMOS 2 is connected to the second end N of the adjustable resistance load R1 , the second The source of the transistor PMOS2 is connected to the first end of the power source V _dd .

Further, the adjustable resistance load R1 may include a plurality of switches S1 SSn and a plurality of resistors R0 and R, each of the plurality of switches S1 SSn receiving one of the control signals, And turning on or off under the action of the control bit to enable or disable the resistance corresponding to the switch, as shown in FIG. 2, R0 in FIG. 2 is a fixed resistor, and two R0 intermediate terminals, that is, The third end VM of the adjustable resistance load R1 is connected between the gate of the first transistor PMOS1 and the gate of the second transistor PMOS2, and the remaining resistors are resistor arrays of the same two resistors R in parallel, The opening and closing of the switch changes the equivalent resistance value of the resistor array, thereby achieving programmable control of the circuit gain. In practical applications, a plurality of control bits in the control signals received by the switches S1 to Sn are program-controlled in the form of a thermometer code to ensure the monotonicity of the gain variation. That is, a switch is controlled by each digital control signal. If a digital control signal is 1, the corresponding switch is turned on. If the digital control signal is 0, The switch should be turned off and vice versa. In some embodiments, the switch can also be programmed and controlled by other coding modes. This embodiment does not limit the coding method of the control switch.

The first differential pair tube includes a third transistor NMOS1 and a fourth transistor NMOS2, a drain of the third transistor NMOS1 is connected to a first end P of the adjustable resistance load R1, and a source of the third transistor NMOS1 The pole is connected to the first end of the first resistor R0, the gate of the third transistor NMOS1 is a first signal input terminal INP, the drain of the fourth transistor NMOS2 is second with the adjustable resistor load R1 The terminal of the fourth transistor NMOS2 is connected to the second end of the first resistor R0, the gate of the fourth transistor NMOS2 is the second signal input terminal INN; the first signal input terminal INP And the second signal input terminal INN is configured to receive the input signal, the first end P and the second end N of the adjustable resistive load R1 are used to provide a result of the first stage output; OUTP and OUTN are differential outputs For outputting the output signal of the primary amplifier shown in FIG.

The current source includes a fifth transistor NMOS3, a sixth transistor NMOS4, and a seventh transistor NMOS5, which are sequentially connected to the gate. The drain of the fifth transistor NMOS3 is connected to an external bias current source I, and the source of the fifth transistor NMOS3. The second terminal of the second transistor NMOS4 is connected to the first end of the first resistor R0, the source of the sixth transistor NMOS4 is connected to the second end of the power source, and the seventh transistor NMOS5 The drain is connected to the second end of the first resistor R0, and the source of the seventh transistor NMOS5 is connected to the second end of the power source. Specifically, in the implementation manner shown in FIG. 1, the first end of the power source V _dd is a power positive voltage terminal, and the second end of the power source V _dd is a ground terminal or a power supply negative voltage terminal.

In another possible implementation manner, the first self-bias transistor load may be an NMOS transistor load, the first differential pair transistor may be a PMOS differential pair tube; the fifth transistor, the sixth transistor And the seventh transistor can be a PMOS transistor; the second end of the power supply V _dd is a power positive voltage terminal, and the first end of the power supply V _dd is a ground terminal or a power supply negative voltage terminal, as shown in FIG. 4 below. Corresponding embodiment.

The technical solution of this embodiment includes a first self-biased transistor load and an adjustable resistance load, a first differential pair tube, a first resistor, and a current source connected in sequence; wherein the first self-bias transistor load is The first stage output of the variable gain amplifier provides a common mode level, the adjustable resistance load is for receiving a control signal, and adjusting a gain of the variable gain amplifier based on the control signal; the first differential pair The tube is used to receive an input signal and perform an input signal Amplifying results of the first stage output; the first resistance is used to increase the linearity of the variable gain amplifier; the current source is used to provide a bias current when the variable gain amplifier is operating. Thereby, the programmable gain of the circuit is controlled by adjusting the equivalent resistance value of the adjustable resistance load; and the programmable control is used to realize the programming control of the adjustable resistance switch, thereby ensuring the monotonicity of the gain variation.

3 is a schematic diagram of a second embodiment of a variable gain amplifier of the present invention. As shown in FIG. 3, based on the foregoing embodiment, the variable gain amplifier provided in this embodiment may further include a second differential pair transistor PMOS3 and PMOS4, a second self-bias transistor load NMOS6 and NMOS7, and a second resistive load. R2 and a third resistive load R3;

The second differential pair tube includes an eighth transistor PMOS3 and a ninth transistor PMOS4, a gate of the eighth transistor PMOS3 is connected to a drain of the third transistor NMOS1, and a drain of the eighth transistor PMOS3 Connected to the first end of the second resistive load R2, the source of the eighth transistor PMOS3 is connected to the first end of the power source V _dd , the gate of the ninth transistor PMOS4 and the fourth transistor NMOS2 a drain connection, a drain of the ninth transistor PMOS4 is connected to a second end of the third resistive load R3, and a source of the ninth transistor PMOS4 is connected to a first end of the power source V _dd ; A gate of the eighth transistor PMOS3 and a gate of the ninth transistor PMOS4 are used to receive a result of the first stage output.

The second self-bias transistor load includes a tenth transistor NMOS6 and an eleventh transistor NMOS7, a gate of the tenth transistor NMOS6 is connected to a gate of the eleventh transistor NMOS7, and the tenth transistor NMOS6 The drain is connected to the first end of the second resistive load R2, the source of the tenth transistor NMOS6 is connected to the second end of the power source V _dd , the drain of the eleventh transistor NMOS7 and the first The second end of the three-resistive load R3 is connected, and the source of the eleventh transistor NMOS7 is connected to the second end of the power source V _dd .

The second end of the second resistive load R2 is connected to the first end of the third resistive load R3, and the second end of the second resistive load R2 is connected to the first end of the third resistive load R3 Between the gate of the tenth transistor NMOS6 and the gate of the eleventh transistor NMOS7, the first end of the second resistive load R2 and the second end of the third resistive load R3 provide a second The result of the level output. In the implementation shown in FIG. 3, the first end of the power supply V _dd is a power positive voltage terminal, and the second end of the power supply V _dd is a ground terminal or a power supply negative voltage terminal. The second resistive load R2 and the third resistive load R3 are fixed resistors having the same resistance.

Further, as shown in FIG. 4, in another implementation manner, the second end of the power source V _dd is a power positive voltage terminal, and the first end of the power source V _dd is a ground terminal or a power supply negative voltage terminal. The first self-biased transistor load may also be an NMOS transistor, specifically NMOS1 and NMOS2 in FIG. 4; the first differential pair transistor may also be a PMOS differential pair transistor, specifically PMOS1 and PMOS2 in FIG. The fifth transistor, the sixth transistor, and the seventh transistor may each be a PMOS transistor, specifically PMOS3, PMOS4, and PMOS5 in FIG. 4; the second self-bias transistor load may also be The PMOS transistor load may be PMOS6 and PMOS7 in FIG. 4; the second differential pair transistor may be an NMOS differential pair transistor, specifically NMOS3 and NMOS4 in FIG. Alternatively, an electronic device capable of achieving equivalent functions may be employed, which is not limited in this embodiment.

It should be noted that, in this embodiment, the variable gain amplifier includes a two-stage amplifying circuit, the first-stage amplifying circuit is similar to the amplifying circuit in FIG. 1, and the second-stage amplifying circuit is used according to the first-stage amplifying circuit. The output gets the final outputs OUTP and OUTN. The adjustable resistance load can be used as a differential mode load of the first stage amplifying circuit of the variable gain amplifier, and the second resistive load and the third resistive load can be used as differential mode loads of the second stage amplifying circuit of the variable gain amplifier, The stage amplifier circuit can achieve higher gain.

In the technical solution of the embodiment, a higher gain can be achieved by providing a two-stage amplifying circuit.

FIG. 5 is a flowchart of Embodiment 1 of a gain calibration method according to the present invention. As shown in FIG. 5, the gain calibration method provided in this embodiment may be applied to a multi-stage analog-to-digital converter including the variable gain amplifier of the above embodiment, and the method may specifically include:

Step 101: Short-circuit the input end of the pre-stage sub-analog converter to a common mode level, and the pre-stage sub-analog-to-digital converter performs sampling and analog-to-digital conversion, and separately counts the pre-stage sub-analog converter conversion The highest bit of the result is a probability of 0 and 1; the magnitude and direction of the comparator offset in the pre-stage sub-analog converter are adjusted until the highest bit of the conversion result of the pre-sub-analog converter is 0 and 1 When the probability of each is 50%, the offset calibration of the comparator of the pre-stage sub-analog converter is completed;

Step 102: Short-circuit the input end of the variable gain amplifier to a common mode level, and the subsequent sub-analog converter of the variable gain amplifier performs sampling and analog-to-digital conversion, and separately counts the subsequent sub-modules The probability that the highest bit of the digital converter conversion result is 0 and 1; the magnitude and direction of the comparator offset in the subsequent sub-analog converter are adjusted until the latter sub-analog converter When the probability that the highest bit of the result is 0 and 1 is 50%, respectively, the offset calibration of the variable gain amplifier and the comparator of the latter sub-analog converter is completed;

Step 103: Short-circuit the input end of the pre-stage sub-analog converter to a common mode level, and outputs at both ends of the comparator of the pre-stage sub-analog converter are 011...1 and 100...0, both The difference is a Least Significant Bit (LSB) 1 LSB of the pre-stage sub-analog converter; and the variable gain amplifier is judged according to whether the output of the variable gain amplifier is equal to an expected value at this time. Whether the gain of the variable gain amplifier is not equal to the expected value, and adjusting the plurality of switches of the adjustable resistive load of the variable gain amplifier step by step to make the variable gain amplifier The output is equal to the expected value, completing the gain calibration of the variable gain amplifier.

Wherein, the gain expected value of the variable gain amplifier output is an ADC system setting value.

The technical solution of the present embodiment is applied to a multi-stage analog-to-digital converter including the variable gain amplifier of the above embodiment, and can realize real-time calibration of the gain and offset of the variable gain amplifier in the foreground.

Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention. range.

Claims

A variable gain amplifier, comprising: a first self-biased transistor load and an adjustable resistance load, a first differential pair tube, a first resistor, and a current source;

Wherein the first self-biasing transistor load provides a common mode level for a first stage output of the variable gain amplifier, the adjustable resistance load is for receiving a control signal, and adjusting the said signal based on the control signal a gain of the variable gain amplifier; the first differential pair tube is for receiving an input signal and amplifying the input signal to obtain a result of the first stage output; the first resistor is for increasing a linearity of the variable gain amplifier The current source is used to provide a bias current when the variable gain amplifier is in operation.
The variable gain amplifier of claim 1 wherein:

The first self-biasing transistor load includes a first transistor and a second transistor, a gate of the first transistor is connected to a gate of the second transistor, and a third end of the adjustable resistance load is connected Between the gate of the first transistor and the gate of the second transistor, the drain of the first transistor is connected to the first end of the adjustable resistance load, the source and the power of the first transistor The first end is connected, the drain of the second transistor is connected to the second end of the adjustable resistance load, and the source of the second transistor is connected to the first end of the power source;

The first differential pair tube includes a third transistor and a fourth transistor, a drain of the third transistor is coupled to a first end of the adjustable resistance load, and a source of the third transistor is coupled to the first a first end of the resistor is connected, a gate of the third transistor is a first signal input end, a drain of the fourth transistor is connected to a second end of the adjustable resistance load, a source of the fourth transistor Connected to the second end of the first resistor, the gate of the fourth transistor is a second signal input end; the first signal input end and the second signal input end are configured to receive the input signal, The first end and the second end of the adjustable resistance load are used to provide a result of the first stage output;

The current source includes a fifth transistor, a sixth transistor, and a seventh transistor, which are sequentially connected to the gate. The drain of the fifth transistor is connected to an external bias current source, and the source of the fifth transistor is connected to the second end of the power source. a drain of the sixth transistor is connected to a first end of the first resistor, a source of the sixth transistor is connected to a second end of the power source, and a drain of the seventh transistor is opposite to the first resistor The second end is connected, and the source of the seventh transistor is connected to the second end of the power source.
A variable gain amplifier according to claim 1 or 2, wherein said said The first self-biasing transistor load is a P-type metal oxide semiconductor PMOS transistor load; the first differential pair transistor is an N-type metal oxide semiconductor NMOS differential pair tube; the fifth transistor, the sixth transistor, and the The seventh transistor is an NMOS transistor; the first end of the power supply is a power positive voltage terminal, and the second end of the power supply is a ground terminal or a power supply negative voltage terminal.
The variable gain amplifier according to claim 1 or 2, wherein said first self-bias transistor load is an NMOS transistor load; said first differential pair transistor is a PMOS differential pair transistor; said fifth transistor The sixth transistor and the seventh transistor are both PMOS transistors; the second end of the power supply is a power positive voltage terminal, and the first end of the power supply is a ground terminal or a power supply negative voltage terminal.
The variable gain amplifier according to any one of claims 1 to 4, further comprising a second differential pair transistor, a second self-bias transistor load, a second resistive load, and a third resistive load;

The second differential pair tube includes an eighth transistor and a ninth transistor, a gate of the eighth transistor is connected to a drain of the third transistor, and a drain of the eighth transistor is opposite to the second a first end of the resistive load is connected, a source of the eighth transistor is connected to the first end of the power source, a gate of the ninth transistor is connected to a drain of the fourth transistor, and the ninth transistor is a drain is connected to the second end of the third resistive load, a source of the ninth transistor is connected to the first end of the power source; a gate of the eighth transistor and a gate of the ninth transistor are used Receiving the result of the first stage output;

The second self-biasing transistor load includes a tenth transistor and a eleventh transistor, a gate of the tenth transistor is connected to a gate of the eleventh transistor, a drain of the tenth transistor is a first end of the second resistive load is connected, a source of the tenth transistor is connected to the second end of the power source, and a drain of the eleventh transistor is connected to the second end of the third resistive load a source of the eleventh transistor is connected to the second end of the power source;

a second end of the second resistive load is coupled to the first end of the third resistive load, and a second end of the second resistive load and a first end of the third resistive load are coupled to the first end Between the gate of the ten transistor and the gate of the eleventh transistor, the first end of the second resistive load and the second end of the third resistive load provide a result of the second stage output.
The variable gain amplifier according to claim 5, wherein when the first end of the power source is a power positive voltage terminal and the second power terminal is a ground terminal or a power supply negative voltage terminal, The second self-biasing transistor load is an NMOS transistor load, and the second differential pair transistor is a PMOS differential pair tube.
The variable gain amplifier according to claim 5, wherein when the second end of the power source is a power positive voltage terminal, and the first end of the power source is a ground terminal or a power supply negative voltage terminal, the second self is The bias transistor load is a PMOS transistor load and the second differential pair transistor is an NMOS differential pair transistor.
The variable gain amplifier according to any one of claims 5 to 7, wherein the second resistive load and the third resistive load are fixed resistors having the same resistance.
The variable gain amplifier according to any one of claims 1 to 8, wherein the adjustable resistance load includes a plurality of switches and a plurality of resistors, each of the plurality of switches receiving the A control bit in the control signal that is turned on or off by the control bit to enable or disable the resistance corresponding to the switch.
The variable gain amplifier of claim 9 wherein the plurality of control bits in said control signal are in the form of a thermometer code.