WO2015158147A1 - 采用多斜坡电压作参考电压的数字像素曝光方法 - Google Patents

采用多斜坡电压作参考电压的数字像素曝光方法 Download PDF

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WO2015158147A1
WO2015158147A1 PCT/CN2014/093762 CN2014093762W WO2015158147A1 WO 2015158147 A1 WO2015158147 A1 WO 2015158147A1 CN 2014093762 W CN2014093762 W CN 2014093762W WO 2015158147 A1 WO2015158147 A1 WO 2015158147A1
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reference voltage
pixel
vref
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姚素英
高志远
徐江涛
史再峰
高静
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Tianjin University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS

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  • the present invention relates to the field of CMOS image sensors, and more particularly to a digital pixel sensor exposure method using a multi-ramp voltage as a reference voltage.
  • a digital pixel sensor is one of CMOS (Complementary Metal Oxide Semiconductor) image sensors. This sensor implements analog to digital conversion inside the pixel, and subsequent data reading and processing are performed in the digital domain.
  • PWM Pulse Width Modulation
  • a typical PWM pixel consists of a photodiode PD, a reset transistor MRST, a pixel-level, a column-level comparator, and a pixel-level, column-level, or array-level memory ( Figure 1 Pixel-level comparators and pixel-level memories are examples).
  • the input terminals of the pixel level comparator are the PD node voltage and the set reference voltage Vref, respectively.
  • the input data of the pixel level memory is input by a global counter external to the pixel array.
  • the PD is first reset to the reset voltage Vrst.
  • the pixel-level comparator compares the relationship between the PD node voltage and Vref.
  • the comparator's output Vout occurs from a high voltage to a voltage transition.
  • This hopping signal controls the pixel level memory to stop the "write" operation, saving the current global counter value.
  • the data in the memory is the integration time tint quantization value of the pixel, which is equivalent to the pulse width formed by the time interval between the pixel starting from the integration and the flipping of the comparator output, and the value is:
  • Iph is photo-generated current and CPD is PD node capacitance.
  • CPD is PD node capacitance.
  • the tint size can represent the pixel photo-generated current value, and tint is inversely proportional to Iph.
  • the photo-generated currents of the PD under the two light intensities are Iph1 and Iph2, respectively, according to ( 1)
  • the corresponding pulse widths are t1 and t2, respectively.
  • the photo-generated current of the PD is large (greater than Iph_max), the node voltage drops to Vref very quickly, and the counter does not have time to generate an effective value to be recorded in the memory, thus losing the information of the high-intensity portion.
  • the classic PWM pixel structure requires higher and lower Vref in low light intensity environment and high light intensity environment, respectively, to shorten or extend tsig to be detected by subsequent circuits, so this type of PWM pixel Fixed Vref values are often not suitable for the current lighting environment, resulting in a small DR. Therefore, in order to obtain a large dynamic range, some techniques use a time-varying reference voltage Vref and eliminate reset noise and inter-pixel deviation by segmentation comparison. The principle is as follows:
  • the reference voltage comparison during pixel exposure is divided into two large phases, the first segment is called the reset sampling phase, and the second segment is the integral sampling phase.
  • the exposure time is divided into a reset sampling phase Trs and an integral sampling phase Tis.
  • Vref linearly rises from Vref_rsl to Vref_rsh
  • Vref rises from Vref_is1 to Vref_ish.
  • the photon voltages are equal to the time values tPD_rs and tPD_is when Vref is twice. Then the difference between the two times is the time value tPD of the reactive light intensity that eliminates the reset noise and the inter-pixel deviation.
  • the slope of the reference voltage must be the same in the reset sampling phase and the integral sampling phase. Otherwise, tPD_rs and tPD_is cannot completely eliminate the reset noise and the inter-pixel deviation, but introduce new deviations.
  • the time between the reset sampling phase time Trs and the integral sampling phase time Tis time is usually very large, and the Tis is usually 100 to 500 times that of the Trs. Therefore, it is difficult to achieve the same reference voltage slope for these two segments.
  • a digital pixel sensor capable of unifying the two sections of the reference voltage change rate in the two-stage comparison technique for the problem that the two-stage change rate of the two-stage variation reference voltage cannot be consistent.
  • the technical solution adopted by the present invention is a digital pixel exposure method using a multi-ramp voltage as a reference voltage, comprising the following steps: by means of a PWM pixel array, the PWM pixel is composed of a photodiode PD, a reset tube MRST, a pixel level, a column level comparator And pixel level, column level or array level memory, the input of the pixel level comparator is the PD node voltage and the set reference voltage respectively, the PWM type digital pixel enters the exposure stage after reset, and divides the exposure time into the reset sampling stage Trs And the integral sampling phase Tis; the reference voltage of the reset sampling phase rises linearly from Vref_rsl to Vref_rsh, and the integral sampling phase is further subdiv
  • the number N of sub-phases depends on the time of the integral sampling stage.
  • the selection of the number N of sub-phases is generated by digital circuits in the PWM pixel array chip, determined at the time of PWM pixel array chip design, and finally solidified in the PWM pixel array chip.
  • Figure 1 is based on the digital pixel structure of the PWM
  • Figure 2 is a plot of the pulse width tint versus the photogenerated current Iph
  • Figure 3 is a schematic diagram showing changes in the comparison digital pixel reference voltage (solid line) and photodiode voltage (dashed line).
  • Figure 4 Schematic diagram of digital pixel reference voltage (solid line) and photodiode voltage (dashed line) for multiple slope reference voltages.
  • the second segment (integral sampling phase) of the two-phase comparison scheme of the reference voltage is divided into N sub-phases.
  • the number N of sub-stages depends on the time of the integral sampling stage. If the integral sampling time is long, then N needs a larger area, which can be 10 or more; if the integration time is short, then the value of N ranges from 1 to Between 10.
  • the selection of this sub-phase is generated by digital circuits in the chip, determined at the time of chip design, and finally solidified in the chip.
  • the reference voltage rises linearly from the lowest voltage Vref_isl_n of each sub-phase in these N sub-phases, reaches the maximum voltage Vref_ish_n of each segment and then jumps to Vref_hold and holds this voltage until the next entry sub-phase. Therefore, the sub-phase includes the reference voltage rise phase and the hold phase.
  • the reference voltage after such segmentation ensures that the slope of the reference voltage rise for each sub-phase coincides with the slope of the reset sampling phase. Then it can be guaranteed that the time difference after the two comparisons can eliminate the reset noise and the inter-pixel deviation.
  • the pixel structure used in the present invention is the same as the conventional PWM pixel shown in Fig. 1, except that the reference voltage and timing are changed.
  • the PWM type digital pixel enters the exposure phase after reset.
  • the exposure time is divided into a reset sampling phase Trs and an integral sampling phase Tis.
  • the reset sampling phase reference voltage rises linearly from Vref_rsl to Vref_rsh.
  • the integral sampling phase is further subdivided into N (N is an integer greater than or equal to 2) sub-phases, except for the last sub-phase, which includes a reference voltage rising phase and a reference voltage holding phase.
  • Each reference voltage rising phase reference voltage is raised from the lowest voltage Vref_isl_n (n is an integer greater than or equal to 1 and less than or equal to N) to the highest voltage Vref_ish_n of each segment.
  • the reference voltage changes to a fixed value Vref_hold until the end of the hold phase, and the next sub-phase, the reference voltage begins to rise again from Vref_isl_n.
  • the last sub-phase voltage rises from Vref_isl_N to Vref_ish_N, so that an exposure period ends and the pixels enter the read and reset phases.
  • the first six sub-phases except the 368us reference voltage rise phase, the rest of the time is the reference voltage hold phase time.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

本发明涉及CMOS图像传感器领域，为提供一种能够将两段比较技术中两段参考电压变化率统一起来的数字像素传感器，为此，本发明采用的技术方案是，采用多斜坡电压作参考电压的数字像素曝光方法，包括如下步骤：借助于PWM像素阵列实现，PWM像素由光电二极管PD、复位管MRST、像素级、列级比较器和像素级、列级或阵列级存储器组成，像素级比较器的输入端分别为PD节点电压和设定的参考电压，PWM型数字像素在复位之后进入曝光阶段，将曝光时间分成复位采样阶段Trs和积分采样阶段Tis；复位采样阶段参考电压从Vref_rsl线性上升到Vref_rsh。本发明主要应用于CMOS图像传感器的设计制造。

Description

采用多斜坡电压作参考电压的数字像素曝光方法 技术领域
本发明涉及CMOS图像传感器领域，尤其涉及一种采用多斜坡电压作为参考电压的数字像素传感器曝光方法。
背景技术
数字像素传感器(digital pixel sensor,DPS)属于CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)图像传感器中的一种。这种传感器在像素内部实现模拟数字的转换，后续的数据读出和处理都是在数字域进行。PWM(Pulse Width Modulation，脉冲宽度调制)是DPS的一种。参考图1，基于PWM的像素结构和工作过程如下：一个典型的PWM像素由光电二极管PD、复位管MRST、像素级、列级比较器和像素级、列级或阵列级存储器组成(图1以像素级比较器和像素级存储器为例)。像素级比较器的输入端分别为PD节点电压和设定的参考电压Vref。像素级存储器的输入数据由像素阵列外部的全局计数器输入。PD先复位至复位电压Vrst，在像素积分的过程中，PD节点电容因外界光强作用产生的光生电流而放电，节点电压下降，像素级比较器比较PD节点电压与Vref之间的关系，当它降低至Vref时，该比较器的输出Vout发生由高电压到底电压的跳变，这一跳变信号控制像素级存储器停止“写”操作，保存当前全局计数器的数值。此时存储器中的数据即为该像素的积分时间tint量化值，等价于像素从积分开始到其比较器输出翻转之间的时间间隔所形成的脉冲宽度，其值为：
Figure PCTCN2014093762-appb-000001
其中，Iph为光生电流，CPD为PD节点电容。参考图2所示，tint大小可表示像素光生电流值，且tint与Iph成反比，例如在图2所示的例子中，两种光强下PD的光生电流分别为Iph1和Iph2，则根据(1)式对应的脉冲宽度分别为t1和t2，则
Figure PCTCN2014093762-appb-000002
设PWM像素可探测的最大、最小信号分别为Iph_max和Iph_min，那么它的DR(Dynamic Range，动态范围)为：
Figure PCTCN2014093762-appb-000003
从以上PWM像素的工作原理可以看出：在弱光条件下，当光强低于一定极限值时，PD的光生电流很小(小于Iph_min)，节点电容放电缓慢，节点电压在规定的最长积分时间内将无法下降至Vref，因此不会产生跳变信号控制存储器进行“写”操作，即该结构对弱光的探测能力受到Vref的限制，对弱光的分辨能力弱。同样，在强光照条件下，PD的光生电流很大(大于Iph_max)，节点电压很快下降到Vref，计数器来不及产生有效值记录在存储器中，因此丢失了高光强部分的信息。综上所述，经典PWM像素结构在低光强环境和高光强环境中分别需要较高和较低的Vref，来缩短或延长tsig以被后续电路探测，所以该型PWM像素中 固定的Vref取值往往不适合当前光照环境，导致DR较小。因此，为了获得较大的动态范围，有些技术采用随时间变化的参考电压Vref，并且通过分段比较消除复位噪声和像素间偏差。其原理如下：
像素曝光期间参考电压比较分为两个大的阶段，第一段称为复位采样阶段，第二段成为积分采样阶段。如图3所示，曝光时间被分成了复位采样阶段Trs和积分采样阶段Tis。在复位采样阶段Vref从Vref_rsl线性上升到Vref_rsh，在积分采样阶段，Vref从Vref_isl上升到Vref_ish。在复位采样段和积分采样段中，光电二极管电压两次等于Vref时的时间值tPD_rs和tPD_is。那么这两次的差值就是消除掉了复位噪声和像素间偏差的反应光强的时间值tPD。这样做法有一个前提就是复位采样阶段和积分采样阶段参考电压的变化斜率必须相同，不然tPD_rs和tPD_is无法完全消除复位噪声和像素间偏差，反而会引入新的偏差。但是复位采样阶段时间Trs和积分采样阶段时间Tis时间差距通常非常大，Tis通常是Trs的100～500倍。所以很难做到这两段的参考电压斜率一致。
发明内容
为克服现有技术的不足，针对两段变化参考电压的两段变化率不能一致的问题，提供一种能够将两段比较技术中两段参考电压变化率统一起来的数字像素传感器，为此，本发明采用的技术方案是，采用多斜坡电压作参考电压的数字像素曝光方法，包括如下步骤：借助于PWM像素阵列实现，PWM像素由光电二极管PD、复位管MRST、像素级、列级比较器和像素级、列级或阵列级存储器组成，像素级比较器的输入端分别为PD节点电压和设定的参考电压，PWM型数字像素在复位之后进入曝光阶段，将曝光时间分成复位采样阶段Trs和积分采样阶段Tis；复位采样阶段参考电压从Vref_rsl线性上升到Vref_rsh，积分采样阶段又细分为N个子阶段，N为大于等于2的整数，除最后一个子阶段外，其余子阶段分别包括一个参考电压上升阶段和一个参考电压保持阶段，每个参考电压上升阶段参考电压由最低电压Vref_isl_n上升到每一段的最高电压Vref_ish_n，n为大于等于1小于等于N的整数；在每个子阶段中的参考电压保持阶段，参考电压变化为固定值Vref_hold，直到保持阶段结束，进入下一个子阶段，参考电压又开始从Vref_isl_n上升，经过N-1个子阶段后，最后一个子阶段电压从Vref_isl_N上升到Vref_ish_N，这样一个曝光周期结束，像素进入读出和复位阶段。
子阶段的个数N取决于积分采样阶段的时间，子阶段个数N的选择通过PWM像素阵列芯片中数字电路来产生，在PWM像素阵列芯片设计时确定，最后固化在PWM像素阵列芯片中。
本发明的技术特点及效果：
在两段比较参考电压的基础上在第二段(积分采样阶段)划分出更多的斜坡来调整两段参考电压变化率的一致性。这样保证了两次比较得到的时间差能够真正消除掉复位噪声和像素间偏差。
附图说明
图1基于PWM的数字像素结构，
图2脉冲宽度tint与光生电流Iph之间的关系曲线，
图3两段比较式数字像素参考电压(实线)与光电二极管电压(虚线)变化示意图，
图4多段斜坡参考电压的数字像素参考电压(实线)与光电二极管电压(虚线)变化示意图。
具体实施方式
本发明中将参考电压两段比较方案的第二段(积分采样阶段)分为N子阶段。子阶段的个数N取决于积分采样阶段的时间，如果积分采样时间很长，那么N需要区较大值，可以选取10甚至以上；如果积分时间较短，那么N的取值范围在1～10之间。这个子阶段的选择通过芯片中数字电路来产生，在芯片设计时确定的，最后固化在芯片中。参考电压在这N个子阶段从每个子阶段的最低电压Vref_isl_n线性上升，达到每段的最高电压Vref_ish_n之后跳变为Vref_hold并且保持这个电压直至下一个进入子阶段。所以子阶段中包括了参考电压上升阶段和保持阶段。这样分段之后的参考电压可以保证每一个子阶段参考电压上升斜率与复位采样阶段的斜率一致。那么可以保证两段比较之后的时间差能够消除掉复位噪声和像素间偏差。
具体描述如下：
本发明所用像素结构与图1所示的常用PWM像素一样，只是在参考电压和时序方面有改动。
PWM型数字像素在复位之后进入曝光阶段。曝光时间被分成了复位采样阶段Trs和积分采样阶段Tis。复位采样阶段参考电压从Vref_rsl线性上升到Vref_rsh。积分采样阶段又细分为N(N为大于等于2的整数)个子阶段，除最后一个子阶段外，其余子阶段分别包括一个参考电压上升阶段和一个参考电压保持阶段。每个参考电压上升阶段参考电压由最低电压Vref_isl_n(n为大于等于1小于等于N的整数)上升到每一段的最高电压Vref_ish_n。在每个子阶段中的参考电压保持阶段，参考电压变化为固定值Vref_hold，直到保持阶段结束，进入下一个子阶段，参考电压又开始从Vref_isl_n上升。经过N-1个子阶段后，最后一个子阶段电压从Vref_isl_N上升到Vref_ish_N，这样一个曝光周期结束，像素进入读出和复位阶段。
以1.2v，65nm制作工艺为例给出本发明的一种实施方式。所设计图像传感器帧频为60帧每秒。那么每帧时间为16.66ms。图4为曝光时间内参考电压与光电二极管电压变化示意图。其中Trs设置为102.4us，Tis设置为16153.6us。在复位采样阶段，参考电压从Vref_rsl＝1.076V上升到Vref_rsh＝1.2V。积分采样阶段分为7个子阶段。7个子阶段的时间分别为636.8us、992us、1544us、2403.2us、3737.6us、5816us和1024us。前六个子阶段的参考电压上升阶段时间为368us，电压从Vref_isl_1～Vref_isl_6＝0.2V上升到Vref_ish_1～Vref_ish_6＝0.568V。前六个子阶段除368us的参考电压上升阶段，其余时间为参考电压保持阶段时间。第7子阶段1024us全部为参考电压上升阶段，参考电压从Vref_isl_7＝0.2V上升到Vref_ish_7＝1.2V。

Claims (2)

  1. 一种采用多斜坡电压作参考电压的数字像素曝光方法，其特征是，包括如下步骤：借助于PWM像素阵列实现，PWM像素由光电二极管PD、复位管MRST、像素级、列级比较器和像素级、列级或阵列级存储器组成，像素级比较器的输入端分别为PD节点电压和设定的参考电压，PWM型数字像素在复位之后进入曝光阶段，将曝光时间分成复位采样阶段Trs和积分采样阶段Tis；复位采样阶段参考电压从Vref_rsl线性上升到Vref_rsh，积分采样阶段又细分为N个子阶段，N为大于等于2的整数，除最后一个子阶段外，其余子阶段分别包括一个参考电压上升阶段和一个参考电压保持阶段，每个参考电压上升阶段参考电压由最低电压Vref_isl_n上升到每一段的最高电压Vref_ish_n，n为大于等于1小于等于N的整数；在每个子阶段中的参考电压保持阶段，参考电压变化为固定值Vref_hold，直到保持阶段结束，进入下一个子阶段，参考电压又开始从Vref_isl_n上升，经过N-1个子阶段后，最后一个子阶段电压从Vref_isl_N上升到Vref_ish_N，这样一个曝光周期结束，像素进入读出和复位阶段。
  2. 如权利要求1所述的采用多斜坡电压作参考电压的数字像素曝光方法，其特征是，子阶段的个数N取决于积分采样阶段的时间，子阶段个数N的选择通过PWM像素阵列芯片中数字电路来产生，在PWM像素阵列芯片设计时确定，最后固化在PWM像素阵列芯片中。
PCT/CN2014/093762 2014-04-14 2014-12-12 采用多斜坡电压作参考电压的数字像素曝光方法 Ceased WO2015158147A1 (zh)

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