WO2015154724A1 - 在石墨烯材料上淀积高k栅介质的方法及应用 - Google Patents

在石墨烯材料上淀积高k栅介质的方法及应用 Download PDF

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WO2015154724A1
WO2015154724A1 PCT/CN2015/076420 CN2015076420W WO2015154724A1 WO 2015154724 A1 WO2015154724 A1 WO 2015154724A1 CN 2015076420 W CN2015076420 W CN 2015076420W WO 2015154724 A1 WO2015154724 A1 WO 2015154724A1
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electron beam
graphene
medium
ald
substrate sample
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叶青
傅云义
郭剑
贾越辉
魏子钧
张亮
任黎明
黄如
张兴
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北京大学
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Definitions

  • the invention belongs to the field of integrated circuit technology, and in particular relates to a method for depositing a high-k gate dielectric on a surface of a graphene material or a device structure based on a graphene material.
  • ALD Atomic layer deposition
  • the precursor of the ALD reaction alternates into the reaction chamber in the form of a gas phase pulse.
  • ALD can precisely control the thickness of the deposition medium.
  • each precursor pulse enters the reaction chamber.
  • ALD atomic-level precise control of the deposition thickness
  • a uniform and dense film is obtained, but it has a serious problem, and the technique is not applicable to all substrate materials because ALD processes, if ALD The precursor cannot effectively react with the original substrate, and the ALD process cannot continue or nucleate only at specific defects. If there is no uniform nucleation point, the ALD deposited medium can only be an island rather than a uniformly continuous film. If the surface of the inert material lacks dangling bonds, it may cause the above problems. For example, the most commonly used channel material Si (100) surface (hydrogenated) substrate is difficult to deposit uniformly and ultra-thin by ALD.
  • High-k oxide gate dielectrics; high quality graphene and carbon nanotube surfaces can also be difficult to deposit a uniform film by ALD due to the lack of dangling bonds. Studies have shown that the ALD method can only deposit the dielectric on the defects, steps and edges of the graphene (including dangling bonds), and almost no other regions are deposited or randomly deposited into discontinuous islands. The distribution of high-k media on graphene is extremely uneven.
  • the O 3 or NO 2 treatment method causes graphene to cause new, additional defects, resulting in a significant decrease in its properties (eg, carrier mobility).
  • the buffer layer or the Al seed layer may increase the overall thickness of the gate dielectric, and it is difficult to achieve the requirements of high quality ultra-thin gate dielectric.
  • the object of the present invention is to provide a method and application for depositing a high-k gate dielectric on a graphene material, by which ALD can be used for dielectric deposition on a surface of a material without dangling bonds, and continuous, uniform, and dense is obtained.
  • ALD atomic layer deposition
  • a method of depositing a high-k gate dielectric on a graphene material comprising the steps of:
  • the substrate sample is placed in a vacuum chamber of a scanning electron microscope, vacuumed to a range of 5E-4 to 1E-7, and the surface of the substrate sample is scanned with a low-energy focused electron beam for 30 s to 5 min, and the low-energy electron beam acceleration voltage is 1 ⁇ 15kV, the beam size is in the range of 0.05nA to 0.6nA; a thin layer of amorphous carbon film can be deposited on the surface of the substrate sample during the scanning process, and the thickness is in the range of 0.3 nm to 3 nm;
  • the electron beam-treated substrate sample is placed in an ALD device for deposition of a high-k dielectric material, the deposition temperature is between 90 ° C and 300 ° C, and the number of cycles of the reaction is generally in the range of 15 to 255.
  • the residence time after each pulse is between 10s and 100s.
  • the present invention still further provides techniques for depositing a medium in situ directly on the channel of a graphene transistor.
  • Graphene transistor fabrication can be achieved by graphene patterning (by electron beam exposure), source and drain metal electrodes (electron beam exposure, vapor deposition of metal and stripping).
  • Directly depositing a high-k gate dielectric directly in the channel region of the device includes the following steps:
  • the surface of the graphene ie, in the channel region
  • High-k dielectric film
  • the method of the present invention scans the surface of a substrate by a low-energy electron beam.
  • an electron beam interacts with the surface of the graphene or an organic precursor around the surface, and the precursor is organic.
  • the CH and CC bonds in the molecule are broken, so that an amorphous carbon film is deposited on the surface of the graphene, and part of the electrons are adsorbed on the insulating substrate.
  • the surface of the substrate material can provide a uniform nucleation point for the ALD precursor molecules, thereby depositing a uniform and dense dielectric film.
  • this method ensures that the lattice structure of the material is not destroyed and does not cause significant degradation of the electrical properties of the material.
  • the method proposed by the present invention only needs to perform in-situ pretreatment on a portion or region where high-k dielectric needs to be deposited, and is particularly suitable for in-situ, local deposition of high-k dielectrics in graphene devices, such as graphite.
  • the channel region of the olefin transistor, the technology does not affect other regions.
  • the position and size control accuracy of the method can reach nanometer scale ( ⁇ 100 nm).
  • the present invention as an interface pretreatment method can solve the selectivity of ALD to a substrate and a deposition material in a short channel device, so that the applicable range of ALD is greatly increased, thereby requiring preparation in a short channel device. High quality high k medium.
  • Figure 1 shows the process of ALD high-k dielectric after electron beam scanning of a mechanically stripped single-layer graphene sample.
  • AFM surface topography of the original graphene sample (b) Raman spectrum of the graphene sample; (c) AFM topography after electron beam scanning of three square regions of the sample surface; The surface morphology of the sample after deposition of 4 nm HfO 2 medium by ALD.
  • Figure 2 is a representation of the deposit after the surface of the SiO 2 has been scanned by electron beam.
  • (a) is an X-ray photoelectron spectroscopy (XPS) spectrum of the deposit;
  • (b) is a Raman spectrum of the deposit;
  • SEM scanning electron microscope
  • Figure 4 is a comparison of the output current curve and the leakage current curve of the device
  • Figure 5 shows the CV characteristics of the device.
  • Example 1 Peeling single-layer graphene surface ALD deposition high-k medium
  • Graphene was prepared by mechanical stripping using a transparent tape and highly oriented graphite flakes, and the substrate was thermally grown SiO 2 on 300 nm of low resistance silicon.
  • Figure 1 (a) is an AFM surface topography of a mechanically exfoliated single-layer graphene sample; the graphene sample is further characterized by Raman scattering spectroscopy, as shown in Figure 1 (b), the ratio of G peak to 2D peak intensity It is about 1/3 and has no D peak, indicating that the sample is a defect-free single-layer graphene.
  • the sample is subjected to electron beam scanning pretreatment
  • Figure 2 is a representation of the SiO 2 surface after electron beam scanning.
  • Figure 2(a) is an XPS spectrum of the deposit. The results show that the surface material consists of 46.4% carbon, 39.09% oxygen and 14.5% silicon. Since the depth of action of XPS is 5 to 10 nm, the oxygen and silicon elements in the detection result are derived from the SiO 2 substrate under the deposit, and the carbon element is derived from the deposit.
  • Figure 2(b) is a Raman spectrum of the deposit, which is visible from the visible Raman spectrum, which is amorphous carbon.
  • the treated sample was placed in an ALD apparatus for growth of a high-k medium.
  • an Al 2 O 3 material is deposited at 130 ° C.
  • the precursors are trimethyl aluminum and H 2 O, pulsed for 50 cycles, and a chemical reaction occurs after each pulse for 10 s, and the thickness of the deposition is about It is 5 nm.
  • Fig. 1(d) shows the surface morphology of the sample after ALD deposition of 4nm HfO 2 medium.
  • the AFM has obvious difference in the substrate of different parts.
  • a uniform high-k dielectric layer is deposited on the surface.
  • the high-k medium deposited on the surface of the graphene scanned by the electron beam is particularly uniform and has no pinholes, and the graphene region medium which is not scanned by the electron beam forms an island, and does not form a continuous uniformity. Film.
  • Example 2 Stripping multilayer graphene surface ALD deposition high-k medium
  • Graphene was prepared by mechanical stripping using a transparent tape and highly oriented graphite flakes, and the substrate was thermally grown SiO 2 on 300 nm of low resistance silicon.
  • the prepared graphene was observed under an optical microscope for its morphology and color, and the surface flatness and the number of graphite layers were preliminarily determined.
  • the Raman scattering spectrum was further characterized, and the number of graphene layers was determined based on the height ratio of the G peak and the 2D peak, and the surface defects of the graphene were judged based on the height of the D peak.
  • Graphene with multiple layers and no defects was selected as a sample, that is, the ratio of the G peak to the 2D peak of the Raman spectrum was greater than 0.5, and there was no significant D peak.
  • the sample is subjected to electron beam scanning pretreatment
  • a scanning electron beam microscope SEM
  • a low-energy focused electron beam of about 5kv.
  • the scanning time is 2 minutes, and the beam size of the low-energy electron beam is 0.27nA.
  • an amorphous carbon film is deposited on the surface of the sample, and the thickness is 1.2. Within the nm range.
  • the treated sample was placed in an ALD apparatus for growth of a high-k medium.
  • a HfO 2 material was deposited at 130 ° C.
  • the precursor was an Hf source organic material and H 2 O.
  • the pulse was cycled for 86 cycles, and a chemical reaction occurred for 30 seconds after each pulse, and the deposited thickness was about 10 nm.
  • the growth medium was characterized by experimental means. The morphology of the surface of the medium was observed by scanning electron microscopy (SEM). It was found that the high-k medium deposited on the surface of the graphene scanned by the electron beam was particularly uniform and free of pinholes, and the graphene region medium not scanned by the electron beam formed a medium. An island that does not form a continuous uniform film.
  • Example 3 ALD deposition of high-k dielectric on CVD graphene
  • Graphene is grown by CVD under copper catalysis, and a uniform single-layer graphene is obtained by a PMMA wet transfer process.
  • the prepared graphene was observed under an optical microscope for its morphology and color, and the surface uniformity of graphene was preliminarily determined.
  • the Raman scattering spectrum was further characterized, and the number of graphene layers was determined based on the height ratio of the G peak and the 2D peak, and the surface defects of the graphene were judged based on the height of the D peak.
  • a single layer and no defect graphene was selected as the sample, that is, the ratio of the G peak to the 2D peak of the Raman spectrum was about 0.5, and there was no significant D peak.
  • the sample is subjected to electron beam scanning pretreatment
  • a scanning electron beam microscope SEM
  • a low-energy focused electron beam of about 2kv.
  • the scanning time is 1 minute, and the beam size of the low-energy electron beam is 0.13nA.
  • An amorphous carbon film is deposited on the surface of the sample during scanning, and the thickness is 1nm. .
  • the treated sample was placed in an ALD apparatus for growth of a high-k medium.
  • a HfO 2 material was deposited at 250 ° C.
  • the precursor was an Hf source organic material and H 2 O.
  • the pulse was cycled for 70 cycles, and a chemical reaction occurred for 5 seconds after each pulse, and the deposited thickness was about 4 nm.
  • Embodiment 4 Depositing a high-k gate dielectric in a channel portion of a graphene transistor
  • a uniform graphene sample was obtained by mechanical lift-off on the substrate by thermally growing SiO 2 on the low-resistance silicon as a substrate.
  • the method of electron beam exposure is used to complete the definition of graphene and the source and drain electrodes, and the metal is evaporated and stripped. Therefore, the preparation of the source and drain metal electrodes is completed, and the source and drain electrodes are the channel regions of the transistors.
  • the acceleration voltage of the scanning electron is about 5kV
  • the scanning time is 3min
  • the beam size of the low-energy electron beam is 0.27nA
  • the upper surface of the channel region is deposited during the scanning process.
  • the Al 2 O 3 material was deposited at 90 ° C.
  • the precursors were trimethyl aluminum and H 2 O, and the pulse was cycled for 100 cycles.
  • a chemical reaction occurred for 60 s after each pulse, and the thickness of the deposition was about 10 nm. Therefore, a dense and uniform dielectric material is obtained in the channel region. As shown in Fig. 3, the square area is the treated channel surface, and a uniform and dense dielectric material is deposited, and other areas are many islands.
  • the sample is made into a top-gate MOS device, and the gate leakage current is measured on the order of fA, and the measured CV curve indicates the effective thickness.
  • the EOT is small and accurately calculated to be 2 nm, so the dielectric constant of the dielectric HfO 2 is about 20.
  • Figure 4 is a comparison of the output current curve and the leakage current curve of the device.
  • Figure 5 shows the CV characteristic curve of the device, which shows that the medium deposited by the method is not only uniform in surface morphology, but also has a particularly small leakage current, which is an ideal gate dielectric material.

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Abstract

发明公开了一种在石墨烯材料上淀积高k栅介质的方法及应用，属于集成电路技术领域，该方法首先选取表面平整、无缺陷或少缺陷的石墨烯材料作为淀积高k介质的基底样品；将基底样品放入扫描电子显微镜的真空腔室，抽真空至5E-4至1E-7范围，用低能量的聚焦电子束扫描基底样品表面30s至5min，低能电子束加速电压为1～15kV；扫描过程中在基底样品表面淀积上一薄层无定形碳薄膜，厚度在0.3nm至3nm范围内；将电子束处理过的基底样品放入ALD装置中，进行高k介质材料的淀积。本发明可在无悬挂键的材料表面照样利用ALD进行介质淀积，并获得连续、均匀、致密的高质量材料，大大扩展ALD的适用范围。

Description

在石墨烯材料上淀积高k栅介质的方法及应用 技术领域
本发明属于集成电路技术领域，具体涉及在石墨烯材料表面或基于石墨烯材料的器件结构上淀积高k栅介质的方法。
背景技术
在基于碳纳米管、石墨烯和类石墨烯材料的场效应晶体管(FET)和射频场效应晶体管(RF-FET)的制备工艺中，栅介质的制备是一个关键工艺，高性能的FET和RF-FET需要有高质量、超薄的栅介质为前提。原子层沉积(ALD)是淀积高k栅介质最常用的方法，它具有淀积质量高、淀积厚度精确可控等优势。ALD是利用自限制表面化学反应，将绝缘介质材料以原子尺度厚度逐层淀积至目标基底表面的。淀积过程中，ALD反应的前躯体以气相脉冲形式交替进入反应腔，ALD之所以能够精确控制淀积介质的厚度，是因为它具有反应自限制性，即每一次的前躯体脉冲进入反应腔，吸附到材料表面发生化学反应时，只能与表面的那层物质发生反应，反应结束就会自动停止，并释放出吸附的多余前躯体。以Al2O3的ALD为例，前躯体一般是TMA(三甲基铝)和H2O，反应化学方程式可以写为2Al(CH3)3+3H2O→Al2O3+3CH4ΔH＝-376kcal。
虽然通过ALD的方法可以实现淀积厚度的原子级精确控制，获得均匀致密的薄膜，然而它却存在一个严重问题，该技术并不适用于所有的衬底材料，因为ALD过程中，如果ALD的前驱体不能有效地与原始基底反应，那么ALD过程就不能继续下去或者只在特定的缺陷处成核生长。如果没有均匀的成核点，ALD淀积的介质只能是一个个岛状物，而不是均匀连续的薄膜。若惰性材料表面缺乏悬挂键，就有可能会导致上述问题出现，例如：最常用的沟道材料Si(100)面(氢化)衬底就很难通过ALD的方法淀积上均匀而超薄的高k氧化物栅介质；高质量的石墨烯和碳纳米管表面也会因为缺乏悬挂键而难以通过ALD淀积上均匀的薄膜。研究表明，用ALD的方法只能在石墨烯的缺陷、台阶以及边缘处(含悬挂键)淀积上介质，其它区域几乎没有介质淀积上去或随机淀积成不连续的岛状物，从而使石墨烯上的高k介质分布极不均匀。
针对此问题，最近几年研究人员提出来若干种预处理的方法，使得石墨烯表面可通过ALD技术获得均匀的高k介质。这些方法主要有：
(1)利用有机聚合物作缓冲层(Farmer,D.B.,et al.,NANO LETTERS,2009.9(12))；(2) 淀积1～2nm Al种子层(Kim,S.,et al.,APPLIED PHYSICS LETTERS,2009.94(0621076))；(3)O3或者NO2气体处理(Jandhyala,S.,et al.,ACS Nano,2012.6(3):p.2722-2730),
但这些预处理方法都存在一定的问题：
(1)它们都不能精确控制对石墨烯表面预处理的具体位置，只能对整个硅片或整片石墨烯薄膜进行整体处理，这必然会对后续工艺过程造成一定的影响。
(2)O3或NO2处理的方法会使石墨烯造成新的、额外的缺陷，使得其性能(例如：载流子迁移率)显著降低。
(3)缓冲层或Al种子层会使得栅介质的整体厚度增加，难以达到高质量超薄栅介质的要求。
发明内容
本发明的目的在于提出一种在石墨烯材料上淀积高k栅介质的方法及应用，利用该方法可在无悬挂键的材料表面照样利用ALD进行介质淀积，并获得连续、均匀、致密的高质量材料，大大扩展ALD的适用范围。
本发明的技术方案如下：
一种在石墨烯材料上淀积高k栅介质的方法，包括以下步骤：
(1)选取表面平整、无缺陷或少缺陷的石墨烯材料作为淀积高k介质的基底样品；
(2)将基底样品放入扫描电子显微镜的真空腔室，抽真空至5E-4至1E-7范围，用低能量的聚焦电子束扫描基底样品表面30s至5min，低能电子束加速电压为1～15kV，束流大小在0.05nA至0.6nA范围之内；扫描过程中可在基底样品表面沉积上一薄层无定形碳薄膜，厚度在0.3nm至3nm范围内；
(3)将电子束处理过的基底样品放入ALD装置中，进行高k介质材料的淀积，淀积温度在90℃至300℃之间，循环反应圈数一般在15到255范围内，每次脉冲之后停留时间在10s到100s之间。
本发明还进一步提供了直接在石墨烯晶体管的沟道上原位沉积介质的技术。石墨烯晶体管制备可通过石墨烯图形化(利用电子束曝光进行)、源和漏金属电极(电子束曝光、蒸镀金属并剥离)实现。在器件的沟道区域上直接原位淀积高k栅介质包括以下步骤：
(1)将石墨烯晶体管放入扫描电子显微镜的真空腔室，抽真空至5E-4至1E-7范围，用低能量的聚焦电子束扫描沟道区域表面30s至5min，低能电子束加速电压为1～15kV；扫描过 程中在沟道区域表面沉积上一层无定形碳薄膜，厚度在0.3nm至3nm范围内；沟道内的扫描区域或沉积上一层无定形碳薄膜的区域，其区域的位置、尺度可通过电子显微镜精确控制；
(2)低能电子束处理后放入ALD装置中，进行高k介质材料的淀积，即可在经上述低能电子束预处理后石墨烯表面(即在沟道区域内的)获得致密、均匀的高k介质薄膜。
本发明的技术效果如下：
(1)本发明通过低能电子束扫描基底表面的方法，石墨烯样品在电子束下扫描时，电子束与石墨烯表面或表面周围的有机物前驱体之间会发生相互作用，并使前驱体有机分子中C-H、C-C键断裂，从而在石墨烯表面沉积沉积一层无定形碳薄膜，同时部分电子被吸附在绝缘衬底上。经过这一步处理，衬底材料表面就能为ALD前驱体分子提供均匀的成核点，从而淀积上均匀而致密的介质薄膜。并且，此方法可以确保不破坏材料晶格结构，不会造成材料电学性能的显著退化。
(2)本发明所提出的方法只需要对需要淀积高k介质的部位或区域进行原位预处理，特别适用于在石墨烯器件中进行原位、局部淀积高k介质，例如：石墨烯晶体管的沟道区，本技术不会影响其它区域。本方法的位置和尺寸控制精度可以达到纳米尺度(<100nm)。
(3)本发明作为一种界面预处理方法，可以解决短沟道器件中ALD对衬底和淀积材料的选择性，使得ALD的适用范围大大增加，从而在短沟道器件中制备所需要的高质量高k介质。
附图说明
图1为机械剥离的单层石墨烯样品经过电子束扫描后ALD高k介质的过程。(a)原始石墨烯样品的AFM表面形貌图；(b)该石墨烯样品的拉曼光谱图；(c)样品表面的三个方形区域经过电子束扫描之后的AFM形貌图；(d)经ALD沉积4nm HfO2介质后的样品表面形貌。
图2是SiO2表面经过电子束扫描之后的沉积物表征。(a)是沉积物的X射线光电子能谱(XPS)能谱图；(b)是沉积物的Raman光谱图；
图3为利用本发明技术原位制备石墨烯晶体管的栅介质的扫描电子显微镜(SEM)图；
图4为器件的输出电流曲线和漏电流曲线的比较；
图5为器件的CV特性曲线。
具体实施方式
下面通过实例对本发明做进一步说明。需要注意的是，公布实施例的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。
实施例一：剥离单层石墨烯表面ALD淀积高k介质
一、制备石墨烯材料
利用透明胶带和高取向石墨鳞片，用机械剥离法制备石墨烯，衬底为低阻硅上300nm热生长SiO2。
石墨烯材料的表征：
将制备好的石墨烯在光学显微镜下观察其形貌和颜色，初步判定其表面平整度和石墨层数。图1(a)为机械剥离的单层石墨烯样品的AFM表面形貌图；该石墨烯样品经拉曼散射光谱进一步表征，如图1(b)所示，G峰和2D峰强度之比约为1/3，且没有D峰，说明该样品是无缺陷的单层石墨烯。
二、对样品进行电子束扫描预处理
将样品放入扫描电子束显微镜(SEM)的真空腔室，抽真空至5E-4至1E-7范围，在显微镜下找到要处理的样品表面的具体位置，选取电子扫描框放到需要处理的位置。然后用1kV的低能聚焦电子束对样品表面进行扫描，扫描时间为2分钟,低能电子束的束流大小在0.06nA，图1(c)样品表面的三个方形区域经过电子束扫描之后的AFM形貌图，被扫描过的三个区域表面均有一层沉积物，该沉积物的厚度在1.5nm；
为确定该沉积物的物质，进行了X射线光电子能谱(XPS)和Raman光谱分析，直接在SiO2表面进行电子束扫描，并确定经电子束扫描后的沉积物。图2是SiO2表面经过电子束扫描之后对沉积物的表征。图2(a)是沉积物的XPS能谱图，检测结果显示表面物质由46.4％的碳元素、39.09％的氧元素和14.5％硅元素组成。由于XPS的作用深度为5～10nm，因而检测结果中的氧元素和硅元素来自于沉积物下面的SiO2衬底，而碳元素则来自于沉积物。图2(b)是沉积物的Raman光谱图，从可见Raman光谱图可见，此沉积物是无定型碳。
三、ALD淀积高k介质
将处理过的样品放入ALD装置，进行高k介质的生长。本实例是在130℃的条件下淀积Al2O3材料，前驱体是三甲基铝和H2O，脉冲循环50圈，每次脉冲之后停留10s时间发生化学反应，淀积的厚度大约为5nm。
对淀积介质的样品做表征：
图1(d)经ALD沉积4nm HfO2介质后的样品表面形貌，AFM在不同部位的衬底区别明显，经低能电子束预处理区域后，其表面淀积了均匀的高k介质层，而未经低能电子束预处理的石墨烯表面没有连续的介质。而且还可发现，经电子束扫描过的石墨烯表面淀积的高k介质特别均匀，且无针孔，而没有被电子束扫描的石墨烯区域介质形成一个个岛状物，没有形成连续均匀的薄膜。
实施例二：剥离多层石墨烯表面ALD淀积高k介质
一、制备石墨烯材料。
利用透明胶带和高取向石墨鳞片，用机械剥离法制备石墨烯，衬底为低阻硅上300nm热生长SiO2。
石墨烯材料的表征：
将制备好的石墨烯在光学显微镜下观察其形貌和颜色，初步判定其表面平整度和石墨层数。用拉曼散射光谱做进一步表征，根据G峰和2D峰的高度比值来判定石墨烯的层数，根据D峰高度判断石墨烯表面缺陷的情况。选取多层且没有缺陷的石墨烯作为样品，即拉曼光谱的G峰和2D峰之比大于0.5，同时没有明显的D峰。
二、对样品进行电子束扫描预处理
将样品放入扫描电子束显微镜(SEM)的真空腔室，抽真空至5E-4至1E-7范围，在显微镜下找到要处理的样品表面的具体位置，选取电子扫描框放到需要处理的位置。然后用5kv左右的低能聚焦电子束对样品表面进行扫描，扫描时间为2分钟,低能电子束的束流大小在0.27nA，扫描过程中在样品表面沉积上一层无定形碳薄膜，厚度在1.2nm范围内。
三、ALD淀积高k介质
将处理过的样品放入ALD装置，进行高k介质的生长。本实例是在130℃的条件下淀积HfO2材料，前驱体是Hf源有机物和H2O，脉冲循环86圈，每次脉冲之后停留30s时间发生化学反应，淀积的厚度大约为10nm。
对淀积介质的样品做表征：
ALD高k介质之后，用实验手段表征生长的介质是否均匀。用扫描电子显微镜(SEM)观察介质表面的形貌，发现用电子束扫描过的石墨烯表面淀积的高k介质特别均匀且无针孔，而没有被电子束扫描的石墨烯区域介质形成一个个岛状物，没有形成连续均匀的薄膜。
实施例三：CVD石墨烯上ALD淀积高k介质
一、制备石墨烯材料
在铜箔催化下，进行CVD生长石墨烯，并利用PMMA湿法转移的过程，得到均匀的单层石墨烯。
石墨烯材料的表征：
将制备好的石墨烯在光学显微镜下观察其形貌和颜色，初步判定石墨烯表面均匀性。用拉曼散射光谱做进一步表征，根据G峰和2D峰的高度比值来判定石墨烯的层数，根据D峰高度判断石墨烯表面缺陷的情况。选取单层且没有缺陷的石墨烯作为样品，也就是拉曼光谱的G峰和2D峰之比约为0.5，同时没有明显的D峰。
二、对样品进行电子束扫描预处理
将样品放入扫描电子束显微镜(SEM)的真空腔室，抽真空至5E-4至1E-7范围，在显微镜下找到要处理的样品表面的具体位置，选取电子扫描框放到需要处理的位置。然后用2kv左右的低能聚焦电子束对样品表面进行扫描，扫描时间为1分钟,低能电子束的束流大小在0.13nA，扫描过程中在样品表面沉积上一层无定形碳薄膜，厚度在1nm。
三、ALD淀积高k介质
将处理过的样品放入ALD装置，进行高k介质的生长。本实例是在250℃的条件下淀积HfO2材料，前驱体是Hf源有机物和H2O，脉冲循环70圈，每次脉冲之后停留5s时间发生化学反应，淀积的厚度大约为4nm。
对淀积介质的样品做表征：
ALD高k介质之后，用实验手段表征生长的介质是否均匀，以及漏电流的量级。用扫描电子显微镜(SEM)观察介质表面的形貌，发现用电子束扫描过的石墨烯表面淀积的高k介质特别均匀且无针孔，而没有被电子束扫描的石墨烯区域介质形成一个个岛状物，没有形成连续均匀的薄膜。
实施例四：石墨烯晶体管沟道部位淀积高k栅介质
一、制备石墨烯材料
利用低阻硅上热生长SiO2作为衬底，在衬底上通过机械剥离法得到均匀的石墨烯样品。
二、图形化与源漏电极制备
用电子束曝光的方法完成石墨烯图形化与源漏电极的定义，蒸金属并剥离，因此完成了源漏金属电极的制备，源漏电极之间即为晶体管的沟道区域。
三、沟道区预处理
在沟道区用低能电子束(如SEM)扫描，扫描电子的加速电压约为5kV，扫描时间在3min，低能电子束的束流大小0.27nA，扫描过程中在沟道区域上表面沉积上一层无定形碳薄膜，厚度在1.8nm。
四、ALD淀积高k介质
在90℃的条件下淀积Al2O3材料，前驱体是三甲基铝和H2O，脉冲循环100圈，每次脉冲之后停留60s时间发生化学反应，淀积的厚度大约为10nm。因此在沟道区得到致密均匀的介质材料。如图3所示，正方形区域为处理后的沟道表面，淀积上均匀而致密介质材料，其他区域则是很多岛状物。
五、制备顶栅器件
利用该高质量的高k氧化物作为石墨烯场效应晶体管(GFET)的栅介质，接着将该样品做成顶栅MOS器件，测得栅极漏电流在fA量级，测量CV曲线表明有效厚度EOT较小，精确计算为2nm，因此介质HfO2的相对介电常数约为20。图4为器件的输出电流曲线和漏电流曲线的比较，图5为器件的CV特性曲线，表明该方法沉积的介质不但表面形貌均匀，而且漏电流特别小，是非常理想的栅介质材料。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (5)

  1. 一种在石墨烯材料上淀积高k栅介质的方法，包括以下步骤：
    (1)选取表面平整的石墨烯材料作为淀积高k介质的基底样品；
    (2)将基底样品放入扫描电子显微镜的真空腔室，抽真空至5E-4至1E-7范围，用低能量的聚焦电子束扫描基底样品表面30s至5min，低能电子束加速电压为1～15kV；扫描过程中在基底样品表面沉积上一层无定形碳薄膜，厚度在0.3nm至3nm范围内；
    (3)将电子束处理过的基底样品放入ALD装置中，进行高k介质材料的淀积。
  2. 如权利要求1所述的制备方法，其特征在于，步骤(2)中低能电子束的束流大小在0.05nA至0.6nA之间。
  3. 如权利要求1所述的制备方法，其特征在于，步骤(3)中淀积温度在90℃至300℃之间，淀积的循环反应圈数在15到255范围内，每次脉冲之后停留时间在10s到100s之间。
  4. 如权利要求1所述的制备方法，其特征在于，步骤(3)中淀积的高k介质材料厚度介于2nm至30nm之间。
  5. 如权利要求1所述方法在制备场效应晶体管中的应用。
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