WO2015146667A1

WO2015146667A1 - Capacitor

Info

Publication number: WO2015146667A1
Application number: PCT/JP2015/057663
Authority: WO
Inventors: 秀俊増田
Original assignee: 太陽誘電株式会社
Priority date: 2014-03-28
Filing date: 2015-03-16
Publication date: 2015-10-01
Also published as: JP6218660B2; JP2015192083A

Abstract

[Problem] To provide a porous capacitor such that occurrences of short circuit faults caused by formation of hydrates in a dielectric layer can be prevented. [Solution] The capacitor is equipped with a dielectric layer, through-holes, a first external electrode layer, a second external electrode layer, first internal electrodes, and second internal electrodes. The dielectric layer is formed by way of anodization of a metal. The through-holes are a plurality of through-holes which provide communication between a first surface of the dielectric layer and a second surface on the opposite side from the first surface. The first external electrode layer is disposed on the first surface. The second external electrode layer is disposed on the second surface and comprises a facing region which faces the first external electrode layer across the dielectric layer and a non-facing region which does not face the first external electrode layer. The first internal electrodes are formed on a portion of the plurality of through-holes, are connected to the first external electrode layer, and are spaced apart from the second external electrode layer. The second internal electrodes are formed on another portion of the plurality of through-holes, are connected to the second external electrode layer, and are spaced apart from the first external electrode layer.

Description

Capacitor

The present invention relates to a porous capacitor.

Recently, a porous capacitor has been developed as a new type of capacitor. Porous capacitors use a property that a metal oxide formed on a metal surface such as aluminum forms a porous (through-hole) structure, forms an internal electrode in the porous, and uses the metal oxide as a dielectric. It is a capacitor. Such a capacitor can be reduced in size and height as compared with a conventional multilayer capacitor, and the demand for mobile communication devices with higher frequency is increasing.

External conductors are laminated on the front and back surfaces of the dielectric, and the internal electrodes formed in the porous are connected to either the external conductor on the front surface or the external conductor on the back surface. The external conductor on the side not connected to the internal electrode is insulated by a gap or an insulating material. Thereby, an internal electrode functions as a counter electrode (a positive electrode or a negative electrode) which opposes via a dielectric.

For example, Patent Document 1 and Patent Document 2 disclose a porous capacitor having such a configuration. In any of the patent documents, an internal electrode is formed in a porous body, one end of the internal electrode is connected to one conductor, and the other end is insulated from the other conductor.

Japanese Patent No. 4493686 JP 2009-76850 A

When a porous capacitor using aluminum oxide as a dielectric is exposed to a humidity environment, a hydration reaction proceeds, and the dielectric material constituting the dielectric changes into a hydrate. Since the hydrate is inferior in insulation, when the hydrate is formed so as to straddle the positive and negative internal electrodes at the periphery of the external conductor, the external conductors laminated on the front and back of the dielectric are electrically connected to each other. Therefore, there is a problem of causing a short circuit failure of the capacitor.

Usually, in order to avoid short-circuit failure due to hydrates, porous capacitors cover external conductors with a protective layer that is slightly larger than external conductors, and prevent moisture from penetrating into the dielectric layer at the periphery of external conductors. It has a structure to prevent. However, even in this configuration, if there is a pinhole or the like in the protective layer, there is a problem that the humidity that has entered from the pinhole reaches the dielectric at the peripheral portion of the external conductor, resulting in a short circuit failure.

In view of the above circumstances, an object of the present invention is to provide a porous capacitor capable of preventing the occurrence of a short circuit failure due to the formation of hydrates in a dielectric layer.

In order to achieve the above object, a capacitor according to an embodiment of the present invention includes a dielectric layer, a first external electrode layer, a second external electrode layer, a first internal electrode, and a second internal electrode. Electrode.
The dielectric layer is formed by metal anodization, and has a first surface and a second surface opposite to the first surface, and the first surface and the second surface are A plurality of through holes communicating with each other are provided.
The first external electrode layer is disposed on the first surface.
The second external electrode layer is disposed on the second surface, and is opposed to the first external electrode layer via the dielectric layer, and the first external via the dielectric layer. A non-opposing region that does not face the external electrode layer.
The first internal electrode is formed in a part of the plurality of through holes, connected to the first external electrode layer, and separated from the second external electrode layer.
The second internal electrode is formed in another part of the plurality of through holes, connected to the second external electrode layer, and separated from the first external electrode layer.

According to this configuration, the first internal electrode and the second internal electrode facing each other through the dielectric layer function as the counter electrode of the capacitor. The first internal electrode is connected to the first external electrode layer, and the second internal electrode is connected to the second external electrode layer, and is connected to the outside (connection terminal or the like) through these. Here, when the capacitor is exposed to a high humidity environment, the dielectric material may undergo a hydration reaction and a hydrate may be generated. Since the hydrate is inferior in insulation, when the hydrate is formed so as to straddle the positive and negative internal electrodes at the periphery of the external electrode layer, the external electrode layers respectively disposed on the front and back of the dielectric layer are electrically connected to each other. As a result, a short circuit failure of the capacitor may occur. Even in such a case, the second external electrode layer is configured to have a region (non-opposite region) that does not oppose a region (opposite region) that faces the first external electrode layer via the dielectric layer. Thus, even if a hydrate is generated at the peripheral portion of the dielectric layer, the external electrode layers are not electrically connected to each other through the internal electrodes, and it is possible to prevent a short circuit failure of the capacitor.

The first external electrode layer includes a facing region that faces the second external electrode layer via the dielectric layer, and a non-facing region that does not face the second external electrode layer via the dielectric layer. You may have.

According to this configuration, since a region where a short circuit does not occur via the internal electrode even if a hydrate is formed is formed on both the first surface and the second surface, the probability of occurrence of a short circuit failure on both surfaces is reduced. It becomes possible to reduce.

The counter area may be surrounded by the non-opposite area.

When the facing region is surrounded by the non-facing region, a region where a short circuit between the first internal electrode and the second internal electrode occurs due to the hydrate is only on the first surface side of the dielectric layer. For this reason, when the capacitor is mounted on the substrate, the first surface side is mounted on the substrate side, and underfill is applied to prevent moisture from entering the first surface side. Hydrate formation on the surface side can be prevented. Since the second surface side is prevented from conducting by the hydrate as described above, it is possible to prevent the occurrence of a short circuit failure and to further improve the reliability of the capacitor.

The width of the non-facing region may be 0.1 μm or more and 100 μm or less.

According to this configuration, by setting the width of the non-facing region to 0.1 μm or more and 100 μm or less, it is possible to reduce the probability of a short circuit failure while securing the capacitance of the capacitor.

An insulating material may be filled between the first internal electrode and the second external electrode layer and between the second internal electrode and the first external electrode layer.

According to this configuration, it is possible to ensure insulation between the first internal electrode and the second external electrode layer and between the second internal electrode and the first external electrode layer by filling the insulating material. is there.

The dielectric layer may be made of a material that forms a porous layer by self-organization when anodized.

According to this configuration, a dielectric layer having a through hole (porous) can be formed by anodizing the material.

The dielectric layer may be made of aluminum oxide formed by anodic oxidation of aluminum.

Aluminum oxide produced when anodizing aluminum produces through-holes due to self-organization during the oxidation process. That is, a dielectric layer having a through hole can be formed by anodizing aluminum.

According to the present invention, it is possible to provide a porous capacitor capable of preventing the occurrence of a short circuit failure due to the formation of hydrates in the dielectric layer.

1 is a perspective view of a capacitor according to the present invention. It is sectional drawing of the same capacitor. It is a perspective view of the dielectric material layer with which the same capacitor is provided. It is sectional drawing of the dielectric material layer with which the same capacitor | condenser is provided. It is sectional drawing which shows a part of structure of the capacitor | condenser. It is a perspective view which shows a part of structure of the capacitor | condenser. It is sectional drawing which shows a part of structure of the capacitor | condenser. It is sectional drawing which shows a part of structure of the capacitor | condenser. It is a perspective view which shows a part of structure of the capacitor | condenser. It is a perspective view which shows a part of structure of the capacitor | condenser. It is sectional drawing which shows a part of structure of the capacitor | condenser. It is a top view which shows a part of structure of the capacitor | condenser. It is a top view which shows a part of structure of the capacitor | condenser. It is a schematic diagram which shows the variation of the structure in the capacitor | condenser. It is a schematic diagram which shows the variation of the structure in the capacitor | condenser. It is a schematic diagram which shows the variation of the structure in the capacitor | condenser. It is a schematic diagram which shows the variation of the structure in the capacitor | condenser. It is sectional drawing of the capacitor | condenser which concerns on the comparative example of this invention. It is an expansion perspective view of the same capacitor. It is an expansion perspective view of the same capacitor. It is sectional drawing which shows a part of structure of the capacitor | condenser. It is an expansion perspective view of the capacitor concerning the present invention. It is sectional drawing which shows a part of structure of the capacitor | condenser. It is sectional drawing which shows a part of structure of the capacitor | condenser. It is a schematic diagram which shows the mounting aspect in the capacitor | condenser. It is a schematic diagram which shows the manufacturing process of the same capacitor. It is a schematic diagram which shows the manufacturing process of the same capacitor. It is a schematic diagram which shows the manufacturing process of the same capacitor. It is a schematic diagram which shows the manufacturing process of the same capacitor. It is a schematic diagram which shows the manufacturing process of the same capacitor. It is a schematic diagram which shows the manufacturing process of the same capacitor. It is a schematic diagram which shows the manufacturing process of the same capacitor.

[Configuration of capacitor]
FIG. 1 is a perspective view of a capacitor 100 according to the present embodiment, and FIG. 2 is a cross-sectional view of the capacitor 100. As shown in these drawings, the capacitor 100 includes a dielectric layer 101, a first internal electrode 102, a second internal electrode 103, a first external electrode layer 104, a second external electrode layer 105, a first protective layer 106, a first protective layer 106, 2 includes a protective layer 107, a first external terminal 114, and a second external terminal 115.

The dielectric layer 101 functions as a dielectric of the capacitor 100. FIG. 3 is a perspective view of the dielectric layer 101, and FIG. 4 is a cross-sectional view of the dielectric layer 101. The dielectric layer 101 is a dielectric material, and a material that forms a porous (pore) by self-organization can be used. As such a material, aluminum oxide (Al ₂ O ₃ ) can be given. The thickness of the dielectric layer 101 is not particularly limited, but can be, for example, several μm to several hundred μm.

As shown in FIGS. 3 and 4, the dielectric layer 101 has a plurality of through holes 101a. When the surface parallel to the layer surface direction of the dielectric layer 101 is a first surface 101b and the opposite surface is a second surface 101c, the through hole 101a is perpendicular to the first surface 101b and the second surface 101c. The first surface 101b and the second surface 101c are formed so as to communicate with each other (in the thickness direction of the dielectric layer 101). The number and size of the through holes 101a shown in FIG. 3 and the like are for convenience, and the actual ones are smaller and more in number. Moreover, the through-hole 101a may have a branch, and may merge with the adjacent through-hole 101a. Further, the side surface of the dielectric layer 101 with respect to the first surface 101b and the second surface 101c is referred to as a side surface 101d.

The first internal electrode 102 functions as one counter electrode of the capacitor 100. FIG. 5 is a cross-sectional view illustrating a configuration of a part of the capacitor 100. The first internal electrode 102 is made of a conductive material such as pure metals such as In, Sn, Pb, Cd, Bi, Al, Cu, Ni, Au, Ag, Pt, Pd, Co, Cr, Fe, and Zn. It can consist of alloys.

As shown in FIG. 5, the first internal electrode 102 is connected to the first external electrode layer 104 and is separated from the second external electrode layer 105. An insulator 102a made of an insulating material is formed between the first internal electrode 102 and the second external electrode layer 105 as shown in FIG. Further, the insulator 102 a may be a gap provided between the first internal electrode 102 and the second external electrode layer 105.

Here, not all of the first internal electrodes 102 are connected to the first external electrode layer 104, but the first internal electrode 102 is located in a region where the first external electrode layer 104 is not disposed on the first surface 101b. The first internal electrode 102 is not connected to the first external electrode layer 104. The arrangement area of the first external electrode layer 104 will be described later.

The second internal electrode 103 functions as the other counter electrode of the capacitor 100. The second internal electrode 103 is made of a conductive material such as pure metals such as In, Sn, Pb, Cd, Bi, Al, Cu, Ni, Au, Ag, Pt, Pd, Co, Cr, Fe, Zn, and the like. It can consist of alloys.

As shown in FIG. 5, the second internal electrode 103 is connected to the second external electrode layer 105 and is separated from the first external electrode layer 104. Between the second internal electrode 103 and the first external electrode layer 104, an insulator 103a made of an insulating material is formed as shown in FIG. The insulator 103a may be a gap provided between the second internal electrode 103 and the first external electrode layer 104.

Here, not all of the second internal electrodes 103 are connected to the second external electrode layer 105, but are located in a region where the second external electrode layer 105 is not provided on the second surface 101c. The second internal electrode 103 is not connected to the second external electrode layer 105. The arrangement region of the second external electrode layer 105 will be described later.

Although the first internal electrodes 102 and the second internal electrodes 103 are shown to be alternately arranged in FIG. 5, they are not necessarily alternate and may be randomly arranged. First internal electrode 10
This is because a capacitor is formed if the second internal electrode 103 and the second internal electrode 103 are disposed to face each other with the dielectric layer 101 interposed therebetween. The number of the first internal electrodes 102 and the number of the second internal electrodes 103 may not be the same, but it is preferable to make them equal because the capacitance of the capacitor increases.

The first external electrode layer 104 is disposed on the first surface 101b as shown in FIG. The first external electrode layer 104 is a conductive material, for example, a pure metal such as Cu, Ni, Cr, Ag, Pd, Fe, Sn, Pb, Pt, Ir, Rh, Ru, Al, Ti, or an alloy thereof. Can be. The thickness of the first external electrode layer 104 can be several tens of nm to several μm, for example. In addition, the first external electrode layer 104 may be disposed so that a plurality of layers of conductive materials are laminated.

As shown in FIG. 2, the first external electrode layer 104 electrically connects the first internal electrode 102 and the first external terminal 114. FIG. 6 is a perspective view showing the first external electrode layer 104. As shown in FIGS. 5 and 6, the first external electrode layer 104 only needs to be disposed on at least the first surface 101 b, and does not have to cover the entire first surface 101 b.

The second external electrode layer 105 is disposed on the second surface 101c as shown in FIG. The second external electrode layer 105 is a conductive material, for example, a pure metal such as Cu, Ni, Cr, Ag, Pd, Fe, Sn, Pb, Pt, Ir, Rh, Ru, Al, Ti, or an alloy thereof. Can be. The thickness of the second external electrode layer 105 can be several tens of nm to several μm, for example. Further, the second external electrode layer 105 may be disposed so that a plurality of layers of conductive materials are laminated.

As shown in FIG. 2, the second external electrode layer 105 electrically connects the second internal electrode 103 and the second external terminal 115. FIG. 7 is a perspective view showing the second external electrode layer 105. As shown in FIGS. 5 and 7, the second external electrode layer 105 only needs to be disposed on at least the second surface 101 c, and may not be configured to cover the entire second surface 101 c.

Here, the first external electrode layer 104 and the second external electrode layer 105 are not completely opposed to each other, and partial regions of the first external electrode layer 104 and the second external electrode layer are opposed to each other. Not. The arrangement region of the first external electrode layer 104 and the second external electrode layer 105 will be described later.

As shown in FIG. 2, the first protective layer 106 covers the first external electrode layer 104 and insulates the first external electrode layer 104 and the second external terminal 115 from each other. FIG. 8 is a cross-sectional view showing a configuration of a part of the capacitor 100, and FIG. 9 is a perspective view showing the first protective layer 106. The first protective layer 106 is disposed on the first surface 101 b and further disposed on the first external electrode layer 104. As shown in FIGS. 8 and 9, the first protective layer 106 has an opening 106a formed on the first external electrode layer 104, and the first external electrode layer 104 is exposed from the opening 106a. . The shape, size, and number of the openings 106a are not particularly limited.

As shown in FIG. 2, the second protective layer 107 covers the second external electrode layer 105 and insulates the second external electrode layer 105 from the first external terminal 114. FIG. 10 is a perspective view showing the second protective layer 107. The second protective layer 107 is disposed on the second surface 101 c and further disposed on the second external electrode layer 105. As shown in FIGS. 8 and 10, the second protective layer 107 has an opening 107a formed on the second external electrode layer 105, and the second external electrode layer 105 is exposed from the opening 107a. . The shape, size, and number of the openings 107a are not particularly limited.

The first protective layer 106 and the second protective layer 107 are made of an insulating material, and a material particularly excellent in moisture resistance is suitable. As an index of moisture resistance, those having a hygroscopicity of 2% or less and a moisture permeability of 1 mg / mm ² or less per 1 μm thickness are suitable. Such materials include epoxy resins,
Mention may be made of silicone resins, polyimide resins or polyolefin resins.

The first external terminal 114 functions as a terminal of the first internal electrode 102. As shown in FIGS. 1 and 2, the first external terminal 114 is disposed on the first protective layer 106, the second protective layer 107, and the first external electrode layer 104, and is connected to the first protective layer 106 and the first protective layer 106. Two protective layers 107 are disposed on the side surface 101d. The first external terminal 114 is electrically connected to the first internal electrode 102 via the first external electrode layer 104, that is, functions as a terminal for connecting the first internal electrode 102 and the outside.

The second external terminal 115 functions as a terminal of the second internal electrode 103. As shown in FIGS. 1 and 2, the second external terminal 115 is disposed on the first protective layer 106, the second protective layer 107, and the second external electrode layer 105, and is connected to the first protective layer 106 and the second protective layer 106. 2 between the protective layer 107 and the side surface 101d. The second external terminal 115 is electrically connected to the second internal electrode 103 via the second external electrode layer 105, that is, functions as a terminal for connecting the second internal electrode 103.

The capacitor 100 has the above configuration. As described above, in the capacitor 100, the first internal electrode 102 and the second internal electrode 103 are opposed to each other with the dielectric layer 101 therebetween, thereby forming a capacitor. That is, the first internal electrode 102 and the second internal electrode 103 function as counter electrodes of the capacitor. Note that either the first internal electrode 102 or the second internal electrode 103 may be a positive electrode. The first internal electrode 102 is connected to an external wiring, a terminal, or the like via the first external electrode layer 104, and the second internal electrode 103 is connected via the second external electrode layer 105, respectively.

[Regarding Arrangement Area of First External Electrode Layer and Second External Electrode Layer]
An arrangement region of the first external electrode layer 104 and the second external electrode layer 105 included in the capacitor according to the present embodiment will be described.

As described above, the first external electrode layer 104 and the second external electrode layer 105 have regions that do not face each other with the dielectric layer 101 interposed therebetween. FIG. 11 is a cross-sectional view illustrating a partial configuration of the capacitor 100, and FIG. 12 is a plan view illustrating a partial configuration of the capacitor 100 viewed from the second surface 101c side.

As shown in these drawings, the first external electrode layer 104 and the second external electrode layer 105 have the same size, do not completely face each other through the dielectric layer 101, and are in the layer surface direction (perpendicular to the thickness). It is possible that they are arranged to be shifted in the direction). As a result, a facing region and a non-facing region are formed in the first external electrode layer 104 and the second external electrode layer 105.

FIG. 13 is a schematic diagram showing opposing regions and non-opposing regions in the first external electrode layer 104 and the second external electrode layer 105. As shown in the figure, the first external electrode layer 104 is formed with a facing region L1 that is a region facing the second external electrode layer 105 and a non-facing region L2 that is a region not facing the second external electrode layer 105. ing. The second external electrode layer 105 is formed with a facing region L3 that is a region facing the first external electrode layer 104 and a non-facing region L4 that is a region not facing the first external electrode layer 104.

Here, as shown in FIG. 11, the second internal electrode 103 formed in the facing region L1 is connected to the second external electrode layer 105, and the second internal electrode 103 formed in the non-facing region L2 is The second external electrode layer 105 is not connected. The first internal electrode 102 formed in the facing region L3 is connected to the first external electrode layer 104, and the first internal electrode 102 formed in the non-facing region L4 is connected to the first external electrode layer 104. It can be unconnected.

As shown in FIG. 13, the non-facing region L <b> 2 is provided along each of the long side and the short side of the first external electrode layer 104, and the non-facing region L <b> 4 includes the long side of the second external electrode layer 105. Each of the short sides may be provided along one side. As shown in the figure, the width of the non-facing region L2 (the distance between the periphery of the facing region L1 and the periphery of the non-facing region L2) is defined as the width D1 and the width D2, and the width of the non-facing region L4 (the periphery of the facing region L3) The distance of the peripheral edge of the non-facing region LL4) is defined as a width D3 and a width D4. The widths D1 to D4 may be the same as or different from each other. The widths D1 to D4 are not particularly limited, but are preferably 0.1 μm or more and 100 μm or less.

In addition, the arrangement | positioning area | region of the 1st external electrode layer 104 and the 2nd external electrode layer 105 is not restricted above-mentioned. FIG. 14 to FIG. 17 are schematic views showing variations in the arrangement region of the first external electrode layer 104 and the second external electrode layer 105. 14A to 17A are cross-sectional views of each capacitor 100, and FIGS. 14B to 17B are plan views corresponding to the respective cross-sectional views. Each plan view is a view of the capacitor 100 as viewed from the second surface 101b side.

For example, as shown in FIG. 14, the first external electrode layer 104 and the second external electrode layer 105 have the same size, and may be arranged shifted in one direction in the layer surface direction. Thus, the non-facing region L2 can be provided along one short side of the facing region L1, and the non-facing region L4 can be provided along one short side of the facing region L3.

Alternatively, the first external electrode layer 104 and the second external electrode layer 105 may have different sizes from each other. For example, as shown in FIG. 15, the first external electrode layer 104 and the second external electrode layer 105 may have different long sides and short sides. Thereby, the non-facing region L2 can be provided along the long side of the facing region L1, and the non-facing region L4 can be provided along the long side of the facing region L3.

In addition, as shown in FIG. 16, the second external electrode layer 105 has all sides larger than the first external electrode layer 104, and all the sides of the second external electrode layer 105 and the first external electrode layer as viewed from the thickness direction. The sides may be separated. As a result, the opposing region L3 is surrounded by the non-opposing region L4, and the first external electrode layer 104 does not have the non-facing region L2.

Further, as shown in FIG. 17, the second external electrode layer 105 has all sides larger than the first external electrode layer 104, and one side of each of the long side and the short side of the second external electrode layer 105 when viewed from the thickness direction. The long side and the short side of the first external electrode layer 104 may be separated from each other. Thus, the non-facing region L4 is provided along one of the short side and the long side of the facing region L3, and the first external electrode layer 104 does not have the non-facing region L2.

Also in each of these configurations, the width of the non-facing region L2 and the width of the non-facing region L4 (see FIG. 13) are not particularly limited, but are preferably 0.1 μm or more and 100 μm or less. In addition, as described above, the non-facing region L2 may not exist in the first external electrode layer 104.

The configurations of the first external electrode layer 104 and the second external electrode layer 105 are not limited to those shown here, and any structure may be used as long as at least the second external electrode layer 105 has the facing region L3 and the non-facing region L4. The shapes of the first external electrode layer 104 and the second external electrode layer 105 are not limited to rectangles, and may be circular, elliptical, or polygonal.

[Effect of capacitor]
The effect of the capacitor 100 will be described using a comparative example. FIG. 18 is a cross-sectional view of a capacitor 200 according to a comparative example. As shown in the figure, the capacitor 200 includes a dielectric layer 201, a first internal electrode 202, a second internal electrode 203, a first external electrode layer 204, a second external electrode layer 205, a first protective layer 206, a second A protective layer 207, a first external terminal 214, and a second external terminal 215 are provided. Further, an insulator 202 a is filled between the first internal electrode 202 and the second external electrode layer 205, and an insulator 203 a is filled between the second internal electrode 203 and the first external electrode layer 204.

In the dielectric layer 201, as shown in FIG. 18, a first external electrode layer 204 is disposed on the first surface 201a, and a second external electrode layer 205 is disposed on the second surface 201b. The first external electrode layer 204 and the second external electrode layer 205 have the same size, and are configured to completely face each other with the dielectric layer 201 interposed therebetween.

19 and 20 are enlarged views of the peripheral portions of the first external electrode layer 204 and the second external electrode layer 205 of the capacitor 200, and the dielectric layer 201 is the first external electrode layer 204 and the second external electrode layer. It is a figure which shows the state cut | disconnected in the peripheral part vicinity of 205. FIG. In both figures, the first protective layer 206, the second protective layer 207, the first external terminal 214, and the second external terminal 215 are not shown.

Here, when the capacitor 200 is exposed to a humidity environment, a hydration reaction occurs in the dielectric layer 201, and a hydrate such as boehmite is generated. The dielectric layer 201 is covered with the first protective layer 206 and the second protective layer 207, but if there are pin poles in the first protective layer 206 and the second protective layer 207, moisture may reach the dielectric layer 201. There is.

Since the first external electrode layer 204 and the second external electrode layer 205 are formed on the first surface 201 a and the second surface 201 b of the dielectric layer 201, the infiltrated moisture is in the first external electrode layer 204 and the second external electrode layer 205. 2 Reach the peripheral edge of the external electrode layer 205.

Thereby, for example, as shown in FIG. 19, a hydrate W is formed at the peripheral portion of the first external electrode layer 204 in the dielectric layer 201. Since the hydrate W is inferior in insulation, when formed across the first internal electrode 202 and the second internal electrode 203, the first internal electrode 202 and the second internal electrode 203 are electrically connected as shown in FIG. Connected. Therefore, the first external electrode layer 204 connected to the first internal electrode 202 and the second external electrode layer 205 connected to the second internal electrode 203 are electrically connected to each other (conductive path D in the figure), causing a short circuit failure. There is a fear.

Such a short circuit failure due to a hydrate occurs because the second external electrode layer 205 exists on the opposite side of the peripheral portion of the first external electrode layer 204 through the dielectric layer 201. Although the peripheral portion of the first external electrode layer 204 has been described here, a short-circuit failure due to hydrate may occur in the peripheral portion of the second external electrode layer 205 on the opposite side of the dielectric layer 201 in the same manner. There is.

FIG. 21 is a schematic diagram of the dielectric layer 201, the first internal electrode 202, the second internal electrode 203, the first external electrode layer 204, and the second external electrode layer 205. In the figure, the first external electrode layer 204 or the second external electrode layer 205 exists on the opposite side of the peripheral portion of the first external electrode layer 204 and the second external electrode layer 205 with the dielectric layer 201 interposed therebetween. Regions are indicated by black arrows. This region is a region along the periphery of the first external electrode layer 204 and the second external electrode layer 205. If a hydrate is generated in the region indicated by the black arrow, a short circuit failure may occur in the first external electrode layer 204 and the second external electrode layer 205. Hereinafter, this region is referred to as a short circuit occurrence region T1.

Here, as described above, in the capacitor 100 according to the present embodiment, at least one of the first external electrode layer 104 and the second external electrode layer 105 has an opposing region and a non-opposing region, that is, the first external electrode. The electrode layer 104 and the second external electrode layer 105 are not completely opposed to each other with the dielectric layer 101 interposed therebetween, and are disposed so as to be shifted in the layer surface direction (direction orthogonal to the thickness).

FIG. 22 is an enlarged view of the periphery of the first external electrode layer 104 and the second external electrode layer 105 of the capacitor 100, and the dielectric layer 101 is the periphery of the first external electrode layer 104 and the second external electrode layer 105. It is a figure which shows the state cut | disconnected by the part vicinity. 22A is a diagram viewed from the first surface 101b side, and FIG. 22B is a diagram viewed from the second surface 101c side. In the figure, the first protective layer 106, the second protective layer 107, the first external terminal 114, and the second external terminal 115 are not shown. As described above, the first external electrode layer 104 and the second external electrode layer 105 are not completely opposed to each other, and the first external electrode layer 104 has a facing region L1 and a non-facing region L2. The second external electrode layer 105 represents only the facing region L3 in the range shown in FIG.

Thereby, the hydrate W is formed in the dielectric layer 101 at the peripheral edge of the first external electrode layer 104 as in the comparative example, and the first internal electrode 102 and the second internal electrode 103 are interposed via the hydrate W. Even if electrically connected, the first external electrode layer 104 and the second external electrode layer 105 are not electrically connected. This is because the second internal electrode 103 is not connected to the second external electrode layer 105 in the non-facing region L2 of the first external electrode layer 104 (see FIG. 11).

FIG. 23 is a schematic diagram of the dielectric layer 101, the first internal electrode 102, the second internal electrode 103, the first external electrode layer 104, and the second external electrode layer 105. In the drawing, the first external electrode layer 104 or the second external electrode layer 105 exists on the opposite side of the peripheral portion of the first external electrode layer 104 and the second external electrode layer 105 with the dielectric layer 101 interposed therebetween. Regions are indicated by black arrows. This region is a region along the periphery of the opposing region L1 of the first external electrode layer 104 and the periphery of the opposing region L3 of the second external electrode layer 105. Hereinafter, this region is referred to as a short circuit occurrence region T1.

Further, a region where the first external electrode layer 104 or the second external electrode layer 105 does not exist on the opposite side of the peripheral portion of the first external electrode layer 104 and the second external electrode layer 105 with the dielectric layer 101 interposed therebetween. Shown with white arrows. This region is a region along the periphery of the non-facing region L2 of the first external electrode layer 104 and the non-facing region L4 of the second external electrode layer 105. Hereinafter, this region is referred to as a short circuit prevention region T2.

When a hydrate is generated in the short-circuit generation region T1, a short-circuit failure may occur in the first external electrode layer 104 and the second external electrode layer 105 as described above. However, when a hydrate is generated in the short circuit prevention region T2, there is no possibility of causing a short circuit failure in the first external electrode layer 104 and the second external electrode layer 105. This is because the second internal electrode 103 is not connected to the second external electrode layer 105 in the non-facing region L2 of the first external electrode layer 104 as shown in FIG. In addition, the first internal electrode 102 is not connected to the first external electrode layer 104 in the non-facing region L4 of the second external electrode layer 105.

As described above, in the capacitor 100 according to the present embodiment, the first external electrode layer 104 has the facing region L1 and the non-facing region L2, and the second external electrode layer 105 has the facing region L3 and the non-facing region L4. For this reason, even if a hydrate is formed in the dielectric layer 101, it is possible to reduce the probability of occurrence of a short-circuit failure as compared with the capacitor 200 according to the comparative example.

Further, as shown in FIG. 16, in the second external electrode layer 105, the facing region L3 can be surrounded by the non-facing region L4. FIG. 24 is a schematic diagram of the dielectric layer 101, the first internal electrode 102, the second internal electrode 103, the first external electrode layer 104, and the second external electrode layer 105 in the capacitor 100 in this case.

In this case, the first external electrode layer 104 does not exist on the opposite side of the peripheral portion of the second external electrode layer 105 through the dielectric layer 101 over the entire circumference. For this reason, as shown in the figure, the entire circumference of the peripheral portion of the second external electrode layer 105 becomes the short-circuit prevention region T2. Further, the second external electrode layer 105 exists on the opposite side of the peripheral portion of the first external electrode layer 104 through the dielectric layer 101 over the entire periphery. For this reason, as shown in the figure, the entire periphery of the peripheral portion of the first external electrode layer 104 is a short-circuit generation region T1.

That is, in this configuration, the short-circuit generation region T1 exists only on one surface (the first surface 101b side) of the capacitor 100. Here, when the capacitor 100 is mounted on the substrate, the surface can be the mounting substrate side. FIG. 25 is a schematic diagram showing how the capacitor 100 is mounted in this case.

As shown in the figure, when the capacitor 100 is mounted on the mounting substrate B, the first surface 101b side of the capacitor 100 is covered with the underfill U by mounting the first surface 101b side as the mounting substrate B side. Is done. Accordingly, it is possible to prevent moisture from entering the first surface 101b side by the underfill U, and it is possible to prevent hydrate formation. As described above, since only the short-circuit prevention region T2 exists on the second surface 101c side, it is possible to prevent a short-circuit failure even if a hydrate is formed.

[Capacitor manufacturing method]
A method for manufacturing the capacitor 100 according to the present embodiment will be described. In addition, the manufacturing method shown below is an example and the capacitor | condenser 100 can also be manufactured with the manufacturing method different from the manufacturing method shown below. 26 to 32 are schematic views showing a manufacturing process of the capacitor 100. FIG.

FIG. 26A shows the base material 301 that is the basis of the dielectric layer 101. When the dielectric layer 101 is made of a metal oxide (for example, aluminum oxide), the base material 301 is a metal (for example, aluminum) before the oxidation.

For example, when a voltage is applied with the substrate 301 as an anode in an oxalic acid (0.1 mol / l) solution adjusted to 15 ° C. to 20 ° C., the substrate 301 is oxidized (anodized) as shown in FIG. ) To form a base oxide 302. At this time, holes H are formed in the base material oxide 302 by the self-organizing action of the base material oxide 302. The holes H grow in the direction of progress of oxidation, that is, in the thickness direction of the substrate 301.

It should be noted that regular pits (concave portions) may be formed in the base material 301 before the anodic oxidation, and the holes H may be grown using the pits as base points. The arrangement of the holes H can be controlled by the arrangement of the pits. The pit can be formed, for example, by pressing a mold (mold) against the base material 301.

The voltage applied to the base material 301 is increased after a predetermined time has elapsed from the start of anodization. Since the pitch of the holes H formed by the self-organization is determined by the magnitude of the applied voltage, the self-organization proceeds so that the pitch of the holes H increases. Thereby, as shown in FIG.26 (c), formation of a hole is continued about some holes H, and a hole diameter expands. On the other hand, since the pitch of the holes H is increased, the hole forming speed of the other holes H is very slow. Hereinafter, the hole H in which the formation speed of the hole is slow is referred to as a hole H1, and the hole H in which the formation of the hole is continued (enlarged) is referred to as a hole H2.

The anodizing conditions can be set as appropriate. For example, the applied voltage of the first stage anodizing shown in FIG. 26B can be set to several V to several hundred V, and the processing time can be set to several minutes to several days. . With the applied voltage of the second stage of anodic oxidation shown in FIG. 26 (c), the voltage value can be several times that of the first stage, and the processing time can be set to several minutes to several tens of minutes.

For example, a hole H having a hole diameter of 100 nm is formed by setting the applied voltage at the first stage to 40V, and a hole diameter of the hole H2 is enlarged to 200 nm by setting the applied voltage at the second stage to 80V. By setting the voltage value of the second stage within the above-described range, the number of holes H1 and holes H2 can be made substantially equal. Further, by setting the processing time of the second stage voltage application within the above-mentioned range, the base oxide 302 formed on the bottom by the second stage voltage application while the pitch conversion of the holes H2 is sufficiently completed. Can be reduced in thickness. Since the base material oxide 302 formed by the voltage application in the second stage is removed in a later process, it is preferable that the base material oxide 302 be as thin as possible.

Subsequently, as shown in FIG. 27A, the non-oxidized base material 301 is removed. The substrate 301 can be removed by wet etching, for example. Hereinafter, the surface of the base oxide 302 on which the holes H1 and H2 are formed is referred to as a front surface 302a, and the opposite surface is referred to as a back surface 302b.

Subsequently, as shown in FIG. 27B, the base material oxide 302 is removed from the back surface 302b side with a predetermined thickness. This can be done by reactive ion etching (RIE). At this time, the base oxide 302 is removed so that the hole H2 communicates with the back surface 302b and the hole H1 does not communicate with the back surface 302b.

Subsequently, as shown in FIG. 27C, a first conductor layer 303 made of a conductive material is formed on the surface 302a. The first conductor layer 303 can be formed by any method such as sputtering or vacuum deposition.

Subsequently, as shown in FIG. 28A, the first plating conductor M1 is embedded in the hole H2. The first plating conductor M1 can be embedded by performing electrolytic plating on the base material oxide 302 using the first conductor layer 303 as a seed layer. Since the plating solution does not enter the hole H1, the first plating conductor M1 is not formed in the hole H1.

Subsequently, as shown in FIG. 28B, the base material oxide 302 is removed again from the back surface 302b with a predetermined thickness. This can be done by reactive ion etching. At this time, the base oxide 302 is removed with a thickness that allows the hole H1 to communicate with the back surface 302b.

Subsequently, as shown in FIG. 28C, the second plating conductor M2 is embedded in the hole H1, and at the same time, the third plating conductor M3 is embedded in the hole H2.

The second plating conductor M2 and the third plating conductor M3 can be embedded by performing electrolytic plating on the base material oxide 302 using the first conductor layer 303 as a seed layer. At this time, since the first plating conductor M1 is formed in the hole H2 by the previous process, the tip of the third plating conductor M3 protrudes from the tip of the second plating conductor M2. Hereinafter, the first plating conductor M1 and the third plating conductor M3 are referred to as a first inner conductor 304, and the second plating conductor M2 is referred to as a second inner conductor 305.

Subsequently, as shown in FIG. 29A, the base material oxide 302 is removed again from the back surface 302b with a predetermined thickness. This can be done by mechanical polishing or the like. At this time, the base oxide 302 is removed with such a thickness that the first inner conductor 304 is exposed on the back surface 302b and the first inner conductor 305 is not exposed on the back surface 302b.

Subsequently, as shown in FIG. 29B, an insulator 306 is embedded in the gap of the hole H1. The insulator 306 can be embedded by filling the gap with any insulating material.

Subsequently, as shown in FIG. 29C, a second conductor layer 307 made of a conductive material is formed on the back surface 302b. The second conductor layer 307 can be formed by any method such as sputtering or vacuum deposition.

Subsequently, as shown in FIG. 30A, the first conductor layer 303 is removed. The removal of the first conductor layer 303 can be performed by a wet etching method, a dry etching method, an ion milling method, a CMP (Chemical-Mechanical-Polishing) method, or the like.

Subsequently, as shown in FIG. 30B, electrolytic etching is performed on the base material oxide 302 using the second conductor layer 307 as a seed layer. Since the first inner conductor 304 is electrically connected to the second conductor layer 307, it is etched by electrolytic etching. As a result, a gap is formed in the hole H2 from which the first inner conductor 304 has been removed. On the other hand, since the second inner conductor 305 is insulated from the second conductor layer 307, it is not etched by electrolytic etching.

Subsequently, as shown in FIG. 30C, an insulator 308 is embedded in the gap of the hole H2. The insulator 308 can be embedded by filling the gap with an arbitrary insulating material.

Subsequently, as shown in FIG. 31A, a third conductor layer 309 made of a conductive material is formed on the surface 302a. The third conductor layer 309 can be formed by any method such as sputtering or vacuum deposition.

Subsequently, as shown in FIG. 31B, the second conductor layer 307 is removed. The removal of the second conductor layer 307 can be performed by a wet etching method, a dry etching method, an ion milling method, a CMP (Chemical-Mechanical-Polishing) method, or the like.

Subsequently, as shown in FIG. 31C, a fourth conductor layer 310 made of a conductive material is formed on the back surface 302b. At this time, the fourth conductor layer 310 can be formed by shifting in the layer surface direction with respect to the third conductor layer 309. Thereby, a non-facing region L4 that is a region that does not face the facing region L3 that is the region facing the third conductor layer 309 via the base material oxide 302 is formed in the fourth conductor layer 310. In addition, a non-facing region L2 that is a region that does not face the facing region L1 that is a region facing the fourth conductor layer 310 via the base oxide 302 is also formed in the third conductor layer 309.

Subsequently, as shown in FIG. 32A, the first protective layer 311 is disposed on the third conductor layer 309 and the second protective layer 312 is disposed on the fourth conductor layer 310. The first protective layer 311 and the second protective layer 312 can be formed by applying a resin material on the third conductor layer 309 and the fourth conductor layer 310 and patterning them by photolithography or the like. During the patterning, an opening 311a from which the third conductor layer 309 is exposed is formed in the first protective layer 311, and an opening 312 a from which the fourth conductor layer 310 is exposed is formed in the second protective layer 312.

Subsequently, as shown in FIG. 32B, the first outer conductor 313 is disposed on the side surface 302 c, the third conductor layer 309, the first protective layer 311, and the second protective layer 312. A second outer conductor 314 is disposed on the side surface 302 c, the fourth conductor layer 310, the first protective layer 311, and the second protective layer 312.

The first outer conductor 313 and the second outer conductor 314 can be formed by applying a metal material on the front surface 302a, the side surface 302c, and the back surface 302b and patterning the material by photolithography or the like. By separating the metal material during patterning, the first outer conductor 313 and the second outer conductor 314 are formed.

The capacitor 100 can be manufactured as described above. The base oxide 302 corresponds to the dielectric layer 101, the second internal conductor 305 corresponds to the first internal electrode 102, and the first internal conductor 304 corresponds to the second internal electrode 103. The third conductor layer 309 is the first external electrode layer 104, the fourth conductor layer 310 is the second external electrode layer 105, the first protective layer 311 is the first protective layer 106, and the second protective layer 312 is the second protective layer. In the layer 107, the first external conductor 313 corresponds to the first external terminal 114, and the second external conductor 314 corresponds to the second external terminal 115, respectively.

DESCRIPTION OF SYMBOLS 100 ... Capacitor 101 ... Dielectric layer 101a ... Through-hole 101b ... 1st surface 101c ... 2nd surface 102 ... 1st internal electrode 103 ... 2nd internal electrode 104 ... 1st external electrode layer 105 ... 2nd external electrode layer L1, L3 ... Opposite area L2, L4 ... Non-opposite area

Claims

A plurality of through-holes formed by metal anodization, having a first surface and a second surface opposite to the first surface, and communicating with the first surface and the second surface A dielectric layer comprising:
A first external electrode layer disposed on the first surface;
A second external electrode layer disposed on the second surface, an opposing region facing the first external electrode layer via the dielectric layer, and the first external electrode layer via the dielectric layer. A second external electrode layer having a non-opposing region that does not oppose the first external electrode layer;
A first internal electrode formed in a part of the plurality of through holes, connected to the first external electrode layer and spaced apart from the second external electrode layer;
And a second internal electrode formed in another part of the plurality of through holes, connected to the second external electrode layer, and spaced apart from the first external electrode layer.
The capacitor according to claim 1,
The first external electrode layer includes a facing region that faces the second external electrode layer via the dielectric layer, and a non-facing region that does not face the second external electrode layer via the dielectric layer. Having a capacitor.
The capacitor according to claim 1,
The counter area is surrounded by the non-opposite area.
The capacitor according to claim 1,
The width of the non-opposing region is 0.1 μm or more and 100 μm or less.
The capacitor according to claim 2 or 3,
A capacitor filled with an insulating material between the first internal electrode and the second external electrode layer and between the second external electrode layer and the first external electrode layer.
The capacitor according to claim 4,
The dielectric layer is a capacitor made of a material that forms a porous layer by self-organization when anodized.
The capacitor according to claim 5,
The dielectric layer is a capacitor made of aluminum oxide formed by anodization of aluminum.