JP2016004827A - Capacitor, circuit module, and mobile communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a porous capacitor having a high withstanding voltage, and to provide a circuit module and mobile communication equipment comprising the porous capacitor.SOLUTION: A capacitor comprises a dielectric layer, a first conductor layer, a second conductor layer, a first internal electrode, and a second internal electrode. The dielectric layer is formed of a dielectric material, and comprises a first surface, a second surface, and a plurality of through-holes communicated with the first and second surfaces. Each through-hole has a predetermined hole diameter. The respective through-holes are adjacent to each other at predetermined intervals. A ratio of the interval to the hole diameter is 1.0 or more. The first conductor layer is formed of a conductive material, and arranged on the first surface. The second conductor layer is formed of a conductive material, and arranged on the second surface. The first internal electrode is formed of a conductive material, formed in the plurality of through-holes, and connected with the first conductor layer. The second internal electrode is formed of a conductive material, formed in the plurality of through-holes, and connected with the second conductor layer.

Description

  The present invention relates to a porous capacitor, a circuit module including the porous capacitor, and a mobile communication device.

  In recent years, a porous capacitor has been developed as a new type of capacitor. Porous capacitors use a property that a metal oxide formed on a metal surface such as aluminum forms a porous structure (through-hole of pores), and forms an internal electrode in the through-hole. As a capacitor. The porous structure can be formed by self-organizing action by anodizing the metal.

  Conductors are stacked on the front and back surfaces of the dielectric, and the internal electrode formed in the through hole is connected to either the front or back conductor. A gap or an insulating material is used to insulate between the internal electrode and the conductor not connected. Thereby, an internal electrode functions as a counter electrode (a positive electrode or a negative electrode) which opposes via a dielectric.

  For example, Patent Document 1 discloses a porous capacitor having such a configuration. In any patent document, an internal electrode is formed in the through hole, one end of the internal electrode is connected to one conductor, and the other end is insulated from the other conductor.

Japanese Patent No. 4493686

  Here, the withstand voltage and capacitance of the porous capacitor are affected by the distance between the opposed internal electrodes, that is, the distance between the adjacent through holes. Increasing the spacing increases the withstand voltage, but decreases the capacitance. When the interval is reduced, the withstand voltage is reduced and the capacitance is increased. In order to form a porous structure, it is necessary to sufficiently deepen the through holes formed by the self-organizing action. However, if the treatment time of the anodizing treatment is increased, the interval between the through holes is reduced, and the resistance of the porous capacitor is reduced. The voltage may be insufficient.

  In view of the circumstances as described above, an object of the present invention is to provide a porous capacitor having a high withstand voltage, a circuit module including the porous capacitor, and a mobile communication device.

In order to achieve the above object, a capacitor according to an embodiment of the present invention includes a dielectric layer, a first conductor layer, a second conductor layer, a first internal electrode, and a second internal electrode. It has.
The dielectric layer is made of a dielectric material, and has a first surface, a second surface opposite to the first surface, and a plurality of penetrations communicating with the first surface and the second surface. Each of the through holes has a predetermined hole diameter, the through holes are adjacent to each other at a predetermined interval, and the ratio of the interval to the hole diameter is 1.0 or more.
The first conductor layer is made of a conductive material and is disposed on the first surface.
The second conductor layer is made of a conductive material and is disposed on the second surface.
The first internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the first conductor layer.
The second internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the second conductor layer.

In order to achieve the above object, a capacitor included in a circuit module according to an embodiment of the present invention includes a dielectric layer, a first conductor layer, a second conductor layer, a first internal electrode, and a second And an internal electrode.
The dielectric layer is made of a dielectric material, and has a first surface, a second surface opposite to the first surface, and a plurality of penetrations communicating with the first surface and the second surface. Each of the through holes has a predetermined hole diameter, the through holes are adjacent to each other at a predetermined interval, and the ratio of the interval to the hole diameter is 1.0 or more.
The first conductor layer is made of a conductive material and is disposed on the first surface.
The second conductor layer is made of a conductive material and is disposed on the second surface.
The first internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the first conductor layer.
The second internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the second conductor layer.

In order to achieve the above object, a capacitor included in a mobile communication device according to an aspect of the present invention includes a dielectric layer, a first conductor layer, a second conductor layer, a first internal electrode, 2 internal electrodes.
The dielectric layer is made of a dielectric material, and has a first surface, a second surface opposite to the first surface, and a plurality of penetrations communicating with the first surface and the second surface. Each of the through holes has a predetermined hole diameter, the through holes are adjacent to each other at a predetermined interval, and the ratio of the interval to the hole diameter is 1.0 or more.
The first conductor layer is made of a conductive material and is disposed on the first surface.
The second conductor layer is made of a conductive material and is disposed on the second surface.
The first internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the first conductor layer.
The second internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the second conductor layer.

1 is a perspective view of a capacitor according to an embodiment of the present invention. It is sectional drawing of the same capacitor. It is a perspective view of the dielectric material layer with which the same capacitor is provided. It is sectional drawing of the dielectric material layer with which the same capacitor | condenser is provided. It is an enlarged view of the dielectric material layer with which the same capacitor is provided. It is a graph which shows the relationship between a hole space | interval / hole diameter ratio, and withstand voltage. It is a schematic diagram which shows the manufacturing method of the capacitor | condenser. It is a schematic diagram which shows the manufacturing method of the capacitor | condenser. It is a schematic diagram which shows the manufacturing method of the capacitor | condenser. It is a schematic diagram which shows the manufacturing method of the capacitor | condenser. It is a schematic diagram which shows the manufacturing method of the capacitor | condenser. It is a table | surface which shows the relationship between the conditions of anodization and an acid treatment, a hole diameter, and a hole space | interval. It is a table | surface which shows the manufacturing conditions and measurement result of the capacitor | condenser which concern on the Example and comparative example of this invention. It is a table | surface which shows the manufacturing conditions and measurement result of the capacitor | condenser which concern on the Example and comparative example of this invention. It is a table | surface which shows the manufacturing conditions and measurement result of the capacitor | condenser which concern on the Example and comparative example of this invention. It is a table | surface which shows the manufacturing conditions and measurement result of the capacitor | condenser which concern on the Example and comparative example of this invention. It is a table | surface which shows the manufacturing conditions and measurement result of the capacitor | condenser which concern on the Example and comparative example of this invention. It is a table | surface which shows the manufacturing conditions and measurement result of the capacitor | condenser which concern on the Example and comparative example of this invention. It is a graph which shows a measurement result about the capacitor concerning an example and a comparative example of the present invention. It is a graph which shows the measurement result about the capacitor | condenser which concerns on the Example and comparative example of this invention.

A capacitor according to an embodiment of the present invention includes a dielectric layer, a first conductor layer, a second conductor layer, a first internal electrode, and a second internal electrode.
The dielectric layer is made of a dielectric material, and has a first surface, a second surface opposite to the first surface, and a plurality of penetrations communicating with the first surface and the second surface. Each of the through holes has a predetermined hole diameter, the through holes are adjacent to each other at a predetermined interval, and the ratio of the interval to the hole diameter is 1.0 or more.
The first conductor layer is made of a conductive material and is disposed on the first surface.
The second conductor layer is made of a conductive material and is disposed on the second surface.
The first internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the first conductor layer.
The second internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the second conductor layer.

  By setting the ratio of the interval between the through holes to the diameter of the through holes to be 1.0 or more, it is possible to improve the withstand voltage (voltage at which dielectric breakdown occurs) of the capacitor.

  The ratio of the spacing to the pore diameter may be less than 2.0.

  When the ratio is 2.0 or more, the facing area (that is, the capacitance) of the internal electrodes (first internal electrode and second internal electrode) disposed in a certain range of the dielectric layer is insufficient, The space of the dielectric layer cannot be used effectively. Therefore, the ratio is preferably less than 2.0.

  The interval may be 10 nm or more, and the pore diameter may be 200 nm or less.

  When the interval between the through holes is less than 10 nm, the withstand voltage becomes insufficient. Further, if the pore diameter exceeds 200 nm, the opposing area (that is, the capacitance) of the internal electrodes (first internal electrode and second internal electrode) arranged in a certain range of the dielectric layer is insufficient, and the dielectric The layer space cannot be used effectively. Accordingly, the interval between the through holes is preferably 10 nm or more, and the hole diameter of the through holes is preferably 200 nm or less.

A capacitor included in a circuit module according to an embodiment of the present invention includes a dielectric layer, a first conductor layer, a second conductor layer, a first internal electrode, and a second internal electrode. .
The dielectric layer is made of a dielectric material, and has a first surface, a second surface opposite to the first surface, and a plurality of penetrations communicating with the first surface and the second surface. Each of the through holes has a predetermined hole diameter, the through holes are adjacent to each other at a predetermined interval, and the ratio of the interval to the hole diameter is 1.0 or more.
The first conductor layer is made of a conductive material and is disposed on the first surface.
The second conductor layer is made of a conductive material and is disposed on the second surface.
The first internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the first conductor layer.
The second internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the second conductor layer.

A capacitor included in a mobile communication device according to an embodiment of the present invention includes a dielectric layer, a first conductor layer, a second conductor layer, a first internal electrode, and a second internal electrode. It has.
The dielectric layer is made of a dielectric material, and has a first surface, a second surface opposite to the first surface, and a plurality of penetrations communicating with the first surface and the second surface. Each of the through holes has a predetermined hole diameter, the through holes are adjacent to each other at a predetermined interval, and the ratio of the interval to the hole diameter is 1.0 or more.
The first conductor layer is made of a conductive material and is disposed on the first surface.
The second conductor layer is made of a conductive material and is disposed on the second surface.
The first internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the first conductor layer.
The second internal electrode is made of a conductive material, is formed in the plurality of through holes, and is connected to the second conductor layer.

  A capacitor according to an embodiment of the present invention will be described.

[Configuration of capacitor]
FIG. 1 is a perspective view of a capacitor 100 according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the capacitor 100. As shown in these drawings, the capacitor 100 includes a dielectric layer 101, a first external electrode layer 102, a second external electrode layer 103, a first internal electrode 104, and a second internal electrode 105.

  The first external electrode layer 102, the dielectric layer 101, and the second external electrode layer 103 are laminated in this order, that is, the dielectric layer 101 is sandwiched between the first external electrode layer 102 and the second external electrode layer 103. . The first internal electrode 104 and the second internal electrode 105 are formed inside a through hole 101a formed in the dielectric layer 101 as shown in FIG.

The dielectric layer 101 is a layer that functions as a dielectric of the capacitor 100. The dielectric layer 101 can be made of a dielectric material capable of forming a through hole (porous), and a material that generates a porous layer by self-organizing action when anodized is particularly suitable. As such a material, aluminum oxide (Al ₂ O ₃ ) can be given. In addition, the dielectric layer 101 can be made of an oxide of valve metal (Al, Ta, Nb, Ti, Zr, Hf, Zn, W, Sb). Although the thickness of the dielectric material layer 101 is not specifically limited, For example, it can be several micrometers-several hundred micrometers.

  FIG. 3 is a perspective view of the dielectric layer 101, and FIG. 4 is a cross-sectional view of the dielectric layer 101. As shown in these drawings, the dielectric layer 101 has a plurality of through holes 101a. When the surface parallel to the layer surface direction of the dielectric layer 101 is a first surface 101b and the opposite surface is a second surface 101c, the through hole 101a is perpendicular to the first surface 101b and the second surface 101c. The first surface 101b and the second surface 101c are formed so as to communicate with each other (in the thickness direction of the dielectric layer 101). The number and size of the through holes 101a shown in FIG. 3 and the like are for convenience, and the actual ones are smaller and more in number. The through holes 101a have a predetermined hole diameter and are formed so as to be adjacent to each other at a predetermined interval. Details of this will be described later.

  As shown in FIG. 2, the first external electrode layer 102 is disposed on the first surface 101 b of the dielectric layer 101. The first external electrode layer 102 is made of a conductive material, for example, a pure metal such as Cu, Ni, Cr, Ag, Pd, Fe, Sn, Pb, Pt, Ir, Rh, Ru, Al, Ti, or an alloy thereof. Can be. The thickness of the first external electrode layer 102 can be several tens of nm to several μm, for example. Further, the first external electrode layer 102 may be disposed so that a plurality of layers of conductive materials are laminated.

  The second external electrode layer 103 is disposed on the second surface 101c of the dielectric layer 101 as shown in FIG. The second external electrode layer 103 can be made of the same conductive material as the first external electrode layer 102, and the thickness thereof can be, for example, several nm to several μm. The constituent material of the second external electrode layer 103 may be the same as or different from the constituent material of the first external electrode layer 102. The second external electrode layer 103 can also be arranged so that a plurality of layers of conductive materials are laminated.

  The first internal electrode 104 functions as one counter electrode of the capacitor 100. The first internal electrode 104 is made of a conductive material such as pure metals such as In, Sn, Pb, Cd, Bi, Al, Cu, Ni, Au, Ag, Pt, Pd, Co, Cr, Fe, Zn, and the like. It can consist of alloys. As shown in FIG. 2, the first internal electrode 104 is formed in the through hole 101 a and is connected to the first external electrode layer 102. Further, the first internal electrode 104 is formed apart from the second external electrode layer 103 and is insulated from the second external electrode layer 103. Further, the gap between the first internal electrode 104 and the second external electrode layer 103 may be filled with an insulator.

  The second internal electrode 105 functions as the other counter electrode of the capacitor 100. The second internal electrode 105 is made of a conductive material such as pure metals such as In, Sn, Pb, Cd, Bi, Al, Cu, Ni, Au, Ag, Pt, Pd, Co, Cr, Fe, Zn, and the like. It can consist of alloys. As shown in FIG. 2, the second internal electrode 105 is formed in the through hole 101 a and connected to the second external electrode layer 103. The second internal electrode 105 is formed away from the first external electrode layer 102 and is insulated from the first external electrode layer 102. Further, the gap between the second internal electrode 105 and the first external electrode layer 102 may be filled with an insulator.

  In FIG. 2 and the like, the first internal electrodes 104 and the second internal electrodes 105 are shown alternately every other, but these are for convenience and do not actually exist alternately. Also good.

  The capacitor 100 has the above configuration. The first internal electrode 104 and the second internal electrode 105 face each other through the dielectric layer 101 to form a capacitor. That is, the first internal electrode 104 and the second internal electrode 105 function as counter electrodes (positive electrode or negative electrode) of the capacitor. Note that either the first internal electrode 104 or the second internal electrode 105 may be a positive electrode.

  The capacitor 100 has a configuration other than that shown here, for example, a resin layer formed on the first external electrode layer 102 and the second external electrode layer 103, or the first external electrode layer 102 and the second external electrode, respectively. An electrode layer that is electrically connected to the layer 103 may be provided. The 1st internal electrode 104 and the 2nd internal electrode 105 shall be connected to the exterior (a terminal, wiring, etc. of a mounting board) via these electrode layers.

[Dielectric layer]
As described above, through holes 101a are formed in dielectric layer 101, and through holes 101a have a predetermined hole diameter and are adjacent to each other at a predetermined interval. FIG. 5 is an enlarged plan view of a part of the dielectric layer 101, as viewed from the first surface 101b side. Note that the second surface 101c is the same as FIG.

  As shown in the figure, the through hole 101a has a hole diameter R. The hole diameter R can be an average value of the hole diameters of the through holes 101a measured in an arbitrary cross section of the dielectric layer 101 by a plane perpendicular to the first surface 101b and the second surface 101c. Further, when the hole diameter of the through hole 101a in an arbitrary cross section differs depending on the measurement direction (for example, when the cross section of the through hole 101a is an elliptical diameter), the direction of the maximum diameter and the direction of the minimum diameter in the arbitrary cross section are two directions. The average value can be used as the pore diameter R.

  The pore diameter R is not particularly limited but is preferably 200 nm or less. When the hole diameter R exceeds 200 nm, the opposing area (that is, electrostatic capacity) of the internal electrodes (first internal electrode 104 and second internal electrode 105) disposed in a certain range of the dielectric layer 101 is insufficient, and the dielectric This is because the space of the layer 101 cannot be used effectively.

  Moreover, as shown in FIG. 5, the through-hole 101a is adjacent to the other through-holes 101a with a predetermined hole interval D. The hole interval D can be an average value of the interval between the through holes 101a measured in an arbitrary cross section of the dielectric layer 101 by a plane perpendicular to the first surface 101b and the second surface 101c. Further, when the interval between the through holes 101a in an arbitrary cross section varies depending on the measurement direction, the average value of the intervals measured along a certain direction where the interval is minimized can be set as the hole interval D.

  The hole interval D is not particularly limited, but is preferably 10 nm or more. This is because when the hole interval D is less than 10 nm, the first internal electrode 104 and the second internal electrode 105 come close to each other and insulation between the two becomes insufficient.

  In FIG. 5, the pitch (arrangement interval) of the through holes 101 a is shown as a pitch P. The pitch P is the distance between the centers of the through holes 101a, and is the sum of the hole interval D and the hole diameter R. These hole diameter R, hole interval D, and pitch P can be adjusted according to the manufacturing conditions of the dielectric layer 101 described later.

  Here, the ratio of the hole interval D to the hole diameter R (hole interval D / hole diameter R) (hereinafter referred to as hole interval / hole diameter ratio) is preferably 1.0 or more. FIG. 6 is a graph showing the relationship between the hole spacing / hole diameter ratio and the withstand voltage (voltage at which dielectric breakdown occurs) of the capacitor 100. As shown in the figure, the withstand voltage is remarkably improved when the hole interval / hole diameter ratio is 1.0 or more.

  As described above, the dielectric layer 101 is made of aluminum oxide formed by oxidation of aluminum, and a porous structure formed by self-organization of aluminum oxide can be used as the through hole 101a. It is known that aluminum oxide produced by anodization has a region where oxygen is deficient at the boundary between its cells (one unit of a through-hole and a wall surrounding it). That the wall thickness (hole interval D) of the through-hole 101a is thin means that the inner wall portion of the through-hole in which oxygen is not lost is removed. That is, it can be understood that nonlinearity appears in the dependency of FIG. 6 by increasing the ratio of the oxygen deficient region to the total wall thickness existing between adjacent through holes.

  Also, the hole spacing / hole diameter ratio is preferably less than 2.0. When the hole interval / hole diameter ratio is 2.0 or more, the opposing area (that is, electrostatic capacity) of the internal electrodes (first internal electrode 104 and second internal electrode 105) disposed in a certain range of the dielectric layer 101. This is because the space of the dielectric layer 101 cannot be used effectively. For this reason, the hole interval / hole diameter ratio is preferably 1.0 or more and less than 2.0.

[Production method]
A method for manufacturing the capacitor 100 will be described. In addition, the manufacturing method shown below is an example and the capacitor | condenser 100 can also be manufactured with the manufacturing method different from the manufacturing method shown below. 7 to 11 are schematic views showing the manufacturing process of the capacitor 100. FIG.

  FIG. 7A shows a base material 301 that is the basis of the dielectric layer 101. When the dielectric layer 101 is made of a metal oxide (for example, aluminum oxide), the base material 301 is a metal (for example, aluminum) before the oxidation.

  When the substrate 301 is anodized, the substrate 301 is oxidized and a substrate oxide 302 is formed as shown in FIG. At this time, holes H are formed in the base material oxide 302 by the self-organizing action of the base material oxide 302. The holes H grow in the direction of progress of oxidation, that is, in the thickness direction of the substrate 301. Anodization can be performed, for example, by applying a voltage using the substrate 301 as an anode in an oxalic acid (0.1 mol / l) solution adjusted to 15 ° C. to 20 ° C. The applied voltage can be, for example, several volts to several hundred volts, and the processing time can be, for example, several minutes to several days (see Examples).

  Note that regular pits (concave portions) may be formed in the base material 301 before the anodic oxidation, and the holes H may be grown using the pits as base points. The arrangement of the holes H can be controlled by the arrangement of the pits. The pit can be formed, for example, by pressing a mold (mold) against the base material 301.

  When the applied voltage to the substrate 301 is increased at the stage where the anodic oxidation has progressed to some extent, as shown in FIG. 7C, the pitch (hole diameter and hole interval) of some holes H is increased so as to increase. Organization progresses. On the other hand, when the pitch of the holes H is increased, the formation of holes for the other holes H is stopped. Hereinafter, the hole H in which the formation of the hole has stopped is referred to as a hole H1, and the hole H in which the formation of the hole has been continued (the hole diameter is enlarged) is referred to as a hole H2.

  The applied voltage at this time can be several times the voltage, and the processing time can be several minutes to several tens of minutes. The applied voltage in the first stage anodization shown in FIG. 7B and the applied voltage in the second stage anodization shown in FIG. The numbers can be roughly equivalent. Further, by setting the processing time of the second stage voltage application within the above-mentioned range, the base oxide 302 formed on the bottom by the second stage voltage application while the pitch conversion of the holes H2 is sufficiently completed. Can be reduced in thickness. Since the base material oxide 302 formed by the voltage application in the second stage is removed in a later process, it is preferable that the base material oxide 302 be as thin as possible.

  Subsequently, the base oxide 302 is subjected to an acid treatment. The acid treatment can be performed by immersing the base oxide 302 in an acidic solution for a predetermined time. For example, phosphoric acid (5 wt%) can be used as the acidic solution, and the immersion time can be several minutes to several tens of minutes. By this acid treatment, it is possible to enlarge the hole diameter (reducing the hole interval) while maintaining the pitch of the holes H1 and H2 (see FIG. 5) (see Examples).

  FIG. 12 is a table showing the enlargement of the pore diameter by acid treatment. “Anodic oxidation applied voltage” is the applied voltage of the first stage of anodic oxidation (FIG. 7B), and the anodic oxidation is performed in an oxalic acid (0.3M) solution adjusted to 10 ° C. The time is 24 hours. “Acid treatment time” is the time for immersing the metal oxide in phosphoric acid (5 wt%) after anodic oxidation. As shown in the figure, when the applied voltage of the anodic oxidation is the same, the pitch is the same regardless of whether or not the acid treatment is performed, but the hole diameter is enlarged and the hole interval is reduced by the acid treatment. In this way, the hole diameter can be enlarged while maintaining the pitch by the acid treatment, and the ratio of the above-described hole interval D to the hole diameter R (see FIG. 5) can be adjusted.

  Subsequently, as shown in FIG. 8A, the non-oxidized base material 301 is removed. The substrate 301 can be removed by wet etching, for example. Hereinafter, the surface of the base oxide 302 on which the holes H1 and H2 are formed is referred to as a front surface 302a, and the opposite surface is referred to as a back surface 302b.

  Subsequently, as shown in FIG. 8B, the base material oxide 302 is removed from the back surface 302b side with a predetermined thickness. This can be done by reactive ion etching (RIE). At this time, the base oxide 302 is removed so that the hole H2 communicates with the back surface 302b and the hole H1 does not communicate with the back surface 302b.

  Subsequently, as shown in FIG. 8C, a first conductor layer 303 made of a conductive material is formed on the surface 302a. The first conductor layer 303 can be formed by any method such as sputtering or vacuum deposition.

  Subsequently, as shown in FIG. 9A, the first plating conductor M1 is disposed in the hole H2. The first plating conductor M1 can be disposed by subjecting the base oxide 302 to electrolytic plating using the first conductor layer 303 as a seed layer. Since the plating solution does not enter the hole H1, the first plating conductor M1 is not formed in the hole H1.

  Subsequently, as shown in FIG. 9B, the base material oxide 302 is removed again from the back surface 302b with a predetermined thickness. This can be done by reactive ion etching. At this time, the base oxide 302 is removed with a thickness that allows the hole H1 to communicate with the back surface 302b.

  Subsequently, as shown in FIG. 9C, the second plating conductor M2 is disposed in the hole H1, and the third plating conductor M3 is disposed in the hole H2. The second plating conductor M2 and the third plating conductor M3 can be disposed by performing electrolytic plating on the base material oxide using the first conductor layer 303 as a seed layer. At this time, since the first plating conductor M1 is formed in the hole H2 by the previous process, the tip of the third plating conductor M3 protrudes from the tip of the second plating conductor M2.

  Hereinafter, the first plating conductor M1 and the third plating conductor M3 are collectively referred to as a first inner conductor 304, and the second plating conductor M2 is referred to as a second inner conductor 305.

  Subsequently, as shown in FIG. 10A, the base material oxide 302 is removed again from the back surface 302b with a predetermined thickness. This can be done by mechanical polishing or the like. At this time, the base oxide 302 is removed with such a thickness that the first inner conductor 304 is exposed on the back surface 302b and the second inner conductor 305 is not exposed on the back surface 302b.

  Subsequently, as shown in FIG. 10B, a second conductor layer 306 made of a conductive material is disposed on the back surface 302b. The second conductor layer 306 can be disposed by any method such as sputtering or vacuum deposition.

  Subsequently, as shown in FIG. 10C, the first conductor layer 303 is removed. The removal of the first conductor layer 303 can be performed by wet etching, dry etching, ion milling, CMP (Chemical Mechanical Polishing), or the like.

  Subsequently, as shown in FIG. 11A, the substrate oxide 302 is subjected to electrolytic etching using the second conductor layer 306 as a seed layer. Since the first inner conductor 304 is electrically connected to the second conductor layer 306, it is etched by electrolytic etching. As a result, a gap is formed in the hole H2 from which the first inner conductor 304 has been removed. On the other hand, since the second inner conductor 305 is not conductive to the second conductor layer 306, it is not etched by electrolytic etching.

  Subsequently, as shown in FIG. 11B, a third conductor layer 307 made of a conductive material is disposed on the surface 302a. The third conductor layer 307 can be disposed by any method such as sputtering or vacuum deposition.

  As described above, the capacitor 100 can be manufactured. The base oxide 302 corresponds to the dielectric layer 101, the third conductor layer 307 corresponds to the first external electrode layer 102, and the second conductor layer 306 corresponds to the second external electrode layer 103. The first inner conductor 304 corresponds to the first inner electrode 104, and the second inner conductor 305 corresponds to the second inner electrode 105.

  The capacitor 100 according to the present embodiment can constitute a circuit module together with other electronic components. Further, the circuit module including the capacitor 100 can be mounted on a mobile communication device such as a mobile phone.

  An example and a comparative example of the capacitor according to the embodiment will be described. Capacitors having through holes formed under various conditions were manufactured by the manufacturing method shown in the above embodiment, and the hole diameter, hole interval, and dielectric strength were measured. 13 to 18 are tables showing the conditions for creating through holes and the measurement results.

  Specifically, anodization was performed by applying a voltage for 24 hours using aluminum immersed in an oxalic acid (0.3 M) solution at 10 ° C. as an anode. Thereafter, the applied voltage was increased to increase the pitch of the through holes, and aluminum oxide having the through holes was formed. This aluminum oxide was immersed in phosphoric acid (5 wt%), and acid treatment was performed.

  As shown in FIGS. 13 to 18, aluminum oxides having different through-hole formation conditions were prepared by changing the applied voltage of anodic oxidation and the treatment time of acid treatment. 13 to 15 show conditions in which target values for hole intervals are set and conditions are set. FIGS. 16 to 18 show conditions in which target values for hole diameters are set. Thereafter, using the prepared aluminum oxide as a dielectric layer, an internal electrode was formed in the through hole in the same manner as in the above embodiment, and a conductor layer was disposed on both surfaces of the dielectric layer to produce a capacitor.

  For each capacitor, breakdown voltage (voltage at which dielectric breakdown occurs) was measured. Further, the dielectric layer of each capacitor was cut in an arbitrary cross section, and the hole diameter and the hole interval were measured.

  The hole diameter was measured at 30 points in an arbitrary cross section of the dielectric layer, and the average value was taken. When the hole diameter of the through hole in the arbitrary cross section differs depending on the measurement direction, the measurement was performed in two directions of the maximum diameter and the minimum diameter in the arbitrary cross section, and the average value was taken as the hole diameter.

  The hole interval was measured at 30 points in an arbitrary cross section of the dielectric layer, and the average value was taken. When the hole interval in an arbitrary cross section differs depending on the measurement direction, the average value of the intervals measured along a certain direction in which the hole interval is minimized was taken as the hole interval.

  The measurement results of withstand voltage, hole diameter and hole interval, and the hole interval / hole diameter ratio calculated for each capacitor are shown in FIGS. The slope described in each figure is the slope of the withstand voltage with respect to the hole spacing / hole diameter ratio. As shown in these figures, the hole spacing / hole diameter ratio can be adjusted by the anodizing voltage and the acid treatment time. Capacitors shown in these figures include those having a hole spacing / hole diameter ratio of 1.0 or more (Example) and those having a hole spacing / less than 1.0 (Comparative Example).

  Moreover, the withstand voltage graph with respect to the hole interval / hole diameter ratio in the measurement results shown in FIGS. 13 to 15 is shown in FIG. 19, and the withstand voltage with respect to the hole interval / hole diameter ratio in the measurement results shown in FIGS. Is shown in FIG. These graphs were linearly approximated to determine the slope and inflection point. The inclination and the inflection point are shown in FIGS. As shown in these drawings, it can be seen that when the hole interval / hole diameter ratio is 1.0 or more, the slope of the graph increases and the withstand voltage is remarkably improved.

DESCRIPTION OF SYMBOLS 100 ... Capacitor 101 ... Dielectric layer 101a ... Through-hole 102 ... 1st external electrode layer 103 ... 2nd external electrode layer 104 ... 1st internal electrode 105 ... 2nd internal electrode

Claims (5)

A first surface, a second surface opposite to the first surface, and a plurality of through-holes communicating with the first surface and the second surface, A dielectric layer comprising a plurality of through-holes having through-holes having a predetermined hole diameter, each through-hole being adjacent at a predetermined interval, and a ratio of the interval to the hole diameter being 1.0 or more;
A first conductive layer made of a conductive material and disposed on the first surface;
A second conductive layer made of a conductive material and disposed on the second surface;
A first internal electrode made of a conductive material, formed in the plurality of through holes, and connected to the first conductor layer;
A capacitor comprising a second internal electrode made of a conductive material, formed in the plurality of through holes, and connected to the second conductor layer. The capacitor according to claim 1,
The ratio of the spacing to the hole diameter is less than 2.0 capacitor. The capacitor according to claim 1,
The interval is 10 nm or more, and the hole diameter is 200 nm or less. A first surface, a second surface opposite to the first surface, and a plurality of through-holes communicating with the first surface and the second surface, A dielectric layer comprising a plurality of through-holes having through-holes having a predetermined hole diameter, each through-hole being adjacent at a predetermined interval, and a ratio of the interval to the hole diameter being 1.0 or more;
A first conductive layer made of a conductive material and disposed on the first surface;
A second conductive layer made of a conductive material and disposed on the second surface;
A first internal electrode made of a conductive material, formed in the plurality of through holes, and connected to the first conductor layer;
A circuit module comprising a capacitor made of a conductive material, formed in the plurality of through holes, and having a second internal electrode connected to the second conductor layer. A first surface, a second surface opposite to the first surface, and a plurality of through-holes communicating with the first surface and the second surface, A dielectric layer comprising a plurality of through-holes having through-holes having a predetermined hole diameter, each through-hole being adjacent at a predetermined interval, and a ratio of the interval to the hole diameter being 1.0 or more;
A first conductive layer made of a conductive material and disposed on the first surface;
A second conductive layer made of a conductive material and disposed on the second surface;
A first internal electrode made of a conductive material, formed in the plurality of through holes, and connected to the first conductor layer;
A mobile communication device comprising a capacitor made of a conductive material, formed in the plurality of through holes, and having a second internal electrode connected to the second conductor layer.

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