WO2015145920A1 - 信号分離装置及び信号分離方法 - Google Patents
信号分離装置及び信号分離方法 Download PDFInfo
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- WO2015145920A1 WO2015145920A1 PCT/JP2015/000099 JP2015000099W WO2015145920A1 WO 2015145920 A1 WO2015145920 A1 WO 2015145920A1 JP 2015000099 W JP2015000099 W JP 2015000099W WO 2015145920 A1 WO2015145920 A1 WO 2015145920A1
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- H—ELECTRICITY
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- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
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- H—ELECTRICITY
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- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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- the present invention relates to a signal separation device and a signal separation method.
- Patent Document 1 discloses a technique for performing signal separation by independent component analysis.
- Patent Document 2 proposes a method of bidirectional communication at the same frequency in order to improve the bandwidth utilization in satellite communication.
- this communication method two ground stations transmit signals in the same band to the same communication satellite, and the satellite receives an interference signal in which the two signals interfere. Since the interference signal is directly frequency-converted and transmitted to the ground station, the ground station cannot perform signal separation based on the direction of arrival. Therefore, the ground station uses the transmission signal of its own station as a replica of one of the interference signals, and subtracts this replica from the interference signal to separate the signals of the other stations.
- the present invention has been made in view of the above circumstances, and an object of the present invention is to separate the interference signal without depending on the power and the arrival direction of the interference signal.
- the signal separation device includes a delay adjustment unit that acquires a plurality of interference signals composed of the same signal component and synchronizes a predetermined signal component of each interference signal, and the delay adjustment.
- a phase adjusting unit that adjusts a phase of the predetermined signal component included in the plurality of interference signals whose delays are adjusted by the unit, and a phase of the predetermined one signal component is adjusted by the waveform shaping unit. Adding means for adding and outputting the plurality of signals.
- a plurality of interference signals composed of the same signal components are acquired, a predetermined one signal component of each interference signal is synchronized, and the delays are adjusted.
- the phase of the predetermined one signal component included in the interference signal is adjusted, the plurality of signals in which the phase of the predetermined one signal component is adjusted are added, and the addition result is output.
- the interference signal can be separated without depending on the power and direction of arrival of the interference signal.
- FIG. 1 is a block diagram schematically showing a configuration of a signal separation device according to a first exemplary embodiment.
- FIG. 2 is a block diagram showing in more detail the configuration of the signal separation device according to the first exemplary embodiment; It is a figure which shows the relative delay of the signal component contained in common in two interference signals. It is a figure which shows the cross correlation of two interference signals. It is a figure which shows the timing of two interference signals in the output stage of a delay adjustment part.
- FIG. 3 is a block diagram schematically showing a configuration of a signal separation device according to a second exemplary embodiment.
- FIG. 6 is a block diagram schematically showing a configuration of a signal separation device according to a third exemplary embodiment.
- FIG. 6 is a block diagram schematically showing a configuration of a signal separation device according to a fourth exemplary embodiment.
- FIG. 1 is a block diagram schematically illustrating the configuration of the signal separation device 100 according to the first embodiment.
- the signal separation device 100 includes a delay adjustment unit 11, a waveform shaping unit 21, and an addition unit 31.
- the delay adjustment unit, the waveform shaping unit, and the addition unit are provided as a delay adjustment unit, a waveform shaping unit, and an addition unit for the interference signal, respectively.
- the delay adjustment unit 11 receives an interference signal S1 (also referred to as a first mixed signal) and an interference signal S2 (also referred to as a second mixed signal).
- the interference signal S1 and the interference signal S2 are generated when a single interference signal transmitted from the same transmission source reaches the signal separation device 100 via different paths. Therefore, the interference signal S1 and the interference signal S2 are signals representing the same information.
- the interference signal S1 and the interference signal S2 include a plurality of signal components.
- a common signal component C1 and a common signal component C2 as signal components included in common in the interference signal S1 and the interference signal S2.
- the interference signal S1 and the interference signal S2 pass through different paths, different delays occur between the interference signal S1 and the interference signal S2.
- the delay adjusting unit 11 can adjust the relative delay between the interference signal S1 and the interference signal S2. At this time, the delay adjustment unit 11 performs delay adjustment so that the timings of the common signal component C1 or the common signal component C2 included in the interference signal S1 and the interference signal S2 coincide. In the present embodiment, an example will be described in which the delay adjustment unit 11 performs delay adjustment so that the timings of the common signal component C1 included in the interference signal S1 and the interference signal S2 match.
- the waveform shaping unit 21 receives the interference signal S1 and the interference signal S2 whose relative delay has been adjusted by the delay adjustment unit 11.
- the waveform shaping unit 21 can phase-synchronize any of the common signal components included in the input interference signal S1 and interference signal S2. In the present embodiment, an example in which the waveform shaping unit 21 synchronizes the phase of the common signal component C1 will be described.
- the adding unit 31 adds the interference signal S1 and the interference signal S2 output from the waveform shaping unit 21 and in which any of the common signal components is phase-synchronized, and outputs the addition result as the output signal OUT1.
- FIG. 2 is a block diagram showing in more detail the configuration of the signal separation device 100 according to the first exemplary embodiment.
- the delay adjustment unit 11 includes a delay detector 111, a delay controller 112, and a delay device 113.
- the delay detector 111, the delay controller 112, and the delay device 113 are provided as interference signal delay detection means, delay control means, and delay means, respectively.
- the delay detector 111 is also referred to as first delay detection means.
- the delay controller 112 is also referred to as first delay control means.
- the delay device 113 is also referred to as first delay means.
- the delay detector 111 measures the relative delay between the interference signal S1 and the interference signal S2.
- the delay device 113 delays the interference signal S1.
- the delay controller 112 controls the delay amount of the interference signal S1 in the delay unit 113.
- the waveform shaping unit 21 includes an adaptive filter 211 and a subtractor 212.
- the adaptive filter is provided as means for adjusting the phase of the interference signal.
- the adaptive filter 211 is also referred to as first adjusting means.
- the subtractor 212 is also referred to as a first subtracter.
- the adaptive filter 211 shapes the output waveform of the interference signal S2.
- the subtractor 212 subtracts the output of the adaptive filter 211 from the output of the delay unit 113.
- the output of the subtracter 212 is fed back to the adaptive filter 211.
- the adaptive filter 211 adjusts the phase of the interference signal S2 by adjusting its own filter coefficient so that the output power of the subtractor 212 is minimized.
- the adder unit 31 includes an adder 311 that adds the interference signal S1 and the interference signal S2 output from the waveform shaping unit 21 and in which any common signal component is phase-synchronized, and outputs the addition result as the output signal OUT1. .
- the adder 311 is also referred to as a first adder.
- FIG. 3 is a diagram illustrating a relative delay of signal components included in common in two interference signals.
- common signal component C1 and common signal component C2 are included as signal components included in common in interference signal S1 and interference signal S2.
- FIG. 3 is assumed that common signal component C1 and common signal component C2 are included as signal components included in common in interference signal S1 and interference signal S2.
- the common signal component C1 of the interference signal S1 is the signal S1C1
- the common signal component C2 of the interference signal S1 is the signal S1C2
- the common signal component C1 of the interference signal S2 is the signal S2C1
- the common signal component C2 of the interference signal S2 is the signal.
- S2C2 is displayed.
- the relative delay that is the time difference between the signal S1C1 and the signal S2C1 is t1
- the relative delay that is the time difference between the signal S1C2 and the signal S2C2 is t2.
- FIG. 4 is a diagram showing the cross-correlation between two interference signals.
- the common signal component C1 has a strong correlation in the relative delay t1.
- the common signal component C2 has a strong correlation at the relative delay t2.
- the delay detector 111 obtains the correlation between the common signal components C1 and C2, and measures the relative delay from the position where a strong correlation is obtained.
- the delay detector 111 outputs the measured relative delays t1 and t2 to the delay controller 112. In the example of FIG. 4, the delay detector 111 obtains the relative delays t1 and t2 from the position of the cross correlation peak.
- the delay controller 112 corrects the relative delay between the two interference signals by controlling the delay amount of the delay device 113 based on the relative delay measured by the delay detector 111. Specifically, the delay controller 112 controls the delay amount of the interference signal S1 in the delay device 113 based on the relative delay t1. In this example, the delay controller 112 sets the delay amount of the interference signal S1 in the delay device 113 to t1.
- FIG. 5 is a diagram illustrating the timing of two interference signals at the output stage of the delay adjustment unit 11. The interference signal S1 is delayed by the delay device 113 by t1. Therefore, the relative delay between the signal S1C1 and the signal S2C1 at the output stage of the delay adjustment unit 11 is zero. On the other hand, the relative delay between the signal S1C2 and the signal S2C2 is t2-t1.
- the common signal component C1 included in the signal output by the adaptive filter 211 after adjusting the phase and amplitude of the signal S2 is expressed as a signal S2C1_A
- the common signal component C2 is expressed as a signal S2C2_A.
- the signal fed back from the subtractor 212 to the adaptive filter 211 is a signal S10 in which the signal S1C1 at the output stage of the delay adjustment unit 11 interferes with the signal S2C1_A output from the adaptive filter 211.
- the adaptive filter 211 adjusts its own filter coefficient so that the power of the output of the subtractor 212 (that is, the signal S10) is minimized. Minimizing the power of the signal S10 means minimizing an error between the signal S1C1 and the signal S2C1_A output from the adaptive filter 211, that is, matching the phase and amplitude of both signals.
- the adder 311 adds the signal S1C1 at the output stage of the delay adjustment unit 11 and the signal S2C1_A output from the adaptive filter 211 in a phase-synchronized state.
- the power of the common signal component C1 in the output signal OUT1 is the sum of the power of the signal S1C1 and the power of the signal S2C1 at the output stage of the delay adjustment unit 11.
- the adder 311 further adds the signal S1C2 at the output stage of the delay adjustment unit 11 and the signal S2C2_A output from the adaptive filter 211.
- the relative delay (t2-t1) between the signal S1C2 and the signal S2C2_A is sufficiently larger than the time corresponding to the number of taps of the adaptive filter 211, the phases of the signal S1C2 and the signal S2C2 can be matched. Can not. Therefore, the amplitude of the common signal component C2 is not significantly amplified.
- the signal separation device 100 can substantially separate and extract the common signal component C1 from the common signal component C2.
- a predetermined signal component can be extracted with a simple configuration using a plurality of interference signals regardless of the power difference or arrival direction of the interference signals.
- FIG. 6 is a block diagram schematically illustrating the configuration of the signal separation device 200 according to the second embodiment.
- the signal separation device 200 has a configuration in which the delay adjustment unit 11 of the signal separation device 100 is replaced with a delay adjustment unit 12.
- the delay adjustment unit 12 adds a delay unit 123 (also referred to as second delay unit) to the delay adjustment unit 11, and the delay controller 112 of the delay adjustment unit 11 corresponds to the delay controller 122 (second delay control unit). To be). Since the other configuration of the signal separation device 200 is the same as that of the signal separation device 100, description thereof is omitted.
- the delay unit 123 delays the interference signal S2.
- the delay controller 122 controls the delay amount of the interference signal S 1 in the delay device 113 and the delay amount of the interference signal S 2 in the delay device 123. That is, the delay controller 122 corrects the relative delay between the two interference signals by controlling the delay amounts in the delay unit 113 and the delay unit 123 based on the relative delay measured by the delay detector 111. Specifically, the delay controller 112 controls the delay amount of the interference signal S1 in the delay device 113 and the delay amount of the interference signal S2 in the delay device 123 based on the relative delays t1 and t2.
- the signal separation device 200 can adjust the delay amount of the interference signal more flexibly than the signal separation device 100.
- FIG. 7 is a block diagram schematically illustrating the configuration of the signal separation device 300 according to the third embodiment.
- the signal separation device 300 has a configuration in which the delay adjustment unit 11, the waveform shaping unit 21, and the addition unit 31 of the signal separation device 100 are replaced with a delay adjustment unit 13, a waveform shaping unit 23, and an addition unit 32, respectively.
- the delay adjustment unit 13 has a configuration in which a delay unit 133 (also referred to as second delay unit) and a delay controller 132 (also referred to as second delay control unit) are added to the delay adjustment unit 11.
- the delay unit 133 delays the interference signal S1.
- the delay controller 132 controls the delay amount of the interference signal S 1 in the delay unit 133.
- the waveform shaping unit 23 has a configuration in which an adaptive filter 231 (also referred to as a second adjustment unit) and a subtractor 232 (also referred to as a second subtractor) are added to the waveform shaping unit 21.
- the adaptive filter 231 and the subtracter 232 correspond to the adaptive filter 211 and the subtracter 212 of the waveform shaping unit 21, respectively, and have the same functions as these.
- the adaptive filter 231 shapes the output waveform of the interference signal S2.
- the subtracter 232 subtracts the output of the adaptive filter 231 from the output of the delay unit 133.
- the output (signal S11) of the subtractor 232 is fed back to the adaptive filter 231.
- the adaptive filter 231 adjusts the phase of the interference signal S2 by adjusting its own filter coefficient so that the output power of the subtractor 232 is minimized.
- the addition unit 32 has a configuration in which an adder 321 (also referred to as a second adder) is added to the addition unit 31.
- the adder 321 adds the output of the delay unit 133 and the output of the adaptive filter 231 and outputs the addition result as the output signal OUT2.
- the delay controller 132 of the delay adjustment unit 13 controls the delay amount of the delay unit 133 based on the relative delay measured by the delay detector 111, thereby reducing the relative delay between the two interference signals. to correct. Specifically, the delay controller 132 controls the delay amount of the interference signal S1 in the delay unit 133 based on the relative delay t2. In this example, the delay controller 132 sets the delay amount of the interference signal S2 in the delay device 113 to t2. As a result, the relative delay between the signal S1C2 and the signal S2C2 at the output stage of the delay unit 133 becomes zero. On the other hand, the relative delay between the signal S1C1 and the signal S2C1 is t1-t2.
- the operations of the waveform shaping unit 23 and the addition unit 32 are the same as those of the waveform shaping unit 21 and the addition unit 31 of the signal separation device 100, respectively, and thus description thereof is omitted.
- the correlation between the signal S1C2 and the signal S2C2 is strong and the phase is synchronized.
- the power of the common signal component C2 in the output signal OUT2 of the adder 32 becomes the sum of the power of the signal S1C2 and the power of the signal S2C2 in the output stage of the delay adjustment unit 11.
- the common signal component C2 can be extracted with high power.
- FIG. 8 is a block diagram schematically illustrating a configuration of the signal separation device 400 according to the fourth embodiment.
- the signal separation device 400 has a configuration in which the delay adjustment unit 11, the waveform shaping unit 21, and the addition unit 31 of the signal separation device 100 are replaced with the delay adjustment unit 14, the waveform shaping unit 24, and the addition unit 33, respectively.
- the delay adjustment unit 14 includes a delay detector 141 (also referred to as second delay detection unit), a delay controller 142 (also referred to as third delay control unit), and a delay unit 143 (third delay unit). (Also referred to as).
- the delay detector 141 measures the relative delay between the interference signal S1 and the interference signal S3.
- the interference signal S3 is a signal similar to the interference signal S3 and is a signal that has reached the signal separation device 400 via a path different from that of the interference signals S1 and S2.
- the delay device 143 delays the interference signal S3.
- the delay controller 142 controls the delay amount of the interference signal S3 in the delay unit 143.
- the waveform shaping unit 24 has a configuration in which an adaptive filter 241 (also referred to as a third adjustment unit) and a subtractor 242 (also referred to as a third subtractor) are added to the waveform shaping unit 21.
- the adaptive filter 241 and the subtractor 242 correspond to the adaptive filter 211 and the subtracter 212 of the waveform shaping unit 21, respectively, and have the same functions as these.
- the adaptive filter 241 shapes the waveform of the interference signal S3 delayed by the delay unit 142.
- the subtractor 242 subtracts the output of the adaptive filter 241 from the output of the delay unit 113.
- the output (signal S12) of the subtractor 242 is fed back to the adaptive filter 241.
- the adaptive filter 241 adjusts the phase of the interference signal S3 by adjusting its filter coefficient so that the output power of the subtractor 242 is minimized.
- the adder 33 has a configuration in which an adder 331 (also referred to as a third adder) is added to the adder 31.
- the adder 331 adds the output of the adder 311 and the output of the adaptive filter 241 and outputs the addition result as an output signal OUT1.
- the delay controller 142 of the delay adjustment unit 14 controls the delay amount of the delay unit 143 based on the relative delay measured by the delay detector 141, thereby reducing the relative delay between the two interference signals. to correct.
- the delay controller 142 controls the delay amount of the interference signal S3 in the delay device 143 based on the relative delay t3 of the common signal component C1 of the interference signal S1 and the interference signal S3.
- t4 be the relative delay of the common signal component C2 of the interference signal S1 and the interference signal S3.
- the delay controller 142 sets the delay amount of the interference signal S3 in the delay unit 143 to t3.
- the relative delay between the signal S1C1 and the signal S3C1 at the output stage of the delay device 143 becomes zero.
- the relative delay between the signal S1C2 and the signal S3C2 is t3-t4.
- the signal S3C1 reaches the delay adjustment unit 14 earlier than the signal S2C1.
- the adaptive filter 241 and the subtractor 242 correspond to the adaptive filter 211 and the subtracter 212 of the waveform shaping unit 21, respectively, and have the same functions as these. Therefore, the common signal component C1 of the interference signal S1 and the interference signal S3 is in a phase-synchronized state.
- the adder 331 adds the output of the adder 311 (common signal component C1) and the output of the adaptive filter 241 (common signal component C1) in a phase-synchronized state.
- the signal separation device 400 outputs the result of adding the three interference signals as the output signal OUT1 in a state where one common signal is in phase synchronization. Therefore, the power of the output signal OUT1 can be further increased as compared with the signal separation device 100.
- two delay devices may be provided so as to adjust the delays of the two interference signals.
- the signal separation devices according to the third and fourth embodiments can be combined. That is, a single signal separation device can extract a plurality of signal components and increase the power of the extracted signal components.
- the subtractor of the above-described embodiment is an example. Therefore, the order of subtraction may be reversed. That is, it suffices if the difference in power between the two signals input to the subtractor can be obtained.
- the interference signal input to the subtractor and the interference signal input to the adaptive filter may be interchanged.
- the interference signal is not limited to two. It is possible to add one signal component of three or more interference signals and output the addition result. Further, the number of signal components included in the interference signal is not limited to two. As long as there is one phase-synchronized signal component of the added interference signal, the mixed signal can include three or more signal components.
- phase adjustment of one signal component of the interference signal can be established by the delay adjustment unit, it is possible to configure a signal separation device that omits the waveform shaping unit.
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Abstract
Description
実施の形態1にかかる信号分離装置について説明する。図1は、実施の形態1にかかる信号分離装置100の構成を模式的に示すブロック図である。信号分離装置100は、遅延調整部11、波形整形部21及び加算部31を有する。遅延調整部、波形整形部及び加算部は、それぞれ混信信号の遅延調整手段、波形整形手段部及び加算手段として設けられる。
S10=S1C1-S2C1_A+S1C2-S2C2_A
実施の形態2にかかる信号分離装置200について説明する。図6は、実施の形態2にかかる信号分離装置200の構成を模式的に示すブロック図である。信号分離装置200は、信号分離装置100の遅延調整部11を遅延調整部12に置換した構成を有する。遅延調整部12は、遅延調整部11に遅延器123(第2の遅延手段とも称する)を追加し、遅延調整部11の遅延制御器112を遅延制御器122(第2の遅延制御手段に対応する)に置換した構成を有する。信号分離装置200のその他の構成は、信号分離装置100と同様であるので、説明を省略する。
実施の形態3にかかる信号分離装置300について説明する。図7は、実施の形態3にかかる信号分離装置300の構成を模式的に示すブロック図である。信号分離装置300は、信号分離装置100の遅延調整部11、波形整形部21及び加算部31を、それぞれ遅延調整部13、波形整形部23及び加算部32に置換した構成を有する。
実施の形態4にかかる信号分離装置400について説明する。図8は、実施の形態4にかかる信号分離装置400の構成を模式的に示すブロック図である。信号分離装置400は、信号分離装置100の遅延調整部11、波形整形部21及び加算部31を、それぞれ遅延調整部14、波形整形部24及び加算部33に置換した構成を有する。
21、23、24 波形整形部
31~33 加算部
111、141 遅延検出器
112、122、132、142 遅延制御器
113、123、133、143 遅延器
211、231、241 適応フィルタ
212、232、242 減算器
311、321、331 加算器
OUT1、OUT2 出力信号
100、200、300、400 信号分離装置
Claims (11)
- 同一の信号成分で構成される複数の混信信号を取得し、各混信信号の所定の1つの信号成分の同期をとる遅延調整手段と、
前記遅延調整手段で遅延が調整された前記複数の混信信号に含まれる前記所定の1つの信号成分の位相を調整する波形整形手段と、
前記波形整形手段により前記所定の1つの信号成分の位相が調整された前記複数の信号を加算し、出力する加算手段と、を備える、
信号分離装置。 - 前記所定の1つの信号成分と前記混信信号とを用いて、前記混信信号に含まれる前記所定の1つの信号成分とは異なる信号成分を取得する手段をさらに備える、
請求項1に記載の信号分離装置。 - 前記波形整形手段は、更に、前記遅延調整手段で遅延が調整された前記複数の信号に含まれる前記所定の1つの信号成分の振幅を調整して、前記加算手段から出力される前記信号の大きさを調整する、
請求項1又は2に記載の信号分離装置。 - 前記波形整形手段は、前記遅延調整手段から出力される複数の混信信号のうちの1つの混信信号の位相を調整し、位相が調整された混信信号を出力し、
前記位相が調整された混信信号と、前記位相が調整された混信信号とは異なる複数の混信信号のうちの1つと、の差を出力する第1の減算器を備える、
請求項1乃至3のいずれか一項に記載の信号分離装置。 - 前記複数の混信信号は、第1の混信信号と、前記第1の混信信号とは異なる経路で前記遅延調整手段に到達する第2の混信信号と、を含み、
前記波形整形手段は、
前記遅延調整手段で調整された前記第1の混信信号及び前記第2の混信信号の一方の位相を調整した信号を出力する第1の調整手段を備え、
前記第1の調整手段は、前記第1の減算器の出力の大きさが最小となるように、前記第1の混信信号又は前記第2の混信信号に含まれる前記所定の1つの信号成分の位相又は位相と振幅とを調整し、
前記加算手段は、前記第1の混信信号及び前記第2の混信信号のうちで前記第1の減算器に入力されるものと、前記第1の調整手段が出力する前記信号と、を加算した信号を出力する第1の加算器を備える、
請求項4に記載の信号分離装置。 - 前記遅延調整手段は、
前記第1の混信信号の前記所定の1つの信号成分と、前記第2の混信信号の前記所定の1つの信号成分と、の間の第1の相対遅延を検出する第1の遅延検出手段と、
前記第1の混信信号及び前記第2の混信信号の一方又は両方を遅延させる第1の遅延手段と、
検出した前記第1の相対遅延に基づいて、前記第1の遅延手段での前記第1の混信信号及び前記第2の混信信号の一方又は両方の遅延を制御する第1の遅延制御手段と、を備える、
請求項5に記載の信号分離装置。 - 前記遅延調整手段は、
前記第1の混信信号及び前記第2の混信信号に含まれる前記所定の1つの信号である第1の信号成分とは異なる第2の信号成分間に遅延が生じないように、前記第1の混信信号及び前記第2の混信信号の一方又は両方の遅延を調整し、
前記波形整形手段は、前記第2の信号成分間に遅延が生じないように遅延が調整された前記第1の混信信号及び前記第2の混信信号に含まれる前記第2の信号成分の位相を同期させ、
前記加算手段は、前記波形整形手段により前記第2の信号成分の位相が同期された前記第1の混信信号と前記第2の混信信号とを加算した信号を更に出力する、
請求項6に記載の信号分離装置。 - 前記第1の遅延検出手段は、前記第1の混信信号の前記第2の信号成分と、前記第2の混信信号の前記第2の信号成分と、の間の第2の相対遅延を更に検出し、
前記遅延調整手段は、
前記第1の混信信号及び前記第2の混信信号の一方又は両方を遅延させる第2の遅延手段と、
検出した前記第2の相対遅延に基づいて、前記第2の遅延手段での前記第1の混信信号及び前記第2の遅延手段の一方又は両方の遅延を制御する第2の遅延制御手段と、を更に備え、
前記波形整形手段は、
前記第2の信号成分間に遅延が生じないように遅延が調整された前記第1の混信信号及び前記第2の混信信号の一方の位相を調整した信号を出力する第2の調整手段と、
前記第2の信号成分間に遅延が生じないように遅延が調整された前記第1の混信信号及び前記第2の混信信号の他方と、前記第2の調整手段が出力する前記信号と、の差を出力する第2の減算器と、を更に備え、
前記第2の調整手段は、前記2の減算器の出力の大きさが最小となるように、前記第1の混信信号又は前記第2の混信信号に含まれる前記第2の信号成分の位相又は位相と振幅とを調整し、
前記加算手段は、前記第2の信号成分間に遅延が生じないように遅延が調整された前記第1の混信信号及び前記第2の混信信号のうちで前記第2の減算器に入力されるものと、前記第2の調整手段が出力する前記信号と、を加算した信号を出力する第2の加算器を備える、
請求項7に記載の信号分離装置。 - 前記複数の混信信号は、前記第1の混信信号及び前記第2の混信信号とは異なる第3の混信信号を含み、
前記遅延調整手段は、
前記第1の混信信号及び前記第3の混信信号に含まれる前記所定の1つの信号成分間に遅延が生じないように、前記第1の混信信号及び前記第3の混信信号の一方又は両方の遅延を調整し、
前記波形整形手段は、前記遅延調整手段で遅延が調整された前記第1の混信信号及び前記第3の混信信号に含まれる前記第2の信号成分の位相を同期させ、
前記加算手段は、前記波形整形手段により前記所定の1つの信号成分の位相が同期された前記第1の混信信号と前記第3の混信信号とを加算した信号と、前記波形整形手段により前記所定の1つの信号成分の位相が同期された前記第1の混信信号と前記第2の混信信号とを加算した前記信号と、を加算した信号を出力する、
請求項7に記載の信号分離装置。 - 前記複数の混信信号は、前記第1の混信信号及び前記第2の混信信号とは異なる第3の混信信号を含み、
前記遅延調整手段は、
前記第1の混信信号の前記所定の1つの信号成分と、前記第3の混信信号の前記所定の1つの信号成分と、の間の第3の相対遅延を検出する第2の遅延検出手段と、
前記第1の混信信号及び前記第3の混信信号の一方又は両方を遅延させる第3の遅延手段と、
検出した前記第3の相対遅延に基づいて、前記第3の遅延手段での前記第1の混信信号及び前記第3の混信信号の一方又は両方の遅延を制御する第3の遅延制御手段と、を備え、
前記波形整形手段は、
前記遅延調整手段で調整された前記第1の混信信号及び前記第3の混信信号の一方の位相を調整した信号を出力する第3の調整手段と、
前記遅延調整手段で調整された前記第1の混信信号及び前記第3の混信信号の他方と、前記第3の調整手段が出力する前記信号と、の差を出力する第3の減算器と、を備え、
前記第3の調整手段は、前記第3の減算器の出力の大きさが最小となるように、前記第1の混信信号又は前記第3の混信信号に含まれる前記所定の1つの信号成分の位相又は位相と振幅とを調整し、
前記加算手段は、前記第1の加算器の出力と、前記第3の調整手段が出力する前記信号と、を加算した信号を出力する第3の加算器を更に備える、
請求項9に記載の信号分離装置。 - 同一の信号成分で構成される複数の混信信号を取得し、
各混信信号の所定の1つの信号成分の同期をとり、
遅延が調整された前記複数の混信信号に含まれる前記所定の1つの信号成分の位相を調整し、
前記所定の1つの信号成分の位相が調整された前記複数の信号を加算し、
加算結果を出力する、
信号分離方法。
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JPH11231900A (ja) * | 1998-02-17 | 1999-08-27 | Nagano Japan Radio Co | 雑音低減方法および雑音低減装置 |
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WO2012049986A1 (ja) * | 2010-10-12 | 2012-04-19 | 日本電気株式会社 | 信号処理装置、信号処理方法、並びに信号処理プログラム |
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JPH11231900A (ja) * | 1998-02-17 | 1999-08-27 | Nagano Japan Radio Co | 雑音低減方法および雑音低減装置 |
JP2011022604A (ja) * | 2003-09-02 | 2011-02-03 | Nec Corp | 信号処理方法および装置 |
WO2012049986A1 (ja) * | 2010-10-12 | 2012-04-19 | 日本電気株式会社 | 信号処理装置、信号処理方法、並びに信号処理プログラム |
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