WO2015141384A1 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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Definitions
- the present invention relates to a semiconductor device such as a semiconductor device mounted on a power converter or the like and a method for manufacturing the semiconductor device.
- FIG. 1 A cross-sectional view of a conventional semiconductor device is shown in FIG.
- the semiconductor chip 6 mounted on the semiconductor device there are an IGBT (Insulated Gate Bipolar Transistor), MOSFET, (MOS field effect transistor), FWD (Free Wheeling Diode) and the like.
- IGBT Insulated Gate Bipolar Transistor
- MOSFET MOSFET
- FWD Free Wheeling Diode
- the semiconductor device on which the IGBT is mounted is referred to as an IGBT device.
- an IGBT device will be described as an example of a semiconductor device.
- Insulating circuit board 4 having a small linear expansion coefficient (linear expansion coefficient of ceramic substrate: 4.6 to 7.3 ⁇ 10 ⁇ 6 K ⁇ 1 ) and metal plate 3 having a large linear expansion coefficient (linear expansion coefficient of copper: 16. This is because the main surface of 6 ⁇ 10 ⁇ 6 K ⁇ 1 ) is joined at a high temperature via the solder 5, so that when it returns to room temperature, it bends to the side with a larger linear expansion coefficient.
- Patent Document 1 discloses that the back surface of the metal plate opposite to the surface to which the insulating circuit substrate is bonded is subjected to shot peening treatment to warp in a concave shape. A method of flattening a metal plate is disclosed.
- Patent Document 2 discloses a metal-ceramic bonding substrate in which a metal circuit board is bonded to one surface of a ceramic substrate and one surface of the heat dissipation plate is bonded to the other surface. A method is described in which a metal-ceramic bonding substrate having a work hardened layer on its surface prevents the back surface from greatly warping even when heated for soldering.
- JP 2006-332084 A (Summary, Claim 1, FIG. 6) Japanese Patent No. 3971296 (paragraph 0011, FIGS. 1 to 3)
- the metal plate is likely to warp due to a difference in linear expansion coefficient between assembly parts.
- the metal plate has a warp as shown in FIG. An air gap is formed between the surface of the cooler.
- the gap due to the warp of the metal plate (referred to as a concave warp or a negative warp) is difficult to be eliminated even if a bolt is inserted into a hole provided around the metal plate and tightened with the bolt. There was a problem that heat dissipation was reduced.
- FIG. 7C In order to prevent the negative warpage of the metal plate in the semiconductor device, as shown in FIG. 7C, a positive warpage that warps in the opposite direction to the negative warp is given to the metal plate as an initial warp in advance.
- FIG. 7D there is known a method of forming a flat or weakly warped metal plate after the soldering process.
- the correction method of the normal warp shown in (c) and (d) when a metal plate having an initial warp is used, there is a gap between the metal plate and the insulating circuit board. There is a problem that it tends to decrease.
- insulating substrates mainly composed of aluminum nitride or silicon nitride will be widely used in the future.
- the thermal conductivity is better than that of the substrate, the linear expansion coefficient is small, and the difference in linear expansion coefficient with the metal plate is large, so that the amount of warpage of the metal plate tends to further increase.
- the inventor found that in a semiconductor device in which one insulating circuit board was soldered to one surface of a metal plate, the metal plate was bent as a whole, and a plurality of insulating circuit boards were soldered.
- the present inventors have found an unknown technical problem that a complicated warpage occurs in a semiconductor device.
- the back surface regions (4a to 4f) where the plurality of insulated circuit boards are arranged are indicated by the contour lines of the metal plate 3 indicated by dotted lines in FIG. 8 (b). It showed in.
- local warping occurs in each place where a plurality of insulated circuit boards are arranged.
- the phenomenon of local warpage in the metal plate corresponding to the insulation circuit board and the metal plate warping may interfere with the spread of the heat dissipation grease or cause a thick portion of the heat dissipation grease to dissipate heat. Sex worsens.
- an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce not only warpage of the entire metal plate joined to the cooler but also local warpage caused by joining a plurality of insulated circuit boards. Is to provide.
- a semiconductor device includes an insulating substrate, a circuit unit connected to a semiconductor element on the front surface of the insulating substrate, and a plurality of insulating units each including a metal unit on the back surface of the insulating substrate.
- a semiconductor device comprising a circuit board, a metal plate that is larger than the insulated circuit board and is joined to the metal portion of the plurality of insulated circuit boards, and a joining member that joins the insulated circuit board and the metal plate.
- the metal plate has a first region corresponding to the arrangement of the metal portion on the back surface of the metal plate, the insulating circuit board being spaced apart from each other on the front surface of the metal plate. And a second region excluding the first region, and a surface work hardened layer is provided on at least a part of the surface of the first region, and the second region is different from the hardness of the surface work hardened layer. It is characterized by that.
- the present invention by forming a surface work hardened layer on at least a part of the first region corresponding to each insulated circuit board position of the metal plate having a plurality of insulated circuit boards, only warpage of the entire metal plate is achieved. In addition, local negative warpage of the metal plate can be prevented, the gap between the metal plate and the cooler can be narrowed, and heat dissipation can be improved.
- the surface work hardened layer extends over the plurality of first regions.
- the direction in which the surface work hardened layer extends across the plurality of first regions is a direction in which the width of the metal plate is short.
- the amount of warpage in the first region is preferably 50 ⁇ m or less.
- the amount of warpage means the difference in elevation between the center of the curved surface and the edge.
- the local warpage of the first region can be suppressed, the gap between the metal plate and the cooler can be narrowed, and the heat dissipation can be improved.
- the area of the surface work hardened layer in the first region is preferably 30% or more of the area of the first region.
- the amount of local warpage of the first region can be suppressed to 50 ⁇ m or less.
- the material of the insulating substrate is preferably composed mainly of aluminum oxide, aluminum nitride, or silicon nitride.
- the metal plate is a heat dissipation plate for cooling the semiconductor element.
- a method of manufacturing a semiconductor device includes an insulating substrate, a circuit portion connected to a semiconductor element on a front surface of the insulating substrate, a plurality of insulating circuit substrates including a metal portion on the back surface of the insulating substrate, A first area corresponding to the arrangement of the metal portion on the back surface, and a second area excluding the first area, the insulating circuit board being larger than the insulating circuit board and spaced apart from each other on the front surface;
- a method of manufacturing a semiconductor device comprising a metal plate provided with a region and a joining member that joins the insulating circuit substrate and the metal plate, at least a part of the first region of the back surface of the metal plate is provided.
- the surface work hardened layer is formed in at least a part of the first region, the local negative warpage of the metal plate is prevented, the gap between the metal plate and the cooler is narrowed, and the heat dissipation is improved. Can be improved.
- the method for manufacturing a semiconductor device of the present invention it is preferable to include a step of heat-treating the semiconductor device after forming the surface work hardened layer.
- the heat treatment is preferably performed at a heating temperature of 60 ° C. or higher and 175 ° C. or lower.
- a cooling process is performed after the heating process, and the heating process and the cooling process are alternately repeated.
- the number of cycles of the heat treatment and the cooling treatment is preferably 1 cycle or more.
- the heat treatment is preferably performed at 150 ° C.
- the cooling treatment is preferably performed at ⁇ 40 ° C.
- the present invention by forming a surface work hardened layer on at least a part of the first region corresponding to each insulated circuit board position of the metal plate having a plurality of insulated circuit boards, only warpage of the entire metal plate is achieved. In addition, local negative warpage of the metal plate can be prevented, the gap between the metal plate and the cooler can be narrowed, and heat dissipation can be improved.
- FIG. 3 is an enlarged view of FIG. It is a cross-sectional schematic diagram for demonstrating the shot peening process concerning a prior art. It is a cross-sectional schematic diagram for demonstrating the shot peening process based on this invention. It is sectional drawing of a common semiconductor device. It is a cross-sectional schematic diagram for demonstrating the curvature of the metal plate of a semiconductor device. It is a contour map which shows an example of the curvature of the metal plate which concerns on a semiconductor device of a prior art.
- FIG. 1 schematically shows a cross-sectional view showing a state in which a semiconductor device according to the present invention is attached to a cooler 1.
- a semiconductor device 100 is mounted on the cooler 1 via heat radiation grease 2.
- the semiconductor device 100 includes a metal plate 20, a semiconductor device structure 30, external terminals 8, and a terminal case 9 that accommodates these, and the terminal case 9 is filled with a sealing resin 10.
- the semiconductor device structure 30 includes a semiconductor chip 6 such as IGBT, MOSFET, FWD, and an insulating circuit substrate 21 in which a circuit portion 25 is disposed on the front surface of the insulating substrate 7 and a metal portion 26 is disposed on the back surface.
- the back surface of the semiconductor chip 6 is joined to the circuit portion 25 of the insulating circuit board 21 via the solder 5.
- the electrode on the front surface side of the semiconductor chip 6 is electrically connected to the external terminal 8 by a bonding wire (not shown).
- the material of the insulating substrate 7 is preferably a material such as aluminum oxide, aluminum nitride, or silicon nitride that is excellent in heat conduction.
- the circuit portion 25 and the metal portion 26 are made of a highly conductive metal such as a copper plate or copper foil as a main material. It is desirable to do.
- a plurality of semiconductor device structures 30 are arranged on the metal plate 20 so as to be separated from each other, and the metal portion 26 of the insulating circuit board 21 is soldered to the metal plate 20.
- the arrangement of the semiconductor device structures 30 is not particularly limited. In FIG. 1, six semiconductor device structures 30 are arranged in a row at intervals, but the number of metal portions 26 of the insulating circuit board 21 is, for example, three They can be arranged in two rows at intervals. Furthermore, when there are many numbers, it can also arrange in a different arrangement
- a region corresponding to the arrangement of the metal portion 26 of the insulating circuit board 21 is defined as a first region.
- One region 13 is used, and a region excluding the first region 13 is a second region 14.
- the surface work hardened layer 11 is formed in at least a part of the first region 13, and the second region 14 is different from the hardness of the surface work hardened layer 11.
- the effect of the surface work hardened layer 11 is to reduce local negative warpage in the first region 13.
- the formation method of the surface work hardening layer 11 is not specifically limited, For example, it can form by the shot peening process etc. which are mentioned later.
- the surface work hardened layer 11 is drawn in the same shape and size as the first region 13, but in another embodiment, the surface work hardened layer 11 is partially formed inside the first region 13. In another embodiment, the surface work hardened layer 11 may be formed so as to extend across a plurality of the first regions 13. For example, within the allowable range of warpage, the region where the surface work hardened layer 11 is formed may be a simplified pattern including a plurality of first regions 13. Since the warpage is small in the direction in which the width of the metal plate 20 is short, the direction in which the surface work hardened layer 11 extends across the first region 13 is preferably the direction in which the width of the metal plate 20 is short.
- the local warpage amount (the difference in elevation between the center of the curved surface and the edge) in the first region 13 of the metal plate 20 is 50 ⁇ m or less. Therefore, the area of the surface work hardened layer 11 in the first region 13 is preferably 30% or more of the area of the first region 13.
- FIG. 5 schematically shows a cross section of a semiconductor device that is subjected to shot peening processing in order to form the surface work hardened layer 11 in the first region 13 of the metal plate 20.
- a plurality of insulating circuit boards 21 are arranged on a flat metal plate 20 that has not been warped in advance, the semiconductor chip 6, the insulating circuit board 21 and the metal plate 20 are connected by solder 5, The semiconductor chips 6 and the semiconductor chips 6 and external terminals (not shown) are wire-bonded, accommodated in a terminal case (not shown), and filled with a sealing resin (not shown) to complete the semiconductor module. Then, the region not to be treated is covered with a mask 12 so that the surface work hardened layer 11 can be selectively formed on the surface of the metal plate 20.
- the material of the mask is not particularly limited, and for example, a resist mask or a metal mask can be used.
- a shot material 27 obtained by kinetic energy by the ultrasonic vibration device 28 is strongly struck on the unmasked exposed surface of the metal plate 20 to compress the surface layer.
- a method of forming a surface work hardened layer 11 in which stress is maintained is illustrated.
- the shot material 27 is not particularly limited, and for example, metal particles, ceramic particles, glass particles having an average particle diameter of about 1 to 3 mm can be used.
- the method of giving kinetic energy to the shot material 27 is not particularly limited, and other than the ultrasonic vibration device, a method of mixing and blowing the pressure airflow and the shot material 27 may be used.
- the surface work hardened layer 11 having a thickness of several ⁇ m to several hundreds ⁇ m is formed on the surface of the lower surface of the metal plate 20, and the hardness between the formed surface work hardened layer 11 and the inside of the metal plate 20. Due to the difference, compressive stress is generated so that the surface work hardened layer 11 side becomes convex, so that the metal plate 20 is warped as a whole, and local negative warpage is reduced in the first region 13. .
- the difference from the conventional shot peening process is not a method of processing the entire surface of the metal plate 20, but the mask 12 is formed so that the surface work hardened layer 11 is selectively formed on at least a part of the first region 13. It is used.
- the negative warpage of the first region 13 corresponding to the insulated circuit board 21 cannot be improved only by performing the shot peening process on the entire surface of the metal plate 20. The reason is considered that local unevenness of the metal plate 20 is warped by the same amount in the same direction due to the entire surface shot peening.
- the method for manufacturing a semiconductor device of the present invention it is possible to selectively perform shot peening and reduce local negative warpage at the place where the insulating circuit substrate 21 is disposed. It is not necessary to use the metal plate 20 provided with Therefore, since the metal plate 20 such as copper having no initial warp can be used, the yield rate of the soldering process is improved.
- the method for manufacturing a semiconductor device of the present invention can include heat treatment of the semiconductor device after the surface work hardened layer 11 is formed on the metal plate 20, and can relieve stress at the solder joints when the semiconductor device is used. The change with time of the warpage amount of the metal plate can be suppressed.
- the heat treatment is preferably performed at a temperature at which the solder does not melt, and the heating temperature is preferably 60 ° C. or higher and 175 ° C. or lower. In this temperature range, the change with time of the warpage amount of the metal plate 20 can be effectively suppressed.
- the heat treatment may be a heat treatment for keeping the semiconductor device at a constant temperature, or may be a heat cooling treatment in which the heat treatment and the cooling treatment are alternately repeated. It is desirable to repeat the heating and cooling treatment until the warpage amount of the metal plate 20 is saturated.
- the warpage of the metal plate can be largely controlled to the forward warpage side, the coefficient of linear expansion is smaller than that of the insulating circuit substrate having an insulating substrate mainly composed of alumina, but the heat conduction. Since an insulating circuit substrate having an insulating substrate whose main component is aluminum nitride or silicon nitride having a higher rate can be applied, the semiconductor device can be reduced in size and weight. Furthermore, since the metal plate can be warped, and negative warp in each region of the opposite metal plate corresponding to each position in the plurality of insulated circuit boards can be reduced. The wetting and spreading property of the resin is improved, and it becomes possible to further reduce the thickness of the heat dissipating grease, thereby improving the heat dissipating property.
- Example 1 A test sample in which six insulating circuit boards 21 are arranged on a metal plate 20 made of copper as shown in FIG. 5 (as shown in FIG. 8B in plan view) is manufactured, and then the insulating circuit board is prepared. A region other than the first region 13 corresponding to 21 was covered with a resist mask and selectively shot peened, and then the warpage value was measured with a 3D laser displacement meter.
- the warpage amount in the longitudinal direction (the difference in elevation between the center of the curved surface and the edge) shown in FIG. 2A is a positive warp amount of 500 ⁇ m as a whole, and is locally localized due to the influence of the insulating circuit board 21. Warping has been almost eliminated.
- FIG. 3 is an enlarged view of FIG.
- FIG. 9A A test sample was prepared in the same procedure as in Example 1, and the warp value was measured with a 3D laser displacement meter as it was without performing shot peening.
- the warp in the longitudinal direction shown in FIG. 9A is a positive warp amount of about 200 ⁇ m as a whole, and locally a negative warp amount of about 50 ⁇ m due to the influence of the insulating circuit board 21. Yes.
- the warp in the short direction shown in FIG. 9B is a positive warp amount of about 100 ⁇ m as a whole, and a negative warp amount of about 50 ⁇ m locally due to the influence of the insulating circuit board 21. It has become.
- FIG. 10 is an enlarged view of FIG.
- FIG. 11A A test sample was prepared in the same procedure as in Example 1, and then subjected to shot peening treatment over the entire surface of the metal plate 20, and then the warpage value was measured with a 3D laser displacement meter.
- the warp in the longitudinal direction shown in FIG. 11A is a positive warp amount of about 600 ⁇ m as a whole, and locally a negative warp amount of about 30 ⁇ m due to the influence of the insulating circuit board 21. Yes.
- the warp in the short direction shown in FIG. 11B is a total warp amount of 200 ⁇ m as a whole, and there is no local warp due to the influence of the insulating circuit board 21.
- FIG. 12 is an enlarged view of FIG.
- the local negative warpage corresponding to the insulating circuit board 21 can be improved only to about half of the case where the shot peening process is not performed. It was. According to the selective shot peening process of the present invention, local negative warping can be almost eliminated. According to the present invention, the overall normal warpage increases, but this is not a problem because the four corners of the metal plate 20 can be bolted to the cooler 1 to be in close contact.
- FIG. 13 is a diagram showing the amount of change in the warp value of the metal plate 20 when the temperature is returned to room temperature (25 ° C.) after the heat treatment only once at each temperature.
- the heating time was 1 hour.
- a value obtained by subtracting the minimum value from the maximum value of the warp value of the metal plate 20 at room temperature (25 ° C.), and a value obtained by subtracting the minimum value from the maximum value of the warp value at each temperature (125 ° C., 150 ° C., 175 ° C.) was the amount of change in the warp value.
- the semiconductor can be obtained by performing heat treatment in the range of 60 ° C. or more and 175 ° C. or less.
- the increase in the warp value of the metal plate 20 after the device is activated can be suppressed within an allowable range.
- the warpage of the metal plate 20 is stable, so that the partial warpage can be suppressed and the amount of warpage of the semiconductor device fixed with a bolt to the cooler increases during operation.
- the distribution of the heat dissipation grease can be prevented from changing during the operation of the semiconductor device and the uniformity of heat dissipation can be prevented.
Abstract
Description
銅を材質とする金属板20に6個の絶縁回路基板21を図5に示されるように(平面的には図8(b)のように)配置した試験サンプルを作製し、次いで絶縁回路基板21に対応する第一領域13以外をレジストマスクで被覆して選択的にショットピーニング処理した後、3Dレーザー変位計で反り値を測定した。図2(a)に示される長手方向の反り量(曲面の中央と縁の標高差)は、全体的には500μmの正反り量となっており、絶縁回路基板21の影響による局所的な反りはほぼ解消されている。また、図2(b)に示される短手方向の反りは、全体的には200μmの正反り量となっており、絶縁回路基板21の影響による局所的な反りはない。なお、図3は、図2(a)の拡大図である。
実施例1と同じ手順で試験サンプルを作製し、ショットピーニング処理は実施せずに、そのまま3Dレーザー変位計で反り値を測定した。図9(a)に示される長手方向の反りは、全体的には200μm程度の正反り量となっており、絶縁回路基板21の影響によって局所的には50μm程度の負反り量となっている。また、図9(b)に示される短手方向の反りは、全体的には100μm程度の正反り量となっており、絶縁回路基板21の影響によって局所的には50μm程度の負反り量となっている。なお、図10は、図9(a)の拡大図である。
実施例1と同じ手順で試験サンプルを作製し、次いで金属板20の全面に亘ってショットピーニング処理した後、3Dレーザー変位計で反り値を測定した。図11(a)に示される長手方向の反りは、全体的には600μm程度の正反り量となっており、絶縁回路基板21の影響によって局所的には30μm程度の負反り量となっている。また、図11(b)に示される短手方向の反りは、全体的には200μmの正反り量となっており、絶縁回路基板21の影響による局所的な反りはない。なお、図12は、図11(a)の拡大図である。
図13は、各温度で一度のみ加熱処理後に室温(25℃)に戻した場合における金属板20の反り値の変化量を示す図である。加熱時間は1時間で行った。室温(25℃)における金属板20の反り値の最大値から最小値を引いた値と、各温度(125℃、150℃、175℃)における反り値の最大値から最小値を引いた値との差を反り値の変化量とした。半導体装置の最高動作温度である175℃の反り値の変化量を基準として、反り値の変化量の許容値を100μm以下とすると、60℃以上175℃以下の範囲で加熱処理を行えば、半導体装置が作動後の金属板20の反り値の増加を許容範囲内に抑制できる。
加熱冷却処理による反りの安定化を検証するために、比較例2で作製したサンプルに対して-40℃1時間保持と150℃1時間保持とを繰り返す熱サイクル試験を実施した。その結果を図14に示す。最初の1サイクルで全体的な正反りが増加するが、その後は殆ど変化していない。従って、少なくとも1サイクル以上加熱冷却サイクルを行うことで、金属板20の反り値の変化量を安定化できる。
2 放熱グリス
3 金属板
4 絶縁回路基板
4a,4b,4c,4d,4e,4f 金属板3の裏面にある、複数枚の絶縁回路基板4が配置された場所の裏面領域
5 はんだ
6 半導体チップ
7 絶縁基板
8 外部端子
9 端子ケース
10 封止樹脂
11 表面加工硬化層
12 マスク
13 第一領域
14 第二領域
20 金属板
21 絶縁回路基板
25 回路部
26 金属部
27 ショット材
28 超音波振動装置
30 半導体デバイス構造体
31 ボンディングワイヤ
100 半導体装置
Claims (13)
- 絶縁基板、前記絶縁基板のおもて面に半導体素子と接続された回路部、前記絶縁基板の裏面に金属部を備えた複数の絶縁回路基板と、
前記絶縁回路基板より大きく、かつ、前記複数の絶縁回路基板の前記金属部に接合される金属板と、
前記絶縁回路基板と前記金属板とを接合する接合部材と、
を備える半導体装置において、
前記金属板は、前記金属板のおもて面に前記絶縁回路基板が互いに離間して配置されており、かつ、前記金属板の裏面に前記金属部の配置に対応する第一領域と、前記第一領域を除く第二領域とを備え、
前記第一領域の少なくとも一部の表面には、表面加工硬化層を備え、
前記第二領域は、前記表面加工硬化層の硬度とは異なることを特徴とする半導体装置。 - 前記表面加工硬化層が、複数の前記第一領域に跨って延在された請求項1に記載の半導体装置。
- 前記表面加工硬化層が複数の前記第一領域に跨って延在された方向は、前記金属板の幅が短い方向とする請求項2に記載の半導体装置。
- 前記第一領域内の反り量は、50μm以下である請求項1~3のいずれか一項に記載の半導体装置。
- 前記第一領域内における前記表面加工硬化層の面積は、前記第一領域の面積の30%以上である請求項1~4のいずれか一項に記載の半導体装置。
- 前記絶縁基板の材質は、酸化アルミニウム、窒化アルミニウム又は窒化シリコンを主成分とする請求項1~5のいずれか一項に記載の半導体装置。
- 前記金属板は、前記半導体素子を冷却するための放熱板である請求項1~6のいずれか一項に記載の半導体装置。
- 絶縁基板、前記絶縁基板のおもて面に半導体素子と接続された回路部、前記絶縁基板の裏面に金属部を備えた複数の絶縁回路基板と、
前記絶縁回路基板より大きく、かつ、おもて面に前記絶縁回路基板が互いに離間して配置され、かつ、裏面に前記金属部の配置に対応する第一領域と、前記第一領域を除く第二領域とを備えた金属板と、
前記絶縁回路基板と前記金属板とを接合する接合部材と、
を備える半導体装置の製造方法において、
前記金属板の裏面の内、前記第一領域の少なくとも一部を除いてマスクを形成する工程と、
前記第一領域の前記マスクを形成されなかった領域にショットピーニング処理によって表面加工硬化層を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記表面加工硬化層を形成した後に、前記半導体装置を加熱処理する工程を含む請求項8に記載の半導体装置の製造方法。
- 前記加熱処理は、加熱温度が60℃以上175℃以下である請求項9に記載の半導体装置の製造方法。
- 前記加熱処理後に冷却処理を行い、前記加熱処理および前記冷却処理を交互に繰り返す請求項9又は10に記載の半導体装置の製造方法。
- 前記加熱処理および前記冷却処理のサイクル数は、1サイクル以上である請求項11に記載の半導体装置の製造方法。
- 前記加熱処理は150℃で行い、前記冷却処理は-40℃で行う請求項12に記載の半導体装置の製造方法。
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JP2006332084A (ja) * | 2005-05-23 | 2006-12-07 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法、および半導体装置 |
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WO2017169857A1 (ja) * | 2016-03-31 | 2017-10-05 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
CN107924889A (zh) * | 2016-03-31 | 2018-04-17 | 富士电机株式会社 | 半导体装置及半导体装置的制造方法 |
JPWO2017169857A1 (ja) * | 2016-03-31 | 2018-07-26 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
US10199305B2 (en) | 2016-03-31 | 2019-02-05 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
CN107924889B (zh) * | 2016-03-31 | 2021-02-12 | 富士电机株式会社 | 半导体装置及半导体装置的制造方法 |
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US10276474B2 (en) | 2019-04-30 |
CN105612614A (zh) | 2016-05-25 |
US20160225688A1 (en) | 2016-08-04 |
DE112015000153T5 (de) | 2016-06-02 |
JPWO2015141384A1 (ja) | 2017-04-06 |
JP6090529B2 (ja) | 2017-03-08 |
DE112015000153B4 (de) | 2021-04-29 |
CN105612614B (zh) | 2018-12-28 |
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