WO2015133047A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2015133047A1
WO2015133047A1 PCT/JP2015/000081 JP2015000081W WO2015133047A1 WO 2015133047 A1 WO2015133047 A1 WO 2015133047A1 JP 2015000081 W JP2015000081 W JP 2015000081W WO 2015133047 A1 WO2015133047 A1 WO 2015133047A1
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WO
WIPO (PCT)
Prior art keywords
step portion
electrode
insulation film
gate wiring
region
Prior art date
Application number
PCT/JP2015/000081
Other languages
French (fr)
Inventor
Yoshifumi Yasuda
Original Assignee
Toyota Jidosha Kabushiki Kaisha
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Publication date
Application filed by Toyota Jidosha Kabushiki Kaisha filed Critical Toyota Jidosha Kabushiki Kaisha
Publication of WO2015133047A1 publication Critical patent/WO2015133047A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]

Definitions

  • the teachings disclosed herein relate to a semiconductor device.
  • a semiconductor device having a semiconductor substrate, an electrode formed on the semiconductor substrate, and wiring connected to the electrode is disclosed in Japanese Patent Application Publication No.S63-104448.
  • a barrier-metal is formed between the electrode and the wiring. Unnecessary barrier-metals are removed by etching or the like. Even though such unnecessary barrier-metals are removed, a part of them may be unremoved and remained as a residual substance. Such a metallic residual substance may cause an electric short-circuit.
  • the object of the teachings disclosed herein is to provide a semiconductor device capable of suppressing the generation of short-circuits caused by metallic residual substances.
  • the semiconductor device disclosed herein comprises: a semiconductor substrate in which a first switching element is formed; a gate electrode of the first switching element formed on the semiconductor substrate; an insulation film covering the gate electrode and the semiconductor substrate; and a first conductive member formed on the insulation film.
  • the semiconductor device further comprises a gate wiring formed on the insulation film, separated from the first conductive member, and being in contact with the gate electrode.
  • An upper surface of the insulation film comprises a first portion, a second portion, and a step portion. The first portion is located on the gate electrode, the second portion is located on the substrate, and the step portion is located between the first and second portions.
  • the first conductive member covers the step portion, and the gate wiring does not cover the step portion.
  • the above metallic residual substance is likely to remain in the step portion of the insulation film.
  • the first conductive member contacts the residual substance while the gate wiring does not.
  • a short circuit between the first conductive member and the gate wiring through the residual substance remaining in the step portion can be inhibited.
  • FIG.1 is a plan view of a semiconductor device having an emitter electrode and gate wiring formed thereon (upper surface of the semiconductor substrate is seen from vertical direction).
  • FIG.2 is a cross-sectional view taken from line II-II of FIG.1.
  • FIG.3 is a cross-sectional view taken from line III-III of FIG.1.
  • FIG.4 is a cross-sectional view taken from line IV-IV of FIG.1.
  • FIG.5 is an enlarged view of an primary part V of FIG.1.
  • FIG.6 is a plan view of the semiconductor device having an emitter electrode, gate wiring, and sense electrode formed thereon (upper surface of the semiconductor substrate is seen from vertical direction).
  • FIG.7 is a cross-sectional view taken from line VII-VII of FIG.6.
  • FIG.8 is a cross-sectional view taken from line VIII-VIII of FIG.6.
  • FIG.9 is an enlarged view of an primary part IX of FIG.6.
  • FIG.10 is a view corresponding to FIG.9
  • a gate wiring may be formed on a first portion of an upper surface of an insulation film that is located on a gate electrode.
  • a first conductive member may be a negative electrode of a first switching element.
  • a second switching element may be further formed in the semiconductor substrate, and the first conductive member may be a negative electrode of the second switching element.
  • the negative electrode may comprise a first region, a second region formed with an interval from the first region, and a connecting region connecting the first region and the second region.
  • the connecting region may cover a step portion of the upper surface of the insulation film.
  • a semiconductor device 1 includes an emitter electrode 30 (one example of a first conductive member), and gate wiring 40. As shown in FIGS.2 to FIG.4 (cross sectional views of FIG.1), the semiconductor device 1 includes: a semiconductor substrate 10, gate electrode 20, and insulation film 50.
  • the semiconductor substrate 10 includes an IGBT formed therein.
  • the emitter electrode 30 is an emitter electrode of the IGBT.
  • the emitter electrode 30 is exposed on the upper surface of the semiconductor device 1.
  • the emitter electrode 30 is a negative electrode.
  • the emitter electrode 30 includes: a first region 31; a second region 32; a third region 33; and a connecting region 34.
  • the first region 31 and the second region 32 are neighboring each other.
  • the first region 31 and the second region 32 have a clearance therebetween.
  • the third region 33 is formed around the periphery of the first region 31 and the second region 32, and enclosing these regions.
  • the connecting region 34 allows the first region 31, second region 32, and third region 33 to connect each other.
  • the gate wiring 40 is connected to the gate electrode 20 of the IGBT described above.
  • the gate wiring 40 is exposed on the upper surface of the semiconductor device 1.
  • the gate wiring 40 includes: a first region 41; second region 42; and third region 43.
  • the first region 41 of the gate wiring 40 is formed around the periphery of the first region 31 of the emitter electrode 30 and enclosing the first region 31.
  • the first region 41 of the gate wiring 40 is formed between the first region 31 and the third region 33 of the emitter electrode 30.
  • the second region 42 of the gate wiring 40 is formed around the periphery of the second region 32 of the emitter electrode 30 and enclosing the second region 32 of the emitter electrode 30.
  • the second region 42 of the gate wiring 40 is formed between the second region 32 and the third region 33 of the emitter electrode 30.
  • the third region 43 of the gate wiring 40 is formed between the first region 31 and the second region 32 of the emitter electrode 30.
  • the first region 41, second region 42, and third region 43 of the gate wiring 40 are connected to a gate pad 44.
  • the gate pad 44 is electrically connected to an external circuit.
  • the emitter electrode 30 and the gate wiring 40 are separated apart from each other.
  • the emitter electrode 30 and the gate wiring 40 are insulated each other.
  • a potential different from that for the emitter electrode 30 is applied on the gate wiring 40.
  • the semiconductor device 1 includes: a semiconductor substrate 10; an insulation film 70 formed on the semiconductor substrate 10; and a gate electrode formed on the insulation film 70.
  • the semiconductor device 1 also includes: an insulation film 50 formed on the gate electrode 20 and the semiconductor substrate 10; and an emitter electrode 30 formed on the insulation film 50 and the semiconductor substrate 10.
  • the semiconductor device 1 includes a barrier-metal 80 formed on the gate electrode 20.
  • the gate wiring 40 is formed on the barrier-metal 80.
  • silicon Si
  • silicon carbide SiC
  • IGBT Insulated Gate Bipolar Transistor
  • the IGBT is formed by having the inside of the semiconductor substrate 10 be doped with impurities. That is, inside of the semiconductor substrate 10 includes: an n type emitter region; p type body region; n-type drift region; and p type collector region (not shown), and so on, and these regions form the IGBT.
  • the semiconductor substrate 10 includes: an IGBT as a main element (an example of the first switching elements) having a large area and allowing a large current to flow therein; and an IGBT as a sense element (an example of the second switching elements) having a small area and allowing a small current to flow therein.
  • the emitter electrode 30 is contacting the emitter region of the IGBT of the main element (an example of the first switching elements).
  • the insulation film 70 is partially formed on the upper surface of the semiconductor substrate 10.
  • a material for the insulation film 70 for example, silicon dioxide (SiO 2 ) can be used.
  • the insulation film 70 insulates the semiconductor substrate 10 and the gate electrode 20.
  • the gate electrode 20 is formed on the upper surface of the insulation film 70.
  • the gate electrode 20 is formed on the semiconductor substrate 10 through the insulation film 70.
  • the gate electrode 20 has the thickness "t20".
  • the insulation film 50 is formed on the upper surface of the gate electrode 20.
  • the insulation film 50 covers whole of the gate electrode 20.
  • the insulation film 50 is also formed on the upper surface of the semiconductor substrate 10.
  • the insulation film 50 covers the gate electrode 20 and the semiconductor substrate 10 from the above.
  • the insulation film 50 covers edges 21 on both sides of the gate electrode 20.
  • silicon dioxide (SiO 2 ) can be used as a material for the insulation film 50.
  • the upper surface of the insulation film 50 includes: a high-order section 52; a low-order section 53; and a first step portion 54.
  • the high-order section 52 is placed upper than the low-order section 53.
  • the high-order section 52, low-order section 53, and first step portion 54 are formed according to the thickness "t20" of the gate electrode 20. That is, the high-order section 52 is placed on the gate electrode 20, and the low-order section 53 is placed on the semiconductor substrate 10 (namely, an area on the semiconductor substrate 10 where the gate electrode 20 is not existing).
  • the first step portion 54 is formed on the boundary between the high-order section 52 and the low-order section 53.
  • a bent portion 55 is formed on a part of the first step portion 54.
  • the bent portion 55 concavely curved is formed on the upper surface of the insulation film 50 in the boundary portion between the side surface of the first step portion 54 and the low-order portion 53.
  • the step portions on the insulation film 50 are formed on both (right and left) sides of the gate electrode 20 in FIGS.2 to 4, however, in this embodiment, the step portion of the left side (first step portion 54) in the figures is explained.
  • FIG.5 is an enlarged view that illustrates the primary part V of FIG.1.
  • the dotted line and the dashed-dotted line represent the first step portion 54.
  • the first step portion 54 is represented by the dotted line in the area where the emitter electrode 30 covers the first step portion 54.
  • the first step portion 54 is represented by the dashed-dotted line in the area where the emitter electrode 30 does not cover the first step portion 54.
  • the first step portion 54 is essentially invisible in planar view in the area where the emitter electrode 30 and the first step portion 54 are overlapping, the first step portion 54 is represented by the dotted line as a matter of convenience.
  • the emitter electrode 30 is formed at a place where it overlaps with the first step portion 54.
  • An opening 51 is formed on the insulation film 50.
  • the opening 51 is formed in the high-order section 52 of the insulation film 50.
  • the opening 51 penetrates the insulation film 50.
  • the opening 51 is not formed on the insulation film 50.
  • a barrier-metal 80 is formed on the opening 51.
  • the barrier-metal 80 covers the inner surface of the opening 51 and the upper surface of the gate electrode 20.
  • the barrier-metal 80 covers a part of the upper surface of the insulation film 50.
  • the barrier-metal 80 is formed over the whole of the insulation film 50. Then, unnecessary portions are removed by selectively etching the barrier-metal 80. In such a manner, the barrier-metal 80 is formed on the opening 51.
  • a barrier-metal residual substance 81 may be accumulated in the bent portion 55 of the step portion 54 of the insulation film 50.
  • the barrier metal may be partially left untouched and remained in the bent portion 55 .
  • the residual substance 81 is a barrier-metal deposit, thus, having a conductivity.
  • the opening 51 of the insulation film 50 is filled with gate wiring 40.
  • the gate wiring 40 is formed on the barrier-metal 80.
  • the gate wiring 40 contacts the gate electrode 20 through the barrier-metal 80.
  • the gate wiring 40 is electrically connected to the gate electrode 20.
  • the gate wiring 40 is formed on the upper part of the gate electrode 20. Therefore, the gate wiring 40 is formed on the high-order section 52 of the insulation film 50 but formed on neither the low-order section 53 nor the first step portion 54. In cross-sectional view as in FIG.3, the opening 51, barrier-metal 80, and gate wiring 40 are not formed.
  • the emitter electrode 30 covers the upper surface of the semiconductor substrate 10.
  • the emitter electrode 30 covers the low-order section 53, first step portion 54, and a part of the high-order section 52 of the insulation film 50.
  • the emitter electrode 30 is formed away from the gate wiring 40.
  • the emitter electrode 30 covers the low-order section 53, first step portion 54, and high-order section 52 of the insulation film 50.
  • the emitter electrode 30 does not cover the first step portion 54 of the insulation film 50.
  • the barrier-metal residual substance 81 is present in the bent portion 55.
  • the emitter electrode 30 covers the barrier-metal residual substance 81.
  • the first step portion 54 is extending in y-direction in the vicinity of the third region 43 while it is extending in x-direction in the vicinity of the first region 41.
  • the first step portion 54 is not covered by the emitter electrode 30 and is exposing to the surface. That is, the first step portion 54 is not covered by any conductive member other than the emitter electrode 30.
  • the connecting region 34 of the emitter electrode 30 covers the bent portion 55 of the first step portion 54.
  • the gate wiring 40 is formed so as not to overlap with the first step portion 54 at any place. That is, the gate wiring 40 does not cover the first step portion 54. Therefore, the gate wiring 40 does not contact the barrier-metal residual substance 81 which is accumulating in the first step portion 54.
  • the first step portion 54 is covered by the emitter electrode 30, the first step portion 54 is not covered by the gate wiring 40. In addition, as for the first step portion 54, the first step portion 54 is not covered by any conductive member other than the emitter electrode 30. Moreover, outside the range of FIG.5, the first step portion 54 is also not covered any conductive member other than the emitter electrode 30.
  • the first step portion 54 is covered by the emitter electrode 30 but not by the gate wiring 40.
  • the conductive barrier-metal residual substance 81 is accumulating in the first step portion 54, the residual substance 81 is contacted by the emitter electrode 30 but not by the gate wiring 40.
  • the emitter electrode 30 and the gate wiring 40 will never be electrically connected via the residual substance 81 remaining in the first step portion 54. Therefore, the occurrence of short-circuit between the emitter electrode 30 and the gate wiring 40 owing to the conductive residual substance 81 remaining on the insulation film 50 can be suppressed.
  • the first step portion 54 is not covered by any conductive member other than the emitter electrode 30, the occurrence of short-circuit between the emitter electrode 30 and a conductive member other than the gate wiring can also be suppressed.
  • the emitter electrodes 30 includes the first region 31, the second region 32 separated from the first region 31, and the connecting region 34 for connecting the first region 31 and the second region 32.
  • the first step portion 54 formed on the upper surface of the insulation film 50 is likely to overlap with the emitter electrode 30. Therefore, the above configuration is especially effective in suppressing the occurrence of short-circuit between the emitter electrode 30 and the gate wiring 40 through the residual substance 81 accumulating in the first step portion 54.
  • the semiconductor device 1 of the second embodiment further includes a plurality of sense electrodes 60 (one example of first conductive members). In planar view, the sense electrodes 60 are aligned with clearances in between them. The sense electrodes 60 are connected to the emitter region of the IGBT as sense elements (one example of second switching elements).
  • the sense electrodes 60 are formed between the first region 31 of the emitter electrode 30 and the first region 41 of the gate wiring 40, and between the second region 32 of the emitter electrode 30 and the second region 42 of the gate wiring 40.
  • the sense electrodes 60 are used for detecting electric current and temperature.
  • the emitter electrode 30, gate wiring 40, and sense electrodes 60 are separated apart from each other.
  • the insulation film 50 is formed between the emitter electrode 30, gate wiring 40, and sense electrodes 60.
  • the emitter electrode 30, gate wiring 40, and sense electrodes 60 are insulated from each other.
  • the emitter electrode 30, gate wiring 40, and sense electrodes 60 have conductivity. Different potentials are respectively applied to the emitter electrode 30, gate wiring 40, and sense electrodes 60.
  • the semiconductor device 1 includes: a semiconductor substrate 10; an insulation film 70 formed on the semiconductor substrate 10; and a gate electrode 20 formed on the insulation film 70.
  • the semiconductor device 1 also includes: an insulation film 50 formed on the gate electrode 20 and the semiconductor substrate 10; and an emitter electrode 30 formed on the insulation film 50 and the semiconductor substrate 10.
  • the semiconductor device 1 further includes: a barrier-metal 80 formed on the gate electrode 20; and gate wiring 40 formed on the barrier-metal 80.
  • the semiconductor device 1 still further includes a sense electrode 60 formed on the insulation film 50.
  • gate electrodes 20 are shown in FIG.8, these are just separated apart from each other in the cross-sectional view as shown in FIG.8, they are connected at portions that are not depicted in the figure, thus having the same configuration.
  • the gate electrodes 20 shown in FIG.8 is referred to as: the left side gate electrode 20a for that on the left side; and the right side gate electrode 20b for that on the right side.
  • the upper surface of the insulation film 50 includes: a high-order section 52; a low-order section 53; and a second step portion 54.
  • the high-order section 52, low-order section 53, and second step portion 254 are formed according to the thickness "t20" of the gate electrode 20.
  • the second step portion 254 is formed according to the height positional difference between the high-order section 52 and the low-order section 53.
  • the step portions on the insulation film 50 are formed on both (right and left) sides of the gate electrode 20 in FIG.7, however, in this embodiment, the step portion of the right side (second step portion 254) in the figure is explained.
  • the high-order section 52 is formed on the gate electrode 20.
  • the low-order section 53 and the second step portion 254 are formed on the flank of an edge 21 of the gate electrode 20.
  • the low-order section 53 is formed on the semiconductor substrate 10.
  • the second step portion 254 is formed between the high-order section 52 and the low-order section 53.
  • the height of the high-order section 52 is higher than that of the low-order section 53.
  • a bent portion 55 is formed on a part of the second step portion 254.
  • the upper surface of the insulation film 50 for covering the left side gate electrode 20a includes: a high-order section 52; a low-order section 53; and a third step portion 354.
  • the high-order section 52, low-order section 53, and third step portion 354 are formed according to the thickness "t20" of the gate electrode 20.
  • the third step portion 354 is formed according to the height positional difference between the high-order section 52 and the low-order section 53.
  • the step portions on the insulation film 50 are formed on both (right and left) sides of the left side gate electrode 20a in FIG.8, however, in this embodiment, the step portion of the left side (third step portion 354) in the figure is explained.
  • the high-order section 52 is formed on the left side gate electrode 20a.
  • the low-order section 53 and the third step portion 354 are formed on the flank of the edge 21 of the left side gate electrode 20a.
  • the third step portion 354 is formed between the high-order section 52 and the low-order section 53.
  • the bent portion 55 is formed on a part of the third step portion 354.
  • the upper surface of the insulation film 50 for covering the right side gate electrode 20b includes: the high-order section 52; low-order section 53; and fourth step portion 454.
  • the high-order section 52, low-order section 53, and fourth step portion 454 are formed according to the thickness "t20" of the gate electrode 20.
  • the fourth step portion 454 is formed according to the height positional difference between the high-order section 52 and the low-order section 53.
  • the step portions on the insulation film 50 are formed on both (right and left) sides of the right side gate electrode 20b in FIG.4, however, in this embodiment, the step portion of the left side (fourth step portion 454) in the figure is explained.
  • the high-order section 52 is formed on the right side gate electrode 20b.
  • the low-order section 53 and the fourth step portion 454 are formed on the flank of the edge 21 of the right side gate electrode 20b.
  • the fourth step portion 454 is formed between the high-order section 52 and the low-order section 53.
  • the bent portion 55 is formed on a part of the fourth step portion 454.
  • a barrier-metal 80 is formed on the opening 51 of the insulation film 50.
  • a barrier-metal residual substance 81 may be accumulated in the second step portion 254, third step portion 354, and fourth step portion 454 of the insulation film 50. That is, even after carrying out an etching for the barrier-metal 80 formed over the whole of the upper surface of the insulation film 50, the barrier metal may be partially left untouched and remained on the surface of the second step portion 254, third step portion 354, and fourth step portion 454. Thereby, the residual substance 81 is accumulated in the second step portion 254, third step portion 354, and fourth step portion 454.
  • the residual substance 81 is a barrier-metal deposit, thus, having a conductivity.
  • an emitter electrode 30 is formed on the upper surface of the insulation film 50.
  • the emitter electrode 30 is formed away from the gate wiring 40. Different potential is applied on the emitter electrode 30 and the gate wiring 40.
  • the emitter electrode 30 covers the high-order section 52, low-order section 53, and the second step portion 254 of the insulation film 50.
  • the emitter electrode 30 is formed on the second step portion 254, and contacts the barrier-metal residual substance 81 accumulated in the second step portion 254.
  • the opening 51 of the insulation film 50 on the left side gate electrode 20a is filled with gate wiring 40.
  • the gate wiring 40 is formed on the barrier-metal 80.
  • the gate wiring 40 contacts the gate electrode 20 through the barrier-metal 80.
  • the gate wiring 40 is electrically connected to the gate electrode 20.
  • the gate wiring 40 is formed on the high-order section 52, low-order section 53, and third step portion 354 of the insulation film 50.
  • the gate wiring 40 is formed on neither the second step portion 254 (not shown in FIG.8) nor the fourth step portion 454 of the insulation film 50.
  • the low-order section 53 and the fourth step portion 454 are placed on the frank of the gate wiring 40.
  • the gate wiring 40 is formed on the third step portion 354, and contacts the barrier-metal residual substance 81 accumulated in the third step portion 354.
  • the sense electrode 60 is formed on the upper surface of the insulation film 50 on the right side gate electrode 20b.
  • the opening 51 is not formed on the insulation film 50 on the right side gate electrode 20b.
  • the insulation film 50 covers whole of the right side gate electrode 20b.
  • the sense electrode 60 is formed on the high-order section 52, low-order section 53, and fourth step portion 454 of the insulation film 50.
  • the sense electrode 60 is formed on neither the second step portion 254 (not shown in FIG.8) nor the third step portion 354 of the insulation film 50.
  • the sense electrode 60 is formed on the fourth step portion 454, and contacts the barrier-metal residual substance 81 accumulated in the fourth step portion 454.
  • the forming positions of the second step portion 254, third step portion 354, and fourth step portion 454 are different from that of the first step portion 54 in planar view, however, the configuration of these portions is the same as that of the first step portion 54 in cross-sectional view. That is, the second step portion 254, third step portion 354, and fourth step portion 454 are formed according to the thickness "t20" of the gate electrode 20. The second step portion 254, third step portion 354, and fourth step portion 454 are formed according to the height positional difference between the high-order section 52 and the low-order section 53. The second step portion 254, third step portion 354, and fourth step portion 454 are formed at a curved portion on the upper surface of the insulation film 50.
  • the second step portion 254, third step portion 354, and fourth step portion 454 are formed on the flank of the edge 21 of the gate electrode 20.
  • the second step portion 254, third step portion 354, and fourth step portion 454 are formed between the high-order section 52 and the low-order section 53.
  • the second step portion 254 is covered by the emitter electrode 30.
  • the third step portion 354 is covered by the gate wiring 40.
  • the fourth step portion 454 is covered by the sense electrode 60.
  • FIG.9 is an enlarged view that illustrates the primary part IX of FIG.6.
  • the emitter electrode 30 is formed at a place where it overlaps with the second step portion 254.
  • the second step portion 254 is represented by the dotted line in the area where the emitter electrode 30 covers the second step portion 254.
  • the second step portion 254 is represented by the dashed-dotted line in the area where the emitter electrode 30 does not cover the second step portion 254.
  • the second step portion 254 is essentially invisible in planar view in the area where the emitter electrode 30 and the second step portion 254 are overlapping, the second step portion 254 is represented by the dotted line as a matter of convenience.
  • the emitter electrode 30 contacts the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the second step portion 254.
  • the second step portion 254 is extending in nearly parallel with the upper surface of the semiconductor substrate 10. In planar view as shown in FIG.9, the second step portion 254 is extending along the edge of the emitter electrode 30. The second step portion 254 is extending in the x direction and y direction of FIG.9. The second step portion 254 is extending in a position that overlaps with the emitter electrode 30. On the other hand, the second step portion 254 is extending in a position that does not overlap with the gate wiring 40 and the sense electrode 60. The second step portion 254 is extending outside the edge of the gate wiring 40. In addition, the second step portion 254 is extending outside the edge of the sense electrode 60. The area of the second step portion 254 not overlapping with the emitter electrode 30 (the area represented by the dashed-dotted line in FIG.9) is exposed to the outside.
  • the gate wiring 40 is formed at a place where it does not overlap with the second step portion 254.
  • the gate wiring 40 does not cover the second step portion 254. Therefore, the gate wiring 40 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the second step portion 254.
  • the sense electrode 60 is formed at a place where it does not overlap with the second step portion 254.
  • the sense electrode 60 does not cover the second step portion 254. Therefore, the sense electrode 60 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the second step portion 254.
  • the gate wiring 40 is formed at a place where it overlaps with the third step portion 354.
  • the third step portion 354 is represented by the dotted line in the area where the gate wiring 40 covers the third step portion 354.
  • the third step portion 354 is represented by the dotted line as a matter of convenience.
  • the gate wiring 40 contacts the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the third step portion 354.
  • the third step portion 354 is extending in nearly parallel with the upper surface of the semiconductor substrate 10. In planar view as shown in FIG.9, the third step portion 354 is extending along the edge of the gate wiring 40. The third step portion 354 is extending in the x direction of FIG.9. The third step portion 354 is extending as far as it overlaps with the gate wiring 40. On the other hand, the third step portion 354 is not extending as far as it overlaps with the emitter electrode 30 and the sense electrode 60. The third step portion 354 is extending outside the edge of the emitter electrode 30. In addition, the third step portion 354 is extending outside the edge of the sense electrode 60. The area of the third step portion 354 not overlapping with the gate wiring 40 (not shown) is exposed to the outside.
  • the emitter electrode 30 is formed at a place where it does not overlap with the third step portion 354.
  • the emitter electrode 30 does not cover the third step portion 354. Therefore, the emitter electrode 30 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the third step portion 354.
  • the sense electrode 60 is formed at a place where it does not overlap with the third step portion 354. The sense electrode 60 does not cover the third step portion 354. Therefore, the sense electrode 60 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the third step portion 354.
  • the sense electrode 60 is formed at a place where it overlaps with the fourth step portion 454.
  • the fourth step portion 454 is represented by the dotted line in the area where the sense electrode 60 covers the fourth step portion 454.
  • the fourth step portion 454 is represented by the dashed-dotted line in the area where the sense electrode 60 does not cover the fourth step portion 454.
  • the fourth step portion 454 is essentially invisible in planar view in the area where the sense electrode 60 and the fourth step portion 454 are overlapping, the fourth step portion 454 is represented by the dotted line as a matter of convenience.
  • the sense electrode 60 contacts the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the fourth step portion 454.
  • the fourth step portion 454 is extending in nearly parallel with the upper surface of the semiconductor substrate 10. In planar view as shown in FIG.9, the fourth step portion 454 is extending along the edge of the sense electrode 60. The fourth step portion 454 is extending in the x direction and y direction of FIG.9. The fourth step portion 454 is extending as far as it overlaps with the sense electrode 60. On the other hand, the fourth step portion 454 is not extending as far as it overlaps with the gate wiring 40 and the emitter electrode 30. The fourth step portion 454 is extending outside the edge of the gate wiring 40. The fourth step portion 454 is extending outside the edge of the emitter electrode 30. The area of the fourth step portion 454 not overlapping with the sense electrode 60 (the area represented by the dashed-dotted line in FIG.9) is exposed to the outside.
  • the gate wiring 40 is formed at a place where it does not overlap with the fourth step portion 454.
  • the gate wiring 40 does not cover the fourth step portion 454. Therefore, the gate wiring 40 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the fourth step portion 454.
  • the emitter electrode 30 is formed at a place where it does not overlap with the fourth step portion 454.
  • the emitter electrode 30 does not cover the fourth step portion 454. Therefore, the emitter electrode 30 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the fourth step portion 454.
  • the semiconductor device 1 having above configuration includes: the second step portion 254; third step portion 354; and fourth step portion 454, these formed on the upper surface of the insulation film 50 that covers the gate electrode 20 according to the thickness "t20" of the gate electrode 20.
  • the emitter electrode 30 covers the second step portion 254, however, the gate wiring 40 and the sense electrode 60 having different potential from that of the emitter electrode 30 do not cover the second step portion 254.
  • the emitter electrode 30 contacts the residual substance 81, but the gate wiring 40 and sense electrode 60 do not contact the residual substance 81.
  • the emitter electrode 30, the gate wiring 40, and sense electrode 60 will never be electrically connected via residual substance 81 remaining in the second step portion 254. Therefore, the occurrence of short-circuit between the emitter electrode 30, gate wiring 40, and sense electrode 60 owing to the conductive residual substance 81 remaining in the insulation film 50 can be suppressed.
  • the gate wiring 40 covers the third step portion 354, however, the emitter electrode 30 and the sense electrode 60 having different potential from that of the gate wiring 40 do not cover the third step portion 354.
  • the gate wiring 40, emitter electrode 30, and sense electrode 60 will never be electrically connected via conductive residual substance 81 remaining in the third step portion 354. Therefore, the occurrence of short-circuit between the gate wiring 40, emitter electrode 30, and sense electrode 60 owing to the conductive residual substance 81 remaining on the insulation film 50 can be suppressed.
  • the sense electrode 60 covers the fourth step portion 454, however, the gate wiring 40 and the emitter electrode 30 having different potential from that of the sense electrode 60 do not cover the fourth step portion 454.
  • the sense electrode 60, emitter electrode 30, and gate wiring 40 will never be electrically connected via conductive residual substance 81 remaining in the fourth step portion 454. Therefore, the occurrence of short-circuit between the sense electrode 60, emitter electrode 30, and gate wiring 40 owing to the conductive residual substance 81 remaining in the insulation film 50 can be suppressed.
  • an IGBT was described as a switching element in the embodiment, however, the present invention is not limited to this configuration.
  • a FET may be described as a switching element in other embodiment.
  • a source electrode may be described as a first conductive member. The source electrode is a negative electrode.
  • the locating position and configuration for the emitter electrode 30, gate wiring 40, and sense electrode 60 are not specially limited and may be modified as necessary.
  • the step portion having a conductive barrier-metal residual substance 81 accumulated therein is covered by the first conductive member, but not covered by the other conductive member having different potential from that of the first conductive member. Thereby, the occurrence of short-circuit between the first conductive member and the conductive member other than the first conductive member through the conductive barrier-metal residual substance 81 can be suppressed.
  • the configuration of the fourth step portion 454 is not limited to above embodiments.
  • a plurality of fourth step portions 454 is formed in planar view.
  • the plurality of fourth step portions 454 are formed with a clearance.
  • Each of the fourth step portions 454 is formed at a place where it overlaps with the sense electrode 60.
  • Each of the fourth step portions 454 is covered by the sense electrode 60.
  • the conductive member other than the sense electrode 60 does not cover the fourth step portion 454.

Abstract

The semiconductor device 1 includes a semiconductor substrate 10 in which a IGBT is formed; a gate electrode 20 of the IGBT; an insulation film 50 covering the gate electrode 20 and the semiconductor substrate 10; and an emitter electrode 30 formed on the insulation film 50. A gate wiring 40 is formed on the insulation film 50, separated from the emitter electrode 30, and in contact with the gate electrode 20. An upper surface of the insulation film 50 includes a first portion, a second portion, and a step portion 54, the first portion being located on the gate electrode 20, the second portion being located on the substrate 10, and the step portion 54 being located between the first and second portions. The emitter electrode 30 covers the step portion 54, and the gate wiring 40 does not cover the step portion 54.

Description

SEMICONDUCTOR DEVICE
The teachings disclosed herein relate to a semiconductor device.
A semiconductor device having a semiconductor substrate, an electrode formed on the semiconductor substrate, and wiring connected to the electrode is disclosed in Japanese Patent Application Publication No.S63-104448.
In the above semiconductor device, in order to connect an electrode and wiring formed on a semiconductor substrate, a barrier-metal is formed between the electrode and the wiring. Unnecessary barrier-metals are removed by etching or the like. Even though such unnecessary barrier-metals are removed, a part of them may be unremoved and remained as a residual substance. Such a metallic residual substance may cause an electric short-circuit. The object of the teachings disclosed herein is to provide a semiconductor device capable of suppressing the generation of short-circuits caused by metallic residual substances.
The semiconductor device disclosed herein comprises: a semiconductor substrate in which a first switching element is formed; a gate electrode of the first switching element formed on the semiconductor substrate; an insulation film covering the gate electrode and the semiconductor substrate; and a first conductive member formed on the insulation film. The semiconductor device further comprises a gate wiring formed on the insulation film, separated from the first conductive member, and being in contact with the gate electrode. An upper surface of the insulation film comprises a first portion, a second portion, and a step portion. The first portion is located on the gate electrode, the second portion is located on the substrate, and the step portion is located between the first and second portions. The first conductive member covers the step portion, and the gate wiring does not cover the step portion.
The above metallic residual substance is likely to remain in the step portion of the insulation film. In such a configuration, when a metallic residual substance is accumulating in the step portion, the first conductive member contacts the residual substance while the gate wiring does not. As a result, a short circuit between the first conductive member and the gate wiring through the residual substance remaining in the step portion can be inhibited.
FIG.1 is a plan view of a semiconductor device having an emitter electrode and gate wiring formed thereon (upper surface of the semiconductor substrate is seen from vertical direction). FIG.2 is a cross-sectional view taken from line II-II of FIG.1. FIG.3 is a cross-sectional view taken from line III-III of FIG.1. FIG.4 is a cross-sectional view taken from line IV-IV of FIG.1. FIG.5 is an enlarged view of an primary part V of FIG.1. FIG.6 is a plan view of the semiconductor device having an emitter electrode, gate wiring, and sense electrode formed thereon (upper surface of the semiconductor substrate is seen from vertical direction). FIG.7 is a cross-sectional view taken from line VII-VII of FIG.6. FIG.8 is a cross-sectional view taken from line VIII-VIII of FIG.6. FIG.9 is an enlarged view of an primary part IX of FIG.6. FIG.10 is a view corresponding to FIG.9 of one embodiment.
Preferred aspects of below embodiments will be listed.
(Feature 1) In the semiconductor device, a gate wiring may be formed on a first portion of an upper surface of an insulation film that is located on a gate electrode.
(Feature 2) A first conductive member may be a negative electrode of a first switching element.
(Feature 3) A second switching element may be further formed in the semiconductor substrate, and the first conductive member may be a negative electrode of the second switching element.
(Feature 4) The negative electrode may comprise a first region, a second region formed with an interval from the first region, and a connecting region connecting the first region and the second region. The connecting region may cover a step portion of the upper surface of the insulation film.
(First Embodiment)
Embodiments are explained below with reference to the attached drawings. As shown in FIG.1, one embodiment of a semiconductor device 1 includes an emitter electrode 30 (one example of a first conductive member), and gate wiring 40. As shown in FIGS.2 to FIG.4 (cross sectional views of FIG.1), the semiconductor device 1 includes: a semiconductor substrate 10, gate electrode 20, and insulation film 50.
Not illustrated though, the semiconductor substrate 10 includes an IGBT formed therein. The emitter electrode 30 is an emitter electrode of the IGBT. The emitter electrode 30 is exposed on the upper surface of the semiconductor device 1. The emitter electrode 30 is a negative electrode. In planar view as shown in FIG.1, the emitter electrode 30 includes: a first region 31; a second region 32; a third region 33; and a connecting region 34. The first region 31 and the second region 32 are neighboring each other. The first region 31 and the second region 32 have a clearance therebetween. The third region 33 is formed around the periphery of the first region 31 and the second region 32, and enclosing these regions. The connecting region 34 allows the first region 31, second region 32, and third region 33 to connect each other.
The gate wiring 40 is connected to the gate electrode 20 of the IGBT described above. The gate wiring 40 is exposed on the upper surface of the semiconductor device 1. In planar view, the gate wiring 40 includes: a first region 41; second region 42; and third region 43. The first region 41 of the gate wiring 40 is formed around the periphery of the first region 31 of the emitter electrode 30 and enclosing the first region 31. The first region 41 of the gate wiring 40 is formed between the first region 31 and the third region 33 of the emitter electrode 30. The second region 42 of the gate wiring 40 is formed around the periphery of the second region 32 of the emitter electrode 30 and enclosing the second region 32 of the emitter electrode 30. The second region 42 of the gate wiring 40 is formed between the second region 32 and the third region 33 of the emitter electrode 30. The third region 43 of the gate wiring 40 is formed between the first region 31 and the second region 32 of the emitter electrode 30. The first region 41, second region 42, and third region 43 of the gate wiring 40 are connected to a gate pad 44. The gate pad 44 is electrically connected to an external circuit.
In planar view, the emitter electrode 30 and the gate wiring 40 are separated apart from each other. The emitter electrode 30 and the gate wiring 40 are insulated each other. A potential different from that for the emitter electrode 30 is applied on the gate wiring 40.
In cross-sectional view as in FIGS. 2 to 4, the semiconductor device 1 includes: a semiconductor substrate 10; an insulation film 70 formed on the semiconductor substrate 10; and a gate electrode formed on the insulation film 70. The semiconductor device 1 also includes: an insulation film 50 formed on the gate electrode 20 and the semiconductor substrate 10; and an emitter electrode 30 formed on the insulation film 50 and the semiconductor substrate 10. Furthermore, the semiconductor device 1 includes a barrier-metal 80 formed on the gate electrode 20. The gate wiring 40 is formed on the barrier-metal 80.
For example, silicon (Si), silicon carbide (SiC), or the like can be used as a material for the semiconductor substrate 10. The IGBT (Insulated Gate Bipolar Transistor) is formed by having the inside of the semiconductor substrate 10 be doped with impurities. That is, inside of the semiconductor substrate 10 includes: an n type emitter region; p type body region; n-type drift region; and p type collector region (not shown), and so on, and these regions form the IGBT. More specifically, the semiconductor substrate 10 includes: an IGBT as a main element (an example of the first switching elements) having a large area and allowing a large current to flow therein; and an IGBT as a sense element (an example of the second switching elements) having a small area and allowing a small current to flow therein. The emitter electrode 30 is contacting the emitter region of the IGBT of the main element (an example of the first switching elements).
The insulation film 70 is partially formed on the upper surface of the semiconductor substrate 10. As a material for the insulation film 70, for example, silicon dioxide (SiO2) can be used. The insulation film 70 insulates the semiconductor substrate 10 and the gate electrode 20.
The gate electrode 20 is formed on the upper surface of the insulation film 70. The gate electrode 20 is formed on the semiconductor substrate 10 through the insulation film 70. The gate electrode 20 has the thickness "t20". As a material for the gate electrode 20, for example, polysilicon can be used.
The insulation film 50 is formed on the upper surface of the gate electrode 20. The insulation film 50 covers whole of the gate electrode 20. In addition, the insulation film 50 is also formed on the upper surface of the semiconductor substrate 10. The insulation film 50 covers the gate electrode 20 and the semiconductor substrate 10 from the above. The insulation film 50 covers edges 21 on both sides of the gate electrode 20. As a material for the insulation film 50, for example, silicon dioxide (SiO2) can be used.
The upper surface of the insulation film 50 includes: a high-order section 52; a low-order section 53; and a first step portion 54. The high-order section 52 is placed upper than the low-order section 53. The high-order section 52, low-order section 53, and first step portion 54 are formed according to the thickness "t20" of the gate electrode 20. That is, the high-order section 52 is placed on the gate electrode 20, and the low-order section 53 is placed on the semiconductor substrate 10 (namely, an area on the semiconductor substrate 10 where the gate electrode 20 is not existing). The first step portion 54 is formed on the boundary between the high-order section 52 and the low-order section 53. A bent portion 55 is formed on a part of the first step portion 54. Specifically, the bent portion 55 concavely curved is formed on the upper surface of the insulation film 50 in the boundary portion between the side surface of the first step portion 54 and the low-order portion 53. The step portions on the insulation film 50 are formed on both (right and left) sides of the gate electrode 20 in FIGS.2 to 4, however, in this embodiment, the step portion of the left side (first step portion 54) in the figures is explained.
FIG.5 is an enlarged view that illustrates the primary part V of FIG.1. In FIG.5, the dotted line and the dashed-dotted line represent the first step portion 54. In FIG.5, the first step portion 54 is represented by the dotted line in the area where the emitter electrode 30 covers the first step portion 54. The first step portion 54 is represented by the dashed-dotted line in the area where the emitter electrode 30 does not cover the first step portion 54. Although the first step portion 54 is essentially invisible in planar view in the area where the emitter electrode 30 and the first step portion 54 are overlapping, the first step portion 54 is represented by the dotted line as a matter of convenience. In planar view as shown in FIG.5, the emitter electrode 30 is formed at a place where it overlaps with the first step portion 54.
An opening 51 is formed on the insulation film 50. The opening 51 is formed in the high-order section 52 of the insulation film 50. The opening 51 penetrates the insulation film 50. In cross-sectional view as in FIG.3, the opening 51 is not formed on the insulation film 50.
As shown in FIGS.2 and 4, a barrier-metal 80 is formed on the opening 51. The barrier-metal 80 covers the inner surface of the opening 51 and the upper surface of the gate electrode 20. In addition, the barrier-metal 80 covers a part of the upper surface of the insulation film 50. To form the barrier-metal 80, firstly, the barrier-metal 80 is formed over the whole of the insulation film 50. Then, unnecessary portions are removed by selectively etching the barrier-metal 80. In such a manner, the barrier-metal 80 is formed on the opening 51. After forming the barrier-metal 80, a barrier-metal residual substance 81 may be accumulated in the bent portion 55 of the step portion 54 of the insulation film 50. That is, even after carrying out the etching for the barrier-metal 80 formed over the whole of the upper surface of the insulation film 50, the barrier metal may be partially left untouched and remained in the bent portion 55 . The residual substance 81 is a barrier-metal deposit, thus, having a conductivity.
Moreover, the opening 51 of the insulation film 50 is filled with gate wiring 40. The gate wiring 40 is formed on the barrier-metal 80. The gate wiring 40 contacts the gate electrode 20 through the barrier-metal 80. The gate wiring 40 is electrically connected to the gate electrode 20. The gate wiring 40 is formed on the upper part of the gate electrode 20. Therefore, the gate wiring 40 is formed on the high-order section 52 of the insulation film 50 but formed on neither the low-order section 53 nor the first step portion 54. In cross-sectional view as in FIG.3, the opening 51, barrier-metal 80, and gate wiring 40 are not formed.
Moreover, the emitter electrode 30 covers the upper surface of the semiconductor substrate 10. In cross-sectional view as in FIG.2, the emitter electrode 30 covers the low-order section 53, first step portion 54, and a part of the high-order section 52 of the insulation film 50. The emitter electrode 30 is formed away from the gate wiring 40. In cross-sectional view as in FIG.3, the emitter electrode 30 covers the low-order section 53, first step portion 54, and high-order section 52 of the insulation film 50. On the other hand, in cross-sectional view as in FIG.4, the emitter electrode 30 does not cover the first step portion 54 of the insulation film 50. As shown in FIGS.2 to 4, the barrier-metal residual substance 81 is present in the bent portion 55. As shown in FIGS.2 and 3, in the portion where the emitter electrode 30 and the first step portion 54 are overlapping, the emitter electrode 30 covers the barrier-metal residual substance 81.
In planar view as shown in FIG.5, the first step portion 54 is extending in y-direction in the vicinity of the third region 43 while it is extending in x-direction in the vicinity of the first region 41. At the position represented by the dashed-dotted line, the first step portion 54 is not covered by the emitter electrode 30 and is exposing to the surface. That is, the first step portion 54 is not covered by any conductive member other than the emitter electrode 30. The connecting region 34 of the emitter electrode 30 covers the bent portion 55 of the first step portion 54.
As shown in FIG.5, the gate wiring 40 is formed so as not to overlap with the first step portion 54 at any place. That is, the gate wiring 40 does not cover the first step portion 54. Therefore, the gate wiring 40 does not contact the barrier-metal residual substance 81 which is accumulating in the first step portion 54.
As above, while the first step portion 54 is covered by the emitter electrode 30, the first step portion 54 is not covered by the gate wiring 40. In addition, as for the first step portion 54, the first step portion 54 is not covered by any conductive member other than the emitter electrode 30. Moreover, outside the range of FIG.5, the first step portion 54 is also not covered any conductive member other than the emitter electrode 30.
As clarified from above explanation, for the semiconductor device 1 having the above configuration, the first step portion 54 is covered by the emitter electrode 30 but not by the gate wiring 40. Thus, when the conductive barrier-metal residual substance 81 is accumulating in the first step portion 54, the residual substance 81 is contacted by the emitter electrode 30 but not by the gate wiring 40. As a result, the emitter electrode 30 and the gate wiring 40 will never be electrically connected via the residual substance 81 remaining in the first step portion 54. Therefore, the occurrence of short-circuit between the emitter electrode 30 and the gate wiring 40 owing to the conductive residual substance 81 remaining on the insulation film 50 can be suppressed. Moreover, since the first step portion 54 is not covered by any conductive member other than the emitter electrode 30, the occurrence of short-circuit between the emitter electrode 30 and a conductive member other than the gate wiring can also be suppressed.
In above semiconductor device 1, the emitter electrodes 30 includes the first region 31, the second region 32 separated from the first region 31, and the connecting region 34 for connecting the first region 31 and the second region 32. In such a configuration, as compared to the configuration having no connecting region 34, the first step portion 54 formed on the upper surface of the insulation film 50 is likely to overlap with the emitter electrode 30. Therefore, the above configuration is especially effective in suppressing the occurrence of short-circuit between the emitter electrode 30 and the gate wiring 40 through the residual substance 81 accumulating in the first step portion 54.
(Second Embodiment)
One embodiment of the present invention has been explained above, however, specific aspects are not limited to the above embodiment. In the following explanation, the same reference signs used in the above explanation are used here for the same configuration to omit the explanation. In the above embodiment, a configuration for suppressing the occurrence of short-circuit between the emitter electrode 30 and the gate wiring 40 has been explained, however, the present invention is not limited to this configuration. As shown in FIG.6, the semiconductor device 1 of the second embodiment further includes a plurality of sense electrodes 60 (one example of first conductive members). In planar view, the sense electrodes 60 are aligned with clearances in between them. The sense electrodes 60 are connected to the emitter region of the IGBT as sense elements (one example of second switching elements). The sense electrodes 60 are formed between the first region 31 of the emitter electrode 30 and the first region 41 of the gate wiring 40, and between the second region 32 of the emitter electrode 30 and the second region 42 of the gate wiring 40. The sense electrodes 60 are used for detecting electric current and temperature.
In planar view, the emitter electrode 30, gate wiring 40, and sense electrodes 60 are separated apart from each other. The insulation film 50 is formed between the emitter electrode 30, gate wiring 40, and sense electrodes 60. The emitter electrode 30, gate wiring 40, and sense electrodes 60 are insulated from each other. The emitter electrode 30, gate wiring 40, and sense electrodes 60 have conductivity. Different potentials are respectively applied to the emitter electrode 30, gate wiring 40, and sense electrodes 60.
In cross-sectional view as in FIGS. 7 and 8, the semiconductor device 1 includes: a semiconductor substrate 10; an insulation film 70 formed on the semiconductor substrate 10; and a gate electrode 20 formed on the insulation film 70. The semiconductor device 1 also includes: an insulation film 50 formed on the gate electrode 20 and the semiconductor substrate 10; and an emitter electrode 30 formed on the insulation film 50 and the semiconductor substrate 10. The semiconductor device 1 further includes: a barrier-metal 80 formed on the gate electrode 20; and gate wiring 40 formed on the barrier-metal 80. The semiconductor device 1 still further includes a sense electrode 60 formed on the insulation film 50. Although two gate electrodes 20 are shown in FIG.8, these are just separated apart from each other in the cross-sectional view as shown in FIG.8, they are connected at portions that are not depicted in the figure, thus having the same configuration. In this embodiment, the gate electrodes 20 shown in FIG.8 is referred to as: the left side gate electrode 20a for that on the left side; and the right side gate electrode 20b for that on the right side.
As shown in FIG.7, the upper surface of the insulation film 50 includes: a high-order section 52; a low-order section 53; and a second step portion 54. The high-order section 52, low-order section 53, and second step portion 254 are formed according to the thickness "t20" of the gate electrode 20. The second step portion 254 is formed according to the height positional difference between the high-order section 52 and the low-order section 53. The step portions on the insulation film 50 are formed on both (right and left) sides of the gate electrode 20 in FIG.7, however, in this embodiment, the step portion of the right side (second step portion 254) in the figure is explained. The high-order section 52 is formed on the gate electrode 20. The low-order section 53 and the second step portion 254 are formed on the flank of an edge 21 of the gate electrode 20. The low-order section 53 is formed on the semiconductor substrate 10. The second step portion 254 is formed between the high-order section 52 and the low-order section 53. The height of the high-order section 52 is higher than that of the low-order section 53. A bent portion 55 is formed on a part of the second step portion 254.
As shown in FIG.8, the upper surface of the insulation film 50 for covering the left side gate electrode 20a includes: a high-order section 52; a low-order section 53; and a third step portion 354. The high-order section 52, low-order section 53, and third step portion 354 are formed according to the thickness "t20" of the gate electrode 20. The third step portion 354 is formed according to the height positional difference between the high-order section 52 and the low-order section 53. The step portions on the insulation film 50 are formed on both (right and left) sides of the left side gate electrode 20a in FIG.8, however, in this embodiment, the step portion of the left side (third step portion 354) in the figure is explained. The high-order section 52 is formed on the left side gate electrode 20a. The low-order section 53 and the third step portion 354 are formed on the flank of the edge 21 of the left side gate electrode 20a. The third step portion 354 is formed between the high-order section 52 and the low-order section 53. The bent portion 55 is formed on a part of the third step portion 354.
As shown in FIG.8, the upper surface of the insulation film 50 for covering the right side gate electrode 20b includes: the high-order section 52; low-order section 53; and fourth step portion 454. The high-order section 52, low-order section 53, and fourth step portion 454 are formed according to the thickness "t20" of the gate electrode 20. The fourth step portion 454 is formed according to the height positional difference between the high-order section 52 and the low-order section 53. The step portions on the insulation film 50 are formed on both (right and left) sides of the right side gate electrode 20b in FIG.4, however, in this embodiment, the step portion of the left side (fourth step portion 454) in the figure is explained. The high-order section 52 is formed on the right side gate electrode 20b. The low-order section 53 and the fourth step portion 454 are formed on the flank of the edge 21 of the right side gate electrode 20b. The fourth step portion 454 is formed between the high-order section 52 and the low-order section 53. The bent portion 55 is formed on a part of the fourth step portion 454.
As shown in FIG.7 and 8, a barrier-metal 80 is formed on the opening 51 of the insulation film 50. After forming the barrier-metal 80, a barrier-metal residual substance 81 may be accumulated in the second step portion 254, third step portion 354, and fourth step portion 454 of the insulation film 50. That is, even after carrying out an etching for the barrier-metal 80 formed over the whole of the upper surface of the insulation film 50, the barrier metal may be partially left untouched and remained on the surface of the second step portion 254, third step portion 354, and fourth step portion 454. Thereby, the residual substance 81 is accumulated in the second step portion 254, third step portion 354, and fourth step portion 454. The residual substance 81 is a barrier-metal deposit, thus, having a conductivity.
As shown in FIG. 7, an emitter electrode 30 is formed on the upper surface of the insulation film 50. The emitter electrode 30 is formed away from the gate wiring 40. Different potential is applied on the emitter electrode 30 and the gate wiring 40. The emitter electrode 30 covers the high-order section 52, low-order section 53, and the second step portion 254 of the insulation film 50. The emitter electrode 30 is formed on the second step portion 254, and contacts the barrier-metal residual substance 81 accumulated in the second step portion 254.
As shown in FIG. 8, the opening 51 of the insulation film 50 on the left side gate electrode 20a is filled with gate wiring 40. The gate wiring 40 is formed on the barrier-metal 80. The gate wiring 40 contacts the gate electrode 20 through the barrier-metal 80. The gate wiring 40 is electrically connected to the gate electrode 20. The gate wiring 40 is formed on the high-order section 52, low-order section 53, and third step portion 354 of the insulation film 50. The gate wiring 40 is formed on neither the second step portion 254 (not shown in FIG.8) nor the fourth step portion 454 of the insulation film 50. The low-order section 53 and the fourth step portion 454 are placed on the frank of the gate wiring 40. The gate wiring 40 is formed on the third step portion 354, and contacts the barrier-metal residual substance 81 accumulated in the third step portion 354.
As shown in FIG. 8, the sense electrode 60 is formed on the upper surface of the insulation film 50 on the right side gate electrode 20b. The opening 51 is not formed on the insulation film 50 on the right side gate electrode 20b. The insulation film 50 covers whole of the right side gate electrode 20b. The sense electrode 60 is formed on the high-order section 52, low-order section 53, and fourth step portion 454 of the insulation film 50. The sense electrode 60 is formed on neither the second step portion 254 (not shown in FIG.8) nor the third step portion 354 of the insulation film 50. The sense electrode 60 is formed on the fourth step portion 454, and contacts the barrier-metal residual substance 81 accumulated in the fourth step portion 454.
The forming positions of the second step portion 254, third step portion 354, and fourth step portion 454 are different from that of the first step portion 54 in planar view, however, the configuration of these portions is the same as that of the first step portion 54 in cross-sectional view. That is, the second step portion 254, third step portion 354, and fourth step portion 454 are formed according to the thickness "t20" of the gate electrode 20. The second step portion 254, third step portion 354, and fourth step portion 454 are formed according to the height positional difference between the high-order section 52 and the low-order section 53. The second step portion 254, third step portion 354, and fourth step portion 454 are formed at a curved portion on the upper surface of the insulation film 50. The second step portion 254, third step portion 354, and fourth step portion 454 are formed on the flank of the edge 21 of the gate electrode 20. The second step portion 254, third step portion 354, and fourth step portion 454 are formed between the high-order section 52 and the low-order section 53.
The second step portion 254 is covered by the emitter electrode 30. The third step portion 354 is covered by the gate wiring 40. The fourth step portion 454 is covered by the sense electrode 60.
FIG.9 is an enlarged view that illustrates the primary part IX of FIG.6. In planar view as shown in FIG.9, the emitter electrode 30 is formed at a place where it overlaps with the second step portion 254. In FIG.9, the second step portion 254 is represented by the dotted line in the area where the emitter electrode 30 covers the second step portion 254. The second step portion 254 is represented by the dashed-dotted line in the area where the emitter electrode 30 does not cover the second step portion 254. Although the second step portion 254 is essentially invisible in planar view in the area where the emitter electrode 30 and the second step portion 254 are overlapping, the second step portion 254 is represented by the dotted line as a matter of convenience. In the area where the emitter electrode 30 and the second step portion 254 are overlapping, the emitter electrode 30 contacts the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the second step portion 254.
The second step portion 254 is extending in nearly parallel with the upper surface of the semiconductor substrate 10. In planar view as shown in FIG.9, the second step portion 254 is extending along the edge of the emitter electrode 30. The second step portion 254 is extending in the x direction and y direction of FIG.9. The second step portion 254 is extending in a position that overlaps with the emitter electrode 30. On the other hand, the second step portion 254 is extending in a position that does not overlap with the gate wiring 40 and the sense electrode 60. The second step portion 254 is extending outside the edge of the gate wiring 40. In addition, the second step portion 254 is extending outside the edge of the sense electrode 60. The area of the second step portion 254 not overlapping with the emitter electrode 30 (the area represented by the dashed-dotted line in FIG.9) is exposed to the outside.
In planar view as shown in FIG.9, the gate wiring 40 is formed at a place where it does not overlap with the second step portion 254. The gate wiring 40 does not cover the second step portion 254. Therefore, the gate wiring 40 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the second step portion 254. Moreover, in planar view as shown in FIG.9, the sense electrode 60 is formed at a place where it does not overlap with the second step portion 254. The sense electrode 60 does not cover the second step portion 254. Therefore, the sense electrode 60 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the second step portion 254.
In addition, in planar view as shown in FIG.9, the gate wiring 40 is formed at a place where it overlaps with the third step portion 354. In FIG.9, the third step portion 354 is represented by the dotted line in the area where the gate wiring 40 covers the third step portion 354. Although the third step portion 354 is essentially invisible in planar view in the area where the gate wiring 40 and the third step portion 354 are overlapping, the third step portion 354 is represented by the dotted line as a matter of convenience. In the area where the gate wiring 40 and the third step portion 354 are overlapping, the gate wiring 40 contacts the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the third step portion 354.
The third step portion 354 is extending in nearly parallel with the upper surface of the semiconductor substrate 10. In planar view as shown in FIG.9, the third step portion 354 is extending along the edge of the gate wiring 40. The third step portion 354 is extending in the x direction of FIG.9. The third step portion 354 is extending as far as it overlaps with the gate wiring 40. On the other hand, the third step portion 354 is not extending as far as it overlaps with the emitter electrode 30 and the sense electrode 60. The third step portion 354 is extending outside the edge of the emitter electrode 30. In addition, the third step portion 354 is extending outside the edge of the sense electrode 60. The area of the third step portion 354 not overlapping with the gate wiring 40 (not shown) is exposed to the outside.
As planar view as shown in FIG.9, the emitter electrode 30 is formed at a place where it does not overlap with the third step portion 354. The emitter electrode 30 does not cover the third step portion 354. Therefore, the emitter electrode 30 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the third step portion 354. Moreover, in planar view as shown in FIG.9, the sense electrode 60 is formed at a place where it does not overlap with the third step portion 354. The sense electrode 60 does not cover the third step portion 354. Therefore, the sense electrode 60 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the third step portion 354.
In addition, in planar view as shown in FIG.9, the sense electrode 60 is formed at a place where it overlaps with the fourth step portion 454. In FIG.9, the fourth step portion 454 is represented by the dotted line in the area where the sense electrode 60 covers the fourth step portion 454. The fourth step portion 454 is represented by the dashed-dotted line in the area where the sense electrode 60 does not cover the fourth step portion 454. Although the fourth step portion 454 is essentially invisible in planar view in the area where the sense electrode 60 and the fourth step portion 454 are overlapping, the fourth step portion 454 is represented by the dotted line as a matter of convenience. In the area where the sense electrode 60 and the fourth step portion 454 are overlapping, the sense electrode 60 contacts the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the fourth step portion 454.
The fourth step portion 454 is extending in nearly parallel with the upper surface of the semiconductor substrate 10. In planar view as shown in FIG.9, the fourth step portion 454 is extending along the edge of the sense electrode 60. The fourth step portion 454 is extending in the x direction and y direction of FIG.9. The fourth step portion 454 is extending as far as it overlaps with the sense electrode 60. On the other hand, the fourth step portion 454 is not extending as far as it overlaps with the gate wiring 40 and the emitter electrode 30. The fourth step portion 454 is extending outside the edge of the gate wiring 40. The fourth step portion 454 is extending outside the edge of the emitter electrode 30. The area of the fourth step portion 454 not overlapping with the sense electrode 60 (the area represented by the dashed-dotted line in FIG.9) is exposed to the outside.
In planar view as shown in FIG.9, the gate wiring 40 is formed at a place where it does not overlap with the fourth step portion 454. The gate wiring 40 does not cover the fourth step portion 454. Therefore, the gate wiring 40 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the fourth step portion 454. In addition, in planar view as shown in FIG.9, the emitter electrode 30 is formed at a place where it does not overlap with the fourth step portion 454. The emitter electrode 30 does not cover the fourth step portion 454. Therefore, the emitter electrode 30 does not contact the barrier-metal residual substance 81 (not shown in FIG.9) which is accumulating in the fourth step portion 454.
As clarified from above explanation, the semiconductor device 1 having above configuration includes: the second step portion 254; third step portion 354; and fourth step portion 454, these formed on the upper surface of the insulation film 50 that covers the gate electrode 20 according to the thickness "t20" of the gate electrode 20. In addition, the emitter electrode 30 covers the second step portion 254, however, the gate wiring 40 and the sense electrode 60 having different potential from that of the emitter electrode 30 do not cover the second step portion 254. Thus, when the conductive barrier-metal residual substance 81 is accumulating in the second step portion 254, the emitter electrode 30 contacts the residual substance 81, but the gate wiring 40 and sense electrode 60 do not contact the residual substance 81. As a result, the emitter electrode 30, the gate wiring 40, and sense electrode 60 will never be electrically connected via residual substance 81 remaining in the second step portion 254. Therefore, the occurrence of short-circuit between the emitter electrode 30, gate wiring 40, and sense electrode 60 owing to the conductive residual substance 81 remaining in the insulation film 50 can be suppressed.
Similarly, the gate wiring 40 covers the third step portion 354, however, the emitter electrode 30 and the sense electrode 60 having different potential from that of the gate wiring 40 do not cover the third step portion 354. As a result, the gate wiring 40, emitter electrode 30, and sense electrode 60 will never be electrically connected via conductive residual substance 81 remaining in the third step portion 354. Therefore, the occurrence of short-circuit between the gate wiring 40, emitter electrode 30, and sense electrode 60 owing to the conductive residual substance 81 remaining on the insulation film 50 can be suppressed. Similarly, the sense electrode 60 covers the fourth step portion 454, however, the gate wiring 40 and the emitter electrode 30 having different potential from that of the sense electrode 60 do not cover the fourth step portion 454. As a result, the sense electrode 60, emitter electrode 30, and gate wiring 40 will never be electrically connected via conductive residual substance 81 remaining in the fourth step portion 454. Therefore, the occurrence of short-circuit between the sense electrode 60, emitter electrode 30, and gate wiring 40 owing to the conductive residual substance 81 remaining in the insulation film 50 can be suppressed.
Embodiments of the present invention have been explained above, however, specific aspects are not limited to those described above. For example, an IGBT was described as a switching element in the embodiment, however, the present invention is not limited to this configuration. A FET may be described as a switching element in other embodiment. In terms of a FET, a source electrode may be described as a first conductive member. The source electrode is a negative electrode.
In planar view, the locating position and configuration for the emitter electrode 30, gate wiring 40, and sense electrode 60 are not specially limited and may be modified as necessary.
As explained above, the step portion having a conductive barrier-metal residual substance 81 accumulated therein is covered by the first conductive member, but not covered by the other conductive member having different potential from that of the first conductive member. Thereby, the occurrence of short-circuit between the first conductive member and the conductive member other than the first conductive member through the conductive barrier-metal residual substance 81 can be suppressed.
(Third Embodiment)
Specific aspects of the semiconductor device are not limited to above embodiments. For example, the configuration of the fourth step portion 454 is not limited to above embodiments. In another embodiment as in FIG.10, a plurality of fourth step portions 454 is formed in planar view. The plurality of fourth step portions 454 are formed with a clearance. Each of the fourth step portions 454 is formed at a place where it overlaps with the sense electrode 60. Each of the fourth step portions 454 is covered by the sense electrode 60. The conductive member other than the sense electrode 60 does not cover the fourth step portion 454.
Specific examples of the teachings herein have been described in detail, however, these are mere exemplary indications and thus do not limit the scope of the claims. The art described in the claims includes modifications and variations of the specific examples presented above. Technical features described in the description and the drawings may technically be useful alone or in various combinations, and are not limited to the combinations as originally claimed. Further, the art described in the description and the drawings may concurrently achieve a plurality of aims, and technical significance thereof resides in achieving any one of such aims.

Claims (5)

  1. A semiconductor device, comprising:
    a semiconductor substrate in which a first switching element is formed;
    a gate electrode of the first switching element formed on the semiconductor substrate;
    an insulation film covering the gate electrode and the semiconductor substrate;
    a first conductive member formed on the insulation film; and
    a gate wiring formed on the insulation film, separated from the first conductive member, and being in contact with the gate electrode;
    wherein an upper surface of the insulation film comprises a first portion, a second portion, and a step portion, the first portion being located on the gate electrode, the second portion being located on the substrate, and the step portion being located between the first and second portions, and
    the first conductive member covers the step portion, and the gate wiring does not cover the step portion.
  2. The semiconductor device according to claim 1, wherein
    the gate wiring is formed on the first portion.
  3. The semiconductor device according to claim 1 or 2, wherein
    the first conductive member is a negative electrode of the first switching element.
  4. The semiconductor device according to claim 1 or 2, wherein
    a second switching element is further formed in the semiconductor substrate, and
    the first conductive member is a negative electrode of the second switching element.
  5. The semiconductor device according to claim 3 or 4, wherein
    the negative electrode comprises a first region, a second region formed with an interval from the first region, and a connecting region connecting the first region and the second region, and
    the connecting region covers the step portion.
PCT/JP2015/000081 2014-03-03 2015-01-09 Semiconductor device WO2015133047A1 (en)

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JP2019102656A (en) * 2017-12-04 2019-06-24 株式会社ジャパンディスプレイ Wiring structure and display device including wiring structure

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US20020149079A1 (en) * 2001-04-13 2002-10-17 International Rectifier Corp. Semiconductor device and process for its manufacture to increase threshold voltage stability
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JPS63104448A (en) 1986-10-22 1988-05-09 Hitachi Ltd Semiconductor integrated circuit device
US5686750A (en) * 1991-09-27 1997-11-11 Koshiba & Partners Power semiconductor device having improved reverse recovery voltage
US20020149079A1 (en) * 2001-04-13 2002-10-17 International Rectifier Corp. Semiconductor device and process for its manufacture to increase threshold voltage stability
US20080079081A1 (en) * 2006-09-29 2008-04-03 Yasunori Hashimoto Semiconductor apparatus and manufacturing method
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