WO2015117392A1 - 提高数字pfc电路可靠性的方法及装置 - Google Patents

提高数字pfc电路可靠性的方法及装置 Download PDF

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Publication number
WO2015117392A1
WO2015117392A1 PCT/CN2014/089097 CN2014089097W WO2015117392A1 WO 2015117392 A1 WO2015117392 A1 WO 2015117392A1 CN 2014089097 W CN2014089097 W CN 2014089097W WO 2015117392 A1 WO2015117392 A1 WO 2015117392A1
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Prior art keywords
wave
pfc
module
bus
current
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PCT/CN2014/089097
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English (en)
French (fr)
Inventor
王静思
杨运东
王明金
王鸿
高养怀
程志荣
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中兴通讯股份有限公司
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Publication of WO2015117392A1 publication Critical patent/WO2015117392A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/18—Arrangements for adjusting, eliminating or compensating reactive power in networks
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/18—Arrangements for adjusting, eliminating or compensating reactive power in networks
    • H02J3/1892—Arrangements for adjusting, eliminating or compensating reactive power in networks the arrangements being an integral part of the load, e.g. a motor, or of its control circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/30—Reactive power compensation

Definitions

  • the invention belongs to the field of AC/DC (Alternating Current/Direct Current) power conversion technology, and particularly relates to a method and device for improving the reliability of a digital power factor correction (PFC) circuit.
  • AC/DC Alternating Current/Direct Current
  • PFC digital power factor correction
  • PFC circuits play a large role in improving grid transmission efficiency and reducing harmonic pollution of power grids.
  • single-phase PFC control most of the control schemes are based on the average current control strategy of the Boost converter.
  • a typical Boost digital PFC control block diagram as shown in Figure 1, the entire system consists of two parts: the main circuit and the control circuit.
  • the main circuit consists of a single-phase bridge rectifier and a DC/DC (Direct Current/Direct Current) Boost converter.
  • the control circuit is composed of a digital signal controller (DSC, Digital Signal Controller) running the control algorithm program and a peripheral signal conditioning circuit.
  • DSC Digital Signal Controller
  • the loop control adopts a double closed loop PI control algorithm, which is jointly controlled by the current inner loop and the voltage outer loop.
  • the current inner loop PI regulator Gcea adjusts the inductor current so that the waveform follows the change in the input voltage.
  • the output of the voltage outer loop PI regulator Gvea is multiplied by a multiplier and the main circuit input rectified voltage, and the product is used as the reference signal Iref of the current control link.
  • the reference signal Iref By adjusting the value of the reference signal Iref, the output voltage of the PFC side is output buffer voltage. V0 remains constant.
  • the PFC digital control method Compared with the traditional analog control method, the PFC digital control method has many advantages such as flexibility, portability, saving hardware circuit space and cost. At the same time, the digital control method also has the inherent defect of delay control. In the PFC digital control system, due to the analog/digital (AD, Analog/Digital) sampling time and the operation time, the pulse width obtained by the current period calculation can only be The cycle can be used, so the PFC is delayed by one switching cycle. In the steady state where the input voltage and output load are stable, the effects of digital and analog control are not much different. By properly optimizing the loop control algorithm, the digital control method may even get better PF and THD indicators.
  • AD Analog/Digital
  • the purpose of the invention is to enable timely protection during the overvoltage of the Bus overvoltage and the PFC inductor, and to significantly reduce the Bus voltage and the inductor current stress during the dynamic switching of the input and output, so as to improve the reliability of the PFC circuit.
  • a method for improving the reliability of a digital PFC circuit includes performing a Bus overvoltage protection strategy, and the step of executing a Bus overvoltage protection strategy includes the following steps:
  • the threshold V1 is the highest operating voltage allowed by the Bus capacitor.
  • the threshold V2 is higher than the maximum value of the Bus actual voltage during steady-state operation.
  • the threshold V3 is the Bus voltage reference value, where V1>V2 >V3;
  • the Bus voltage is greater than the threshold value V1, it is determined to be a high voltage protection state, the input voltage is disconnected, the slow start parameter is initialized, the PFC drive is turned off, and the rectifier is set to a stop state;
  • the Bus overvoltage off driving state determining the relationship between the Bus voltage and the threshold V3, when the Bus voltage is less than the threshold V3, the PFC drive is resumed, and the voltage loop integral variable is cleared; if the Bus voltage is greater than the threshold V3, the maintenance is maintained.
  • the Bus overvoltage off drive state remains unchanged.
  • the method further includes performing a PFC inductive overcurrent protection policy, where the step of performing the PFC inductive overcurrent protection policy includes the following steps:
  • the comparison module compares the sampled PFC inductor current with the set wave-by-wave current limit point
  • the comparison module When the PFC inductor current value exceeds the wave-by-wave current limit point, the comparison module outputs a high-level signal and sends it to the TZ trigger unit of the pulse width modulation PWM module to block the PWM wave, and the blocking state is maintained to the current switch. End of cycle
  • the comparison module When the PFC inductor current value is lower than the wave-by-wave current limit point, the comparison module outputs a low level signal, the PWM outputs normally, and the drive signal recovers.
  • the method further includes the step of performing a strategy of reducing the PFC inductor current, the step of performing the strategy of reducing the PFC inductor current comprising performing a step of reducing a wave-by-wave current limit point strategy on a wave-by-wave basis, the performing reducing the wave-by-wave limit
  • the steps of the flow point strategy include the following steps:
  • the wave-by-wave current limiting point When detecting a wave-by-wave occurrence, the wave-by-wave current limiting point is reduced to a wave-by-wave current limiting point I2, and a timer is started at the same time, wherein I1>I2, and the size of I2 needs to ensure that the inductor current is not drastically wave-by-wave;
  • the wave-by-wave current limit point is restored to the I1 after the period T of the timer expires or when no wave-by-wave generation occurs.
  • the step of performing a strategy of reducing the PFC inductor current further comprises the step of executing a clear loop intermediate variable strategy, the step of executing the clear loop intermediate variable strategy comprising the steps of:
  • the program detects that the PFC inductor current reference is greater than the specific value I, the output of the current inner loop PI regulator and the integral variable are cleared, and the output of the voltage outer loop PI regulator and the integral variable are cleared; wherein, the specific value I is higher than the steady state normal operating value and can reduce the inductor current.
  • a device for improving the reliability of a digital PFC circuit comprising a Bus overvoltage protection module, the Bus overvoltage protection module comprising a threshold setting module, a BUS voltage primary protection module and a BUS voltage secondary protection module, wherein:
  • the threshold setting module is configured to: set three thresholds V1, V2, and V3, wherein the threshold V1 is the highest operating voltage allowed by the Bus capacitor, and the threshold V2 is higher than the maximum value of the Bus actual voltage during steady-state operation.
  • the threshold V3 is a Bus voltage reference value, where V1>V2>V3;
  • the BUS voltage primary protection module is configured to: when the Bus voltage is greater than the threshold V1, determine a high voltage protection state, disconnect the input voltage, initialize a slow start parameter, turn off the PFC drive, and set the rectifier to a stop state;
  • the BUS voltage secondary protection module is configured to: when the Bus voltage is greater than the threshold V2 but less than the threshold value V1, it is determined that the Bus overvoltage is off driving state, and the PFC driving is turned off; in the Bus overvoltage shutdown driving state, determining The relationship between the bus voltage and the threshold value V3, when the Bus voltage is less than the threshold value V3, the PFC drive is resumed, and the voltage loop integral variable is cleared; when the Bus voltage is greater than the threshold value V3, the Bus overvoltage off driving state is maintained. .
  • the device further includes a PFC inductor overcurrent protection module, where the PFC inductor overcurrent protection module includes an inductor current comparison module, a blocking module, and a recovery module, where:
  • the inductor current comparison module is configured to: compare the sampled PFC inductor current with the set wave-by-wave current limit point in each switching cycle;
  • the blocking module is configured to: when the PFC inductor current value exceeds the wave-by-wave current limiting point, cause the inductor current comparison module to output a high level signal and send the signal to the TZ trigger unit of the pulse width modulation PWM module, The blocking module blocks the PWM wave, and the blocking state is maintained until the end of the current switching cycle;
  • the recovery module is configured to: when the PFC inductor current value is lower than the wave-by-wave current limit point, such that the inductor current comparison module outputs a low-level signal, the recovery module causes the PWM to output normally, and the driving signal is restored.
  • the apparatus further includes a reduced PFC inductor current module, the reduced PFC inductor current module comprising a reduced wave-by-wave current limit point module, the reduced wave-by-wave current limit point module being configured to:
  • the set wave-by-wave current limit point is kept as the default wave-by-wave current limit point I1 during normal operation;
  • the wave-by-wave current limiting point When detecting a wave-by-wave occurrence, the wave-by-wave current limiting point is reduced to a wave-by-wave current limiting point I2, and a timer is started at the same time, wherein I1>I2, and the size of I2 needs to ensure that the inductor current is not drastically wave-by-wave;
  • the wave-by-wave current limiting point is restored to the I1 when the period T of the timer expires or when no wave-by-wave generation occurs.
  • the reducing PFC inductor current module further includes a clear loop intermediate variable module,
  • the clear loop intermediate variable module is configured to: when the PFC inductor current reference is detected in the program to be greater than a specific value I, the output of the current inner loop PI regulator and the integral variable are cleared, and the voltage outer loop PI regulator is The output and integral variables are cleared; wherein the specific value I is higher than the steady state normal operation value and can reduce the inductor current.
  • the device is located in a digital controller DSC.
  • a computer program comprising program instructions that, when executed by a digital controller DSC, cause the digital controller DSC to perform the above-described method of improving the reliability of a digital PFC circuit.
  • the invention overcomes the deficiencies of the related art, and discloses a method and a device for improving the reliability of a digital PFC circuit.
  • the digital control is performed by using DSC, and the AC/DC partial topology is a structure of a PFC converter; wherein the method of the present invention includes a Bus Voltage protection strategy, PFC inductor overcurrent protection strategy and PFC inductor current reduction strategy.
  • the Bus overvoltage protection strategy adopts the secondary protection mode
  • the PFC inductor overcurrent protection strategy adopts the wave-by-wave current limiting protection strategy.
  • the PFC inductor current strategy is adopted to reduce the wave-by-wave current limiting point and the inductor current reference is larger than a specific one.
  • the apparatus of the present invention corresponds to a method.
  • the technical solution of the present invention has the beneficial effects that not only the Bus overvoltage and the inductor overcurrent can be protected in time, but also the input and output can be significantly reduced under the premise of ensuring the steady state normal operation of the rectifier.
  • the electrical stress of the PFC device during dynamic switching increases the reliability of the rectifier power device.
  • FIG. 1 is a block diagram of a typical Boost type digital PFC control in the related art
  • FIG. 2 is a flow chart showing the steps of a Bus overvoltage protection strategy according to an embodiment of the present invention
  • FIG. 3 is a flow chart showing the steps of a PFC inductor overcurrent protection strategy according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of PFC inductor current wave-by-wave current limiting protection in a PFC inductor overcurrent protection strategy according to an embodiment of the present invention
  • FIG. 5 is a flow chart showing steps of a strategy for reducing a wave-by-wave current limiting point in a wave-by-wave manner in a PFC inductor current reduction strategy according to an embodiment of the present invention
  • FIG. 6 is a flow chart showing the steps of a strategy for clearing a loop intermediate variable in a PFC inductor current strategy according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of an apparatus for improving reliability of a digital PFC circuit according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram showing a connection relationship between a Bus overvoltage protection module and a PFC circuit according to an embodiment of the present invention
  • FIG. 9 is a schematic structural diagram of a Bus overvoltage protection module according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram showing a connection relationship between a PFC inductor overcurrent protection module and a PFC circuit according to an embodiment of the present invention
  • FIG. 11 is a schematic structural diagram of a wave-by-wave current limiting protection module according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of a PFC inductor current reduction module according to an embodiment of the present invention.
  • the input voltage and the output load may sometimes be dynamically changed due to the complicated and varied field application environment.
  • a large PFC inductor current and a Bus voltage are caused by dynamics.
  • the embodiment of the invention discloses a method for improving the reliability of a digital PFC circuit, including a Bus overvoltage protection strategy.
  • the Bus overvoltage protection strategy the Bus overvoltage is protected by the secondary protection mode.
  • the Bus voltage signal of the main power circuit is sent to the DSC for processing after passing through the Bus voltage sampling circuit, and the DSC ADC will simulate the Bus voltage sampling signal. It is converted into a digital signal, and the Bus signal voltage is compared with a preset threshold value, and different processing measures are taken according to the comparison result.
  • the Bus overvoltage protection strategy as shown in Figure 2, the specific process is:
  • Step 11 Set three thresholds V1, V2, and V3.
  • the threshold V1 is the PFC-side output capacitor, that is, the highest operating voltage allowed by the Bus capacitor.
  • the threshold V2 is slightly higher than the actual Bus voltage during steady-state operation, and the threshold V3 is the Bus voltage reference. Value, where V1>V2>V3;
  • the threshold V2 needs to be greater than the maximum value of the actual Bus voltage during steady state operation, but not greater than V1.
  • the threshold V2 is 40V higher than the actual Bus voltage during steady state operation.
  • V1 is the maximum operating voltage allowed by the Bus capacitor.
  • the Bus capacitor exceeds the voltage, the heat accumulation will be quickly blown up.
  • the principle of V2 setting must be guaranteed to be slightly higher than the actual Bus voltage during steady-state operation; V3
  • the setting is more flexible, generally taking the Bus voltage reference value. The purpose is to judge the normal operation and restore the PFC drive once the Bus voltage returns to the vicinity of the Bus voltage reference value.
  • the three thresholds and the Bus overvoltage protection strategy are implemented by the software code in the DSC.
  • Step 12 determining the relationship between the Bus voltage and the threshold values V1 and V2; if the Bus voltage is greater than the threshold value V1, step 13 is performed; if the Bus voltage is greater than the threshold value V2 but less than the threshold value V1, step 14 is performed;
  • Step 13 Determine the high voltage protection state, disconnect the input voltage, initialize the slow start parameter, turn off the PFC drive, and set the rectifier to the stop state;
  • step 13 when it is detected that the Bus voltage Vbus is greater than the threshold value V1, it is determined to be a high voltage protection state, and the first level protection is activated.
  • the input voltage is disconnected, the slow start parameter is initialized, the PFC drive is turned off, and the rectifier is set to the stop state.
  • Step 14 determining that the Bus is over-voltage-off driving state, and turning off the PFC driving;
  • Step 15 In the Bus overvoltage shutdown driving state, determine the relationship between the Bus voltage and V3; if the Bus voltage is less than the threshold V3, go to Step 16. If the Bus voltage is greater than the threshold V3, go to Step 17.
  • Step 16 Restore the PFC driver and clear the voltage loop integral variable.
  • Step 17 Maintain the Bus overvoltage off drive state.
  • step 13 is the first level protection of the Bus voltage
  • steps 14-16 are the second level protection of the Bus voltage.
  • the reason why the two-stage overvoltage protection is applied to the Bus voltage is that the input voltage and the output load are not always stable during the actual operation of the rectifier, and the Bus voltage fluctuates up and down when they fluctuate.
  • the Bus voltage exceeds the reference voltage, it is not appropriate to use a single strategy for protection, because if the first-level protection is used directly, the rectifier will stop the shutdown, although it is more reliable, but it will It affects the steady state normal operation; if the second stage protection is used, only the PFC drive is turned off.
  • the rectifier can be operated with load, if the input voltage is large, the Bus voltage will continue to rise and cause the bomber. Therefore, it is necessary to develop a hierarchical protection strategy based on the severity of the Bus overvoltage.
  • the digital controller of the embodiment of the present invention is not limited to adopting DSC, and other technologies such as a single chip microcomputer or an ARM may also be implemented;
  • the topology of the PFC converter is not limited to a single-phase Boost type PFC converter, and other topologies are Buck type PFC, totem pole PFC, etc. can also be implemented.
  • the method for improving the reliability of the digital PFC circuit further includes a PFC inductor overcurrent protection strategy, wherein the PFC inductor of the main power circuit
  • the current signal is sent to the DSC through the PFC inductor current sampling circuit, and the DSC performs overcurrent protection on the PFC inductor current sampling signal.
  • the wave-by-wave current limiting protection module is implemented by the comparison module of the DSC internal ADC. Referring to FIG. 3 and FIG. 4, the PFC is shown.
  • the implementation process of the inductor overcurrent protection strategy specifically includes the following steps:
  • Step 21 determining whether the current PFC inductor current is greater than the set wave-by-wave current limit point in the current switching cycle, and if so, executing step 22;
  • the switching period refers to the turn-on and turn-off period of the PFC circuit MOS transistor.
  • the wave-by-wave current limiting point refers to a threshold point for limiting the magnitude of the PFC inductor current per switching cycle, which is common knowledge for those skilled in the art and will not be described herein.
  • step 21 the sampled PFC inductor current is compared to the set wave-by-wave current limit using a comparison module internal to the DSC.
  • Step 22 The comparison module outputs a high level signal and sends it to the TZ trigger unit of the pulse width modulation PWM module inside the DSC to block the PWM wave, and the blocking state is maintained until the end of the current switching period;
  • step 22 when the current limit value is exceeded, the comparison module outputs a high level signal, which is directly sent to the TZ (Trip Zone) trigger unit of the PWM (Pulse Width Modulation) module. Trigger an event to block the PWM wave.
  • the process is shown in the dotted line in Figure 4, and the blocking state is maintained until the end of the current switching cycle.
  • Step 23 Determine whether the sampled PFC inductor current is greater than the set in the next switching cycle. Wave-by-wave current limit point; if yes, continue to step 22, if not, perform step 24;
  • Step 24 The comparison module outputs a low level signal, the PWM outputs normally, and the driving signal is recovered.
  • the method for improving the reliability of the digital PFC circuit further includes performing the step of reducing the PFC inductor current strategy, wherein the performing is reduced, because the PF and the THD are not considered in the dynamic state.
  • the step of the PFC inductor current strategy includes the step of performing a wave-by-wave current limit point strategy on a wave-by-wave basis. Referring to FIG. 5, the step of performing the wave-by-wave current limit point strategy includes the following steps:
  • Step 31 Keep the wave-by-wave current limiting point as the default wave-by-wave current limiting point I1 during normal operation;
  • Step 32 When detecting a wave-by-wave occurrence, reduce the current-by-wave current limiting point to I2, and start a timer at the same time, wherein I1>I2, and the size of I2 needs to ensure that the inductor current is not drastically wave-by-wave;
  • Step 33 After the timer period T time, or when no wave-by-wave generation occurs, the wave-by-wave current limit point is restored to I1.
  • the wave-by-wave current limiting point strategy is a pure software strategy, that is, when the current level program detects that the wave-by-wave occurs, the wave-by-wave current limiting point is lowered and maintained for a certain time, when the time is maintained. The wave-by-wave current limit is restored to the default value when the end or no wave-by-wave occurs.
  • the default wave-by-wave current limit point I1 must be set to the appropriate size. If the setting is too low, the wave-by-wave current limiting protection strategy will also be triggered during steady state operation, which will affect the steady state normal. Operation; if set too high, it will not protect the PFC inductor current.
  • the setting of I2 is more flexible and needs to be slightly lower than I1, and it is necessary to ensure that the inductor current is not drastically wave-by-wave.
  • the reason for adopting the strategy of reducing the wave-by-wave current limiting point by wave-by-wave is as follows: the steady-state guarantee is not wave-by-wave, the default wave-by-wave current limiting point I1 is set relatively high; in the dynamic state, in order to reduce the PFC inductor current, Appropriate wave-by-wave is allowed, so the wave-by-wave point can be moderately reduced immediately after detecting the wave-by-wave, thereby reducing the PFC inductor current during dynamics.
  • Iref is always in a suitable range, so that the inductor current Iin and the Bus voltage Vo are both stable; however, when the input voltage and the output load appear to be similar to the input voltage power cycle time.
  • the PFC inductor current strategy further includes a clear loop intermediate variable strategy.
  • the clear loop intermediate variable is The strategy includes the following steps:
  • the clear loop intermediate variable strategy is a pure software strategy, that is, when the current level program detects that the inductor current reference value is greater than a certain value, the intermediate variable of the voltage loop and the current loop PI algorithm is cleared.
  • the setting of I should not be too small, so as not to affect the steady state normal operation; but it should not be too large, otherwise it will not reduce the inductor current, that is, the specific value I is higher than the steady state normal operation.
  • the value of the time and can play a role in reducing the inductor current.
  • the subtlety of this strategy is that the integral variable of the PI control loop is also cleared, so that when the inductor current reference Iref is less than the I recovery control loop output, the output of the control loop is only related to the input at this moment, and The previous output is independent, which greatly reduces the inductor current stress at the recovery moment.
  • the invention further discloses an apparatus for improving the reliability of a digital PFC circuit.
  • the utility model comprises a Bus overvoltage protection module 1, a wave-by-wave current limiting protection module 2 and a reduced PFC inductor current module 3.
  • Bus overvoltage protection module 1 For the Bus overvoltage protection module 1, as shown in FIG. 8, the Bus voltage signal of the main power circuit is sent to the DSC for processing after passing through the Bus voltage sampling circuit, and the DSC ADC converts the analog Bus voltage sampling signal into a digital signal for the Bus.
  • the pressure protection module 1 is used.
  • the threshold setting module 11 is configured to: set three thresholds V1, V2 and V3, the threshold V1 is the highest working voltage allowed by the Bus capacitor, the threshold V2 is slightly higher than the actual Bus voltage during steady state operation, and the threshold V3 is the Bus voltage reference value. , where V1>V2>V3;
  • the BUS voltage primary protection module 12 is configured to: when the Bus voltage is greater than the threshold V1, determine the high voltage protection state, disconnect the input voltage, initialize the slow start parameter, turn off the PFC drive, and set the rectifier to the stop state;
  • the BUS voltage secondary protection module 13 is configured to: when the Bus voltage is between the threshold V2 and the threshold V1, it is determined that the Bus overvoltage is off driving state, and the PFC driving is turned off; in the Bus overvoltage shutdown driving state, when the Bus voltage is less than the threshold V3 When the PFC driver is restored, the voltage loop integral variable is cleared.
  • the PFC inductor current signal of the main power circuit is sent to the DSC through the PFC inductor current sampling circuit, and the DSC sends the PFC inductor current sampling signal to the wave-by-wave current limiting protection module 2 deal with.
  • the wave-by-wave current-limit protection module 2 is implemented by using a comparison module of the DSC internal ADC.
  • the wave-by-wave current-limit protection module 2, as shown in FIG. 11, includes:
  • the inductor current comparison module 21 is configured to: compare the sampled PFC inductor current with the set wave-by-wave current limit point;
  • the blocking module 22 is configured to: when the PFC inductor current value exceeds the wave-by-wave current limiting point, the inductor current comparison module 21 outputs a high-level signal and sends it to the TZ trigger unit of the pulse width modulation module to block the PWM wave and block the signal. The state is maintained until the end of the current switching cycle;
  • the recovery module 23 is configured to: when the PFC inductor current value is lower than the wave-by-wave current limit point, the inductor current comparison module 21 outputs a low-level signal, the PWM is normally output, and the driving signal is recovered.
  • the reduced PFC inductor current module includes a wave-by-wave reduction wave-by-wave current limit point module 31 and a clear loop intermediate variable module 32;
  • the wave-by-wave current limiting point module 31 is configured to: maintain the wave-by-wave current limiting point as the default wave-by-wave current limiting point I1 during normal operation; and reduce the wave-by-wave current limiting point to I2 when detecting a wave-by-wave occurrence.
  • the timer is started, where I1>I2; after T time, or when no wave-by-wave generation occurs, the wave-by-wave current limit is restored to I1.
  • the clear loop intermediate variable module 32 is set to: when the PFC inductor current reference is detected in the program to be greater than a certain value I, the output of the current inner loop PI regulator, the integral variable is cleared, and the voltage outer loop PI is adjusted. The output of the device and the integral variable are cleared.
  • the device in the embodiment of the present invention corresponds to the method in the foregoing embodiment, and the device described in the above method is also used to explain the device of the present invention, and details are not described herein again.
  • the technical scheme of the invention not only can protect the Bus overvoltage and the inductor overcurrent in time under the premise of ensuring the steady state normal operation of the rectifier, but also can significantly reduce the electrical stress of the PFC device during the dynamic switching of the input and output, and improve the reliability of the rectifier power device. Sex. Therefore, the present invention has strong industrial applicability.

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Abstract

一种提高数字PFC电路可靠性的方法及装置，该方法包括总线过压保护策略、电感过流保护策略和降低电感电流策略，其中，总线过压保护策略采用二级保护方式，电感过流保护策略采用逐波限流保护，降低电感电流策略采用逐波时降低逐波限流点、电感电流参考大于某特定值时清零环路中间变量，该方法能够降低输入输出动态切换时器件的电应力。

Description

提高数字PFC电路可靠性的方法及装置 技术领域
本发明属于涉及交流/直流(AC/DC，Alternating Current/Direct Current)电源变换技术领域，尤其涉及一套提高数字功率因数校正(PFC，Power Factor Correction)电路可靠性的方法及装置。
背景技术
PFC电路在提高电网传输效率、降低电网谐波污染方面具有很大的作用。目前单相PFC控制，大多数的控制方案都是基于Boost变换器平均电流控制策略。
典型的Boost型数字PFC控制框图，如图1所示，整个系统由主电路和控制电路两部分组成。主电路由单相桥式整流器和直流/直流(DC/DC，Direct Current/Direct Current)Boost变换器组成。控制电路由运行控制算法程序的数字信号控制器(DSC，Digital Signal controller)和外围信号调理电路所组成。为了提高功率因数(PF，Power Factor)、减小总谐波失真(THD，Total Harmonic Distortion)，环路控制采用了双闭环PI控制算法，即由电流内环和电压外环共同控制。电流内环PI调节器Gcea调节电感电流，使之波形上跟随输入电压的变化。电压外环PI调节器Gvea输出经过一个乘法器和主电路输入整流电压相乘，乘积作为电流控制环节的基准信号Iref，通过调节基准信号Iref的值，使得PFC侧的输出电压——输出Bus电压V0保持恒定。
与传统的模拟控制方式相比，PFC数字控制的方式具有灵活、可移植性强、节省硬件电路空间和成本等很多优点。但同时数字控制方式亦有延迟控制的固有缺陷，即在PFC数字控制系统中，由于模拟/数字(AD，Analog/Digital)采样时间以及运算时间，使得当前周期计算所得到的脉宽只能在下个周期才能使用，因此PFC在控制上要延迟一个开关周期。在输入电压和输出负载稳定不变的稳态情况下，数字和模拟控制的效果相差不大，通过对环路控制算法进行适当的优化，数字控制方式甚至可能得到更好的PF和THD指标。但当输入电压和输出负载出现与输入电压工频周期差不多的连续的动 态变化时，由于数字PFC的延迟控制特性，使得它不能像模拟控制那样对动态变化作出快速的反应，从而会使环路失控，电感电流和Bus电压超出正常值，严重时还会导致炸机故障。因此，必须设计一套合理的控制方法和保护方式，在不影响稳态正常运行的前提下，尽可能降低PFC功率器件的电应力，提高PFC电路的可靠性。
发明内容
本发明的目的在于使得在Bus过压和PFC电感过流时能够及时进行保护，并在输入输出动态切换时显著降低Bus电压和电感电流应力，以提高PFC电路可靠性。
为解决上述技术问题，采用如下技术方案：
一种提高数字PFC电路可靠性的方法，包括执行Bus过压保护策略，所述执行Bus过压保护策略的步骤包括以下步骤：
设定三个阈值V1、V2及V3，阈值V1为Bus电容允许的最高工作电压，阈值V2高于稳态工作时Bus实际电压的最大值，阈值V3为Bus电压参考值，其中，V1＞V2＞V3；
当Bus电压大于所述阈值V1时，判定为高压防护状态，断开输入电压，初始化缓启动参数，关闭PFC驱动，整流器设置为停止状态；
当Bus电压大于阈值V2但小于所述阈值V1时，判定为Bus过压关驱动状态，关闭PFC驱动；
在Bus过压关驱动状态下，判断Bus电压与所述阈值V3的关系，当Bus电压小于所述阈值V3时，恢复PFC驱动，并清零电压环积分变量；若Bus电压大于阈值V3，维持Bus过压关驱动状态不变。
可选地，该方法还包括执行PFC电感过流保护策略，所述执行PFC电感过流保护策略的步骤包括以下步骤：
在各个开关周期中，比较模块比较采样得到的PFC电感电流与设定的逐波限流点；
当PFC电感电流值超出所述逐波限流点时，所述比较模块输出高电平信号并送到脉宽调变PWM模块的TZ触发单元，对PWM波进行封锁，封锁状态维持到当前开关周期结束；
当PFC电感电流值比逐波限流点低时，所述比较模块输出低电平信号，PWM正常输出，驱动信号恢复。
可选地，该方法还包括执行降低PFC电感电流策略的步骤，执行所述降低PFC电感电流策略的步骤包括执行在逐波时降低逐波限流点策略的步骤，所述执行降低逐波限流点策略的步骤包括以下步骤：
将逐波限流点在正常运行时保持为默认的逐波限流点I1；
检测到逐波发生时，将所述逐波限流点降低至为逐波限流点I2，同时启动定时器，其中，I1>I2，且I2的大小需保证电感电流不会剧烈逐波；
所述定时器的周期T到时后，或者无逐波产生时，将所述逐波限流点恢复为所述I1。
可选地，所述执行降低PFC电感电流策略的步骤还包括执行清零环路中间变量策略的步骤，所述执行清零环路中间变量策略的步骤包括以下步骤：
当程序中检测到PFC电感电流参考大于特定值I时，将电流内环PI调节器的输出和积分变量清零，并将电压外环PI调节器的输出和积分变量清零；其中，特定值I高于稳态正常运行时的值，且能起到降低电感电流的作用。
一种提高数字PFC电路可靠性的装置，包括Bus过压保护模块，所述Bus过压保护模块包括阈值设定模块、BUS电压一级保护模块和BUS电压二级保护模块，其中：
所述阈值设定模块设置成：设定三个阈值V1、V2及V3，所述阈值V1为Bus电容允许的最高工作电压，所述阈值V2高于稳态工作时Bus实际电压的最大值，所述阈值V3为Bus电压参考值，其中，V1＞V2＞V3；
所述BUS电压一级保护模块设置成：当Bus电压大于所述阈值V1时，判定为高压防护状态，断开输入电压，初始化缓启动参数，关闭PFC驱动，将整流器设置为停止状态；
所述BUS电压二级保护模块设置成：当Bus电压大于所述阈值V2但小于所述阈值V1时，判定为Bus过压关驱动状态，关闭PFC驱动；在Bus过压关驱动状态下，判断Bus电压与所述阈值V3的关系，当Bus电压小于所述阈值V3时，恢复PFC驱动，并清零电压环积分变量；当Bus电压大于所述阈值V3，维持Bus过压关驱动状态不变。
可选地，该装置还包括PFC电感过流保护模块，所述PFC电感过流保护模块包括电感电流比较模块、封锁模块和恢复模块，其中：
所述电感电流比较模块设置成：在各个开关周期中，比较采样得到的PFC电感电流与设定的逐波限流点；
所述封锁模块设置成：当PFC电感电流值超出所述逐波限流点时，使得所述电感电流比较模块输出高电平信号并送到脉宽调变PWM模块的TZ触发单元，所述封锁模块对PWM波进行封锁，封锁状态维持到当前开关周期结束；
所述恢复模块设置成：当PFC电感电流值比所述逐波限流点低时，使得所述电感电流比较模块输出低电平信号，所述恢复模块使得PWM正常输出，驱动信号恢复。
可选地，该装置还包括降低PFC电感电流模块，所述降低PFC电感电流模块包括降低逐波限流点模块，所述降低逐波限流点模块设置成：
将设定的逐波限流点在正常运行时保持为默认的逐波限流点I1；
检测到逐波发生时，将所述逐波限流点降低至为逐波限流点I2，同时启动定时器，其中，I1>I2，且I2的大小需保证电感电流不会剧烈逐波；
所述定时器的周期T到时以后，或者无逐波产生时，将所述逐波限流点恢复为所述I1。
可选地，所述降低PFC电感电流模块还包括清零环路中间变量模块，
所述清零环路中间变量模块设置成：当程序中检测到PFC电感电流参考大于特定值I时，将电流内环PI调节器的输出和积分变量清零，并将电压外环PI调节器的输出和积分变量清零；其中，特定值I高于稳态正常运行时的值，且能起到降低电感电流的作用。
可选地，该装置位于数字控制器DSC中。
一种计算机程序，包括程序指令，当该程序指令被数字控制器DSC执行时，使得该数字控制器DSC可执行上述的提高数字PFC电路可靠性的方法。
一种载有上述计算机程序的载体。
本发明克服了相关技术的不足，公开一种提高数字PFC电路可靠性的方法及装置，利用DSC进行数字控制，AC/DC部分拓扑结构为PFC变换器的结构；其中，本发明方法包括Bus过压保护策略、PFC电感过流保护策略和降低PFC电感电流策略。其中，Bus过压保护策略采用二级保护方式，PFC电感过流保护策略采用逐波限流保护的策略，降低PFC电感电流策略采用逐波时降低逐波限流点、电感电流参考大于某特定值时清零环路中间变量的策略。本发明的装置与方法相对应。
与相关技术的不足相比，本发明技术方案所具有的有益效果是：在保证整流器稳态正常运行的前提下，不仅能够对Bus过压和电感过流及时进行保护，还能够显著降低输入输出动态切换时PFC器件的电应力，提高整流器功率器件的可靠性。
附图概述
图1是相关技术中典型的Boost型数字PFC控制框图；
图2是本发明实施例的Bus过压保护策略的步骤流程图；
图3是本发明实施例的PFC电感过流保护策略的步骤流程图；
图4是本发明实施例的PFC电感过流保护策略中PFC电感电流逐波限流保护示意图；
图5是本发明实施例的降低PFC电感电流策略中逐波时降低逐波限流点策略的步骤流程图；
图6是本发明实施例的降低PFC电感电流策略中清零环路中间变量策略的步骤流程图；
图7是本发明实施例的提高数字PFC电路可靠性的装置的结构示意图；
图8是本发明实施例的Bus过压保护模块与PFC电路的连接关系示意图；
图9是本发明实施例的Bus过压保护模块的结构示意图；
图10是本发明实施例的PFC电感过流保护模块与PFC电路的连接关系示意图；
图11是本发明实施例的逐波限流保护模块的结构示意图；
图12是本发明实施例的降低PFC电感电流模块的结构示意图。
本发明的较佳实施方式
以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
以用于通信领域的开关电源为例，由于现场应用环境复杂多变，输入电压和输出负载有时候可能是动态变化的。如前所述，由于数字PFC的延迟控制特性，在动态时会导致很大的PFC电感电流和Bus电压。
本发明实施例的公开了一种提高数字PFC电路可靠性的方法，包括Bus过压保护策略。在该Bus过压保护策略中，采用二级保护方式对Bus过压进行保护，主功率电路的Bus电压信号经过Bus电压采样电路后送入DSC进行处理，DSC的ADC将模拟的Bus电压采样信号转化为数字信号，通过该数字信号Bus电压与预设阈值进行比较，并根据比较结果分别采取不同的处理措施。其中，Bus过压保护策略，参照图2所示，具体过程为：
步骤11、设定三个阈值V1、V2及V3，阈值V1为PFC侧输出电容，即Bus电容允许的最高工作电压，阈值V2比稳态工作时Bus实际电压略高，阈值V3为Bus电压参考值，其中，V1＞V2＞V3；
可选地，阈值V2需大于稳态工作时Bus实际电压的最大值，但不能大于V1。
可选地，阈值V2比稳态工作时Bus实际电压高40V。
在步骤11中，V1为Bus电容允许的最高工作电压，Bus电容超过该电压工作热积累会很快而炸掉；V2设置的原则是必须保证比稳态工作时Bus实际电压略高；V3的设置比较灵活，一般取Bus电压参考值，目的是一旦Bus电压恢复到Bus电压参考值附近时即判断工作正常，恢复PFC驱动。此处3个阈值及Bus过压保护策略，均由DSC中的软件代码实现。
步骤12、判断Bus电压与阈值V1和V2的关系；若Bus电压大于阈值V1，执行步骤13；若Bus电压大于阈值V2但小于阈值V1时，执行步骤14；
步骤13、判定为高压防护状态，断开输入电压，初始化缓启动参数，关闭PFC驱动，整流器设置为停止状态；
在步骤13中，当检测到Bus电压Vbus大于阈值V1时，判定为高压防护状态，启动第一级保护。在第一级保护里，断开输入电压，初始化缓启动参数，关闭PFC驱动，整流器设置为停止状态。
步骤14、判定为Bus过压关驱动状态，关闭PFC驱动；
步骤15、在Bus过压关驱动状态下，判断Bus电压与V3的关系；若Bus电压小于阈值V3，执行步骤16；若Bus电压大于阈值V3，执行步骤17。
步骤16、恢复PFC驱动，并清零电压环积分变量。
步骤17、维持Bus过压关驱动状态不变。
在本发明实施例中，步骤13为Bus电压的第一级保护，步骤14～16为Bus电压的第二级保护。对Bus电压采用两级过压保护的原因为：在整流器实际运行中，输入电压和输出负载不一定是一直稳定的，当它们波动时Bus电压也会上下波动。当Bus电压超出参考电压时，不宜采用单一策略进行保护，因为若直接采用第一级保护，整流器会停止关机，虽然比较可靠，但会 影响稳态正常工作；若采用第二级保护，仅仅关闭PFC驱动，虽然整流器可带载运行，但是若输入电压很大，Bus电压依然会继续升高而导致炸机。因此，需要根据Bus过压的严重程度制定分级保护策略。
在实际应用过程中，本发明实施例的数字控制器不限制于采用DSC，其它如单片机或者ARM等也可以实施；PFC变换器的拓扑结构并不限于单相Boost型PFC变换器，其它拓扑结构如Buck型PFC、图腾柱PFC等也可以实施。
在进一步的实施过程中，为了进一步公开数字PFC电路可靠性，在本发明实施例中，所述提高数字PFC电路可靠性的方法还包括PFC电感过流保护策略，其中，主功率电路的PFC电感电流信号经过PFC电感电流采样电路后送入DSC，DSC将PFC电感电流采样信号进行过流保护，逐波限流保护模块利用DSC内部ADC的比较模块实现，参照图3和图4所示，PFC电感过流保护策略的执行过程具体包括以下步骤：
步骤21、判断当前开关周期中，采样得到的PFC电感电流是否大于设定的逐波限流点，若是，执行步骤22；
其中，该开关周期是指PFC电路MOS管的开通关断周期。
逐波限流点是指每个开关周期对PFC电感电流大小进行限制的阈值点，对于本领域技术人员来说是公知常识，在此不再赘述。
在步骤21中，利用DSC内部的比较模块将采样得到的PFC电感电流与设定的逐波限流点进行比较。
步骤22、比较模块输出高电平信号并送到DSC内部的脉宽调变PWM模块的TZ触发单元，对PWM波进行封锁，封锁状态维持到当前开关周期结束；
在步骤22中，当超出限流值时，比较模块输出高电平信号，这个高电平信号会直接送到脉宽调变(PWM，Pulse Width Modulation)模块的TZ(Trip Zone)触发单元，触发一个事件对PWM波进行封锁，过程如图4中虚线部分所示，封锁状态维持到当前开关周期结束。
步骤23、判断下一开关周期中，采样得到的PFC电感电流是否大于设定 的逐波限流点；若是，继续执行步骤22，若否，执行步骤24；
步骤24、比较模块输出低电平信号，PWM正常输出，驱动信号恢复。
在本发明实施例图4中，为了对逐波限流过程描述清楚，假设电感电流是线性变化的，实际情况下电感电流是曲线变化形式。
在进一步的实施过程中，由于动态时不考察PF和THD等指标，在本发明实施例中，所述提高数字PFC电路可靠性的方法还包括执行降低PFC电感电流策略的步骤，所述执行降低PFC电感电流策略的步骤包括执行在逐波时降低逐波限流点策略的步骤，参照图5所示，所述执行降低逐波限流点策略的步骤包括以下步骤：
步骤31、将逐波限流点在正常运行时保持为默认的逐波限流点I1；
步骤32、检测到逐波发生时，将逐波限流点降低至为I2，同时启动定时器，其中，I1>I2，且I2的大小需保证电感电流不会剧烈逐波；
步骤33、定时器周期T时间以后，或者无逐波产生时，将逐波限流点恢复为I1。
在本发明实施例中，逐波时降低逐波限流点策略为纯软件策略，即当前级程序检测到逐波发生时，将逐波限流点降低并维持一定的时间，当维持的时间结束或者没有逐波发生时，逐波限流点恢复为默认值。
在具体应用过程中，默认的逐波限流点I1必须设置为合适的大小，若设置的过低，则在稳态运行时也会触发逐波限流保护策略，这将影响稳态的正常运行；若设置的过高，则对PFC电感电流起不到保护作用。I2的设置较灵活，需要比I1略低，同时需保证电感电流不会剧烈逐波。
采用逐波时降低逐波限流点的策略的原因为：稳态时为保证不逐波，默认的逐波限流点I1设置得相对较高；在动态时，为减小PFC电感电流，允许适度逐波，因此可在检测到逐波后，立即适度降低逐波点，从而降低动态时的PFC电感电流。
在进一步的实施过程中，参照图1所示，电感电流参考信号Iref的计算 公式为：Iref＝KmA·B/C2；其中A为输入电压瞬时采样值，B为电压环输出，C为输入电压有效值。在输入输出均比较稳定的情况下，Iref始终处于一个比较合适的范围，从而能够保证电感电流Iin和Bus电压Vo均维持稳定；但当输入电压和输出负载出现与输入电压工频周期时间差不多的连续的动态变化时，比如输入电压高低压波动、输入电压为油机发电、后级输出负载为空-满载-限流切换等，Iref会变得很大，从而会导致很大的PFC电感电流。为从根本上减小动态时PFC电感电流应力，在本发明实施例中，所述PFC电感电流策略还包括清零环路中间变量策略，参照图6所示，所述清零环路中间变量策略包括以下步骤：
S41、当程序中检测到PFC电感电流参考Iref大于某个特定值I时，将电流内环PI调节器Gcea的输出Uca、积分变量清零；
S42、将电压外环PI调节器Gvea的输出Uva和积分变量同时清零。
在本发明实施例中，清零环路中间变量策略为纯软件策略，即当前级程序检测到电感电流参考值大于某个特定值时，将电压环和电流环PI算法的中间变量清零。
在步骤41、42中，I的设置不能太小，以不影响稳态正常运行为准；但也不能太大，否则起不到降低电感电流的作用，即特定值I高于稳态正常运行时的值，且能起到降低电感电流的作用。此策略的精妙之处在于对PI控制环路的积分变量也清零，这样在电感电流参考Iref小于I恢复控制环路输出时，此时控制环路的输出只与本时刻的输入有关，与之前的输出无关，这大大减小了恢复时刻的电感电流应力。
本发明进一步公开了一种提高数字PFC电路可靠性的装置，参照图7所示，包括Bus过压保护模块1、逐波限流保护模块2以及降低PFC电感电流模块3。
对于Bus过压保护模块1，参照图8所示，主功率电路的Bus电压信号经过Bus电压采样电路后送入DSC进行处理，DSC的ADC将模拟的Bus电压采样信号转化为数字信号供Bus过压保护模块1使用。所述Bus过压保护 模块1，参照图9所示，包括：
阈值设定模块11设置成：设定三个阈值V1、V2及V3，阈值V1为Bus电容允许的最高工作电压，阈值V2比稳态工作时Bus实际电压略高，阈值V3为Bus电压参考值，其中，V1＞V2＞V3；
BUS电压一级保护模块12设置成：当Bus电压大于阈值V1时，判定为高压防护状态，断开输入电压，初始化缓启动参数，关闭PFC驱动，整流器设置为停止状态；
BUS电压二级保护模块13设置成：当Bus电压在阈值V2与阈值V1之间时，判定为Bus过压关驱动状态，关闭PFC驱动；在Bus过压关驱动状态，当Bus电压小于阈值V3时，恢复PFC驱动，并清零电压环积分变量。
对于逐波限流保护模块2，参照图10所示，主功率电路的PFC电感电流信号经过PFC电感电流采样电路后送入DSC，DSC将PFC电感电流采样信号送入逐波限流保护模块2处理。逐波限流保护模块2利用DSC内部ADC的比较模块实现，该逐波限流保护模块2，参照图11所示，包括：
电感电流比较模块21设置成：比较采样得到的PFC电感电流与设定的逐波限流点；
封锁模块22设置成：当PFC电感电流值超出逐波限流点时，使得电感电流比较模块21输出高电平信号并送到脉宽调变模块的TZ触发单元，对PWM波进行封锁，封锁状态维持到当前开关周期结束；
恢复模块23设置成：当PFC电感电流值比逐波限流点低时，使得所述电感电流比较模块21输出低电平信号，PWM正常输出，驱动信号恢复。
对于降低PFC电感电流模块3，参照图12所示，所述降低PFC电感电流模块包括逐波时降低逐波限流点模块31以及清零环路中间变量模块32；其中，
降低逐波限流点模块31设置成：将逐波限流点在正常运行时保持为默认的逐波限流点I1；检测到逐波发生时，将逐波限流点降低至为I2，同时启动定时器，其中，I1>I2；T时间以后，或者无逐波产生时，将逐波限流点恢复为I1。
清零环路中间变量模块32设置成：当程序中检测到PFC电感电流参考大于某个特定值I时，将电流内环PI调节器的输出、积分变量清零，并将电压外环PI调节器的输出、积分变量清零。
本发明实施例中所述装置与上述实施例中所述方法相对应，以上述方法记载内容同样解释本发明所述装置，在此不再赘述。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
工业实用性
本发明技术方案在保证整流器稳态正常运行的前提下，不仅能够对Bus过压和电感过流及时进行保护，还能够显著降低输入输出动态切换时PFC器件的电应力，提高整流器功率器件的可靠性。因此本发明具有很强的工业实用性。

Claims (11)

  1. 一种提高数字PFC电路可靠性的方法，包括执行Bus过压保护策略，所述执行Bus过压保护策略的步骤包括以下步骤：
    设定三个阈值V1、V2及V3，阈值V1为Bus电容允许的最高工作电压，阈值V2高于稳态工作时Bus实际电压的最大值，阈值V3为Bus电压参考值，其中，V1＞V2＞V3；
    当Bus电压大于所述阈值V1时，判定为高压防护状态，断开输入电压，初始化缓启动参数，关闭PFC驱动，整流器设置为停止状态；
    当Bus电压大于阈值V2但小于所述阈值V1时，判定为Bus过压关驱动状态，关闭PFC驱动；
    在Bus过压关驱动状态下，判断Bus电压与所述阈值V3的关系，当Bus电压小于所述阈值V3时，恢复PFC驱动，并清零电压环积分变量；若Bus电压大于阈值V3，维持Bus过压关驱动状态不变。
  2. 如权利要求1所述的提高数字PFC电路可靠性的方法，该方法还包括执行PFC电感过流保护策略，所述执行PFC电感过流保护策略的步骤包括以下步骤：
    在各个开关周期中，比较模块比较采样得到的PFC电感电流与设定的逐波限流点；
    当PFC电感电流值超出所述逐波限流点时，所述比较模块输出高电平信号并送到脉宽调变PWM模块的TZ触发单元，对PWM波进行封锁，封锁状态维持到当前开关周期结束；
    当PFC电感电流值比逐波限流点低时，所述比较模块输出低电平信号，PWM正常输出，驱动信号恢复。
  3. 如权利要求1所述的提高数字PFC电路可靠性的方法，该方法还包括执行降低PFC电感电流策略的步骤，执行所述降低PFC电感电流策略的步 骤包括执行在逐波时降低逐波限流点策略的步骤，所述执行降低逐波限流点策略的步骤包括以下步骤：
    将逐波限流点在正常运行时保持为默认的逐波限流点I1；
    检测到逐波发生时，将所述逐波限流点降低至为逐波限流点I2，同时启动定时器，其中，I1>I2，且I2的大小需保证电感电流不会剧烈逐波；
    所述定时器的周期T到时后，或者无逐波产生时，将所述逐波限流点恢复为所述I1。
  4. 如权利要求3所述的提高数字PFC电路可靠性的方法，其中，所述执行降低PFC电感电流策略的步骤还包括执行清零环路中间变量策略的步骤，所述执行清零环路中间变量策略的步骤包括以下步骤：
    当程序中检测到PFC电感电流参考大于特定值I时，将电流内环PI调节器的输出和积分变量清零，并将电压外环PI调节器的输出和积分变量清零；其中，特定值I高于稳态正常运行时的值，且能起到降低电感电流的作用。
  5. 一种提高数字PFC电路可靠性的装置，包括Bus过压保护模块，所述Bus过压保护模块包括阈值设定模块、BUS电压一级保护模块和BUS电压二级保护模块，其中：
    所述阈值设定模块设置成：设定三个阈值V1、V2及V3，所述阈值V1为Bus电容允许的最高工作电压，所述阈值V2高于稳态工作时Bus实际电压的最大值，所述阈值V3为Bus电压参考值，其中，V1＞V2＞V3；
    所述BUS电压一级保护模块设置成：当Bus电压大于所述阈值V1时，判定为高压防护状态，断开输入电压，初始化缓启动参数，关闭PFC驱动，将整流器设置为停止状态；
    所述BUS电压二级保护模块设置成：当Bus电压大于所述阈值V2但小于所述阈值V1时，判定为Bus过压关驱动状态，关闭PFC驱动；在Bus过压关驱动状态下，判断Bus电压与所述阈值V3的关系，当Bus电压小于所述阈值V3时，恢复PFC驱动，并清零电压环积分变量；当Bus电压大于所 述阈值V3，维持Bus过压关驱动状态不变。
  6. 如权利要求5所述的提高数字PFC电路可靠性的装置，该装置还包括PFC电感过流保护模块，所述PFC电感过流保护模块包括电感电流比较模块、封锁模块和恢复模块，其中：
    所述电感电流比较模块设置成：在各个开关周期中，比较采样得到的PFC电感电流与设定的逐波限流点；
    所述封锁模块设置成：当PFC电感电流值超出所述逐波限流点时，使得所述电感电流比较模块输出高电平信号并送到脉宽调变PWM模块的TZ触发单元，所述封锁模块对PWM波进行封锁，封锁状态维持到当前开关周期结束；
    所述恢复模块设置成：当PFC电感电流值比所述逐波限流点低时，使得所述电感电流比较模块输出低电平信号，所述恢复模块使得PWM正常输出，驱动信号恢复。
  7. 如权利要求5所述的提高数字PFC电路可靠性的装置，该装置还包括降低PFC电感电流模块，所述降低PFC电感电流模块包括降低逐波限流点模块，所述降低逐波限流点模块设置成：
    将设定的逐波限流点在正常运行时保持为默认的逐波限流点I1；
    检测到逐波发生时，将所述逐波限流点降低至为逐波限流点I2，同时启动定时器，其中，I1>I2，且I2的大小需保证电感电流不会剧烈逐波；
    所述定时器的周期T到时以后，或者无逐波产生时，将所述逐波限流点恢复为所述I1。
  8. 如权利要求7所述的提高数字PFC电路可靠性的装置，其中，所述降低PFC电感电流模块还包括清零环路中间变量模块，
    所述清零环路中间变量模块设置成：当程序中检测到PFC电感电流参考 大于特定值I时，将电流内环PI调节器的输出和积分变量清零，并将电压外环PI调节器的输出和积分变量清零；其中，特定值I高于稳态正常运行时的值，且能起到降低电感电流的作用。
  9. 如权利要求5-8中任一项所述的提高数字PFC电路可靠性的装置，该装置位于数字控制器DSC中。
  10. 一种计算机程序，包括程序指令，当该程序指令被数字控制器DSC执行时，使得该数字控制器DSC可执行权利要求1-4中任一项所述的提高数字PFC电路可靠性的方法。
  11. 一种载有权利要求10所述计算机程序的载体。
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CN113394963B (zh) * 2020-03-11 2023-11-10 上海海立（集团）股份有限公司 一种pfc电路检测方法和装置以及可读存储介质
CN114006524A (zh) * 2021-11-05 2022-02-01 上海儒竞智控技术有限公司 实现抑制过流的方法、介质、控制电路及Boost型PFC控制系统

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