WO2015114790A1

WO2015114790A1 - Gate drive circuit and inverter system having gate drive circuit mounted therein

Info

Publication number: WO2015114790A1
Application number: PCT/JP2014/052199
Authority: WO
Inventors: 歩畑中; 石川　勝美; 徹増田; 景山　寛; 和俊小川; 森　和久
Original assignee: 株式会社日立製作所
Priority date: 2014-01-31
Filing date: 2014-01-31
Publication date: 2015-08-06

Abstract

For the purpose of shortening a dead time in a semiconductor element gate drive circuit and an inverter system having the gate drive circuit mounted therein, a gate drive circuit (100U) of the present invention is provided with: a PWM drive signal generating circuit (110U); a gate resistor (120U); a differential amplifier circuit (130U) for performing differential amplification of a voltage applied to the gate resistor (120U); an RS-type flip-flop circuit (140U); a differential amplifier (150U) for performing differential amplification of an output voltage of the RS-type flip-flop circuit (140U); and an MOSFET (160U) that turns on/off by means of signals of the differential amplifier (150U). In the cases where a voltage applied to the gate resistor (120U) is detected during a period when the PWM signal is in the off-state, the MOSFET (160U) is turned on, and an upper arm MOSFET (SiC-MOSFET) (S1U) using SiC is driven to turn on.

Description

Gate drive circuit and inverter system equipped with the same

The present invention relates to a gate drive circuit for driving a semiconductor gate of a switching element using a wide band gap semiconductor, and an inverter system equipped with the gate drive circuit.

Conventionally, a gate-on signal based on the gate signal (gate voltage / gate current) transmitted from the opposite arm by a level-up circuit as a technique to mitigate conduction loss and deterioration of energization of semiconductor elements using wide band gap semiconductors by reducing dead time There is a configuration in which the dead time is shortened by applying to the gate of the element (for example, see Patent Document 1).

JP 2002-272131 A

In a gate drive circuit of a semiconductor element, when driving a power conversion device such as an inverter, an ON / OFF complementary signal is applied between the gate and source of a switching element (IGBT, etc.) of an upper and lower arm of a certain phase. Is driving. In order to prevent a short circuit between the upper and lower arms, a period (dead time) in which the gate signals of the upper and lower arms are turned off is provided at the timing when the complementary signals are switched. Inverters that convert large power generally have a fixed dead time of about 3 to 5 [μs] so that the upper and lower arms are not short-circuited in consideration of variations in gate drive transmission delay.

When Si-IGBT is used as the switching element, a diode is connected in reverse parallel to the IGBT in order to energize during the dead time period and rectification period. In order to reduce the size of reactors and capacitors used in inverters, it is effective to increase the switching frequency fsw of the inverter, but in the case of a fixed dead time, the dead time period occupies one cycle as fsw increases As the ratio increases, controllability decreases. For this reason, reduction of dead time becomes a problem.

On the other hand, although the operating voltage range is low, when an Si-MOSFET is used, an antiparallel PN diode is built in the MOSFET, so there is no need to connect an additional antiparallel diode. Furthermore, since it is a unipolar element, current can be passed in both directions between the drain and the source when the gate is ON. In other words, while the gate ON period enables low-loss rectification using the low on-resistance of the Si-MOSFET channel, the dead time period energizes the built-in PN diode, which has a larger voltage drop than the channel on-resistance. Become. In other words, in the case of Si-MOSFETs, in addition to improving controllability, reducing dead time is an issue for reducing loss.

In the case of a semiconductor element using a wide band gap semiconductor, for example, SiC-MOSFET, the device breakdown voltage is equivalent to that of Si-IGBT. Although the basic operating mechanism is the same as that of Si-MOSFET, it has a high forward voltage due to the SiC band gap, so there is a large conduction loss during the dead time period, and there is a concern about the deterioration of energization due to SiC crystal defects. There is. Since this problem is caused by energization of the SiC-PN diode, it can be alleviated by shortening the dead time.

One way to solve this problem is to reduce the dead time by applying a gate-on signal to the gate of the device based on the gate signal (gate voltage / gate current) transmitted from the opposing arm by the level-up circuit. For example, there is a configuration described in Patent Document 1. However, with the use of the level-up circuit, signal transmission delay occurs, so there are problems that there is a limit to shortening the dead time and that the circuit scale and cost increase.

In order to solve these problems, an object of the present invention is to provide a semiconductor gate driving circuit capable of reducing dead time by using information of its own arm without using a level-up circuit and an inverter system equipped with the semiconductor gate driving circuit.

In order to solve the above problems, the gate drive circuit of the present invention is, for example, a gate drive circuit having a drive signal output unit for driving the first switching element, and the gate drive circuit includes the drive A drive signal detection unit for detecting a signal, a gate current detection unit for detecting an energization current to the gate terminal of the first switching element, and the detection information of the drive signal detection unit and the gate current detection unit A gate drive control unit that applies an on / off drive signal to the first switching element, and the gate drive control unit is turned on by the gate current detection unit during a period when the drive signal detection unit detects an off state. When the side gate current is detected, the MOSFET is driven to turn on.

The inverter system of the present invention is an inverter system equipped with the gate drive circuit of the present invention including the gate drive circuit described above.

According to the present invention, the dead time of a switching element using a wide band gap semiconductor can be shortened, and controllability can be improved.

It is a figure which shows the semiconductor drive circuit (gate drive circuit) which concerns on Example 1 of this invention. It is a figure which shows the electric current and voltage waveform in Example 1 of this invention. It is a figure which shows the semiconductor drive circuit (gate drive circuit) which concerns on Example 2 of this invention. It is a figure which shows the electric current and voltage waveform in Example 3 of this invention. It is a figure which shows the mounting structure of the semiconductor drive circuit (gate drive circuit) which concerns on Example 4 of this invention.

The present invention does not require a level-up circuit for transmitting information between the upper and lower arms, and can reduce the dead time. Therefore, it is possible to reduce the size and cost and minimize the transmission delay. In addition, the loss during the dead time period when using the MOSFET can be reduced. Moreover, the energization time of the SiC-MOSFET to the PN diode can be reduced, and deterioration of the energization of the PN diode can be reduced. In addition, when using the SiC-MOSFET, it is possible to delete the SiC-SBD connected in antiparallel. Moreover, it is possible to prevent erroneous detection due to gate current conduction due to noise. Further, even when the gate current cannot be detected, it is possible to prevent an excessive increase in loss and deterioration of energization of the body diode. In addition, resonance with the gate wiring as a loop and external noise entering the wiring can be removed, and the wiring impedance can be minimized, so that the gate can be driven at high speed.

In the gate drive circuit of the present invention, the first switching element may be composed of a MOSFET, a junction FET, or an IGBT using a wide band gap semiconductor such as silicon carbide, gallium nitride, or diamond.

Hereinafter, some examples of embodiments of the gate drive circuit of the present invention and an inverter system equipped with the gate drive circuit will be described in detail as examples with reference to the drawings.

Hereinafter, a first embodiment of a semiconductor drive circuit according to the present invention will be described in detail with reference to FIGS. 1 and 2 with reference to the drawings.

FIG. 1 is a circuit configuration diagram of the semiconductor drive circuit of the first embodiment, and shows a portion related to a switching element for one phase (upper and lower arms connected in series).

The semiconductor drive circuit includes a MOSFET (SiC-MOSFET) S1U using SiC in the upper arm, a MOSFET (SiC-MOSFET) S1L using SiC in the lower arm, a gate drive circuit 100U in the upper arm, and a lower arm. A gate drive circuit 100L is provided.

The upper arm gate drive circuit 100U includes a PWM drive signal generation circuit 110U, a gate resistor 120U, a differential amplifier circuit 130U for differentially amplifying the voltage applied to the gate resistor 120U, and an RS flip-flop circuit 140U. , A differential amplifier 150U for differentially amplifying the output voltage of 140U, and a MOSFET U160U that is turned on / off by a signal of 150U.

The PWM drive signal generation circuit 110U includes a voltage source 111U, a PWM signal source 112U, a resistor 113U, and

transistors

114U and 115U that operate in a complementary manner.
The lower arm gate drive circuit 100L has the same configuration as the upper arm gate drive circuit 100U.

Hereinafter, the operation in the first embodiment is shown in FIG. 2 by taking as an example the timing at which the upper arm S1U changes from off to on and the lower arm S1L changes from on to off. Drain current Id_U, Id_L, drain-source voltage Vds_U, Vds_L, gate voltage Vgs_U, Vgs_L, gate current Ig_U, Ig_L and proportional gate resistance voltage Vrg_U, Vrg_L, PWM signal Vpwm_U, Vpwm_L The description will be made with reference to a timing chart of the S terminal, a timing chart of the R terminal, a timing chart of the Q terminal, a 160U drive signal Vsw_U, and an on / off timing chart of Vsw_L of the RS flip-flop circuit.

At time t0 in FIG. 2, the upper arm PWM signal Vpwm_U is off, the lower arm PWM signal Vpwm_L is on, the upper arm gate voltage Vgs_U is off, the lower arm gate voltage Vgs_L is on, and S1L In this state, the energization current is increased.

At time t1, the lower arm PWM signal Vpwm_L is turned off, 115L is turned on, the off-side current flows to the gate current Ig_L, the lower arm gate voltage Vgs_L is turned off, S1L is voltage shared, and Vds_L becomes Vcc On the other hand, the Vds_U of S1U starts decreasing from Vcc toward 0 [V].

At time t2, when Vds_U reaches 0 [V] and Vds_L reaches Vcc, the body diode of the upper arm S1U is energized, the current Id_U increases, and the lower arm current Id_L starts decreasing. This timing is the dead time start.

At time t3, Id_L becomes 0 [A]. Since the discharge current flows through the gate-drain capacitance Cgd when Vds_U decreases from Vcc toward 0 [V], the on-side current is supplied to Ig_U while the pwm signal Vpwm_U is in the off state. Since the gate drain capacitance becomes maximum when Vds_U is near 0 [V], Ig_U becomes the maximum value at this timing. Ig_U is detected by the voltage drop across the gate resistor, differentially amplified by 130U, and an ON signal is applied to S_U at the set terminal of 140U. Since the signal R_U at the reset terminal is in the off state, the 140U Q output is in the on state.

At time t4, the Q output 140U is differentially amplified and applied to the 160U gate as a Vsw_U on signal. 160U is turned on, gate voltage 111U is applied to S1U, Ig_U is energized in the on direction, and Vgs_U is turned on. Here, since S1U is turned on, the current that has been applied to the body diode is applied to the channel side of S1U. This timing is the dead time completion.

At time t5, the upper arm pwm signal Vpwm_U is turned on. Accordingly, R_U is turned on and a reset signal is applied, so that the Q_U signal is turned off. Accordingly, at time t6, the 160U gate voltage Vsw_U is also turned off. On the other hand, when the Vpwm_U signal is turned on, 114U is turned on and 115U is turned off, and application of 111U is continued to S1U.

Conventionally, t1 to t5 are required as the dead time period, but according to the present embodiment, the dead time can be shortened to t1 to t4. SiC-MOSFET body diode loss can be reduced. Furthermore, since the energization time of the SiC-MOSFET to the PN diode can be reduced, it is possible to reduce the deterioration of energization to the PN diode.

In addition, when using SiC-MOSFET, SiC-SBD (Schottky Barrier Diode) is connected in anti-parallel, but this SiC-SBD can be deleted along with the above effect. It becomes.
In this embodiment, SiC-MOSFETs are exemplified as the switching elements S1U and S1L, but MOSFETs, IGBTs, JFETs, bipolar transistors using wide band gap semiconductors such as Si, gallium nitride, or diamond may be used. The same effect can be obtained.

Hereinafter, a second embodiment of the semiconductor drive circuit of the present invention will be described in detail with reference to FIG. FIG. 3 is a diagram corresponding to FIG. 1 in the first embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted, and different parts will be described below.

The

gate drive circuits

100U and 100L shown in FIG. 3 are different from the

gate drive circuits

100U and 100L shown in FIG. 1 in that

integrators

170U and 170L are provided. By adding the

integrators

170U and 170L of this embodiment, the integrated values of the gate currents Ig_U and Ig_L are output. When judging by the current waveform, false detection will occur when a large current (a short-time current having a peak value equal to or higher than Ig_U at time t2 in FIG. 2) is energized, but the integrator 170U is used. In this case, even if the crest value is high, the integral value is small if the current is a short time, so that erroneous detection can be prevented.

According to the present example (second embodiment), it is possible to prevent erroneous detection due to the gate current conduction due to noise.

Hereinafter, a third embodiment of the semiconductor drive circuit of the present invention will be described in detail with reference to the drawings with reference to FIG.

FIG. 4 is a view corresponding to FIG. 2 in the first embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, different parts will be described.

When the ON signal cannot be applied to the set terminal S_U because the gate current Ig_U at time t2 shown in FIG. 4 is small, the Q output terminal remains in the OFF state, and 160U is in the OFF state, reducing dead time. do not do. In this case, the dead time ends at time t5 when 114U is turned on and 115U is turned off by the Vpwm_U signal.

According to the present embodiment (third embodiment), even if the gate current cannot be detected, the dead time ends after a predetermined time has elapsed, thereby preventing excessive loss deterioration and deterioration of the body diode. Is possible.

Hereinafter, a fourth embodiment of the present invention will be described in detail with reference to the drawings with reference to FIG.

Fig. 5 shows the mounting structure of this circuit. Reference numeral 200 denotes a semiconductor module on which S1U and S1L are mounted. Terminal 201P connected to S1U drain side, terminal 201N connected to S1L source side, terminal 201AC connected to S1U source and S1L drain, S1U_S connected to source of S1U, S1U_G connected to gate terminal of S1U In the semiconductor module with S1L_S connected to the S1L gate terminal and S1L_G connected to the S1L gate terminal, the circuit part 200U is connected to the S1U_G and S1U_S terminals, and the circuit part 200L is connected to the S1L_G and S1L_S terminals. , 200U has an S1U_GO terminal and an S1U_SO terminal, and 200L has an S1L_GO terminal and an S1L_SO terminal. 200U is a circuit board incorporating the 120U, 130U, 140U, 150U and 160U of FIG. 1, and 200L is a circuit board incorporating the 120L, 130L, 140L, 150L and 160L of FIG.

According to the present example (fourth embodiment), since the gate circuit is mounted with the shortest wiring from the semiconductor module, resonance due to the gate wiring inductance that occurs when the gate wiring from the semiconductor module is long, or intrusion into the wiring. Since external noise can be removed and the wiring impedance can be minimized, the gate can be driven at high speed.

S1U Upper arm SiC-MOSFET (switching element)
S1L Lower arm SiC-MOSFET (switching element)
100U gate drive circuit for upper arm 100L gate drive circuit for lower arm

Claims

A gate drive circuit having a drive signal output unit for driving the first switching element,
The gate driving circuit includes:
A drive signal detector for detecting the drive signal;
A gate current detector for detecting an energization current to the gate terminal of the first switching element;
A gate drive control unit that applies an on / off drive signal to the first switching element based on detection information of the drive signal detection unit and the gate current detection unit;
The gate drive control unit drives the MOSFET to be turned on when the gate current detection unit detects an on-side gate current during a period in which the drive signal detection unit detects an off state. A gate drive circuit.
The gate drive circuit according to claim 1,
A gate driving circuit, wherein the first switching element is a MOSFET, a junction FET, or an IGBT using a wide band gap semiconductor such as silicon carbide, gallium nitride, or diamond.
The gate drive circuit according to claim 1 or 2,
The gate driving circuit is electrically connected to a gate terminal of the first switching element through a gate resistance element,
The drive signal detector includes a first differential amplifier that differentially amplifies the drive signal,
The gate current detection unit includes a second differential amplifier that differentially amplifies a voltage between terminals drawn from one terminal and the other terminal of the gate resistance element,
The gate drive control unit has an RS flip-flop circuit and a second switching element for applying a gate driving voltage to the gate terminal of the first switching element,
The output of the first differential amplifier circuit is connected to the set terminal of the RS flip-flop circuit, the output of the second differential amplifier circuit is connected to the reset terminal of the RS flip-flop circuit, and the RS flip-flop A third differential amplifier for differentially amplifying the output voltage of the circuit;
A gate driving circuit, wherein an output of the third differential amplifier is connected to an on / off control terminal of a second switching element for outputting a signal for driving the first switching element.
The gate drive circuit according to claim 3.
A gate driving circuit comprising an integrating circuit in series with the second differential amplifier circuit.
The gate drive circuit according to any one of claims 1 to 4,
When the gate current detection unit does not detect the on-side gate current, the drive signal outputs an on signal after a predetermined time has elapsed.
The gate drive circuit according to any one of claims 1 to 5,
A gate driving circuit comprising a Zener diode having an anode terminal connected to the source terminal between a gate terminal and a source terminal of the first switching element.
The gate drive circuit according to any one of claims 1 to 6,
The switching element is mounted on a semiconductor module,
A gate terminal for external connection of the semiconductor module and a source terminal for external connection;
At least one of the drive signal detection unit, the gate current detection unit, and the gate drive control unit is mounted on a printed circuit board directly connected to the external connection gate terminal and the external connection source terminal. A gate drive circuit characterized by that.
An inverter system equipped with a gate drive circuit having a drive signal output unit for driving the first switching element,
The gate driving circuit includes:
A drive signal detector for detecting the drive signal;
A gate current detector for detecting an energization current to the gate terminal of the first switching element;
A gate drive control unit that applies an on / off drive signal to the first switching element based on detection information of the drive signal detection unit and the gate current detection unit;
The gate drive control unit drives the MOSFET to be turned on when the gate current detection unit detects an on-side gate current during a period in which the drive signal detection unit detects an off state. Inverter system.
In the inverter system according to claim 8,
An inverter system, wherein the first switching element is a MOSFET, a junction FET, or an IGBT using a wide band gap semiconductor such as silicon carbide, gallium nitride, or diamond.
In the inverter system according to claim 8 or 9,
The gate driving circuit is electrically connected to a gate terminal of the first switching element through a gate resistance element,
The drive signal detector includes a first differential amplifier that differentially amplifies the drive signal,
The gate current detection unit includes a second differential amplifier that differentially amplifies a voltage between terminals drawn from one terminal and the other terminal of the gate resistance element,
The gate drive control unit has an RS flip-flop circuit and a second switching element for applying a gate driving voltage to the gate terminal of the first switching element,
The output of the first differential amplifier circuit is connected to the set terminal of the RS flip-flop circuit, the output of the second differential amplifier circuit is connected to the reset terminal of the RS flip-flop circuit, and the RS flip-flop A third differential amplifier for differentially amplifying the output voltage of the circuit;
An inverter system, wherein an output of the third differential amplifier is connected to an on / off control terminal of a second switching element for outputting a signal for driving the first switching element.
The inverter system according to claim 10,
An inverter system comprising an integrating circuit in series with the second differential amplifier circuit.
The inverter system according to any one of claims 8 to 11,
When the gate current detection unit does not detect the on-side gate current, the drive signal outputs an on signal after a predetermined time has elapsed.
The inverter system according to any one of claims 8 to 12,
An inverter system comprising a Zener diode having an anode terminal connected to the source terminal between a gate terminal and a source terminal of the first switching element.
In the inverter system according to any one of claims 8 to 13,
The switching element is mounted on a semiconductor module,
A gate terminal for external connection of the semiconductor module and a source terminal for external connection;
At least one of the drive signal detection unit, the gate current detection unit, and the gate drive control unit is mounted on a printed circuit board directly connected to the external connection gate terminal and the external connection source terminal. An inverter system characterized by that.