JP2003143833A - Gate driver of semiconductor switching element - Google Patents
Gate driver of semiconductor switching elementInfo
- Publication number
- JP2003143833A JP2003143833A JP2001335956A JP2001335956A JP2003143833A JP 2003143833 A JP2003143833 A JP 2003143833A JP 2001335956 A JP2001335956 A JP 2001335956A JP 2001335956 A JP2001335956 A JP 2001335956A JP 2003143833 A JP2003143833 A JP 2003143833A
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- Prior art keywords
- gate
- switching element
- semiconductor switching
- normal
- current
- Prior art date
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- Power Conversion In General (AREA)
- Inverter Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体スイッチン
グ素子を用いた電力変換装置に関し、特に電力変換装置
の半導体スイッチング素子のゲート駆動装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power conversion device using a semiconductor switching element, and more particularly to a gate drive device for a semiconductor switching element of the power conversion device.
【０００２】[0002]
【従来の技術】大容量の電力変換装置の半導体スイッチ
ング素子として、電圧駆動型の素子であるＩＧＢＴ（絶
縁ゲート・バイポーラ・トランジスタ）の大容量化が進
み、適応範囲が拡大している。電圧駆動型半導体スイッ
チング素子のゲート電流は、ターンオン・ターンオフ時
に流れるのみであり、その駆動が小電力で簡単にできる
ため、駆動回路の電力容量の小さくて済み、装置が小型
になる。2. Description of the Related Art As a semiconductor switching element of a large-capacity power conversion device, an IGBT (insulated gate bipolar transistor), which is a voltage-driven element, has been increased in capacity and its applicable range has been expanded. The gate current of the voltage-driven semiconductor switching element only flows at turn-on and turn-off, and it can be driven easily with a small amount of power, so that the power capacity of the drive circuit can be small and the device can be made compact.
【０００３】ＩＧＢＴを用いた電力変換装置のＩＧＢＴ
の異常や、故障の検知方法が、特開平８−２９８７８６
号公報に開示されている。特開平８−２９８７８６号公
報では、ＩＧＢＴのゲート−エミッタ間の電圧を監視
し、ＩＧＢＴのゲートしきい値電圧より低い値に、分圧
抵抗で設定した基準電圧に対して、ゲート−エミッタ間
電圧が高いときにはＩＧＢＴをオンと判定し、低いとき
にはオフと判定するフィードバック信号を発生させる。IGBT of power converter using IGBT
Japanese Patent Application Laid-Open No. 8-298786 discloses a method for detecting abnormalities and failures.
It is disclosed in the publication. In JP-A-8-298786, the gate-emitter voltage of the IGBT is monitored, and the gate-emitter voltage is set to a value lower than the gate threshold voltage of the IGBT with respect to a reference voltage set by a voltage dividing resistor. When is high, it determines that the IGBT is on, and when it is low, it generates a feedback signal that determines off.
【０００４】また、特開平１１−３５６０３５号公報に
は、図２に示すようにＩＧＢＴのゲートしきい値電圧よ
り低い電圧を設定していた分圧抵抗と並列に、基準電圧
切り替え抵抗と基準電圧切り替えトランジスタを設けて
いる。この場合、オンとオフの状態を判別するための基
準電圧を夫々設けるため、そのオン状態を判別する基準
電圧に対して、ゲート−エミッタ間電圧が高いときには
ＩＧＢＴをオンと判定し、そのオフ状態を判別する基準
電圧に対して、ゲート−エミッタ間電圧が低いときには
ＩＧＢＴをオフと判定する。Further, in Japanese Unexamined Patent Publication No. 11-356035, a reference voltage switching resistor and a reference voltage are provided in parallel with a voltage dividing resistor that has set a voltage lower than a gate threshold voltage of an IGBT as shown in FIG. A switching transistor is provided. In this case, since the reference voltage for discriminating the ON state and the OFF state is respectively provided, when the gate-emitter voltage is higher than the reference voltage for discriminating the ON state, the IGBT is determined to be the ON state and the OFF state is determined. When the gate-emitter voltage is low with respect to the reference voltage used for determining, the IGBT is determined to be off.
【０００５】図２に示すようにＩＧＢＴ１１のゲート端
子には、ゲート抵抗２１が接続されている。ＩＧＢＴ１
１のゲート−エミッタ間電圧は、コンパレータ３６に入
力する。ＩＧＢＴ１１がオンのときは、分圧抵抗２６と
２７で設定される電圧と比較し、ゲート−エミッタ間電
圧が高いときにはＩＧＢＴをオンと判定し、発光器４６
に“Ｌ”を出力し、発光器４６は発光しない。なお、分
圧抵抗２６と２７で設定される電圧は、オン時のゲート
−エミッタ間電圧よりも３Ｖ程度低く設定している。一
方、ＩＧＢＴ１１がオフのときは、分圧抵抗２６と２７
及び基準電圧切り替え抵抗２９で設定される電圧と比較
し、ゲート−エミッタ間電圧が低いときにはＩＧＢＴを
オフと判定し、発光器４６に“Ｈ”を出力し、発光器４
６は発光する。なお、分圧抵抗２６と２７及び基準電圧
切り替え抵抗２９で設定される電圧は、オン時のゲート
−エミッタ間電圧よりも３Ｖ程度高く設定している。As shown in FIG. 2, a gate resistor 21 is connected to the gate terminal of the IGBT 11. IGBT1
The gate-emitter voltage of 1 is input to the comparator 36. When the IGBT 11 is on, it is compared with the voltage set by the voltage dividing resistors 26 and 27, and when the gate-emitter voltage is high, it is determined that the IGBT is on, and the light emitter 46
"L" is output, and the light emitter 46 does not emit light. The voltage set by the voltage dividing resistors 26 and 27 is set to be about 3 V lower than the gate-emitter voltage at the time of turning on. On the other hand, when the IGBT 11 is off, the voltage dividing resistors 26 and 27 are
And the voltage set by the reference voltage switching resistor 29, and when the gate-emitter voltage is low, it is determined that the IGBT is off, "H" is output to the light emitter 46, and the light emitter 4
6 emits light. The voltage set by the voltage dividing resistors 26 and 27 and the reference voltage switching resistor 29 is set to be about 3 V higher than the gate-emitter voltage at the time of turning on.
【０００６】図３に、従来技術の回路を用いた場合のゲ
ート電圧波形の一例を示す。IGBTのゲートの絶縁特性が
劣化し、ゲート−エミッタ間の抵抗が数百Ωに低下した
場合でも、オン状態でのゲート電圧は、正常範囲の１２
〜１５Ｖ、オフ状態でのゲート電圧は、正常範囲の−１
２〜−９Ｖで、スイッチングを繰り返す。FIG. 3 shows an example of a gate voltage waveform when a conventional circuit is used. Even if the insulation characteristics of the gate of the IGBT deteriorate and the resistance between the gate and the emitter drops to several hundred Ω, the gate voltage in the ON state is 12
~ 15V, the gate voltage in the off state is -1 in the normal range
Switching is repeated at 2 to -9V.
【０００７】[0007]
【発明が解決しようとする課題】しかし、前記特開平８
−２９８７８６号公報に開示の従来技術では、ＩＧＢＴ
のゲートの絶縁が劣化し、ゲート−エミッタ間の漏れ電
流が増加するなどで、正規のオンゲート電圧、あるいは
オフゲート電圧がゲート−エミッタ間に印加されていな
い場合に、これを検出できなかった。However, the above-mentioned Japanese Unexamined Patent Application Publication No. Hei 8
In the prior art disclosed in Japanese Patent Publication No. 298786-, the IGBT is
Since the insulation of the gate is deteriorated and the leakage current between the gate and the emitter is increased, this cannot be detected when the regular on-gate voltage or the off-gate voltage is not applied between the gate and the emitter.
【０００８】また、特開平１１−３５６０３５号公報に
示す従来技術では、ＩＧＢＴのゲートの絶縁特性が劣化
し、ゲート−エミッタ間の抵抗が数百Ω程度の高インピ
ーダンス状態になっている場合、オン状態を判別する基
準電圧よりも低下する前に、ＩＧＢＴのゲートの絶縁特
性は異常になっており、これを検出できなかった。Further, in the prior art disclosed in Japanese Patent Laid-Open No. 11-356035, when the insulation characteristic of the gate of the IGBT is deteriorated and the resistance between the gate and the emitter is in a high impedance state of about several hundreds Ω, it is turned on. Before the voltage was lower than the reference voltage for determining the state, the insulation characteristics of the IGBT gate were abnormal, and this could not be detected.
【０００９】本発明の目的は、このようなオン時に正規
のゲート電圧、またはオフ時に正規のゲート電圧が印加
されないときにおいても素子の故障を検知し、電力変換
装置の安全性，信頼性を更に向上させる半導体スイッチ
ング素子のゲート駆動装置を提供することである。An object of the present invention is to detect a failure of an element even when such a normal gate voltage is not applied when turned on or a normal gate voltage is applied when turned off, thereby further improving the safety and reliability of the power converter. It is an object of the present invention to provide a gate driving device for a semiconductor switching device that is improved.
【００１０】[0010]
【課題を解決するための手段】本発明の半導体スイッチ
ング素子のゲート駆動装置は、半導体スイッチング素子
のゲート端子に接続したゲート抵抗を介して前記半導体
スイッチング素子に駆動信号を加えるものであって、前
記ゲート抵抗に流れるゲート電流測定手段と、該ゲート
電流測定手段が検出したゲート電流測定値と正常範囲電
流値とを比較し、正常又は異常を判別する正常異常判別
手段と、該正常異常判別手段の出力信号を受信し前記半
導体スイッチング素子のゲート駆動回路を制御する制御
手段と、前記正常異常判別手段の出力信号を該制御手段
に伝達する異常信号伝達手段とを有し、さらに前記正常
異常判別手段が、前記ゲート抵抗に流れるターンオン時
のゲート電流、あるいはゲート抵抗に流れるターンオフ
時のゲート電流の少なくともいずれか一方のゲート電流
測定値と正常範囲電流値とを比較する。According to another aspect of the present invention, there is provided a gate driving device for a semiconductor switching element, wherein a drive signal is applied to the semiconductor switching element via a gate resistor connected to a gate terminal of the semiconductor switching element. A gate current measuring means flowing through the gate resistance, a normal / abnormality determining means for comparing the gate current measurement value detected by the gate current measuring means and a normal range current value to determine normality or abnormality, and the normal / abnormality determining means. The control means receives an output signal and controls the gate drive circuit of the semiconductor switching element, and an abnormal signal transmission means for transmitting the output signal of the normal / abnormal determination means to the control means. Is the turn-on gate current flowing through the gate resistance or the turn-off gate current flowing through the gate resistance. Even without comparing the one of the gate current measured value and the normal range current value.
【００１１】また、本発明の半導体スイッチング素子の
ゲート駆動装置は、前記ゲート電流測定手段が、ゲート
抵抗に流れるターンオン時のゲート電流を積分する手
段、あるいはゲート抵抗に流れるターンオフ時のゲート
電流を積分する手段を備え、前記正常異常判別手段が、
少なくともいずれか一方の前記ゲート電流積分値と正常
範囲電流積分値とを比較する。Further, in the gate driving device for a semiconductor switching element of the present invention, the gate current measuring means integrates a turn-on gate current flowing through the gate resistance or a turn-off gate current flowing through the gate resistance. And a means for determining whether the normality or abnormality is present,
At least one of the gate current integrated value and the normal range current integrated value is compared.
【００１２】さらに、本発明の半導体スイッチング素子
のゲート駆動装置は、直列に接続している半導体スイッ
チング素子のゲート駆動回路へ、光ファイバやレーザダ
イオードやフォトダイオードなどの光通信手段で、正常
又は異常の信号を伝達したり、また、集積回路化してい
るゲート駆動回路においては、直列に接続しているスイ
ッチング素子のゲート駆動回路へ、レベルシフト回路を
用いて、正常又は異常の信号を伝達し、正常又は異常の
信号の伝達を、ゲート駆動信号を制御する制御部までフ
ィードバックさせる。Further, the semiconductor switching element gate drive device according to the present invention is normally or abnormally connected to the semiconductor switching element gate drive circuit connected in series by an optical communication means such as an optical fiber, a laser diode or a photodiode. , Or, in a gate drive circuit that is integrated into a circuit, transmits a normal or abnormal signal to the gate drive circuit of the switching elements connected in series by using the level shift circuit, The transmission of the normal or abnormal signal is fed back to the control unit that controls the gate drive signal.
【００１３】[0013]
【発明の実施の形態】本発明の実施例を以下図面を使用
して詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
【００１４】（実施例１）図１に、本実施例の構成図を
示す。半導体スイッチング素子として、ＩＧＢＴやＭＯ
ＳＦＥＴなどの電圧駆動型の素子全般が適用できるが、
以下、ＩＧＢＴの場合を説明する。図１のＩＧＢＴ１１
は、コレクタ端子１３とエミッタ端子１４と、ゲート端
子とを備え、ゲート端子にはゲート抵抗２１を接続す
る。本実施例では、ゲート抵抗２１に流れる電流を測定
するゲート電流測定回路４２を備える。このゲート電流
の測定結果を用いて、正常異常判別回路４３で、ＩＧＢ
Ｔ１１の正常異常を判別する。この判別結果の信号を制
御回路４４に伝送し、駆動回路４１にフィードバックす
る。なお、制御回路４４には、異常のラッチ回路も備え
ている。(Embodiment 1) FIG. 1 shows a block diagram of this embodiment. As a semiconductor switching element, IGBT or MO
All voltage drive type devices such as SFET can be applied,
The case of the IGBT will be described below. IGBT 11 of FIG.
Has a collector terminal 13, an emitter terminal 14, and a gate terminal, and a gate resistor 21 is connected to the gate terminal. In this embodiment, a gate current measuring circuit 42 for measuring the current flowing through the gate resistor 21 is provided. Using the measurement result of the gate current, the normal / abnormal determination circuit 43 detects the IGBT
The normal abnormality of T11 is determined. The signal of this determination result is transmitted to the control circuit 44 and fed back to the drive circuit 41. The control circuit 44 also includes an abnormal latch circuit.
【００１５】本実施例では、先に図２に示した従来技術
とは異なり、図４に示すようにゲート電流波形をモニタ
ーする。ゲート電流を測定する手段として、ゲート抵抗
の両端の電圧を測定し、電流値に換算する方法や、カレ
ントトランスを使用する方法などを用いる。ゲート電流
波形をモニターする期間は、図４に示すターンオン又
は、ターンオフの信号が入力後、５μｓ以降後が望まし
い。この理由は、IGBTのゲートの絶縁特性が正常なもの
では、５μｓ程度でゲート電流が流れなくなるからであ
る。なお、正常なＩＧＢＴのゲート電流値とは、ＩＧＢ
Ｔの製品仕様に記載されている定格値のことである。本
実施例では、正常なゲート電流値の５０〜２００％の範
囲の測定値を正常範囲に設定し、ゲートの絶縁特性が劣
化したIGBTの異常や劣化を検知する。ゲート電流値は、
正常なＩＧＢＴであっても、ゲート容量のばらつき、動
作電圧のばらつき、ゲート抵抗のばらつきなどの影響を
受けるが、これらのばらつきの寄与は合計してもゲート
電流値の３０％程度である。従って正常範囲は、前記５
０〜２００％とすれば充分であり、好ましくは６０〜１
７０％、さらに好ましくは７０〜１３０％とすれば良
い。In this embodiment, unlike the prior art shown in FIG. 2, the gate current waveform is monitored as shown in FIG. As a means for measuring the gate current, a method of measuring the voltage across the gate resistance and converting it into a current value, a method of using a current transformer, or the like is used. The period for monitoring the gate current waveform is preferably 5 μs or more after the turn-on or turn-off signal shown in FIG. 4 is input. The reason for this is that if the gate insulating characteristics of the IGBT are normal, the gate current will stop flowing in about 5 μs. The normal gate current value of the IGBT is the IGBT
It is the rated value described in the product specifications of T. In the present embodiment, the measured value in the range of 50 to 200% of the normal gate current value is set to the normal range, and the abnormality or deterioration of the IGBT having the deteriorated gate insulation characteristic is detected. The gate current value is
Even a normal IGBT is affected by variations in gate capacitance, variations in operating voltage, variations in gate resistance, etc., but the contribution of these variations is about 30% of the gate current value in total. Therefore, the normal range is 5
It is sufficient to set it to 0 to 200%, preferably 60 to 1
It may be 70%, more preferably 70 to 130%.
【００１６】本実施例では、ターンオン又は、ターンオ
フの信号を入力してから１０μｓ経過後の電流値を測定
して、ＩＧＢＴのゲートの絶縁特性が劣化した場合のIG
BTの異常、及び劣化を検知し、これによって安全性，信
頼性の高いゲート駆動回路を実現する。In the present embodiment, the current value 10 seconds after the turn-on or turn-off signal is input is measured, and the IG when the insulation characteristics of the gate of the IGBT is deteriorated is measured.
BT abnormality and deterioration are detected, and thereby a safe and reliable gate drive circuit is realized.
【００１７】（実施例２）図６に、本実施例の構成図を
示す。実施例１と異なる点は、図１のゲート電流測定回
路４２がゲート電流積分回路４７となっている点であ
る。図５に、本実施例のゲート電流の積分波形の一例を
示す。本実施例では、正常なゲート電流積分値の５０〜
２００％の範囲の測定値を正常範囲に設定し、ゲートの
絶縁特性が劣化したＩＧＢＴの異常や劣化を検知する。
ゲート電流積分値は、正常なＩＧＢＴであっても、ゲー
ト容量のばらつき、動作電圧のばらつき、ゲート抵抗の
ばらつきなどの影響を受けるが、これらのばらつきの寄
与は合計してもゲート電流積分値の３０％程度である。
従って正常範囲は、前記５０〜２００％とすれば充分で
あり、好ましくは６０〜１７０％、さらに好ましくは７
０〜１３０％とすれば良い。また、ゲート電流積分の正
常値の範囲は、ターンオン時，ターンオフ時いずれの場
合も同じである。ここで、正常なＩＧＢＴのゲート電流
値とは、ＩＧＢＴの製品仕様に記載されている定格値の
ことである。(Second Embodiment) FIG. 6 shows a block diagram of the present embodiment. The difference from the first embodiment is that the gate current measuring circuit 42 of FIG. 1 is a gate current integrating circuit 47. FIG. 5 shows an example of the integrated waveform of the gate current of this embodiment. In this embodiment, the normal gate current integrated value of 50 to
The measured value in the range of 200% is set to the normal range, and the abnormality or deterioration of the IGBT whose insulating characteristic of the gate is deteriorated is detected.
The gate current integrated value is affected by variations in gate capacitance, operating voltage, and gate resistance even in a normal IGBT. The contributions of these variations are the sum of the gate current integral values. It is about 30%.
Therefore, the normal range is sufficient if it is 50 to 200%, preferably 60 to 170%, more preferably 7%.
It may be 0 to 130%. Further, the range of the normal value of the gate current integration is the same in both cases of turning on and turning off. Here, the normal IGBT gate current value is the rated value described in the product specifications of the IGBT.
【００１８】なお、ゲート電流積分回路４７は、リセッ
トパルス回路４８から、リセットパルスを入力する。リ
セットパルスを入力する第１の方法は、図６に示すよう
に、制御回路４４から駆動回路４１へのオン，オフパル
ス信号から、幅の狭いパルス信号を発生し、ゲート電流
積分回路４７のコンデンサの電荷を放電し、積分器出力
をゼロにリセットする。第２の方法は、ゲート電流が正
または負に変化するどちらか一方のタイミングを利用し
て、ゲート電流積分回路４７のコンデンサの電荷を放電
し、積分器出力をゼロにする方法である。このように本
実施例によって、精度の良い異常検知回路を実現でき、
安全性，信頼性の高いゲート駆動回路が提供できる。The gate current integration circuit 47 receives the reset pulse from the reset pulse circuit 48. As shown in FIG. 6, the first method of inputting the reset pulse is to generate a narrow pulse signal from the ON / OFF pulse signal from the control circuit 44 to the drive circuit 41, and to generate the narrow pulse signal of the capacitor of the gate current integration circuit 47. Discharges the charge and resets the integrator output to zero. The second method is a method in which the charge of the capacitor of the gate current integration circuit 47 is discharged and the output of the integrator is set to zero by utilizing either the timing when the gate current changes to positive or negative. As described above, according to this embodiment, a highly accurate abnormality detection circuit can be realized,
A gate drive circuit with high safety and reliability can be provided.
【００１９】（実施例３）図７に、本実施例の構成図を
示す。本実施例では、最終段ｎｐｎトランジスタ３１，
最終段ｐｎｐトランジスタ３２，ターンオン用ゲート抵
抗２２，ターンオフ用ゲート抵抗２３により、ＩＧＢＴ
１１を駆動する。本実施例が実施例２と異なる点は、タ
ーンオフ用のゲート抵抗２３に流れる電流を積分するこ
とである。本実施例は、駆動電源４０のグランドを基準
に、ゲート電流積分回路４７や、リセットパルス回路４
８を構成できるため、全体回路が簡素化できる。(Embodiment 3) FIG. 7 shows a block diagram of this embodiment. In the present embodiment, the final stage npn transistor 31,
The final stage pnp transistor 32, the turn-on gate resistance 22, and the turn-off gate resistance 23 make the IGBT
11 is driven. The present embodiment is different from the second embodiment in that the current flowing through the turn-off gate resistor 23 is integrated. In the present embodiment, the gate current integrating circuit 47 and the reset pulse circuit 4 are set with the ground of the driving power supply 40 as a reference.
Since 8 can be configured, the entire circuit can be simplified.
【００２０】（実施例４）図８に、本実施例の構成図を
示す。実施例３との相違点は、ターンオン用のゲート抵
抗２２に流れる電流を積分している点である。本実施例
はターンオン時のゲート電流を監視し、実施例３と同様
に精度の良い検知回路であり、安全性，信頼性の高いゲ
ート駆動装置を提供できる。なお、本実施例に実施例３
の構成を組み合わせて、ターンオン時とターンオフ時の
ゲート電流を監視しても良いことは言うまでもない。(Embodiment 4) FIG. 8 shows a block diagram of this embodiment. The difference from the third embodiment is that the current flowing through the turn-on gate resistor 22 is integrated. This embodiment monitors the gate current at turn-on and is a highly accurate detection circuit as in the case of the third embodiment, and can provide a highly safe and reliable gate drive device. In addition, in the present embodiment, the third embodiment will be described.
It goes without saying that the gate currents at turn-on and turn-off may be monitored by combining the above configurations.
【００２１】（実施例５）図９に、本実施例の回路図を
示す。本実施例と実施例２との相違点は、ゲート電流の
積分回路及びリセットパルス回路に、差電圧検出器４９
と、積分器５０を付加している点である。図１０に、差
電圧検出器４９と、積分器５０の回路詳細図を示す。(Embodiment 5) FIG. 9 shows a circuit diagram of this embodiment. The difference between the present embodiment and the second embodiment is that the difference voltage detector 49 is provided in the gate current integration circuit and the reset pulse circuit.
And that an integrator 50 is added. FIG. 10 shows a detailed circuit diagram of the differential voltage detector 49 and the integrator 50.
【００２２】図１０を用いて、本実施例の回路動作を説
明する。差電圧検出器４９は、減算増幅器の回路構成と
なっている。ゲート抵抗２１の両端の電圧をｖ１，ｖ２
（ゲート抵抗側をｖ１）とすると、差電圧検出器のオペ
アンプ３７の出力電圧ｖ３は、抵抗Ｒ１からＲ４の値を
Ｒ２／Ｒ１＝Ｒ４／Ｒ３に設定してあるので、ｖ３＝−
Ｒ２／Ｒ１×(ｖ１−ｖ２)となる。ターンオン時には、
ｖ１＞ｖ２であり、オペアンプ３７の出力電圧ｖ３は負
の値で増幅する。そのため、積分器のオペアンプ３７の
出力ｖ４は、正の値となり、ダイオードＤ１によりコン
デンサＣ１は放電し、ゼロにリセットする。よって、コ
ンパレータ３６は、制御回路へ、ｌｏｗ信号を出力す
る。The circuit operation of this embodiment will be described with reference to FIG. The differential voltage detector 49 has a circuit configuration of a subtraction amplifier. Set the voltage across the gate resistor 21 to v1, v2
Assuming that (the gate resistance side is v1), the output voltage v3 of the operational amplifier 37 of the differential voltage detector has the values of the resistors R1 to R4 set to R2 / R1 = R4 / R3, so v3 =-
It becomes R2 / R1 * (v1-v2). At turn-on,
Since v1> v2, the output voltage v3 of the operational amplifier 37 is amplified by a negative value. Therefore, the output v4 of the operational amplifier 37 of the integrator becomes a positive value, and the capacitor C1 is discharged by the diode D1 and reset to zero. Therefore, the comparator 36 outputs a low signal to the control circuit.
【００２３】一方、ターンオフ時には、ｖ１＜ｖ２であ
り、オペアンプ３７の出力電圧ｖ３は正の値で増幅す
る。積分器のオペアンプ３７の出力ｖ４は、ｖ４＝−１
／Ｃ１・Ｒ５∫ｖ３ｄｔとなる。ＩＧＢＴのゲート電流
（ゲート抵抗両端の差電圧）の積分値が、正常範囲の場
合は、この積分値が、コンパレータ３６の基準電圧より
も、高い状態であり、コンパレータ３６は、制御回路へ
ｌｏｗ信号を出力する。しかし、ＩＧＢＴのゲートの絶
縁特性が異常になった場合、ＩＧＢＴのゲート電流の積
分値すなわちｖ４が大きくなり、コンパレータ３６の基
準電圧よりも低くなり、コンパレータ３６は、制御回路
へｈｉｇｈの異常信号を出力する。同時に、図９の発光
器４６が消燈状態に移行する。発光器４６は、フェール
セーフを考慮すると、正常時に点灯し、異常時に消燈す
ることが望ましい。発光器が消燈することで、異常信号
を制御回路にフィードバックし、直列に接続しているス
イッチング素子のゲート駆動回路をオフ状態に移行す
る。On the other hand, when turned off, v1 <v2, and the output voltage v3 of the operational amplifier 37 is amplified by a positive value. The output v4 of the operational amplifier 37 of the integrator is v4 = -1
/ C1 · R5∫v3dt. When the integrated value of the gate current of the IGBT (the difference voltage across the gate resistance) is in the normal range, this integrated value is higher than the reference voltage of the comparator 36, and the comparator 36 sends a low signal to the control circuit. Is output. However, when the insulation characteristic of the gate of the IGBT becomes abnormal, the integrated value of the gate current of the IGBT, that is, v4, becomes large and becomes lower than the reference voltage of the comparator 36, and the comparator 36 sends a high abnormal signal to the control circuit. Output. At the same time, the light emitter 46 of FIG. 9 shifts to the extinguished state. Considering fail-safe, it is desirable that the light-emitting device 46 be turned on in a normal state and turned off in an abnormal state. When the light emitting device is turned off, the abnormal signal is fed back to the control circuit, and the gate drive circuits of the switching elements connected in series are turned off.
【００２４】また、図１０の回路では、ターンオフ時の
ゲート電流の積分により、正常・異常を判別したが、ゲ
ート抵抗２１の両端の電圧ｖ１，ｖ２を、差電圧検出器
のオペアンプ３７に反対に入力、すなわち逆極性で入力
し、ダイオードＤ１の極性を図１０とは反転して、ター
ンオン時のゲート電流の積分により、正常・異常を判別
しても良い。Further, in the circuit of FIG. 10, normality / abnormality is discriminated by integration of the gate current at the time of turn-off, but the voltages v1 and v2 across the gate resistor 21 are reversed to the operational amplifier 37 of the differential voltage detector. It is also possible to determine whether normal or abnormal by inputting, that is, inputting with reverse polarity, inverting the polarity of the diode D1 from that in FIG. 10, and integrating the gate current at turn-on.
【００２５】なお、ＩＧＢＴのゲート特性が劣化する原
因の多くは、ターンオフ時にIGBTのＲＢＳＯＡ（逆バイ
アス安全動作領域）を超えた場合や、短絡耐量を超えた
場合に、素子が故障し、ゲート特性が劣化するので、タ
ーンオフ時のゲート電流の積分値を正常範囲と比較する
ことが望ましい。Incidentally, most of the causes of the deterioration of the gate characteristics of the IGBT are caused by the failure of the element when the RBSOA (reverse bias safe operation area) of the IGBT is exceeded at the time of turn-off or when the short-circuit withstand capacity is exceeded, and the gate characteristics are deteriorated. Is deteriorated, it is desirable to compare the integrated value of the gate current at turn-off with a normal range.
【００２６】このように、本回路構成により、ターンオ
フ時、あるいはターンオン時のゲート電流の積分値によ
り、ＩＧＢＴのゲートの絶縁特性の劣化を容易に判別で
き、同一アームに直列に接続している素子のゲート回路
にも異常を伝送して、アーム短絡を未然に防止できる。
これにより安全性，信頼性の高いスイッチング素子のゲ
ート駆動装置を実現できる。As described above, according to this circuit configuration, the deterioration of the insulation characteristics of the gate of the IGBT can be easily discriminated by the integrated value of the gate current at the time of turn-off or turn-on, and the elements connected in series to the same arm. Abnormalities can be transmitted to the gate circuit of to prevent arm short circuit.
As a result, it is possible to realize a gate drive device for switching elements with high safety and reliability.
【００２７】（実施例６）図１１に、本実施例の構成図
を示す。本実施例では、電力変換回路の主回路の同一相
に直列に接続されるＩＧＢＴ１１と、上アームのゲート
駆動回路５３，下アームのゲート駆動回路５４、及び制
御回路４４を備えている。上アームのゲート駆動回路５
３と下アームのゲート駆動回路５４は、それぞれ、図９
と図１０に示す回路構成である。(Sixth Embodiment) FIG. 11 shows a block diagram of the present embodiment. In this embodiment, the IGBT 11 connected in series to the same phase of the main circuit of the power conversion circuit, an upper arm gate drive circuit 53, a lower arm gate drive circuit 54, and a control circuit 44 are provided. Upper arm gate drive circuit 5
3 and the gate drive circuit 54 of the lower arm are respectively shown in FIG.
And the circuit configuration shown in FIG.
【００２８】本実施例の回路動作を説明する。例えば、
下アームのＩＧＢＴ１１のゲートの絶縁特性が劣化した
場合、下アームのゲート駆動回路５４でＩＧＢＴ１１の
劣化を検知し、レーザーダイオードや発光ダイオードな
どの発光器４６に信号を伝達する。制御回路４４の、フ
ォトダイオードやフォトトランジスタなどの受光器４５
が異常信号を検知し、故障検知回路５６に異常を伝え、
ゲートパルス出力回路５５により、信号入力を停止す
る。前記制御回路４４と上アームのゲート駆動回路５
３，下アームのゲート駆動回路５４との間は光ファイバ
ーで接続し、前記異常検知信号などを伝送する。なお、
故障検知回路５６からの異常信号は、オペレータや運転
手に異常信号を伝える構成であっても良い。The circuit operation of this embodiment will be described. For example,
When the insulation characteristic of the gate of the lower arm IGBT 11 deteriorates, the lower arm gate drive circuit 54 detects the deterioration of the IGBT 11 and transmits a signal to the light emitter 46 such as a laser diode or a light emitting diode. A light receiver 45 such as a photodiode or phototransistor of the control circuit 44.
Detects an abnormality signal and informs the failure detection circuit 56 of the abnormality,
The gate pulse output circuit 55 stops the signal input. The control circuit 44 and the upper arm gate drive circuit 5
3. An optical fiber is connected to the lower arm gate drive circuit 54 to transmit the abnormality detection signal and the like. In addition,
The abnormal signal from the failure detection circuit 56 may be transmitted to the operator or the driver.
【００２９】このように本実施例によれば、ＩＧＢＴの
ゲートの絶縁特性が劣化した下アームのゲート駆動回路
５４と、同一相に直列に接続されるＩＧＢＴの上アーム
のゲート駆動回路５３への駆動信号を停止でき、アーム
短絡を未然に防止できるので、安全性，信頼性の高いス
イッチング素子のゲート駆動装置を実現できる。As described above, according to this embodiment, the gate drive circuit 54 of the lower arm in which the insulation characteristics of the gate of the IGBT are deteriorated and the gate drive circuit 53 of the upper arm of the IGBT connected in series to the same phase are connected. Since the drive signal can be stopped and the arm short circuit can be prevented in advance, it is possible to realize a highly safe and reliable gate drive device for the switching element.
【００３０】（実施例７）図１２に、本実施例の構成図
を示す。実施例６では、異常信号の伝送を光ファイバや
レーザダイオード等の光通信で行っているが、本実施例
では異常信号を電気信号の直流電位レベルを変換するレ
ベルシフト回路を用いており、産業用インバータや自動
車用インバータ装置にも容易に適用できる。(Embodiment 7) FIG. 12 shows a block diagram of the present embodiment. In the sixth embodiment, the abnormal signal is transmitted by optical communication such as an optical fiber or a laser diode, but in this embodiment, a level shift circuit for converting the abnormal signal into the DC potential level of the electric signal is used. It can be easily applied to inverters for automobiles and inverters for automobiles.
【００３１】本実施例では、正常異常判別回路４３の出
力は駆動回路４１とレベルシフト回路とに入力されてい
て、上アームのゲート駆動回路５３と下アームのゲート
駆動回路５４とを、１チップの集積回路５９にした。例
えば、下アームのＩＧＢＴ11のゲートの絶縁特性が劣化
した場合、正常異常判別回路４３からの異常信号は、レ
ベルシフトアップ回路５７により、同一相に直列に接続
されるＩＧＢＴ１１の上アームのゲート駆動回路５３の
電位レベルに信号を変換し、駆動を停止する。In the present embodiment, the output of the normal / abnormal determination circuit 43 is input to the drive circuit 41 and the level shift circuit, and the upper arm gate drive circuit 53 and the lower arm gate drive circuit 54 are combined into one chip. Integrated circuit 59. For example, when the insulation characteristic of the gate of the lower arm IGBT 11 is deteriorated, the abnormal signal from the normal / abnormality determination circuit 43 is output by the level shift-up circuit 57 to the gate drive circuit of the upper arm of the IGBT 11 connected in series in the same phase. The signal is converted to the potential level of 53 and the driving is stopped.
【００３２】このように本実施例によれば、アーム短絡
を未然に回避できるので、安全性，信頼性の高いスイッ
チング素子のゲート駆動装置を実現できる。As described above, according to this embodiment, the arm short circuit can be avoided in advance, so that the gate driving device for the switching element having high safety and reliability can be realized.
【００３３】[0033]
【発明の効果】本発明によれば、ゲート抵抗に流れるゲ
ート電流を測定する手段、あるいはゲート抵抗に流れる
ゲート電流を積分する手段を設けＩＧＢＴのゲートの絶
縁特性等の異常を精度良く検知できる。さらに、同一ア
ームに直列に接続している他のＩＧＢＴのゲート回路に
も異常を伝送して、アーム短絡を未然に回避し、安全
性，信頼性の高いゲート駆動装置を実現できる。According to the present invention, means for measuring the gate current flowing through the gate resistance or means for integrating the gate current flowing through the gate resistance can be provided to accurately detect abnormalities such as the insulation characteristics of the gate of the IGBT. Further, an abnormality is transmitted to the gate circuits of other IGBTs connected in series to the same arm, arm short circuit is avoided in advance, and a highly safe and reliable gate drive device can be realized.
【図１】実施例１の構成図。FIG. 1 is a configuration diagram of a first embodiment.
【図２】従来技術の回路図。FIG. 2 is a prior art circuit diagram.
【図３】ＩＧＢＴのゲート−エミッタ間耐圧劣化品のゲ
ート電圧波形。FIG. 3 is a gate voltage waveform of an IGBT gate-emitter breakdown voltage deteriorated product.
【図４】ＩＧＢＴのゲート−エミッタ間耐圧劣化品のゲ
ート電流波形。FIG. 4 is a gate current waveform of an IGBT gate-emitter breakdown voltage deteriorated product.
【図５】ＩＧＢＴのゲート−エミッタ間耐圧劣化品のゲ
ート電流積分波形。FIG. 5 is a gate current integral waveform of an IGBT gate-emitter breakdown voltage deteriorated product.
【図６】実施例２の構成図。FIG. 6 is a configuration diagram of a second embodiment.
【図７】実施例３の構成図。FIG. 7 is a configuration diagram of a third embodiment.
【図８】実施例４の構成図。FIG. 8 is a configuration diagram of a fourth embodiment.
【図９】実施例５の回路図。FIG. 9 is a circuit diagram of a fifth embodiment.
【図１０】実施例５の差電圧検出器と積分器，比較器の
回路図。FIG. 10 is a circuit diagram of a differential voltage detector, an integrator, and a comparator according to the fifth embodiment.
【図１１】実施例６の構成図。FIG. 11 is a configuration diagram of a sixth embodiment.
【図１２】実施例７の構成図。FIG. 12 is a configuration diagram of a seventh embodiment.
１１…ＩＧＢＴ、１２…フリーホイルダイオード、１３
…コレクタ端子、１４…エミッタ端子、２１…ゲート抵
抗、２２…ターンオン用ゲート抵抗、２３…ターンオフ
用ゲート抵抗、２４，２８…プルアップ抵抗、２５…エ
ミッタ用抵抗、２６，２７…分圧抵抗、２９…基準電圧
切り替え抵抗、３１…最終段ｎｐｎトランジスタ、３２
…最終段ｐｎｐトランジスタ、３３…次段ｎｐｎトラン
ジスタ、３４…初段ｎｐｎトランジスタ、３５…基準電
圧切り替えトランジスタ、３６…コンパレータ、３７…
オペアンプ、４０…駆動電源、４１…駆動回路、４２…
ゲート電流測定回路、４３…正常異常判別回路、４４…
制御回路、４５…受光器、４６…発光器、４７…ゲート
電流積分回路、４８…リセットパルス回路、４９…差電
圧検出器、５０…積分器、５１…比較器、５２…主回路
電源、５３…上アームのゲート駆動回路、５４…下アー
ムのゲート駆動回路、５５…ゲートパルス出力回路、５
６…故障検知回路、５７…レベルシフトアップ回路、５
８…レベルシフトダウン回路、５９…集積回路。11 ... IGBT, 12 ... Free wheel diode, 13
... collector terminal, 14 ... emitter terminal, 21 ... gate resistance, 22 ... turn-on gate resistance, 23 ... turn-off gate resistance, 24, 28 ... pull-up resistance, 25 ... emitter resistance, 26, 27 ... voltage dividing resistance, 29 ... Reference voltage switching resistance, 31 ... Final stage npn transistor, 32
... final stage pnp transistor, 33 ... next stage npn transistor, 34 ... first stage npn transistor, 35 ... reference voltage switching transistor, 36 ... comparator, 37 ...
Operational amplifier, 40 ... drive power supply, 41 ... drive circuit, 42 ...
Gate current measuring circuit, 43 ... Normal / abnormal determination circuit, 44 ...
Control circuit, 45 ... Light receiver, 46 ... Light emitter, 47 ... Gate current integration circuit, 48 ... Reset pulse circuit, 49 ... Differential voltage detector, 50 ... Integrator, 51 ... Comparator, 52 ... Main circuit power supply, 53 ... upper arm gate drive circuit, 54 ... lower arm gate drive circuit, 55 ... gate pulse output circuit, 5
6 ... Failure detection circuit, 57 ... Level shift up circuit, 5
8 ... Level shift down circuit, 59 ... Integrated circuit.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 稲荷田 聡 茨城県ひたちなか市市毛1070番地 株式会 社日立製作所交通システム事業部水戸交通 システム本部内 (72)発明者 小西出 政臣 茨城県ひたちなか市市毛1070番地 株式会 社日立製作所交通システム事業部水戸交通 システム本部内 (72)発明者 関根 茂樹 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 齋藤 隆一 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 Ｆターム(参考） 5H007 AA05 CA01 CB02 CB05 CC07 DB03 DC02 FA06 FA13 FA19 5H740 AA08 BA11 BB05 BC01 BC02 JA01 JB01 KK01 KK04 MM12 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Satoshi Inarida 1070 Ichimo, Hitachinaka City, Ibaraki Prefecture Stock Association Hitachi, Ltd. Transportation Systems Division Mito Transportation System headquarters (72) Inventor Masaomi Konishi 1070 Ichimo, Hitachinaka City, Ibaraki Prefecture Stock Association Hitachi, Ltd. Transportation Systems Division Mito Transportation System headquarters (72) Inventor Shigeki Sekine 7-1-1, Omika-cho, Hitachi-shi, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor Ryuichi Saito 7-1-1, Omika-cho, Hitachi-shi, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi Ltd. F-term (reference) 5H007 AA05 CA01 CB02 CB05 CC07 DB03 DC02 FA06 FA13 FA19 5H740 AA08 BA11 BB05 BC01 BC02 JA01 JB01 KK01 KK04 MM12
Claims (15)
続したゲート抵抗を介して前記半導体スイッチング素子
に駆動信号を加える半導体スイッチング素子のゲート駆
動装置において、 該ゲート駆動装置が、前記ゲート抵抗に流れるゲート電
流測定手段と、 該ゲート電流測定手段が検出したゲート電流測定値と正
常範囲電流値とを比較し、正常又は異常を判別する正常
異常判別手段と、 該正常異常判別手段の出力信号を受信し前記半導体スイ
ッチング素子のゲート駆動回路を制御する制御手段ある
いは、 前記正常異常判別手段の出力信号を該制御手段に伝達す
る異常信号伝達手段とを有することを特徴とした半導体
スイッチング素子のゲート駆動装置。1. A gate drive device for a semiconductor switching element, which applies a drive signal to the semiconductor switching element via a gate resistor connected to a gate terminal of the semiconductor switching element, wherein the gate drive device supplies a gate current to the gate resistor. A measuring means, a normal / abnormality determining means for comparing the gate current measurement value detected by the gate current measuring means with a normal range current value to determine normality or abnormality, and an output signal of the normal / abnormality determining means for receiving the output signal. A gate drive device for a semiconductor switching element, comprising: a control means for controlling a gate drive circuit of the semiconductor switching element, or an abnormal signal transmission means for transmitting an output signal of the normal / abnormal determination means to the control means.
ンオン時のゲート電流、あるいはゲート抵抗に流れるタ
ーンオフ時のゲート電流の少なくともいずれか一方のゲ
ート電流測定値と正常範囲電流値とを比較することを特
徴とした半導体スイッチング素子のゲート駆動装置。2. The normal / abnormality determining means according to claim 1, wherein the gate current measured value of at least one of the gate current flowing through the gate resistor when turned on and the gate current flowing through the gate resistor when turned off is normal. A gate drive device for a semiconductor switching element, which is characterized by comparing with a range current value.
いて、 前記ゲート電流測定手段が、オンパルス入力から所定の
時間経過後のゲート電流を測定すること、あるいは、オ
フパルス入力から所定の時間経過後の電流を測定するこ
とを特徴とする半導体スイッチング素子のゲート駆動装
置。3. The method according to claim 1, wherein the gate current measuring means measures the gate current after a lapse of a predetermined time from the ON pulse input, or after a lapse of a predetermined time from the OFF pulse input. A gate drive device for a semiconductor switching element, which is characterized by measuring the current of the device.
が、オンパルスあるいはオフパルス入力後、５μｓ以降
の電流を測定することを特徴とする半導体スイッチング
素子のゲート駆動装置。4. A gate drive device for a semiconductor switching element according to claim 3, wherein said gate current measuring means measures a current after 5 μs after inputting an on pulse or an off pulse.
分する手段を備え、該ゲート電流積分値と正常範囲電流
値とを比較することを特徴とする半導体スイッチング素
子のゲート駆動装置。5. The semiconductor switching device according to claim 1, wherein the gate current measuring means includes means for integrating a current flowing through the gate resistance, and the integrated gate current value is compared with a normal range current value. Gate drive.
オン時のゲート電流を積分する手段、あるいはゲート抵
抗に流れるターンオフ時のゲート電流を積分する手段を
備え、 前記正常異常判別手段が、少なくともいずれか一方の前
記ゲート電流積分値と正常範囲電流積分値とを比較する
ことを特徴とする半導体スイッチング素子のゲート駆動
装置。6. The gate current measuring means according to claim 5, further comprising means for integrating a turn-on gate current flowing through the gate resistance or means for integrating a turn-off gate current flowing through the gate resistance, A gate drive device for a semiconductor switching element, wherein the abnormality determining means compares at least one of the gate current integrated value and a normal range current integrated value.
いて、 前記ゲート電流測定手段のゲート抵抗に流れる電流を積
分する手段が、ゲート抵抗の両端に発生する電圧を積分
する積分器であることを特徴とする半導体スイッチング
素子のゲート駆動装置。7. The method according to claim 5, wherein the means for integrating the current flowing through the gate resistance of the gate current measuring means is an integrator for integrating the voltage generated across the gate resistance. A gate drive device for a semiconductor switching element, comprising:
れていることを特徴とする半導体スイッチング素子のゲ
ート駆動装置。8. The gate drive device for a semiconductor switching element according to claim 7, wherein the integrator is composed of an operational amplifier, a capacitor and a resistor.
て、 前記ゲート電流測定手段によるゲート電流の積分値の正
常値範囲が、正常なスイッチング素子のゲート電流積分
値の０.５ 倍から２倍であることを特徴とする半導体ス
イッチング素子のゲート駆動装置。9. The normal value range of the integrated value of the gate current measured by the gate current measuring means is 0.5 times to 2 times the integrated value of the gate current of a normal switching element according to any one of claims 5 to 8. A gate drive device for a semiconductor switching element, which is doubled in number.
直列接続した上アームと下アームとを構成する半導体ス
イッチング素子をオン，オフ制御する半導体スイッチン
グ素子のゲート駆動装置において、 前記同一相に直列に接続される半導体スイッチング素子
をオン，オフ制御する上アームのゲート駆動回路と、下
アームのゲート駆動回路とがそれぞれ、 前記半導体スイッチング素子のゲート端子に接続したゲ
ート抵抗に流れるゲート電流測定手段と、 該ゲート電流測定手段が検出したゲート電流測定値と正
常範囲電流値とを比較し、正常又は異常を判別する正常
異常判別手段と、 前記正常異常判別手段の出力信号を該制御手段に伝達す
る異常信号伝達手段とを有し、 さらに、前記半導体スイッチング素子のゲート駆動装置
が、前記正常異常判別手段の出力信号を受信し前記半導
体スイッチング素子のゲート駆動回路を制御する制御手
段を有することを特徴とした半導体スイッチング素子の
ゲート駆動装置。10. A gate driving device for a semiconductor switching element, which controls on / off of a semiconductor switching element that constitutes an upper arm and a lower arm connected in series to the same phase of a main circuit of a semiconductor power conversion circuit, wherein Gate current measuring means in which a gate drive circuit of an upper arm and a gate drive circuit of a lower arm, which control on / off of semiconductor switching elements connected in series, respectively, flow through a gate resistance connected to a gate terminal of the semiconductor switching element. And a normal / abnormality determining means for comparing the measured gate current value detected by the gate current measuring means with a normal range current value to determine normality or abnormality, and transmitting an output signal of the normal / abnormality determining means to the control means. And a gate driving device for the semiconductor switching element, The gate drive of the semiconductor switching element is characterized by having a control means for controlling the gate driving circuit of received said semiconductor switching element the output signal of the normal discriminating means.
する異常信号伝達手段が、光ファイバと発光器と受光器
とを有する光通信手段であることを特徴とする半導体ス
イッチング素子のゲート駆動装置。11. The abnormality signal transmitting means for transmitting the output signal of the normal / abnormal determination means to the control means is an optical communication means having an optical fiber, a light emitter and a light receiver. Gate drive device for semiconductor switching element.
動回路とが同じ半導体チップに形成された集積回路であ
ることを特徴とする半導体スイッチング素子のゲート駆
動装置。12. The gate drive device for a semiconductor switching element according to claim 10, wherein the gate drive circuit for the upper arm and the gate drive circuit for the lower arm are integrated circuits formed on the same semiconductor chip. .
する異常信号伝達手段が、レベルシフト回路であること
を特徴とする半導体スイッチング素子のゲート駆動装
置。13. The gate drive device for a semiconductor switching element according to claim 12, wherein the abnormal signal transmission means for transmitting the output signal of the normal / abnormal determination means to the control means is a level shift circuit.
または請求項６のいずれかにおいて、 正常又は異常の信号の伝達を、ゲート駆動信号を制御す
る制御手段までフィードバックすることを特徴とする半
導体スイッチング素子のゲート駆動装置。14. The method according to claim 1, claim 2, or claim 5.
7. The gate drive device for a semiconductor switching element according to claim 6, wherein transmission of a normal or abnormal signal is fed back to a control means for controlling the gate drive signal.
る制御手段までフィードバックして、ゲート駆動を停止
することを特徴とする半導体スイッチング素子のゲート
駆動装置。15. The gate drive device for a semiconductor switching element according to claim 14, wherein the transmission of the normal or abnormal signal is fed back to the control means for controlling the gate drive signal to stop the gate drive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001335956A JP3931627B2 (en) | 2001-11-01 | 2001-11-01 | Gate driving device for semiconductor switching element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001335956A JP3931627B2 (en) | 2001-11-01 | 2001-11-01 | Gate driving device for semiconductor switching element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003143833A true JP2003143833A (en) | 2003-05-16 |
| JP3931627B2 JP3931627B2 (en) | 2007-06-20 |
Family
ID=19150871
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001335956A Expired - Fee Related JP3931627B2 (en) | 2001-11-01 | 2001-11-01 | Gate driving device for semiconductor switching element |
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| Country | Link |
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| DE112020007887T5 (en) | 2020-12-28 | 2023-10-12 | Mitsubishi Electric Corporation | SEMICONDUCTOR DRIVER DEVICE AND POWER CONVERTER DEVICE USING THE SAME |
| JP6949280B1 (en) * | 2020-12-28 | 2021-10-13 | 三菱電機株式会社 | Semiconductor drive device and power conversion device using it |
| WO2023135901A1 (en) * | 2022-01-17 | 2023-07-20 | 株式会社日立産機システム | Power conversion device |
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| JP3931627B2 (en) | 2007-06-20 |
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