WO2015102274A1

WO2015102274A1 - Temperature sensing apparatus and temperature sensing method based on temperature dependence of current according to channel length variation

Info

Publication number: WO2015102274A1
Application number: PCT/KR2014/012535
Authority: WO
Inventors: 성만영; 김진세; 장지웅
Original assignee: 고려대학교 산학협력단
Priority date: 2014-01-02
Filing date: 2014-12-18
Publication date: 2015-07-09
Also published as: KR101508578B1

Abstract

The temperature sensing apparatus according to the present invention comprises: a first clock signal output unit for outputting a first clock signal which is generated by delaying an input signal through a ring oscillator having a first delay time, the ring oscillator comprising one or more transistors connected in series; a second clock signal output unit for outputting a second clock signal which is generated by delaying the input signal through a ring oscillator having a second delay time, the ring oscillator comprising one or more transistors connected in series; and a digital signal output unit for receiving the second clock signal and outputting the value of the second clock signal as a digital signal in response to the rising transition of the first clock signal, the digital signal output unit comprising a plurality of buffers each having a unit delay time, wherein the first delay time and the second delay time are determined according to the gate channel length of the transistor included in the first clock signal output unit and the gate channel length of the transistor included in the second clock signal output unit, the first clock signal output unit has a higher sensitivity to temperature variation than the second clock signal output unit, and the second clock signal is set to have the same transition time as the first clock signal at a preset reference temperature.

Description

Temperature sensing device and temperature sensing method based on temperature dependence of current according to channel length change

The present invention relates to a temperature sensing device and a temperature sensing method, and more particularly, to a temperature sensing device and a method based on a temperature dependency of a current according to a change in channel length.

As the use of smart devices such as smartphones and tablet PCs has increased significantly, efforts have been made to simultaneously achieve miniaturization and multifunctionality of products. As part of this effort, the importance of scaling CMOS processes and designing low-power integrated circuits is increasing.

As CMOS processes scale and Moore's law increases the number of transistors per chip exponentially, heat generated per unit area of integrated circuits is increasing. This leads to high power consumption and low reliability of the integrated circuit. Therefore, there is a need for a temperature sensor to monitor thermal characteristics and to compensate for chip performance and operating conditions.

DRAM, for example, requires a temperature-sensing sensor that runs at low power. Since the DRAM records information by the amount of charge stored in the capacitor, the electrons are shorted and the stored information is lost. Therefore, the information must be periodically refreshed. In addition, as the leakage current increases due to process scaling, the operating frequency of the information reproduction current also increases. In this regard, the frequency of the information regeneration current of a DRAM without a temperature sensor should be designed based on the highest temperature conditions in the operating temperature range. In other words, the higher the temperature, the higher the leakage current, and thus, the more information reproduction current is required. Therefore, in order to store the information stored by the leakage current without losing it within the operating temperature range, it must be designed in consideration of the minimum requirements.

In this case, however, a large power consumption is generated because an unnecessary information regeneration current is caused at a temperature below the maximum temperature condition. Accordingly, by monitoring the temperature using a temperature sensor, it is possible to appropriately adjust the frequency of the information reproduction current to implement a low power operation of the DRAM.

In the early temperature sensing device, the PTAT (Proportional To Absolute Temperature) voltage was designed using BJT. When two BJTs are biased with I ₁ and I ₂ , respectively, the difference between the base-emitter voltages of the two transistors can be expressed as [Equation 1]. Accordingly, the PTAT voltage has a value proportional to the absolute temperature and a voltage characteristic proportional to the absolute temperature can be obtained by using a ratio of I ₁ and I ₂ .

[Equation 1]

On the other hand, the thermal voltage proportional to the temperature generated in the PTAT is compared with the reference voltage generated in the bandgap reference through an analog to digital converter (ADC) can detect the temperature change. However, in the case of such a temperature sensing sensor, the design of the bandgap reference and the analog-to-digital converter is very complicated, and it is difficult to keep the voltage of the integrated bandgap reference constant with temperature, and the power caused by the standby current of the analog circuit. Causes consumption.

To overcome these drawbacks, a digital temperature sensor was developed, and the temperature was detected by comparing the delay time irrelevant to the temperature and the delay time proportional to the temperature. Hereinafter, a temperature sensor according to the related art will be described with reference to FIGS. 1 and 2.

1 and 2 are views showing a temperature sensor according to the prior art.

1 illustrates a method using an external clock using a delay time independent of temperature. The circuit diagram shown in FIG. 1 includes a temperature-sensitive delay line including a separate external reference clock (Ref CLK) and a plurality of series-connected CMOS transistors. The temperature can be sensed by comparing the difference in delay time between the reference delay line and the external reference clock through a time to digital converter (TDC), which is a time sensing circuit. However, using an external clock is not only limited to applications requiring various clock frequencies, but also has a disadvantage of being sensitive to external noise.

2 applies a method including an analog bias circuit. In FIG. 2, a temperature sensitive delay line is provided in the same manner as in FIG. 1, but a temperature-insensitive delay line is used instead of an external reference clock. The temperature-independent delay line includes a plurality of NMOS transistors and PMOS transistors respectively connected to CMOS transistors, and these are connected to analog bias circuits, respectively. Each of these delay lines is compared through a time sensing circuit. However, in the case of FIG. 2, there is a problem that not only increases the design complexity but also causes an increase in power consumption due to the standby current of the bias circuit.

In this regard, Korean Patent Laid-Open Publication No. 2006-0122193 (name of the invention: a semiconductor temperature sensor capable of adjusting a sensing temperature) discloses a temperature sensor of a semiconductor device capable of linearly adjusting a sensing temperature.

However, the temperature sensing method according to the prior art has a problem in that the application field is limited, has instability against external noise, and the design is complicated and the power consumption is large. Therefore, it is necessary to solve the above problems by designing a transistor depending on the design variable of the internal transistor.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and some embodiments of the present invention provide a ring oscillator having a temperature-sensitive delay time by varying the gate channel length of the transistor and a ring having a temperature-insensitive delay time. An object of the present invention is to provide a temperature sensing device and a temperature sensing method for sensing a temperature of a semiconductor by measuring a delay time difference through an oscillator.

As a technical means for achieving the above-described technical problem, the temperature sensing device according to the first aspect of the present invention is a first clock that delays an input signal through a ring oscillator including one or more transistors connected in series having a first delay time A first clock signal output unit for outputting a signal, a second clock signal output unit for outputting a second clock signal delayed by the input signal through a ring oscillator including one or more transistors connected in series having a second delay time, and the Receiving a second clock signal, and comprises a plurality of buffers having a unit delay time, and includes a digital signal output unit for outputting the value of the second clock signal corresponding to the case where the first clock signal rises as a digital signal Wherein, the first delay time and the second delay time is a transistor included in the first clock signal output unit And a gate channel length of a transistor included in the second clock signal output unit and a gate channel length of the transistor included in the second clock signal output unit, wherein the first clock signal output unit has a temperature change sensitivity greater than that of the second clock signal output unit. The clock signal is set such that the transition time is equal to the first clock signal at a preset reference temperature.

In addition, the temperature sensing method using the temperature sensing apparatus according to the second aspect of the present invention outputs the first clock signal and the second clock signal by delaying the input signal at the first clock signal output unit and the second clock signal output unit. In the digital signal output unit including a plurality of buffers having a unit delay time to delay the second clock signal, receiving the first clock signal and the second clock signal, the digital signal output unit Delaying the second clock signal and outputting, by the digital signal output unit, a value of a second clock signal corresponding to when the first clock signal rises and transitions as a digital signal; The output portion includes a ring oscillator including one or more transistors connected in series with a first delay time, wherein the second clock signal The output section includes a ring oscillator including one or more transistors connected in series with a second delay time, wherein the first clock signal output section has a higher temperature change sensitivity than the second clock signal output section, and the second clock signal includes the The transition time is set equal to the first clock signal at the preset reference temperature.

According to one embodiment of the above-described problem solving means of the present invention, the temperature dependence of the delay time of the inverter can be controlled by adjusting the channel length of the gate.

In addition, the use of bias circuits and external clocks can be used to reduce the design demand of additional circuits, thereby reducing design costs and reducing the cross-sectional area of the circuit.

1 and 2 are views showing a temperature sensor according to the prior art.

3 is a block diagram of a temperature sensing device according to an embodiment of the present invention.

4 is a diagram illustrating a MOSFET structure having different gate channel lengths.

5 is a graph showing the change in the normalized delay time with respect to the temperature change with the NMOS gate channel length.

6 is a circuit diagram of a temperature sensing device according to an embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a connection between a first and a second clock signal output unit, a first amplifier, and a second amplifier.

8A and 8B are graphs showing the period difference between the first clock signal and the second clock signal before and after the first and second amplifiers are connected.

FIG. 9 is a diagram illustrating an example of a circuit diagram in which a first unit time delay unit, a second unit time delay unit, and a clock signal transfer unit are connected to each other.

10 is a diagram illustrating operating characteristics of a clock signal in a first unit time delay unit and a second unit time delay unit.

11 is a flowchart illustrating a method for detecting a temperature using a temperature sensing device according to an embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless otherwise stated.

3 is a block diagram of a temperature sensing apparatus 100 according to an embodiment of the present invention.

The temperature sensing device 100 according to the present invention includes a first clock signal output unit 110, a second clock signal output unit 120, and a digital signal output unit 150.

For reference, components shown in FIG. 3 according to an embodiment of the present invention mean software components or hardware components such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), and perform predetermined roles. .

However, 'components' are not meant to be limited to software or hardware, and each component may be configured to be in an addressable storage medium or may be configured to reproduce one or more processors.

Thus, as an example, a component may include components such as software components, object-oriented software components, class components, and task components, and processes, functions, properties, procedures, and subs. Routines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.

Components and the functionality provided within those components may be combined into a smaller number of components or further separated into additional components.

The first clock signal output unit 110 outputs a first clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series having a first delay time.

The second clock signal output unit 120 outputs a second clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series having a second delay time.

Meanwhile, the first delay time is determined based on the gate channel length of the transistor included in the first clock signal output unit 110. The second delay time is determined based on the gate channel length of the transistor included in the second clock signal output unit 120. In this case, the gate channel length of the transistor included in the first clock signal output unit is longer than the gate channel length of the transistor included in the second clock signal output unit 120. The first clock signal and the second clock signal are set to have the same transition time at a preset reference temperature.

Specifically, the longer the gate channel length of the transistor included in the ring oscillator, the greater the temperature change sensitivity, and the shorter the gate channel length of the transistor included in the ring oscillator, the smaller the temperature change sensitivity.

Accordingly, the first clock signal output unit has a greater temperature change sensitivity than the second clock signal output unit. That is, since the gate channel length of the transistor included in the first clock signal output unit is formed longer than the gate channel length of the transistor included in the second clock signal output unit, the ring oscillator of the first clock signal output unit may generate a second clock signal. The temperature oscillation sensitivity is higher than the output ring oscillator.

Hereinafter, the first clock signal output unit 110 and the second clock signal output unit 120 will be described in detail with reference to FIGS. 4 to 6.

4 is a diagram illustrating a MOSFET structure having different gate channel lengths, and the temperature dependence of the transistor current according to the gate channel length of the MOSFET will be described as follows.

When forming a MOSFET structure, structural neutral defects are generated by physical collisions between particles during implantation of ions into a source or drain region. In this case, since the pocket ion implantation region has a constant size irrespective of the channel length, as the channel length decreases, the influence of the neutral scattering caused by the pocket ion implantation is increased. If the length of the region occupied by the neutral defect is L _n , the channel length of the MOSFET with the short gate channel length is L _s , the channel length of the MOSFET with the long gate channel length is L _b , and the width of each of the two MOSFETs is W, The ratio of the neutral defects of the two MOSFETs can be compared as shown in [Equation 2].

[Equation 2]

According to the Matheson law, independent scattering phenomena can be combined to represent mobility (μ) as shown in Equation 3, where T is absolute temperature, μ _c is mobility due to Coulomb scattering, and _p is phonon scattering. The mobility by and _n represent the mobility due to neutral scattering, respectively.

[Equation 3]

As such, the scattering of carrier mobility is independently influenced by three factors, ie, coulomb scattering, phonon scattering, and neutral scattering. In addition, the shorter the gate channel length is dominated by the neutral scattering, the longer the gate channel length is dominated by the phonon scattering.

Therefore, the longer the channel length, the phonon scattering becomes a major factor, so that a sensitive change occurs with temperature. On the other hand, shorter channel lengths cause neutral scattering to be a major factor, resulting in insensitive changes in temperature. As such, the shorter the channel length, the smaller the tendency of the carrier mobility to decrease with temperature change.

This phenomenon affects the temperature dependence of transistor current and the delay time of CMOS. At this time, the current of the transistor is proportional to the carrier mobility as shown in [Equation 4].

[Equation 4]

The temperature dependence of this current also affects the temperature dependence of the CMOS delay time. k _N and k _P denote transconductances of NMOS and PMOS, respectively, and when C _ox is NMOS, capacitance of PMOS oxide, μ _N is electron mobility, and μ _P is hole mobility, as shown in [Equation 5] Can be represented.

[Equation 5]

In addition, V _TN and V _TP refer to threshold voltages of the NMOS and the PMOS, respectively. Therefore, the CMOS delay time can be expressed as shown in [Equation 6].

[Equation 6]

As described above, since the temperature dependence of the transistor current affects the temperature dependence of the CMOS delay time, the temperature sensing device 100 according to the present invention can control the temperature dependency of the delay time of the CMOS inverter according to the channel length of the gate. have.

Referring to FIG. 5, when the gate channel length is the longest (3.50 um), the normalized delay time is increased by 30.32% at 100 degrees to 0 degrees, and thus the increase rate of the delay time with respect to the temperature increase is large. On the other hand, when the gate channel length is the smallest (0.11um), the normalized delay time is increased by 9.62% at 100 degrees compared to 0 degrees, indicating that the increase rate of delay time for temperature increase is small.

Referring back to FIG. 3, the digital signal output unit 150 receives a second clock signal and includes a plurality of buffers having a unit delay time. The second clock signal corresponding to the rising edge of the first clock signal is output as a digital signal. In this case, the second clock signal is set to have the same transition time at the preset reference temperature with the first clock signal.

Hereinafter, the temperature sensing apparatus 100 will be described in detail with reference to FIGS. 6 to 11.

6 is a circuit diagram of a temperature sensing device 100 according to an embodiment of the present invention.

The first clock signal output unit 110 outputs a first clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series. In this case, the ring oscillator may include one or more transistors connected in series M, and the input terminal of the first transistor and the output terminal of the M th transistor of the M series connected transistors may be connected in series.

The second clock signal output unit 120 outputs a second clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series. In this case, the ring oscillator may include N or more transistors connected in series. The input terminal of the first transistor and the output terminal of the Nth transistor of the N series connected transistors may be connected in series with each other.

In this case, the transistors of the first clock signal output unit 110 and the second clock signal output unit 120 may be CMOS inverters.

Meanwhile, the temperature sensing device 100 according to the present invention may further include a first amplifier 130 and a second amplifier 140. The first amplifier 130 and the second amplifier 140 will be described with reference to FIGS. 7 and 8 as follows.

FIG. 7 is a diagram illustrating a circuit diagram in which a first clock signal output unit 110 and a second clock signal output unit 120, a first amplifier 130, and a second amplifier 140 are connected. A graph showing a period difference between the first clock signal and the second clock signal before and after the amplifier 130 and the second amplifier 140 are connected.

First, referring to FIG. 7, the first amplifier 130 may amplify the period of the first clock signal, and the second amplifier 140 may amplify the period of the second clock signal. The first amplifying unit 130 and the second amplifying unit 140 may each include one or more D-flip flops connected in series.

The first clock signal and the second clock signal are applied to the CLK terminal of the D flip-flop, and QB is connected to the input terminal D. The D-flip-flop outputs a signal having a period twice that of the clock signal period applied to the CLK stage because the output stage Q is shifted when the clock signal rises. By using this, the period of the first clock signal and the second clock signal output from the ring oscillator of the first clock signal output unit 110 and the second clock signal output unit 120 may be amplified.

Meanwhile, the first clock signal output unit 110 may include a ring oscillator having a large gate channel length composed of M CMOS inverters, and the second clock signal output unit 120 may include a gate channel length composed of N CMOS inverters. May comprise a short ring oscillator. In this case, the period difference between the first clock signal and the second clock signal may be represented by M · β-N · α.

In order to achieve high resolution, setting the values of M and N largely may cause inefficiency of the chip area. Therefore, the first amplifier 130 and the second amplifier 140 are connected in series by x. The period difference between the two clock signals can be amplified as shown in [Equation 7].

[Equation 7]

Referring to FIG. 8A, the period difference between the first clock signal and the second clock signal is about 2.3 ns at 100 degrees to 0 degrees. In contrast, referring to FIG. 8B, the period difference between the first clock signal and the second clock signal passed through the first amplifier 130 and the second amplifier 140 is about 3.5 ns at 0 degrees and about 100 ns at 100 degrees. The difference of 72.6ns is shown to be amplified about 32 times before and after amplification. By converting such a difference in linear delay time into a digital output, the temperature sensing device 100 according to the present invention may sense the temperature through the digital signal output unit 150 to be described below.

Referring back to FIG. 6, the digital signal output unit 150 receives the first clock signal and the second clock signal, and delays the second clock signal with the first unit time delay unit 151 and the second unit time. The delay unit 155 may be included.

The first unit time delay unit 151 may delay the second clock signal through a plurality of buffers having the first unit delay time. The second unit time delay unit 155 may delay the second clock signal through a plurality of buffers having a second unit delay time. In this case, the first unit delay time is greater than the second unit delay time, and the first unit time delay unit 151 and the second unit time delay unit 155 correspond to the second clock signal when the first clock signal rises and transitions. The value of the clock signal can be output as a digital signal.

Meanwhile, the temperature sensing device 100 according to the present invention may further include a clock signal transmitter 153. The clock signal transfer unit 153 transmits the second clock signal to the second unit time delay unit 155 when the delay time of the second clock signal corresponding to the rising edge of the first clock signal is less than the first unit delay time. ) Can be delivered.

Hereinafter, the first unit time delay unit 151, the second unit time delay unit 155, and the clock signal transfer unit 153 will be described in detail with reference to FIGS. 9 and 10.

FIG. 9 is a diagram illustrating an example of a circuit diagram in which a first unit time delay unit 151, a second unit time delay unit 155, and a clock signal transfer unit 153 are connected to each other, and FIG. 10 is a first unit. FIG. 5 illustrates the operation characteristics of the clock signal in the time delay unit 151 and the second unit time delay unit 155.

Referring to FIG. 9, the first unit time delay unit 151 includes a plurality of buffers and D-flip flops. A plurality of buffers are connected to each other so as to transfer the second clock signal amplified to the D stage of the D-flip flop, and the amplified first clock signal is applied to the CLK stage of the D-flip flop to rise. The delayed time through the buffer is output through the Q stage of each D-flip flop. On the other hand, between the buffer and the D-flip-flop includes a line connected to the clock signal transmission unit 153, respectively, through which a delay time smaller than the first unit delay time to the second unit time delay unit 155 I can deliver it. The configuration of the buffer and the D-flip-flop may be similarly formed in the second unit time delay unit 155.

The plurality of buffers included in the first unit time delay unit 151 may have a delay time of 10a, and the plurality of buffers included in the second unit time delay unit 155 may have a delay time of a.

In this case, since the first unit time delay unit 151 may have a time resolution of 10a per cell, the first unit time delay unit 151 may detect a difference in delay time between two clock signals in a large time unit. The amplified first clock signal received by the first unit time delay unit 151 is applied to the CLK stage of the D-flip-flop, and the second clock signal has a delay time of 10a for each stage and D_C [0: 8] Signal is applied to the input of the D-flip flop. As a result, the delay time difference between the first clock signal and the second clock signal is converted into Q_C [0: 8] having a resolution of a large time unit of 10a and output.

The clock signal transfer unit 153 combines Q_C [0: 8] and D_C [0: 8] into logic circuits to determine the remaining time that is not detected by the time resolution unit 10a of the first unit time delay unit 151. It transfers to the second unit time delay unit 155. Therefore, the clock delay time difference of 10a or less is converted by the second unit time delay unit 155 into the output Q_F [0: 8] having a resolution of a small time unit of a.

Meanwhile, a process of outputting a digital signal from the second unit time delay unit 155 will be described below. The amplified second clock signal is set to have a transition time with the first clock signal at the lowest operating temperature condition, and is delayed by a each time it passes through a buffer.

The input signal D <0> of CELL <0> is delayed by a in the amplified second clock signal, and the input signal D <1> of CELL <1> is delayed by 2a in the amplified second clock signal. Therefore, at D <8> which is the input at the last stage, it is delayed by 9a. When the first clock signal applied to the D-flip-flop CLK stage of each CELL rises and transitions, the output Q_F [0: 8] at the lowest operating temperature has a value of [000000000]. Under high operating temperature conditions, the amplified first clock signal has a larger delay time than the amplified second clock signal. Therefore, assuming that the rising transition time of the second clock signal and the rising transition time of the first clock signal have a difference of 10a or more at the highest operating temperature condition, the output Q_F [0: 8] has a value of [111111111]. .

As such, when any temperature has a value between a low operating temperature and a high operating temperature, the degree of temperature change may appear as a change in the digital output. For example, when the delay time between the first clock signal and the second clock signal has a difference of 2a or more and 3a or less, the output value Q_F [0: 8] may have a value of [111000000]. Such an operation principle may be applied to the first unit time delay unit 151, and the first unit time delay unit 151 has a larger time resolution than the second unit time delay unit 155, so that Will output the value.

Next, referring to FIG. 10 to describe an operation characteristic of a clock signal, a residual time that is not detected by the first unit time delay unit 151 may be a small time unit in the second unit time delay unit 155. It is output after being converted into digital code through sensing.

Accordingly, the digital signal output unit 150 including the n first unit time delay units 151 and the n second unit time delay units 155 has a time difference of 100a (n + 1) and has ^two bits of digital. Can be output as a signal. Therefore, since the number of output nodes is reduced in the temperature sensing device 100 according to the present invention, the chip cross-sectional area can be reduced and high resolution can be realized.

11 is a flowchart of a method for sensing a temperature using the temperature sensing device 100 according to an embodiment of the present invention.

In the temperature sensing method according to the present invention, first, after receiving an input signal from the first clock signal output unit 110 and the second clock signal output unit 120, the first and second clock signals are delayed by delaying the input signal. Output a signal (S110).

The first clock signal output unit 110 outputs a first clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series having a first delay time. In addition, the second clock signal output unit 120 outputs a second clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series having a second delay time.

In this case, the gate channel length of the transistor included in the first clock signal output unit 110 is longer than the gate channel length of the transistor included in the second clock signal output unit 120. The second clock signal is set such that the transition time is the same as the first clock signal at a preset reference temperature.

On the other hand, the temperature sensing method according to the present invention may further include amplifying the period of the delayed first clock signal and amplifying the period of the delayed second clock signal (S120). In this case, the amplification of each clock signal period is amplified through one or more D-flip flops each connected in series. Since amplifying the periods of the first clock signal and the second clock signal has been described in detail with reference to FIGS. 7 and 8, the description thereof will be omitted below.

Next, in order to delay the second clock signal, the digital signal output unit 150 including the plurality of buffers having a unit delay time receives the first clock signal and the second clock signal (S130), and the digital signal output unit. 150 delays the second clock signal (S140).

Next, the digital signal output unit 150 outputs the value of the second clock signal corresponding to the case where the first clock signal rises or shifts as a digital signal (S150).

In this case, the digital signal output unit 150 includes a first unit time delay unit 151 including a plurality of buffers having a first unit delay time and a second unit time including a plurality of buffers having a second unit delay time. The delay unit 155 may further include. Accordingly, the step of delaying the second clock signal by the digital signal output unit 150 may include delaying the second clock signal by the first unit time delay unit 151 and second by the second unit time delay unit 155. Delaying the clock signal may be further included. In this case, the first unit delay time may be greater than the second unit delay time.

In addition, the temperature sensing method according to the present invention outputs the value of the second clock signal as a digital signal when the first clock signal rises and shifts in the first unit time delay unit 151, and the second unit time delay unit. In operation 155, the method may further include outputting a value of the second clock signal as a digital signal when the first clock signal rises or shifts.

In this case, when the delay time of the second clock signal corresponding to the rising edge of the first clock signal is less than the first unit delay time, the second clock signal may be transmitted to the second unit time delay unit 155.

Meanwhile, a description of the step of transferring the first unit time delay unit 151, the second unit time delay unit 155, and the second clock signal to the second unit time delay unit 155 is described with reference to FIGS. 9 and 10. As it described in detail, it will be omitted below.

The foregoing description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined form.

The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

Claims

In the temperature sensing device,

A first clock signal output unit configured to output a first clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series having a first delay time;

A second clock signal output unit configured to output a second clock signal delayed by the input signal through a ring oscillator including one or more transistors connected in series having a second delay time;

A digital signal output unit configured to receive the second clock signal and include a plurality of buffers having a unit delay time, and output a value of a second clock signal corresponding to the rising edge of the first clock signal as a digital signal; Including,

The first delay time and the second delay time are determined according to a gate channel length of a transistor included in the first clock signal output unit and a gate channel length of a transistor included in the second clock signal output unit,

The first clock signal output unit has a greater temperature change sensitivity than the second clock signal output unit,

And the second clock signal is set such that a transition time is equal to the first clock signal at a preset reference temperature.
The method of claim 1,

The first clock signal output unit includes one or more transistors connected in series M,

The input terminal of the first transistor and the output terminal of the M-th transistor is connected in series with each other.
The method of claim 1,

The second clock signal output unit includes one or more transistors connected in series N,

The input terminal of the first transistor and the output terminal of the N-th transistor is connected in series with each other.
The method of claim 1,

A first amplifier for amplifying the period of the first clock signal;

Further comprising a second amplifier for amplifying the period of the second clock signal,

Wherein the first amplifying unit and the second amplifying unit each include one or more D-flip flops connected in series.
The method of claim 1,

The digital signal output unit may receive the second clock signal through a first unit time delay unit for delaying the second clock signal through a plurality of buffers having a first unit delay time and a plurality of buffers having a second unit delay time. A second unit time delay unit for delaying;

The first unit delay time is greater than the second unit delay time,

And the first unit time delay unit and the second unit time delay unit respectively output values of the second clock signal corresponding to the case where the first clock signal rises as a digital signal.
The method of claim 5,

A clock signal transfer unit configured to transfer the second clock signal to the second unit time delay unit when the delay time of the second clock signal corresponding to the rising edge of the first clock signal is less than the first unit delay time Further comprising a temperature sensing device.
In the method for sensing the temperature using the temperature sensing device,

Delaying an input signal at the first clock signal output unit and the second clock signal output unit to output the first clock signal and the second clock signal;

Receiving the first clock signal and the second clock signal at a digital signal output unit including a plurality of buffers having a unit delay time to delay the second clock signal;

Delaying the second clock signal by the digital signal output unit; and

And outputting, by the digital signal output unit, a value of a second clock signal corresponding to the case where the first clock signal rises or shifts as a digital signal.

The first clock signal output includes a ring oscillator including one or more transistors connected in series with a first delay time, and the second clock signal output includes a ring oscillator including one or more transistors in series with a second delay time. Including;

The first clock signal output unit has a greater temperature change sensitivity than the second clock signal output unit,

And wherein the second clock signal is set such that a transition time is the same at a preset reference temperature with the first clock signal.
The method of claim 7, wherein

Delaying the second clock signal by the digital signal output unit,

Delaying the second clock signal in a first unit time delay unit including a plurality of buffers having a first unit delay time; and

Delaying the second clock signal in a second unit time delay unit including a plurality of buffers having a second unit delay time,

The digital signal output unit includes the first unit time delay unit and the second unit time delay unit,

And wherein the first unit delay time is greater than the second unit delay time.
The method of claim 8,

The step of outputting the value of the second clock signal corresponding to the case where the first clock signal rises as a digital signal,

Outputting a value of a second clock signal corresponding to the case where the first clock signal rises and shifts in the first unit time delay unit as a digital signal; and

And outputting a value of a second clock signal corresponding to the case where the first clock signal rises by the second unit time delay unit as a digital signal.
The method of claim 8,

And transmitting the second clock signal to the second unit time delay unit when the delay time of the second clock signal corresponding to the rising of the first clock signal is less than the first unit delay time. Temperature sensing method.