KR20030054201A - Interface circuit with high frequency clock of semiconductor memory device - Google Patents

Abstract

PURPOSE: An interface circuit of a memory apparatus using a high frequency clock is provided to reduce the noise due to a setup/hold time violation by using an enable signal generating unit and a control unit. CONSTITUTION: A first internal delay unit(530) receives and delays a data enable signal(DEN) in response to a reference clock signal(CLK) to generate an initial delay data enable signal(PDEN). An enable signal generating unit(550) receives the initial delay data enable signal(PDEN) to generate a delay data enable signal(ENX) delaying an active section of the initial delay data enable signal(PDEN) for a predetermined time. A second internal delay unit(540) receives and delays a data signal(DATA) in response to the reference clock signal(CLK) to generate an initial delay data signal(PDDATA). A data delay control unit(560) receives the initial delay data signal(PDDATA) and responds to a first control signal(CS1) and a second control signal(CS2) to generate a delay data signal(DATAX) delaying the initial delay data signal(PDDATA) for a predetermined time. A transmitting unit(570) receives the delay data signal(DATAX) and responds to the delay data enable signal(PDEN) to apply the delay data signal(DATAX) to a pad(580).

Description

Interface circuit with high frequency clock of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device. In particular, the set-up time of the output data signal and the data enable signal that may occur in a bi-direction pad of a high frequency semiconductor memory and the delay of the pad may be set up. The present invention relates to a noise prevention interface circuit for removing noise caused by violation of time and hold time.

Synchronous Dynamic Random Access Memory (SDRAM) operates in synchronization with the system clock, and the movement of data between the system and memory is faster than DRAM due to the operation of interleaved cell banks and burst modes. Fast and efficient Therefore, it is suitable for multimedia systems that require a large amount of data processing. However, as the system clock becomes higher and higher in frequency, the setup and hold in relation to the input clock of the synchronous DRAM (SDRAM) with respect to the bi-directional pin of the chip connected to the data pin of the synchronous DRAM (SDRAM) There is less margin for setup / hold time violations. In addition, the PAD delay of bi-directional pins takes up a relatively large proportion of the period of the high frequency clock, and as the size and integration of the designed system increase, the bidirectional pins (PAD delay) There is considerable difficulty in matching the internal delay to the pad between the data on the bi-directional pin and the data enable signal. The difference between the data of the bi-directional pin and the internal delay of the data enable signal is relatively high in the clock cycle of high frequency and writes data to the actual synchronous DRAM (SDRAM). There is a problem in that incorrect data can be written to the synchronous DRAM (SDRAM) by causing a setup / hold time violation.

1 is a diagram illustrating an interface circuit connected to bidirectional pads of a conventional synchronous DRAM.

Referring to FIG. 1, the conventional interface circuit 100 includes flip flops 110 and 120, a first internal delay unit 130, a second internal delay unit 140, a transmitter 150, and a bidirectional pad. And 160.

The flip flop 110 receives the data enable signal DEN in response to the reference clock signal CLK and applies it to the first internal delay unit 130. The flip flop 120 receives the data signal DATA in response to the reference clock signal CLK and applies it to the second internal delay unit 140.

The first internal delay unit 130 receives the data enable signal DEN from the flip flop 110 and delays it to generate an initial delay data enable signal PDDATA. The second internal delay unit 140 receives the data signal DATA from the flip flop 120 and delays it to generate an initial delay data signal PDDATA. The transmitter 150 receives the initial delay data signal PDDATA in response to the initial delay data enable signal PDEN, applies the initial delay data signal PDDATA to the bidirectional pad 160, and the bidirectional pad 160 receives the initial delay data signal PDDATA. ) Is applied to the synchronous DRAM (not shown).

The operation of the conventional interface circuit 100 will be described.

In the operation of writing the data signal DATA to the synchronous DRAM (not shown) in the system (not shown), the data signal DATA is positive in a period where the initial delay data enable signal PDEN signal is low level in FIG. 1. It exits to the output of the directional pad 160. At this time, since the data enable signal DEN and the data signal DATA are generated in response to the same reference clock signal CLK, a setup / hold time violation occurs when the internal delays of the two signals are the same. Normally, the reference clock signal CLK and the data signal DATA are inputted to the pin of the synchronous DRAM (not shown) to perform a memory operation. However, as the size and density of the designed system increases, it becomes difficult to equalize the internal delay from the data enable signal DEN to the bidirectional pad 160 of the data signal DATA during logic synthesis. The difference between the internal delays of the two signals is that when the reference clock signal CLK becomes a high frequency, the portion of the reference clock signal CLK increases, so that the input of the synchronous DRAM (not shown) becomes large. The phase difference between the reference clock signal CLK and the output data OUT of the output terminal of the two-way pad 160 may cause a setup / hold time violation.

FIG. 2 is an operation timing diagram when an internal delay of the data enable signal of FIG. 1 is greater than an internal delay of the data signal.

Here, d1 represents the output of the initial delay data signal PDDATA at the falling edge of the initial delay data enable signal PDEN, and d2 represents the initial state in the stable section of the initial delay data enable signal PDEN. The output of the delay data signal PDDATA is shown, and d3 represents the output of the initial delay data signal PDDATA at the rising edge of the initial delay data enable signal PDEN. In addition, the bidirectional pad 160 has a characteristic of d1> d2> d3.

When the internal delay of the data enable signal DEN is greater than the internal delay of the data signal DATA, the initial delay data enable signal PDEN in which Q0 of the initial delay data signal PDDATA is delayed. Is enabled late by and is output by a relatively large pad delay d1, so that the output data OUT of the two-way pad 160 is phased when latched at the positive edge of the high frequency reference clock signal CLK. In this case, the setup time is not satisfied, and therefore, the data write operation cannot be normally performed in the synchronous DRAM (not shown).

3 is an operation timing diagram when an internal delay of the data enable signal of FIG. 1 is smaller than an internal delay of the data signal.

When the internal delay of the data enable signal DEN is smaller than the internal delay of the data signal DATA, the output data OUT of the two-way pad 160 is invalid before Q0. There may occur a case where the section of the data signal DATA may be output as the output data OUT of the two-way pad 160, and the setup time may not be satisfied due to the delay of the output data OUT. Can be.

4 is an operation timing diagram when the output time of the initial delay data signal PDDATA on the rising edge of the initial delay data enable signal PDEN is short.

Since the delay d3 at the positive edge of the initial delay data enable signal PDEN has a relatively smaller value than d1 and d2, the last data Q3 of the initial delay data signal PDDATA is sufficient. If the initial delay data enable signal PDEN goes up to a high level before the output delay, the output data OUT of Q3 does not satisfy the hold time. At this time, when the output data (OUT) is changed to the high impedance state at Q3, if the hold time condition is not satisfied, noise may be generated at this portion, and the noise of the synchronous DRAM (not shown) is latched as it is. You may have a problem.

Accordingly, the present invention provides a data signal DATA and a data enable signal of a bi-directional pin of a pad interface circuit with a synchronous DRAM (not shown) that may be generated by using a high frequency clock. In order to prevent the difference in the internal delay of EN) and the setup / hold time violation, the addition of a predetermined enable signal generator and a data delay controller are added to the interface circuit.

The technical problem to be achieved by the present invention is a set up time due to the effects of the phase difference between the output data signal and the data enable signal and the delay of the pad which may occur in the bi-direction pad of the high frequency semiconductor memory. And an interface circuit for noise prevention to remove noise caused by a violation of the "

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating an interface circuit connected to bidirectional pads of a conventional synchronous DRAM.

FIG. 2 is an operation timing diagram when an internal delay of the data enable signal of FIG. 1 is greater than an internal delay of the data signal.

3 is an operation timing diagram when an internal delay of the data enable signal of FIG. 1 is smaller than an internal delay of the data signal.

4 is an operation timing diagram when the output time of the initial delay data signal on the rising edge of the initial delay data enable signal is short.

5 illustrates an interface circuit according to the present invention.

FIG. 6 is a diagram illustrating a data delay controller of FIG. 5.

7 is a timing diagram illustrating an operation of the interface circuit of FIG. 5.

According to an aspect of the present invention, an interface circuit includes a first internal delay unit, an enable signal generator, a second internal delay unit, a data delay controller, and a transmitter.

The first internal delay unit receives and delays the data enable signal in response to the reference clock signal to generate an initial delay data enable signal. The enable signal generator receives the initial delay data enable signal and generates a delay data enable signal for delaying an active section of the initial delay data enable signal for a predetermined time.

The second internal delay unit receives and delays the data signal in response to the reference clock signal to generate an initial delay data signal. The data delay control unit receives the initial delay data signal and generates a delay data signal in which the initial delay data signal is delayed for a predetermined time in response to the first and second control signals.

The transmitter receives the delay data signal and applies the delay data signal to the pad in response to the delay data enable signal.

The first and second internal delay units have the same delay time.

Preferably, the data delay controller selects one of a first delay element that receives and delays the initial delay data signal, and an output signal of the initial delay data signal and the first delay element in response to the first control signal. First selecting means for outputting, second to n-th delay elements connected in series for receiving and delaying an output signal of the first selecting means, and the first selecting means and the second to second responses in response to the second control signal. and second selecting means for selecting one of the output signals of each of the n delay elements to generate the delay data signal.

The enable signal generator may receive the initial delay data enable signal and delay the initial delay data enable signal for a predetermined time in response to the first and second control signals. And logical AND means for generating the delayed data enable signal by ANDing the output signal of the enable signal delay controller and the initial delayed data enable signal.

The enable signal delay control unit may include a first delay element configured to receive and delay the initial delay data enable signal, and among the initial delay data enable signal and an output signal of the first delay element in response to the first control signal. First selection means for selecting and outputting one, second to mth delay elements connected in series for receiving and delaying an output signal of the first selection means, and the first selection means and the response in response to the second control signal. And second selecting means for selecting one of the output signals of each of the second to mth delay elements to generate the delay data enable signal.

The transmitter is a tri-state buffer for receiving the delay data signal in response to the delay data enable signal and applying it to a pad.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

5 illustrates an interface circuit according to the present invention.

FIG. 6 is a diagram illustrating a data delay controller of FIG. 5.

5 and 6, the noise preventing interface circuit 500 according to the present invention includes a first internal delay unit 530, an enable signal generator 550, a second internal delay unit 540, and a data delay. And a control unit 560 and a transmission unit 570.

The first internal delay unit 530 receives and delays the data enable signal DEN in response to the reference clock signal CLK to generate an initial delay data enable signal PDEN. The enable signal generator 550 receives the initial delay data enable signal PDEN and generates a delay data enable signal ENX that delays the active section of the initial delay data enable signal PDEN for a predetermined time. .

The second internal delay unit 540 receives and delays the data signal DATA in response to the reference clock signal CLK to generate the initial delay data signal PDDATA. The data delay control unit 560 receives the initial delay data signal PDDATA and delays the initial delay data signal PDDATA for a predetermined time in response to the first and second control signals CS1 and CS2. Will occur).

The first and second internal delay units 530 and 540 have the same delay time.

The data delay control unit 560 receives a first delay element DD1 for receiving and delaying an initial delay data signal PDDATA, an initial delay data signal PDDATA, and a first delay element in response to the first control signal CS1. First selecting means 610 for selecting and outputting one of the output signals of DD1, and second to nth delay elements DD2, DD3 to DDn connected in series for receiving and delaying the output signal of the first selecting means 610 ) And one of the output signals of each of the first selection means 610 and the second to nth delay elements DD2 and DD3 to DDn in response to the second control signal CS2 to delay data signal DATAX. And a second selecting means 620 to generate as.

Here, the first to nth delay elements DD1, DD2, and DD3 to DDn have the same delay time or different delay times. In addition, the first to nth delay elements DD1, DD2, DD3 to DDn have a sum of delay times of the respective delay elements equal to or less than a period of the reference clock signal CLK.

The first and second selection means 610, 620 may be multiplexers.

The enable signal generator 550 receives the initial delay data enable signal PDEN and generates the initial delay data enable signal PDEN in response to the first and second control signals CS1 and CS2 for a predetermined time. Logical means 595 for generating a delayed data enable signal ENX by performing a logical AND on the output signal of the enable signal delay control unit 590 and the enable signal delay control unit 590 for delaying, and the initial delay data enable signal 9PDEN. ).

Here, the enable signal delay control unit 590 receives a first delay element (not shown) for receiving and delaying an initial delay data enable signal PDEN and an initial delay data enable signal in response to the first control signal CS1. A first selection means (not shown) for selecting and outputting one of a PDEN and an output signal of the first delay element (not shown), and a serially connected device for receiving and delaying an output signal of the first selection means (not shown). Select one of the output signals of each of the first selecting means (not shown) and the second to mth delay elements (not shown) in response to the second to mth delay elements (not shown) and the second control signal CS2. And second selection means (not shown) for generating as a delay data enable signal ENX.

The first to mth delay elements (not shown) may have the same delay time or different delay times. In addition, the first to m-th delay elements (not shown) are characterized in that the sum of the delay times of the respective delay elements is equal to or less than the period of the reference clock signal.

Here, n and m are the same natural number and the first and second selection means (not shown) may be a multiplexer. The first and second control signals CS1 and CS2 may be externally controllable signals.

The transmitter 570 receives the delayed data signal DATAX and applies the delayed data signal DATAX to the pad 580 in response to the delayed data enable signal ENX. In more detail, the transmitter 570 is a tri-state buffer that receives the delay data signal DATAX and applies it to the pad in response to the delay data enable signal ENX.

7 is a timing diagram illustrating an operation of the interface circuit of FIG. 5.

Hereinafter, the operation of the interface circuit 500 according to the present invention will be described with reference to FIGS. 5, 6, and 7.

In the data delay controller 560 of FIG. 6, a delay module may be configured differently according to a reference clock signal CLK of a system in which the interface circuit 500 of the present invention is used. FIG. 6 shows an example of a circuit configuration of the data delay control unit 560. The data delay control unit 560 used in a system using a reference clock signal CLK having a frequency of 135 MHz, that is, a period of 7.4 ns is shown. It is shown. Since the period of the reference clock signal CLK is 7.4 ns, n is 4 and the first delay element DD1 has a delay time of 1 ns, and the second to fourth delay elements DD2 and DD3 to DDn have a length of 2 ns. Has a delay. The number and delay times of the respective delay elements DD1, DD2, DD3 ˜ DDn may vary depending on the period of the reference clock signal CLK of the system in which the interface circuit 500 is used.

The data delay controller 560 may variably adjust the delay time of the initial delay data signal PDDATA within one period of the 135 MHz reference clock signal CLK. The data delay control unit 560 includes two selection means 610 and 620, and a first control signal CS1 and a second control signal CS2 are used as signals for controlling the selection means 610 and 620. . The first control signal CS1 and the second control signal CS2 are signals that can be controlled externally and perform a function of delaying and outputting the initial delay data signal PDDATA by 0 ns to 7 ns according to an externally determined value.

The enable signal generator 550 receives the initial delay data enable signal PDEN to the enable signal delay control unit 590 and receives the delay data enable signal ENX, which is a pulse signal, by the AND product 595. Occurs. The delay width of the enable data signal ENX is determined by the delay elements of the enable signal delay controller 590.

The enable signal delay control unit 590 has the same circuit configuration as the data delay control unit 560, and thus a detailed description thereof will be omitted.

The interface circuit 500 of the present invention adjusts the enable signal generator 550 and the data delay controller 560 to appropriately delay the initial delay data enable signal PDEN and the initial delay data signal PDDATA. It is possible to match the internal delay of the signal and also to avoid setup time and hold time violation of the output data OUT at the bidirectional pad 580.

That is, the timing of each signal is freely adjusted by the enable signal generator 550 and the data delay controller 560 within one period of the reference clock signal CLK, thereby allowing the data signal DATA and the data enable signal ( If the internal delay of any one of the DENs becomes relatively large compared to the period of the high frequency reference clock signal CLK in the logic circuit synthesis process, mutual compensation is possible so that the output of the normal output data OUT is reduced. May have a phase. In addition, the phase difference between the high frequency clock of the asynchronous DRAM (SDRAM) input and the output data OUT, which may be caused by the influence of the PAD delay, can be compensated.

The operation is described in more detail.

As shown in FIG. 2, when an internal delay of the data enable signal DEN is greater than an internal delay of the data signal DATA, when a setup time violation occurs in the output data OUT, the data signal ( DATA is latched as the output data OUT after the delays d1, d2, and d3 by the data enable signal DEN, respectively, so that only the initial delay data signal PDDATA is delayed using the data delay control unit 560. It is difficult to meet the conditions of the setup time. Therefore, in this case, both the initial delay data enable signal PDEN and the initial delay data signal PDDATA must be delayed by using both the data delay control unit 560 and the enable signal delay control unit 590. Can satisfy

As shown in FIG. 3, even when an internal delay of the data enable signal DEN is smaller than an internal delay of the data signal DATA, the setup time violation occurs in the output data OUT. By delaying the initial delay data enable signal PDEN by using the signal delay controller 590, a setup time violation of the output data OUT may be prevented.

As shown in FIG. 4, the output time of the initial delay data signal PDDATA at the rising edge of the initial delay data enable signal PDEN is short, and a hold time violation occurs in the output data OUT. In this case, after delaying the initial delay data enable signal PDEN by using the enable signal delay control unit 550, and using the logical multiplication means 595, the original initial delay data enable signal PDEN and the delayed initial state. By using the delay data enable signal ENX, which is a result of multiplying the delay data enable signal PDEN, the setup and hold time may be satisfied. This is the case when the initial delay data enable signal PDEN is delayed using only the enable signal delay control unit 590 to simply match the hold time of the last output data OUT, as shown in FIG. 2. This is because there is a possibility that a setup time violation may occur in the output data OUT.

By the above operation, using the enable signal generator 550 and the data delay control unit 560, a data enable signal that may be generated at the bi-directional pin of the high frequency synchronous DRAM (SDRAM) ( DEN) and the difference between the internal delay of the data signal DATA and the setup time and hold time violations and the resulting noise can be eliminated.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the noise prevention interface circuit according to the present invention includes a pad and a phase difference between an output data signal and a data enable signal that may occur in a bi-direction pad of a memory device using a high frequency reference clock. There is an advantage in that noise caused by setup and hold time violation due to the effect of PAD delay can be eliminated.

Claims (16)

A first internal delay unit configured to receive and delay a data enable signal in response to a reference clock signal to generate an initial delay data enable signal; An enable signal generator configured to receive the initial delay data enable signal and generate a delay data enable signal for delaying an active section of the initial delay data enable signal for a predetermined time; A second internal delay unit configured to receive and delay a data signal in response to a reference clock signal to generate an initial delay data signal; A data delay control unit for receiving the initial delay data signal and generating a delay data signal for delaying the initial delay data signal for a predetermined time in response to first and second control signals; And a transmitter configured to receive the delay data signal and apply the delay data signal to a pad in response to the delay data enable signal. The method of claim 1, wherein the first and second internal delay unit, Noise prevention interface circuit having the same delay time. The method of claim 1, wherein the data delay control unit, A first delay element receiving and delaying the initial delay data signal; First selecting means for selecting and outputting one of the initial delay data signal and an output signal of the first delay element in response to the first control signal; Second to nth delay elements connected in series for receiving and delaying an output signal of the first selection means; And Second selecting means for selecting one of the first selecting means and output signals of each of the second to nth (n is a natural number of two or more) delay elements in response to the second control signal and generating the delayed data signal; Noise prevention interface circuit comprising a. The method of claim 3, wherein the first to n-th delay elements, Noise prevention interface circuit having the same delay time. The method of claim 3, wherein the first to n-th delay elements, Noise prevention interface circuit having a different delay time. The method of claim 3, wherein the first to n-th delay elements, And a sum of delay times of respective delay elements is equal to or less than a period of the reference clock signal. The method of claim 3, wherein the first and second selection means, Noise prevention interface circuit, characterized in that the multiplexer. The method of claim 1, wherein the enable signal generator, An enable signal delay controller configured to receive the initial delay data enable signal and delay the initial delay data enable signal for a predetermined time in response to the first and second control signals; And And an AND logic means for generating the delayed data enable signal by ANDing the output signal of the enable signal delay controller and the initial delay data enable signal. The method of claim 8, wherein the enable signal delay control unit, A first delay element receiving and delaying the initial delay data enable signal; First selecting means for selecting and outputting one of the initial delay data enable signal and an output signal of the first delay element in response to the first control signal; Second through m-th (m is a natural number of two or more) delay elements connected in series for receiving and delaying the output signal of said first selecting means; And And second selecting means for selecting one of the first selecting means and output signals of each of the second to mth delay elements in response to the second control signal to generate the delay data enable signal. Noise prevention interface circuit. The method of claim 9, wherein the first to m-th delay elements, Noise prevention interface circuit having the same delay time. The method of claim 9, wherein the first to m-th delay elements, Noise prevention interface circuit having a different delay time. The method of claim 9, wherein the first to m-th delay elements, And a sum of delay times of respective delay elements is equal to or less than a period of the reference clock signal. The method of claim 9, wherein the first and second selection means, Noise prevention interface circuit, characterized in that the multiplexer. The method of claim 1, wherein the first and second control signals, Noise control interface circuit, characterized in that the externally controllable signals. The method of claim 1, wherein the transmission unit, And a tri-state buffer configured to receive the delay data signal in response to the delay data enable signal and apply the same to a pad. The method according to claim 3 or 9, And n and m are the same natural number.