WO2015102274A1 - Appareil de détection de température et procédé de détection de température basés sur une dépendance en température du courant en fonction d'une variation de longueur de canal - Google Patents

Appareil de détection de température et procédé de détection de température basés sur une dépendance en température du courant en fonction d'une variation de longueur de canal Download PDF

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WO2015102274A1
WO2015102274A1 PCT/KR2014/012535 KR2014012535W WO2015102274A1 WO 2015102274 A1 WO2015102274 A1 WO 2015102274A1 KR 2014012535 W KR2014012535 W KR 2014012535W WO 2015102274 A1 WO2015102274 A1 WO 2015102274A1
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clock signal
unit
delay time
delay
signal output
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PCT/KR2014/012535
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English (en)
Korean (ko)
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성만영
김진세
장지웅
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고려대학교 산학협력단
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/34—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using capacitative elements
    • G01K7/346—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using capacitative elements for measuring temperature based on the time delay of a signal through a series of logical ports
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/01—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using semiconducting elements having PN junctions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption

Definitions

  • the present invention relates to a temperature sensing device and a temperature sensing method, and more particularly, to a temperature sensing device and a method based on a temperature dependency of a current according to a change in channel length.
  • CMOS processes scale and Moore's law increases the number of transistors per chip exponentially, heat generated per unit area of integrated circuits is increasing. This leads to high power consumption and low reliability of the integrated circuit. Therefore, there is a need for a temperature sensor to monitor thermal characteristics and to compensate for chip performance and operating conditions.
  • the DRAM for example, requires a temperature-sensing sensor that runs at low power. Since the DRAM records information by the amount of charge stored in the capacitor, the electrons are shorted and the stored information is lost. Therefore, the information must be periodically refreshed.
  • the operating frequency of the information reproduction current also increases.
  • the frequency of the information regeneration current of a DRAM without a temperature sensor should be designed based on the highest temperature conditions in the operating temperature range. In other words, the higher the temperature, the higher the leakage current, and thus, the more information reproduction current is required. Therefore, in order to store the information stored by the leakage current without losing it within the operating temperature range, it must be designed in consideration of the minimum requirements.
  • the PTAT Proportional To Absolute Temperature
  • the PTAT voltage has a value proportional to the absolute temperature and a voltage characteristic proportional to the absolute temperature can be obtained by using a ratio of I 1 and I 2 .
  • the thermal voltage proportional to the temperature generated in the PTAT is compared with the reference voltage generated in the bandgap reference through an analog to digital converter (ADC) can detect the temperature change.
  • ADC analog to digital converter
  • a digital temperature sensor was developed, and the temperature was detected by comparing the delay time irrelevant to the temperature and the delay time proportional to the temperature.
  • a temperature sensor according to the related art will be described with reference to FIGS. 1 and 2.
  • FIG. 1 and 2 are views showing a temperature sensor according to the prior art.
  • FIG. 1 illustrates a method using an external clock using a delay time independent of temperature.
  • the circuit diagram shown in FIG. 1 includes a temperature-sensitive delay line including a separate external reference clock (Ref CLK) and a plurality of series-connected CMOS transistors.
  • the temperature can be sensed by comparing the difference in delay time between the reference delay line and the external reference clock through a time to digital converter (TDC), which is a time sensing circuit.
  • TDC time to digital converter
  • FIG. 2 applies a method including an analog bias circuit.
  • a temperature sensitive delay line is provided in the same manner as in FIG. 1, but a temperature-insensitive delay line is used instead of an external reference clock.
  • the temperature-independent delay line includes a plurality of NMOS transistors and PMOS transistors respectively connected to CMOS transistors, and these are connected to analog bias circuits, respectively. Each of these delay lines is compared through a time sensing circuit.
  • FIG. 2 there is a problem that not only increases the design complexity but also causes an increase in power consumption due to the standby current of the bias circuit.
  • Korean Patent Laid-Open Publication No. 2006-0122193 (name of the invention: a semiconductor temperature sensor capable of adjusting a sensing temperature) discloses a temperature sensor of a semiconductor device capable of linearly adjusting a sensing temperature.
  • the temperature sensing method according to the prior art has a problem in that the application field is limited, has instability against external noise, and the design is complicated and the power consumption is large. Therefore, it is necessary to solve the above problems by designing a transistor depending on the design variable of the internal transistor.
  • the present invention solves the above-mentioned problems of the prior art, and some embodiments of the present invention provide a ring oscillator having a temperature-sensitive delay time by varying the gate channel length of the transistor and a ring having a temperature-insensitive delay time.
  • An object of the present invention is to provide a temperature sensing device and a temperature sensing method for sensing a temperature of a semiconductor by measuring a delay time difference through an oscillator.
  • the temperature sensing device is a first clock that delays an input signal through a ring oscillator including one or more transistors connected in series having a first delay time
  • the Receiving a second clock signal and comprises a plurality of buffers having a unit delay time, and includes a digital signal output unit for outputting the value of the second clock signal corresponding to the case where the first clock signal rises as a digital signal
  • the first delay time and the second delay time is a transistor included in the first clock signal output unit And a gate channel length of a transistor included in the second clock signal output unit and a gate channel length of the transistor included in the second clock signal output unit, wherein the first clock signal output unit has a temperature change
  • the temperature sensing method using the temperature sensing apparatus outputs the first clock signal and the second clock signal by delaying the input signal at the first clock signal output unit and the second clock signal output unit.
  • the digital signal output unit including a plurality of buffers having a unit delay time to delay the second clock signal, receiving the first clock signal and the second clock signal, the digital signal output unit Delaying the second clock signal and outputting, by the digital signal output unit, a value of a second clock signal corresponding to when the first clock signal rises and transitions as a digital signal;
  • the output portion includes a ring oscillator including one or more transistors connected in series with a first delay time, wherein the second clock signal
  • the output section includes a ring oscillator including one or more transistors connected in series with a second delay time, wherein the first clock signal output section has a higher temperature change sensitivity than the second clock signal output section, and the second clock signal includes the The transition time is set equal to the first clock signal at the preset reference temperature.
  • the temperature dependence of the delay time of the inverter can be controlled by adjusting the channel length of the gate.
  • bias circuits and external clocks can be used to reduce the design demand of additional circuits, thereby reducing design costs and reducing the cross-sectional area of the circuit.
  • FIG. 1 and 2 are views showing a temperature sensor according to the prior art.
  • FIG. 3 is a block diagram of a temperature sensing device according to an embodiment of the present invention.
  • FIG. 4 is a diagram illustrating a MOSFET structure having different gate channel lengths.
  • FIG. 5 is a graph showing the change in the normalized delay time with respect to the temperature change with the NMOS gate channel length.
  • FIG. 6 is a circuit diagram of a temperature sensing device according to an embodiment of the present invention.
  • FIG. 7 is a circuit diagram illustrating a connection between a first and a second clock signal output unit, a first amplifier, and a second amplifier.
  • 8A and 8B are graphs showing the period difference between the first clock signal and the second clock signal before and after the first and second amplifiers are connected.
  • FIG. 9 is a diagram illustrating an example of a circuit diagram in which a first unit time delay unit, a second unit time delay unit, and a clock signal transfer unit are connected to each other.
  • FIG. 10 is a diagram illustrating operating characteristics of a clock signal in a first unit time delay unit and a second unit time delay unit.
  • FIG. 11 is a flowchart illustrating a method for detecting a temperature using a temperature sensing device according to an embodiment of the present invention.
  • FIG. 3 is a block diagram of a temperature sensing apparatus 100 according to an embodiment of the present invention.
  • the temperature sensing device 100 includes a first clock signal output unit 110, a second clock signal output unit 120, and a digital signal output unit 150.
  • components shown in FIG. 3 mean software components or hardware components such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), and perform predetermined roles. .
  • FPGA field programmable gate array
  • ASIC application specific integrated circuit
  • 'components' are not meant to be limited to software or hardware, and each component may be configured to be in an addressable storage medium or may be configured to reproduce one or more processors.
  • a component may include components such as software components, object-oriented software components, class components, and task components, and processes, functions, properties, procedures, and subs. Routines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables.
  • Components and the functionality provided within those components may be combined into a smaller number of components or further separated into additional components.
  • the first clock signal output unit 110 outputs a first clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series having a first delay time.
  • the second clock signal output unit 120 outputs a second clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series having a second delay time.
  • the first delay time is determined based on the gate channel length of the transistor included in the first clock signal output unit 110.
  • the second delay time is determined based on the gate channel length of the transistor included in the second clock signal output unit 120.
  • the gate channel length of the transistor included in the first clock signal output unit is longer than the gate channel length of the transistor included in the second clock signal output unit 120.
  • the first clock signal and the second clock signal are set to have the same transition time at a preset reference temperature.
  • the first clock signal output unit has a greater temperature change sensitivity than the second clock signal output unit. That is, since the gate channel length of the transistor included in the first clock signal output unit is formed longer than the gate channel length of the transistor included in the second clock signal output unit, the ring oscillator of the first clock signal output unit may generate a second clock signal.
  • the temperature oscillation sensitivity is higher than the output ring oscillator.
  • first clock signal output unit 110 and the second clock signal output unit 120 will be described in detail with reference to FIGS. 4 to 6.
  • FIG. 4 is a diagram illustrating a MOSFET structure having different gate channel lengths, and the temperature dependence of the transistor current according to the gate channel length of the MOSFET will be described as follows.
  • the scattering of carrier mobility is independently influenced by three factors, ie, coulomb scattering, phonon scattering, and neutral scattering.
  • the shorter the gate channel length is dominated by the neutral scattering the longer the gate channel length is dominated by the phonon scattering.
  • the longer the channel length the phonon scattering becomes a major factor, so that a sensitive change occurs with temperature.
  • shorter channel lengths cause neutral scattering to be a major factor, resulting in insensitive changes in temperature.
  • the shorter the channel length the smaller the tendency of the carrier mobility to decrease with temperature change.
  • k N and k P denote transconductances of NMOS and PMOS, respectively, and when C ox is NMOS, capacitance of PMOS oxide, ⁇ N is electron mobility, and ⁇ P is hole mobility, as shown in [Equation 5] Can be represented.
  • V TN and V TP refer to threshold voltages of the NMOS and the PMOS, respectively. Therefore, the CMOS delay time can be expressed as shown in [Equation 6].
  • the temperature sensing device 100 can control the temperature dependency of the delay time of the CMOS inverter according to the channel length of the gate. have.
  • FIG. 5 is a graph showing the change in the normalized delay time with respect to the temperature change with the NMOS gate channel length.
  • the normalized delay time is increased by 30.32% at 100 degrees to 0 degrees, and thus the increase rate of the delay time with respect to the temperature increase is large.
  • the gate channel length is the smallest (0.11um)
  • the normalized delay time is increased by 9.62% at 100 degrees compared to 0 degrees, indicating that the increase rate of delay time for temperature increase is small.
  • the digital signal output unit 150 receives a second clock signal and includes a plurality of buffers having a unit delay time.
  • the second clock signal corresponding to the rising edge of the first clock signal is output as a digital signal.
  • the second clock signal is set to have the same transition time at the preset reference temperature with the first clock signal.
  • FIG. 6 is a circuit diagram of a temperature sensing device 100 according to an embodiment of the present invention.
  • the first clock signal output unit 110 outputs a first clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series.
  • the ring oscillator may include one or more transistors connected in series M, and the input terminal of the first transistor and the output terminal of the M th transistor of the M series connected transistors may be connected in series.
  • the second clock signal output unit 120 outputs a second clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series.
  • the ring oscillator may include N or more transistors connected in series.
  • the input terminal of the first transistor and the output terminal of the Nth transistor of the N series connected transistors may be connected in series with each other.
  • the transistors of the first clock signal output unit 110 and the second clock signal output unit 120 may be CMOS inverters.
  • the temperature sensing device 100 may further include a first amplifier 130 and a second amplifier 140.
  • the first amplifier 130 and the second amplifier 140 will be described with reference to FIGS. 7 and 8 as follows.
  • FIG. 7 is a diagram illustrating a circuit diagram in which a first clock signal output unit 110 and a second clock signal output unit 120, a first amplifier 130, and a second amplifier 140 are connected. A graph showing a period difference between the first clock signal and the second clock signal before and after the amplifier 130 and the second amplifier 140 are connected.
  • the first amplifier 130 may amplify the period of the first clock signal
  • the second amplifier 140 may amplify the period of the second clock signal.
  • the first amplifying unit 130 and the second amplifying unit 140 may each include one or more D-flip flops connected in series.
  • the first clock signal and the second clock signal are applied to the CLK terminal of the D flip-flop, and QB is connected to the input terminal D.
  • the D-flip-flop outputs a signal having a period twice that of the clock signal period applied to the CLK stage because the output stage Q is shifted when the clock signal rises.
  • the period of the first clock signal and the second clock signal output from the ring oscillator of the first clock signal output unit 110 and the second clock signal output unit 120 may be amplified.
  • the first clock signal output unit 110 may include a ring oscillator having a large gate channel length composed of M CMOS inverters
  • the second clock signal output unit 120 may include a gate channel length composed of N CMOS inverters. May comprise a short ring oscillator.
  • the period difference between the first clock signal and the second clock signal may be represented by M ⁇ ⁇ -N ⁇ ⁇ .
  • the first amplifier 130 and the second amplifier 140 are connected in series by x.
  • the period difference between the two clock signals can be amplified as shown in [Equation 7].
  • the period difference between the first clock signal and the second clock signal is about 2.3 ns at 100 degrees to 0 degrees.
  • the period difference between the first clock signal and the second clock signal passed through the first amplifier 130 and the second amplifier 140 is about 3.5 ns at 0 degrees and about 100 ns at 100 degrees.
  • the difference of 72.6ns is shown to be amplified about 32 times before and after amplification.
  • the temperature sensing device 100 may sense the temperature through the digital signal output unit 150 to be described below.
  • the digital signal output unit 150 receives the first clock signal and the second clock signal, and delays the second clock signal with the first unit time delay unit 151 and the second unit time.
  • the delay unit 155 may be included.
  • the first unit time delay unit 151 may delay the second clock signal through a plurality of buffers having the first unit delay time.
  • the second unit time delay unit 155 may delay the second clock signal through a plurality of buffers having a second unit delay time.
  • the first unit delay time is greater than the second unit delay time, and the first unit time delay unit 151 and the second unit time delay unit 155 correspond to the second clock signal when the first clock signal rises and transitions.
  • the value of the clock signal can be output as a digital signal.
  • the temperature sensing device 100 may further include a clock signal transmitter 153.
  • the clock signal transfer unit 153 transmits the second clock signal to the second unit time delay unit 155 when the delay time of the second clock signal corresponding to the rising edge of the first clock signal is less than the first unit delay time. ) Can be delivered.
  • the first unit time delay unit 151 the second unit time delay unit 155, and the clock signal transfer unit 153 will be described in detail with reference to FIGS. 9 and 10.
  • FIG. 9 is a diagram illustrating an example of a circuit diagram in which a first unit time delay unit 151, a second unit time delay unit 155, and a clock signal transfer unit 153 are connected to each other, and FIG. 10 is a first unit.
  • FIG. 5 illustrates the operation characteristics of the clock signal in the time delay unit 151 and the second unit time delay unit 155.
  • the first unit time delay unit 151 includes a plurality of buffers and D-flip flops.
  • a plurality of buffers are connected to each other so as to transfer the second clock signal amplified to the D stage of the D-flip flop, and the amplified first clock signal is applied to the CLK stage of the D-flip flop to rise.
  • the delayed time through the buffer is output through the Q stage of each D-flip flop.
  • between the buffer and the D-flip-flop includes a line connected to the clock signal transmission unit 153, respectively, through which a delay time smaller than the first unit delay time to the second unit time delay unit 155 I can deliver it.
  • the configuration of the buffer and the D-flip-flop may be similarly formed in the second unit time delay unit 155.
  • the plurality of buffers included in the first unit time delay unit 151 may have a delay time of 10a, and the plurality of buffers included in the second unit time delay unit 155 may have a delay time of a.
  • the first unit time delay unit 151 may detect a difference in delay time between two clock signals in a large time unit.
  • the amplified first clock signal received by the first unit time delay unit 151 is applied to the CLK stage of the D-flip-flop, and the second clock signal has a delay time of 10a for each stage and D_C [0: 8] Signal is applied to the input of the D-flip flop.
  • the delay time difference between the first clock signal and the second clock signal is converted into Q_C [0: 8] having a resolution of a large time unit of 10a and output.
  • the clock signal transfer unit 153 combines Q_C [0: 8] and D_C [0: 8] into logic circuits to determine the remaining time that is not detected by the time resolution unit 10a of the first unit time delay unit 151. It transfers to the second unit time delay unit 155. Therefore, the clock delay time difference of 10a or less is converted by the second unit time delay unit 155 into the output Q_F [0: 8] having a resolution of a small time unit of a.
  • the amplified second clock signal is set to have a transition time with the first clock signal at the lowest operating temperature condition, and is delayed by a each time it passes through a buffer.
  • the input signal D ⁇ 0> of CELL ⁇ 0> is delayed by a in the amplified second clock signal, and the input signal D ⁇ 1> of CELL ⁇ 1> is delayed by 2a in the amplified second clock signal. Therefore, at D ⁇ 8> which is the input at the last stage, it is delayed by 9a.
  • the output Q_F [0: 8] at the lowest operating temperature has a value of [000000000].
  • the amplified first clock signal has a larger delay time than the amplified second clock signal. Therefore, assuming that the rising transition time of the second clock signal and the rising transition time of the first clock signal have a difference of 10a or more at the highest operating temperature condition, the output Q_F [0: 8] has a value of [111111111]. .
  • the degree of temperature change may appear as a change in the digital output.
  • the delay time between the first clock signal and the second clock signal has a difference of 2a or more and 3a or less
  • the output value Q_F [0: 8] may have a value of [111000000].
  • Such an operation principle may be applied to the first unit time delay unit 151, and the first unit time delay unit 151 has a larger time resolution than the second unit time delay unit 155, so that Will output the value.
  • a residual time that is not detected by the first unit time delay unit 151 may be a small time unit in the second unit time delay unit 155. It is output after being converted into digital code through sensing.
  • the digital signal output unit 150 including the n first unit time delay units 151 and the n second unit time delay units 155 has a time difference of 100a (n + 1) and has two bits of digital. Can be output as a signal. Therefore, since the number of output nodes is reduced in the temperature sensing device 100 according to the present invention, the chip cross-sectional area can be reduced and high resolution can be realized.
  • FIG. 11 is a flowchart of a method for sensing a temperature using the temperature sensing device 100 according to an embodiment of the present invention.
  • the first and second clock signals are delayed by delaying the input signal.
  • the first clock signal output unit 110 outputs a first clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series having a first delay time.
  • the second clock signal output unit 120 outputs a second clock signal delayed by an input signal through a ring oscillator including one or more transistors connected in series having a second delay time.
  • the gate channel length of the transistor included in the first clock signal output unit 110 is longer than the gate channel length of the transistor included in the second clock signal output unit 120.
  • the second clock signal is set such that the transition time is the same as the first clock signal at a preset reference temperature.
  • the temperature sensing method according to the present invention may further include amplifying the period of the delayed first clock signal and amplifying the period of the delayed second clock signal (S120).
  • the amplification of each clock signal period is amplified through one or more D-flip flops each connected in series. Since amplifying the periods of the first clock signal and the second clock signal has been described in detail with reference to FIGS. 7 and 8, the description thereof will be omitted below.
  • the digital signal output unit 150 including the plurality of buffers having a unit delay time receives the first clock signal and the second clock signal (S130), and the digital signal output unit. 150 delays the second clock signal (S140).
  • the digital signal output unit 150 outputs the value of the second clock signal corresponding to the case where the first clock signal rises or shifts as a digital signal (S150).
  • the digital signal output unit 150 includes a first unit time delay unit 151 including a plurality of buffers having a first unit delay time and a second unit time including a plurality of buffers having a second unit delay time.
  • the delay unit 155 may further include.
  • the step of delaying the second clock signal by the digital signal output unit 150 may include delaying the second clock signal by the first unit time delay unit 151 and second by the second unit time delay unit 155. Delaying the clock signal may be further included.
  • the first unit delay time may be greater than the second unit delay time.
  • the temperature sensing method outputs the value of the second clock signal as a digital signal when the first clock signal rises and shifts in the first unit time delay unit 151, and the second unit time delay unit.
  • the method may further include outputting a value of the second clock signal as a digital signal when the first clock signal rises or shifts.
  • the second clock signal may be transmitted to the second unit time delay unit 155.

Abstract

La présente invention porte sur un appareil de détection de température, lequel appareil comprend : une première unité de délivrance en sortie de signal d'horloge pour délivrer en sortie un premier signal d'horloge qui est généré en retardant un signal d'entrée à travers un oscillateur en anneau ayant un premier temps de retard, l'oscillateur en anneau comprenant un ou plusieurs transistors connectés en série ; une seconde unité de délivrance en sortie de signal d'horloge pour délivrer en sortie un second signal d'horloge qui est généré en retardant le signal d'entrée à travers un oscillateur en anneau ayant un second temps de retard, l'oscillateur en anneau comprenant un ou plusieurs transistors connectés en série ; et une unité de délivrance en sortie de signal numérique pour recevoir le second signal d'horloge et délivrer en sortie la valeur du second signal d'horloge comme signal numérique en réponse à la transition de montée du premier signal d'horloge, l'unité de délivrance en sortie de signal numérique comprenant une pluralité de tampons ayant chacun un temps de retard unitaire, le premier temps de retard et le second temps de retard étant déterminés en fonction de la longueur de canal de grille du transistor inclus dans la première unité de ce délivrance en sortie de signal d'horloge et de la longueur de canal de grille du transistor inclus dans la seconde unité de délivrance sortie de signal d'horloge, la première unité de délivrance en sortie de signal d'horloge ayant une sensibilité à la variation de température supérieure à celle de la seconde unité de délivrance en sortie de signal d'horloge, et le second signal d'horloge étant établi de façon à avoir le même temps de transition que le premier signal d'horloge à une température de référence pré-établie.
PCT/KR2014/012535 2014-01-02 2014-12-18 Appareil de détection de température et procédé de détection de température basés sur une dépendance en température du courant en fonction d'une variation de longueur de canal WO2015102274A1 (fr)

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KR20030054201A (ko) * 2001-12-24 2003-07-02 삼성전자주식회사 고주파수 클럭을 사용하는 메모리 장치의 인터페이스 회로
KR20070074938A (ko) * 2006-01-11 2007-07-18 삼성전자주식회사 링 오실레이터로 구현된 온도 센서 및 이를 이용한 온도검출 방법
KR20090002487A (ko) * 2007-06-29 2009-01-09 주식회사 하이닉스반도체 펄스 발생 회로 및 이를 이용한 온도 센서 회로

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CN106023890A (zh) * 2016-07-25 2016-10-12 京东方科技集团股份有限公司 温度检测电路和方法、温度补偿装置和方法、及显示装置
CN106023890B (zh) * 2016-07-25 2018-06-01 京东方科技集团股份有限公司 温度检测电路和方法、温度补偿装置和方法、及显示装置
TWI730596B (zh) * 2020-01-20 2021-06-11 瑞昱半導體股份有限公司 溫度感測電路

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