WO2015101067A1

WO2015101067A1 - Rfid reader/writer and rfid system

Info

Publication number: WO2015101067A1
Application number: PCT/CN2014/086713
Authority: WO
Inventors: 李勇; 周小果
Original assignee: 深圳市吉芯微半导体有限公司
Priority date: 2013-12-31
Filing date: 2014-09-17
Publication date: 2015-07-09
Also published as: CN103679239B; CN103679239A

Abstract

An RFID reader/writer, comprising an antenna (3), an RF processing circuit (1), and a card reader integrated chip (2); the RF processing circuit (1) being used for issuing via an antenna (3) a command sequence for an IC card to perform an underlying operation, and via a high-frequency signal passed through said antenna (3) and carrying response data, processing said IC card to obtain a response signal; said card reader integrated chip (2) connecting to a read/write application terminal by means of an audio communications interface and being used for decoding a command, issued by said read/write application terminal by means of said audio communications interface, to obtain an identifiable digital signal, parsing said digital signal as a command sequence and then sending same to said RF processing circuit (1), and processing said response signal obtained by said RF processing circuit (1), and after obtaining the response data, returning same to said read/write application terminal by means of said audio communications interface. Further provided is an RFID system comprising said RFID reader/writer and read/write application terminal.

Description

Radio frequency reader and radio frequency identification system

Technical field

The invention belongs to the technical field of radio frequency identification, and particularly relates to an RF reader and a radio frequency identification system.

Background technique

RF readers are widely used in financial card mobile payment, resident health card reading and writing and identification, public transport card reading and writing and identification, resident ID card reading and writing and identification, product management, logistics management and other fields of wireless intelligent reading. The writing device can realize intelligent reading and recognition of the contact IC card or the non-contact IC card.

As shown in FIG. 1 , the radio frequency reader provided by the prior art includes: an antenna, a radio frequency processing circuit, a field programmable gate array chip, a processor circuit, a local display circuit, and a peripheral interface circuit. In operation, the antenna is used to form a resonant circuit with the coil as an antenna in the IC card, generating a carrier having a certain resonant frequency, and using the carrier to realize bidirectional communication of data; the RF processing circuit is used for processing the UHF signal of the front end; The programmable gate array chip is used to implement the baseband data encoding and decoding specified in the radio frequency protocol; the processor circuit is used to implement some operation interfaces such as instruction jump control and return data display; the peripheral interface circuit is used for connecting a computer, a mobile phone, Peripherals such as memory cards; local display circuits are used to implement local display of transmitted data. As shown in FIG. 2, the radio frequency processing circuit further includes two signal channels that flow in opposite directions, respectively: a transmitting channel, and the transmitting channel first generates a carrier signal of a corresponding operating frequency by a frequency stable quartz crystal oscillator, and the carrier signal will be In the modulation circuit, the amplitude-shift keying modulation is performed by the pseudo-transmitted information sequence that has been encoded by Manchester or the modified Miller or NRZ rule, and finally amplified by the driving amplification circuit, and then transmitted by the antenna; the receiving channel is first filtered by the filtering circuit. In addition to the interference and noise in the high frequency signal received by the antenna, the weak response signal of the IC card is extracted, and then demodulated by the demodulation circuit and sent to the field programmable gate array chip for further processing.

The above-mentioned radio frequency reader/writer provided by the prior art has the following disadvantages: 1. The processor circuit receives an operation command issued by a read/write application terminal having an upper layer application software through a peripheral interface circuit, and the read/write application terminal is connected through a dedicated data interface. Peripheral interface circuits, and different data interface standards adopted by different manufacturers, resulting in low adaptability of RF readers, poor versatility, is not conducive to product promotion; Second, RF processing circuits, field programmable gate array chips The processor circuits are discrete independent chips, which make the RF readers large in size, heavy in weight, high in power consumption and cost, and inconvenient to carry RF readers.

technical problem

The purpose of the embodiments of the present invention is to provide an RF reader for solving the problem that the existing RF reader uses a dedicated data interface to connect peripherals, resulting in low adaptability of the RF reader, and existing The low integration of RF readers leads to the problem of large size, heavy weight, high power consumption and high cost of RF readers, which is not convenient for carrying RFID readers.

Technical solution

The embodiment of the present invention is implemented as follows. An RF reader/writer includes:

antenna;

a radio frequency processing circuit, configured to send a command sequence for performing an underlying operation on the IC card via the antenna, and process the high frequency signal carrying the response data sent by the IC card via the antenna to obtain a response signal;

a card reader integrated chip, wherein the card reader integrated chip is connected to the read/write application terminal through an audio communication interface, and the card reader integrated chip is configured to decode the read/write application terminal by using a command issued by the audio communication interface Obtaining an identifiable digital signal, parsing the digital signal into a command sequence, sending the signal to the radio frequency processing circuit, and processing the response signal obtained by the radio frequency processing circuit to obtain response data, and then passing the audio The communication interface is transmitted back to the read/write application terminal.

Another object of the embodiments of the present invention is to provide a radio frequency identification system including a read/write application terminal and a radio frequency reader/writer, and the radio frequency reader/writer is an RF reader/writer as described above.

Beneficial effect

The radio frequency reader/writer provided by the embodiment of the invention is connected to the reading and writing application terminal through the audio communication interface, and integrates the functional units for processing the interaction signal between the radio frequency processing circuit and the read/write application terminal into a single card reader. In the integrated chip, because the audio communication interface standard is mature and unified, using it to realize data transmission can improve the adaptability of the RF reader and improve the versatility, which is conducive to the promotion of the product. At the same time, the single chip integration is realized, which greatly reduces the The size, weight, power consumption and cost of the RF reader improve the portability of the RF reader.

DRAWINGS

1 is a structural diagram of a radio frequency reader provided by the prior art;

2 is a structural diagram of the radio frequency processing circuit of FIG. 1;

3 is a structural diagram of an RF reader/writer according to an embodiment of the present invention;

4 is a structural diagram of the reader integrated chip of FIG. 3;

FIG. 5 is a diagram showing an example of signal waveforms after the voltage comparator performs binarization processing according to an embodiment of the present invention; FIG.

6 is a structural diagram of the low power control unit of FIG. 4.

Embodiments of the invention

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In view of the problems existing in the existing radio frequency reader, the present invention proposes an RF reader, which is connected to the reading and writing application terminal through an audio communication interface, and will be used for the RF processing circuit and the reading and writing application terminal. The functional units for processing the interaction signals are integrated into a single card reader integrated chip.

FIG. 3 shows the structure of the radio frequency reader/writer provided by the embodiment of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown.

In detail, the radio frequency reader/writer provided by the embodiment of the present invention includes: an antenna 3; a radio frequency processing circuit 1 for issuing a command sequence for performing an underlying operation on the IC card via the antenna 3, and transmitting the IC card through the antenna 3 The high frequency signal carrying the response data is processed to obtain a response signal; the card reader integrated chip 2, the card reader integrated chip 2 is connected to the read and write application terminal through the audio communication interface, and the card reader integrated chip 2 is used for reading and writing applications. The terminal decodes the command sent by the audio communication interface to obtain the identifiable digital signal, parses the digital signal into a command sequence, sends the signal to the RF processing circuit 1, and processes the response signal obtained by the RF processing circuit 1 to obtain the response data. It is transmitted back to the read/write application terminal through the audio communication interface.

The read/write application terminal refers to various terminal devices installed with an upper layer card reading application software and having an audio communication interface, and may be, for example, a computer, a mobile phone, a PDA, or the like.

The RF processing circuit 1 and the card reader integrated chip 2 can be in a standard small volume package form to further reduce the size of the RF reader. The standard small form factor package can be a TSSOP package, a QFN package, or the like.

The RF processing circuit 1 can be integrated or independent of the reader/writer integrated chip 2, and the RF processing circuit 1 can complete the ISO/IEC 14443 standard and the Type A/B standard. Identification and reading and writing of IC cards of ISO/IEC15693 standard, ISO/IEC18092 standard, ISO/IEC21481 standard, and Sony Felica standard.

Further, the radio frequency reader/writer may further include: a non-contact IC card chip (not shown) connected to the antenna 3, and the non-contact IC card chip may be in accordance with the ISO/IEC 14443 standard, the Type A/B standard, IC card chip of ISO/IEC15693 standard or Sony Felica standard. In this way, the RF reader can directly read and write the built-in non-contact IC card chip.

FIG. 4 shows the structure of the reader/writer integrated chip 2 of FIG.

In detail, the reader/writer integrated chip 2 may include: a control register 204; a communication interface unit 201 connected to the radio frequency processing circuit 1; an audio communication interface 202 connected to the read/write application terminal; and a processor 203 for the radio frequency processing circuit 1 The response signal input by the communication interface unit 201 is processed to obtain response data, and the value of the control register 204 is configured. The voltage comparator 206 is configured to perform binarization processing on the command sent by the read/write application terminal through the audio communication interface 202. And extracting the binarized transition edge; the audio signal processing unit 205 is configured to calculate a time interval between adjacent edge edges extracted by the voltage comparator 206, and respectively compare each time interval with the control register 204. The values are compared to obtain a plurality of valid data, and the plurality of valid data are processed correspondingly and sent to the processor 203, and sent by the processor 203 to the radio frequency processing circuit 1 through the communication interface unit 201, and is also used for the processor 203. The obtained response data is processed correspondingly, and the corresponding processed response data is transmitted back to the read/write application terminal through the audio communication interface 202; The system bus 207, the control register 204, the communication interface unit 201, the processor 203, the control register 204, and the audio signal processing unit 205 are all mounted on the system bus 207 and interacted through the system bus 207.

The corresponding processing of the audio signal processing unit 205 refers to: performing synchronous despreading, carrier synchronization and demodulation, frame synchronization, decoding verification, and the like on the signal received through the audio communication interface 202; The signal of the terminal is encoded, spread, and processed by filtering.

The processor 203 can be a central processing unit, or a digital signal processor, or a combination of a central processing unit and a digital signal processor. And the central processing unit or digital signal processor can be, but is not limited to, an 8-bit, 16-bit or 32-bit kernel.

Wherein, when the RF processing circuit 1 is independent of the reader/writer integrated chip 2, the communication interface unit 201 can be, but is not limited to, a universal asynchronous transceiver (Universal) Asynchronous Receiver/Transmitter, UART) interface, Universal Serial Bus (Universal Serial Bus, USB) interface, Serial Peripheral Interface (SPI), parallel interface, I2C bus interface, etc.

The audio communication interface 202 includes three signal lines and one ground line. The three signal lines are the left channel signal line, the right channel signal line and the microphone signal line. One of the left channel signal line or the right channel signal line is used to implement signal transmission from the read/write application terminal to the reader/writer integrated chip 2; the other of the left channel signal line or the right channel signal line is used for charging Or realize the signal transmission of the read/write application terminal to the reader/writer integrated chip 2; the microphone signal line is used for realizing the signal transmission of the reader integrated chip 2 to the read/write application terminal.

Further, the value of the control register 204 may include a carrier frequency and a modulation mode identification bit, a threshold configuration value Lx, a minimum effective value Lmin, and a maximum effective value Lmax, and Lmin < Lx < Lmax. Voltage comparator The signal waveform diagram after the binarization processing is performed, for example, as shown in FIG. 5, assuming that the time interval between the nth (n is a positive integer) adjacent transition edges is Ln, the audio signal processing unit 205 can determine the current transmission. Signal content: If Ln<Lmin or Ln>Lmax, it indicates that the current transmission is an interference signal and discards the processing; in the non-data transmission state, Lmin<Ln<Lx indicates that the current transmission is a carrier signal, and in the data transmission state, the current transmission is indicated. The data bit is the same as the value of the previous bit data; in the non-data transfer state, Lx<Ln<Lmax indicates that the current data transfer start bit is switched to the data transfer state, and the data transfer state indicates that the currently transmitted data bit is before. The value of one bit of data is different. According to this rule, when a certain number of bits of data are received and the subsequent check value is correct, the bit data is combined into a valid data word and switched to a non-data transfer state, and an interrupt signal is generated to notify the processor 203 to proceed to the next step. Processing.

In the embodiment of the present invention, the radio frequency reader can be powered by an external power source, or powered by a self-contained rechargeable battery, or by a combined power supply of an external power source and a rechargeable battery. When the radio frequency reader includes a rechargeable battery, the reader integrated chip 2 may further include: a battery protection circuit 208 for short circuit protection, over current protection, over charge protection and/or over discharge protection of the rechargeable battery; battery management Unit 209, configured to implement a rechargeable battery The charge and discharge management of 208, and the current state of charge of the rechargeable battery 208 is sent to the processor 203 in real time, so that the processor 203 can perform subsequent actions according to the same, for example, if the current state of charge has reached a certain value, the external power source can be The power supply is switched to the rechargeable battery 208 for power supply. Preferably, the rechargeable battery 208 is a lithium battery.

Among them, the short circuit protection is to detect the short circuit of the positive/negative voltage output pin of the rechargeable battery, and perform a protection action when a short circuit is detected; the overcurrent protection means that when a large current flows through the load is detected Controlling the rechargeable battery to stop discharging to the load to protect the rechargeable battery; overcharge protection When detecting that the voltage of the rechargeable battery rises to the charging threshold, the control stops charging the rechargeable battery; over-discharge protection refers to when the rechargeable battery is in a discharged state If it is detected that the voltage of the rechargeable battery falls to the discharge threshold, the control rechargeable battery stops supplying power to the load.

In the embodiment of the present invention, the reader/writer integrated chip 2 may further include: a voltage conversion unit 210, configured to convert the voltage output by the external power source or the rechargeable battery 208 into a voltage required for the operation of each power component, and output the corresponding voltage to the corresponding a power consumption portion; a detecting unit 211 connected to the power supply circuit of each power consumption portion, configured to detect whether the power supply voltage of the phase application power portion is abnormal, and send the detection result to the processor 203, so that the processor 203 responds in time. To protect the device from operating safely.

In the embodiment of the present invention, the reader/writer integrated chip 2 may further include: a peripheral interface unit 212. The peripheral interface unit 212 may be a peripheral interface unit that connects peripheral communication or control devices such as a liquid crystal display, a touch screen, or a smart card, or may be a memory controller that can generate an external memory (eg, external data memory) interface timing. Further, if the peripheral interface unit 212 is a peripheral interface unit, the peripheral interface unit can be, but is not limited to, including: UART interface, USB interface, ISO/IEC7816 standard interface, SPI, parallel interface, I2C bus interface, SWP/eSWP interface or NFC-WI interface. Wherein, if the peripheral interface unit is an ISO/IEC7816 standard interface, the ISO/IEC7816 standard interface can be connected to various contact chip cards, such as: E-SAM card, P-SAM card, various contact memory cards, password cards. Or smart chip card, etc. Wherein, if the peripheral interface unit is a parallel interface, the parallel interface may select whether to filter the input interference signal. This filter function does not work when the passthrough is set, otherwise the interference signal with a stable duration of less than n clock cycles is filtered out.

In the embodiment of the present invention, the reader/writer integrated chip 2 may further include: a random number generator 215 for generating a random number of one or more bits; and an encryption and decryption unit 213 connecting the processor 203 and the random number generator 215, Decrypting the response signal of the RF processing circuit 1 through the communication interface unit 201 to the processor 203 according to the random number generated by the random number generator 215, and also for processing the processor according to the random number generated by the random number generator 215 203 received valid data for encryption processing. Preferably, the encryption and decryption unit 213 is a 3DES encryption and decryption module, an AES encryption and decryption module, an RSA encryption and decryption module, an SM1 encryption and decryption module, SM2 encryption and decryption module, SM3 encryption and decryption module, SM4 encryption and decryption module.

In the embodiment of the present invention, the data error correction and retransmission mechanism may also be integrated in the audio signal processing unit 205. Specifically, when the audio signal processing unit 205 receives the interfered data, it will attempt to recover the correct data, if the interference is severely restricted. If the data is reliably restored, no response signal will be generated, and when the signal source does not receive the response signal, the last transmitted data will be retransmitted.

In the embodiment of the present invention, the reader/writer integrated chip 2 can also solidify the monitoring and debugging software, and can be used for IC testing and assisting end user software development. At this time, after the processor 203 is powered on and working, first judge a certain lead. Whether the pin is a specified level value determines whether the power-on needs to enter the monitoring, debugging mode or normal application software mode. The reader integrated chip 2 can also control the working mode by the voltage applied by the programming voltage pin, specifically: when the voltage applied by the programming voltage pin is a high voltage, the OTP programming mode is specified, and the voltage applied by the programming voltage pin is specified. When it is high, it is in the normal working mode, and when the voltage applied to the programming voltage pin is low, it is forced reset mode.

In the embodiment of the present invention, the reader/writer integrated chip 2 may further include: a low power consumption control unit 214 mounted on the system bus 207 and connected to the audio signal processing unit 205 or the radio frequency processing circuit 1 for use in the processor Under the control of the 203 and the system clock, the trigger of the control audio signal processing unit 205 or the flip-flop of the RF processing circuit 1 does not flip in the non-operating state, thereby reducing the dynamic power consumption of the system.

FIG. 6 shows the structure of the low power control unit 214 of FIG.

Since the dynamic power consumption of the RF reader is mainly caused by the flipping of the circuit node level, the purpose of reducing the dynamic power consumption can be achieved by reducing the circuit node flip. Based on this, in the embodiment of the present invention, the low power consumption control unit 214 may include: a trigger register of the audio signal processing unit 205 or a working register 2145 of the trigger of the radio frequency processing circuit 1; mounted on the system bus 207 and working on System clock A clock enable register 2141 under SCLK for outputting a clock enable signal CLKEN in the configuration of the processor 203; a clock gating unit 2142 connected to the clock enable register 2141 and the work register 2145 and operating under the system clock SCLK For generating the clock gating signal CLKX according to the clock enable signal CLKEN and outputting the clock gating signal CLKX to the working register 2145, and the clock gating signal CLKX is constantly at a high level or low when the clock enable signal CLKEN is inactive. Level, when the clock enable signal CLKEN is active, the phase of the clock gating signal CLKX changes with the change of the system clock SCLK; mounted on the system bus a work enable register 2143 operating on the system clock SCLK, for outputting the work enable signal ENABLEX in the configuration of the processor 203; and an operation mode selection unit 2144 connecting the work register 2145 for enabling according to the work The signal ENABLEX selects the data input signal DINX of the working register 2145 from the input signal of the operation mode selecting unit 2144 and outputs the data input signal DINX to the working register 2145, and selects the working mode selecting unit 2144 when the work enable signal ENABLEX is active. The normal input signal DY is used as the data input signal DINX, and the normal input signal DY is used as the working register. The reset initial value input of 2145 selects the constant initial value input signal DX of the operating mode selecting unit 2144 as the data input signal DINX when the work enable signal ENABLEX is invalid.

The working register 2145 is a flip-flop of the audio signal processing unit 205 or a flip-flop of the radio frequency processing circuit 1. The characteristics of the flip-flop are: only at the clock transition edge, the sampling signal is input, and the input signal is held to the output; in the normal working mode of the working register 2145, that is, the data input signal DINX is the normal input signal DY, the audio signal The processing unit 205 or the radio frequency processing circuit 1 can complete the corresponding processing function. Thus, if the clock gating signal CLKX is constantly at a high level or a low level, that is, no flipping occurs, there is no clock edge, and the working register 44 is not changed, thereby achieving the purpose of reducing the dynamic power consumption of the circuit; When the work enable signal ENABLEX is invalid, the data input signal DINX sent from the working mode selecting unit 2144 to the working register 2145 is a constant value DX. At this time, regardless of whether the clock gating signal CLKX is inverted, the output of the working register 2145 is not inverted. Achieve the purpose of reducing the dynamic power consumption of the circuit.

For example, if the valid value of the clock enable signal CLKEN is "0" and the invalid value is "1", that is, when the clock enable signal CLKEN is "0", the working register 2145 of the audio signal processing unit 205 is turned on. The clock, when the clock enable signal CLKEN is "1", will turn off the clock of the working register 2145 of the audio signal processing unit 205; the effective value of the work enable signal ENABLEX is "1", and the invalid value is "0", that is to say When the work enable signal ENABLEX is "1", the audio signal processing unit 205 is selected to be in the normal function mode. When the work enable signal ENABLEX is "0", the audio signal processing unit 205 is selected to be in the reset mode, and the working register 44 will stop flipping. . Then, when the processor 203 sets the work enable signal ENABLEX to the valid value "1", the working mode selecting unit 2144 selects the normal input signal DY of the working mode selecting unit 2144 as the data input signal DINX, if the processor 203 simultaneously sets the clock enable. The signal CLKEN is a valid value "0", so that the clock gating signal CLKX is enabled, the working register 2145 can work normally; when the processor 203 sets the work enable signal ENABLEX to the invalid value "0", the working mode selecting unit 2144 The constant initial value input signal DX of the operating mode selection unit 2144 is selected as the data input signal DINX. At this time, regardless of whether the clock enable signal CLKEN is valid, the working register 2145 will maintain the output constant value to reduce the dynamic power consumption; 203 setting the clock enable signal CLKEN to an invalid value "1", the clock gating signal CLKX is a constant value of "1" and will not flip to reduce dynamic power consumption. Since the dynamic power consumption of the clock is the main dynamic power consumption of the RF reader, reducing the dynamic power of the clock will greatly reduce the RF reader. The overall dynamic power consumption.

In addition, the embodiment of the present invention further provides a radio frequency identification system, including a read/write application terminal and a radio frequency reader/writer as described above, which are not described herein.

In summary, firstly, the radio frequency reader/writer proposed by the present invention is connected to the reading and writing application terminal through an audio communication interface, and integrates various functional units for processing the interaction signal between the radio frequency processing circuit and the read/write application terminal. In the single card reader integrated chip, because the audio communication interface standard is mature and unified, using it to realize data transmission can improve the adaptability of the RF reader and improve the versatility, which is conducive to the promotion of the product, and at the same time, realizes the single chip. The integration greatly reduces the size, weight, power consumption and cost of the RF reader, and improves the portability of the RF reader. Secondly, the RF reader provides a rich and flexible interface unit that is modular and reduces the complexity of developing more sophisticated IC card applications. Finally, the clock enable and work enable modes are adopted, which greatly reduces the dynamic power consumption of the RF reader and realizes the purpose of extending the standby time.

A person skilled in the art can understand that all or part of the methods of the foregoing embodiments can be implemented, and the related hardware can be controlled by a program, and the program can be stored in a computer readable storage medium, the storage medium, Such as ROM / RAM, disk, CD, etc.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. Within the scope.

Claims

An RF reader/writer, characterized in that the RF reader/writer includes:

antenna;

a radio frequency processing circuit, configured to send a command sequence for performing an underlying operation on the IC card via the antenna, and process the high frequency signal carrying the response data sent by the IC card via the antenna to obtain a response signal;

a card reader integrated chip, wherein the card reader integrated chip is connected to the read/write application terminal through an audio communication interface, and the card reader integrated chip is configured to decode the read/write application terminal by using a command issued by the audio communication interface Obtaining an identifiable digital signal, parsing the digital signal into a command sequence, sending the signal to the radio frequency processing circuit, and processing the response signal obtained by the radio frequency processing circuit to obtain response data, and then passing the audio The communication interface is transmitted back to the read/write application terminal.
The radio frequency reader/writer according to claim 1, wherein the reader/writer integrated chip comprises:

Control register

Connecting a communication interface unit of the radio frequency processing circuit;

Connecting an audio communication interface of the read/write application terminal;

a processor, configured to process the response signal input by the radio frequency processing circuit through the communication interface unit, obtain response data, and configure a value of the control register;

a voltage comparator, configured to perform binarization processing on the command sent by the read/write application terminal through the audio communication interface, and extract a binarized transition edge;

An audio signal processing unit, configured to calculate a time interval between adjacent edge edges extracted by the voltage comparator, and compare each time interval with a value of the control register to obtain multiple valid data, And the multi-bit valid data is correspondingly processed and sent to the processor, and sent by the processor to the radio frequency processing circuit by using the communication interface unit, where the audio signal processing unit is further configured to The response data obtained by the processor is processed correspondingly, and the corresponding processed response data is transmitted back to the read/write application terminal through the audio communication interface;

The system bus, the control register, the communication interface unit, the processor, the control register, and the audio signal processing unit are all mounted on the system bus.
The radio frequency reader/writer according to claim 2, wherein the radio frequency reader/writer further comprises a rechargeable battery, and the reader/writer integrated chip further comprises:

a battery protection circuit for short-circuit protection, over-current protection, over-charge protection, and/or over-discharge protection of the rechargeable battery;

And a battery management unit, configured to implement charge and discharge management of the rechargeable battery, and send the current state of charge of the rechargeable battery to the processor in real time.
The radio frequency reader/writer according to claim 3, wherein the reader/writer integrated chip comprises:

a voltage conversion unit, configured to convert an external power source or a voltage output by the rechargeable battery into a voltage required for operation of each of the power-consuming portions of the reader/writer integrated circuit, and output the voltage to the phase application power portion;

A detecting unit connected to the power supply circuit of each of the power-consuming portions is configured to detect whether the power supply voltage of the phase-applied portion is abnormal, and transmit the detection result to the processor.
The radio frequency reader/writer according to claim 2, wherein said reader/writer integrated chip comprises a peripheral interface unit;

The peripheral interface unit includes: a UART interface, a USB interface, an ISO/IEC7816 standard interface, an SPI, a parallel interface, an I2C bus interface, an SWP/eSWP interface, an NFC-WI interface, and/or a storage controller;

The ISO/IEC 7816 standard interface is used to connect an E-SAM card, a P-SAM card, a contact type memory card, a password card or a smart chip card.
The radio frequency reader/writer according to claim 2, wherein the reader/writer integrated chip comprises:

a random number generator for generating a random number;

And an encryption and decryption unit connected to the processor and the random number generator, configured to input, by the communication interface unit, the processor by the radio frequency processing circuit according to a random number generated by the random number generator The response signal is subjected to decryption processing, and is further configured to perform encryption processing on the valid data received by the processor according to the random number generated by the random number generator.
The radio frequency reader/writer according to claim 2, wherein said reader/writer integrated chip comprises: mounted on said system bus and connected to said audio signal processing unit or said radio frequency processing circuit A power consumption control unit, the low power control unit includes:

a working register as a trigger of the audio signal processing unit or a flip-flop of the radio frequency processing circuit;

a clock enable register mounted on the system bus and operating under the system clock, configured to output a clock enable signal in a configuration of the processor;

a clock gating unit connected to the clock enable register and the working register and operating under the system clock, configured to generate a clock gating signal according to the clock enable signal and output the clock gating signal Giving the working register, and when the clock enable signal is invalid, the clock gating signal is constantly at a high level or a low level, and the clock gating signal is phased when the clock enable signal is active The system clock changes and changes;

a work enable register mounted on the system bus and operating under the system clock, for outputting a work enable signal in a configuration of the processor;

An operation mode selection unit connected to the working register, configured to select a data input signal of the working register from an input signal of the working mode selection unit according to the work enable signal and output the data input signal to The working register, and selecting a normal input signal of the working mode selection unit as the data input signal when the work enable signal is valid, and selecting the working mode selection unit to be constant when the work enable signal is invalid The initial value input signal is used as the data input signal.
The radio frequency reader/writer according to claim 2, wherein the communication interface unit is a UART interface, a USB interface, an SPI, a parallel interface, and an I2C bus interface.
The radio frequency reader/writer according to claim 2, wherein said audio communication interface comprises three signal lines and a ground line, said three signal lines comprising a left channel signal line, a right channel signal line and a microphone Signal line

One of the left channel signal line or the right channel signal line is used to implement signal transmission of the read/write application terminal to the reader/writer integrated chip, the left channel signal line or the right The other of the channel signal lines is used to implement charging or signal transmission of the read/write application terminal to the reader/writer integrated chip, and the microphone signal line is used to implement the reader integrated chip to the read Write the signal transmission of the application terminal.
The radio frequency reader/writer according to claim 1, wherein the radio frequency processing circuit is integrated on the reader/writer integrated chip;

The radio frequency processing circuit is used to complete compliance with the ISO/IEC 14443 standard and the Type A/B standard. , ISO/IEC15693 standard, ISO/IEC18092 standard, ISO/IEC21481 standard, Sony Identification and reading and writing of Felica standard IC cards.
The radio frequency reader/writer according to claim 1, wherein the radio frequency reader/writer further comprises:

a contactless IC card chip connecting the antenna, the non-contact IC card chip conforming to ISO/IEC 14443 Standard, Type A/B standard, ISO/IEC 15693 standard or Sony Felica standard IC card chip.
A radio frequency identification system comprising a read/write application terminal and an RF reader/writer, wherein the radio frequency reader/writer is the radio frequency reader/writer according to any one of claims 1 to 11.